A cross-node heterogeneous memory pooling method and system based on a CXL protocol

Abstract

The application discloses a cross-node heterogeneous memory pooling method and system based on a CXL protocol, and belongs to the technical field of server architecture and memory resource management. The method builds a communication link between a computing node and a heterogeneous memory resource pool through a CXL exchange unit, deploys an FPGA-accelerated intelligent memory controller and optimizes an access path; divides the storage functions of DRAM, CXL memory and HBM, establishes a unified management mechanism to realize resource centralized scheduling; relies on a machine learning model to distinguish different access frequency data and migrate to the corresponding memory, dynamically adjusts the memory bandwidth and capacity; constructs a key data redundancy image, expands an atomic operation protocol to guarantee concurrent access consistency, and establishes a node fault monitoring and recovery mechanism. The system adapts to the above method and integrates hardware and software modules to work cooperatively. The scheme realizes efficient sharing and dynamic management of cross-node memory resources, improves resource utilization and access efficiency, enhances system stability and expandability, and meets the memory requirements of high-performance computing scenarios.

Description

Technical Field

[0001] This invention relates to the field of server architecture and memory resource management technology, and in particular to a cross-node heterogeneous memory pooling method and system based on the CXL protocol. Background Technology

[0002] With the rapid development of fields such as artificial intelligence and high-performance computing, the scale and complexity of data processing continue to increase, placing higher demands on the capacity, bandwidth, latency, and sharing capabilities of memory resources. Currently, server architecture is evolving towards heterogeneity and pooling. The Compute Express Link (CXL) protocol, with its low latency and high bandwidth, has become a core technology choice for connecting computing nodes and memory resources, and is widely used in cross-node memory sharing scenarios. The diversified configuration of heterogeneous memory resources has become the industry mainstream. Memory types with different characteristics, such as DRAM, CXL memory, and HBM, are being integrated and applied to form heterogeneous memory resource pools to meet the differentiated needs of various computing tasks. At the same time, the application of FPGA acceleration technology and machine learning algorithms in memory management is gradually becoming more widespread. The hardware functions of various memory controllers and switching units are constantly being optimized, and the software-level memory management modules are also continuously iterating, driving the gradual maturation of cross-node memory pooling technology and providing fundamental support for large-scale data processing and high-performance computing.

[0003] In current technological practices, cross-node memory pooling still faces several pressing technical challenges. First, the communication links between compute nodes and heterogeneous memory resource pools lack efficient optimization, memory access paths are poorly designed, and the adaptability of hot-swapping and hot-adding functions is insufficient, affecting the flexibility of resource expansion. Second, heterogeneous memory resources lack clear functional division and a unified resource management mechanism, making it difficult to achieve centralized scheduling and efficient sharing of cross-node memory resources. Third, existing technologies cannot accurately distinguish data with different access frequencies and store them accordingly; memory bandwidth and capacity allocation cannot be dynamically adjusted based on the real-time task requirements of compute nodes, resulting in low resource utilization. Finally, critical data lacks effective redundancy protection mechanisms, making it difficult to guarantee data consistency during concurrent access by multiple nodes, and the recovery mechanism after node failure is inadequate, affecting the stability and reliability of system operation. These problems restrict the application effect of cross-node heterogeneous memory pooling technology and cannot fully meet the high-efficiency operation requirements of scenarios such as high-performance computing and large-scale data processing. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a cross-node heterogeneous memory pooling method and system based on the CXL protocol.

[0005] The objective of this invention is achieved through the following technical solution: A cross-node heterogeneous memory pooling method based on the CXL protocol is provided, which includes the following steps: S1. Establish communication links between multiple computing nodes and heterogeneous memory resource pools through CXL switching units, deploy FPGA-accelerated intelligent memory controllers, optimize cross-node memory access paths, and configure hot-swapping and hot-adding functions. S2. Based on the hardware configuration of the heterogeneous memory resource pool, the heterogeneous memory resource pool is divided into three categories: DRAM, CXL memory and HBM. The storage functions of each type of memory are clarified, a unified management mechanism is established to record the resource status and allocation, and centralized scheduling and sharing of cross-node memory resources are realized. S3. Based on the memory access data recorded by the unified management mechanism, distinguish between data with access frequency higher than the set threshold and data with access frequency lower than the set threshold, migrate different types of data to the corresponding memory areas according to the storage function of each type of memory, and dynamically adjust memory bandwidth and capacity allocation according to the real-time task requirements of computing nodes. S4. Based on the data classification information in the memory allocation record, determine the range of key data, build a redundant memory image for the key data, extend the atomic operation protocol based on the CXL.mem protocol, perform data consistency control on concurrent access by multiple nodes, and establish a node fault monitoring and recovery mechanism.

[0006] Furthermore, step S1 includes: S1.1. Use CXL links to connect computing nodes and heterogeneous memory resource pools, and configure the CXL switching unit with multi-logical device functions and dynamic capacity device functions; S1.2. Based on the connection architecture formed by the CXL link, deploy an FPGA-accelerated intelligent memory controller to optimize cross-node memory access paths through hardware-level logic; S1.3. By leveraging the connection between the CXL switching unit and the heterogeneous memory resource pool, hot-swapping and hot-adding functions are enabled for both.

[0007] Furthermore, step S2 includes: S2.1. Define the characteristics of DRAM, CXL memory, and HBM; S2.2. Based on the characteristics of various types of memory, define the storage function division of DRAM, CXL memory and HBM; S2.3. According to the defined storage function division, establish a memory resource registration and monitoring mechanism to record the usage status, remaining capacity and allocation of various types of memory, and form a resource management ledger; S2.4. Extract record information from the resource management ledger and synchronize the memory resource view of each computing node.

[0008] Furthermore, the process of distinguishing data in step S3 includes: S3.1. Construct a machine learning model. The model includes an input layer, a feature extraction layer, a classification layer, and an output layer. The input layer receives memory access logs and read / write record data. The feature extraction layer extracts data access frequency, access interval, and access duration features through convolution and pooling operations. The classification layer uses a fully connected network to process the features. The output layer outputs the classification results. S3.2. Divide the time window to collect memory access logs and read / write records, normalize the collected data, divide the data into training set, validation set and test set, initialize the weight parameters and bias parameters of the machine learning model, set the learning rate, number of iterations and batch size hyperparameters, input the training set data into the constructed machine learning model, update the model parameters through the backpropagation algorithm, and iterate until the model's classification accuracy on the validation set reaches the preset standard. S3.3. Call the trained machine learning model to process the test set data, statistically analyze the distribution of access frequency and access interval, set an access frequency threshold, and use multi-dimensional features to determine data with access frequency higher than the set threshold and data with access frequency lower than the set threshold.

[0009] Furthermore, step S3 also includes: S3.4. Based on the division of storage functions and data judgment results, perform data migration operations to migrate data with access frequency higher than the set threshold, data with access frequency lower than the set threshold, and high-performance computing data to the corresponding memory. S3.5. Collect the running status of computing node tasks, memory usage, and access request queue length after the data migration operation. Based on the collected node-related information, adjust the memory bandwidth allocation ratio and capacity scale, and update the memory allocation record.

[0010] Furthermore, step S4 includes: S4.1. Extract data classification information from memory allocation records, determine the key data range of core parameters, intermediate results and configuration information of computing tasks, and formulate a hierarchical redundant storage strategy; S4.2. Based on the hierarchical redundancy storage strategy and the storage layout of the heterogeneous memory resource pool, create redundant memory images of key data in different physical storage areas; S4.3. Based on the storage method of redundant memory mirroring, the CXL.mem protocol is extended to form an atomic operation protocol to sort and mutually exclude concurrent read and write requests from multiple nodes; S4.4. Based on the communication link between the computing node and the heterogeneous memory resource pool, a node fault monitoring mechanism is established. When a node fault is detected, redundant memory image data is called to migrate the data to the normal node.

[0011] Furthermore, in step S3, a two-level memory allocation strategy is adopted, which combines historical task memory usage data, the current total amount of free memory in the system, and task expansion estimates to pre-allocate multiple large blocks of memory of fixed size, and divide each large block of memory into small blocks of memory of uniform size; when a small block of memory is released, the free status of adjacent memory blocks is detected, adjacent free memory blocks are merged, and the merged memory blocks are managed according to the system memory request scale.

[0012] Furthermore, in step S3, based on the memory blocks divided by the two-level memory allocation strategy, the LRU-K strategy is used to maintain a memory block access history list, recording the access time, access count, and access interval of each memory block; the list data is updated periodically, invalid records are eliminated, and an initial K value is set based on the access information recorded in the list; during the memory reclamation phase, the frequency of the most recent K accesses of each memory block is counted, and memory blocks with access frequencies lower than the set threshold are released first; the system load, memory utilization, and task access characteristics are monitored, and the K value is adjusted accordingly.

[0013] Furthermore, in step S3, based on the memory resource view of each computing node, an independent virtual memory mapping table is configured for each computing node to record the correspondence between local virtual addresses and remote physical addresses, the mapping validity status, and access permissions; the cache consistency support function of the CXL protocol is enabled, an address mapping validity detection mechanism is established, and the accuracy of the mapping relationship is periodically verified; the mapping table is updated according to the verification results and synchronized to the corresponding computing node; the computing node locates the remote physical address through the virtual memory mapping table and accesses the remote memory data.

[0014] In some embodiments, a cross-node heterogeneous memory pooling system based on the CXL protocol is provided. The system includes a heterogeneous memory resource pool, a CXL switching unit, an intelligent memory controller, a dynamic management engine, an operating system kernel module, a cold and hot data tiering algorithm module, a QoS control module, and a fault tolerance module. The heterogeneous memory resource pool includes DRAM, CXL memory, and HBM, with each type of memory providing storage services according to its preset functional positioning. The CXL switching unit connects the compute nodes to the heterogeneous memory resource pool via CXL links, and is configured with multi-logic device functions, dynamic capacity device functions, and hot-swapping and hot-adding functions. The intelligent memory controller adopts an FPGA-accelerated design, optimizes access paths, and establishes an instruction interaction channel with the CXL switching unit. The dynamic management engine receives memory allocation data, migration status, and load information from each module and issues adjustment instructions. The operating system kernel module integrates the memory management engine to realize dynamic memory allocation and hot-swapping related operations. The cold and hot data stratification algorithm module includes a data acquisition submodule, a model training submodule, and a data migration submodule. The data acquisition submodule collects memory access data, the model training submodule builds and trains machine learning models, and the data migration submodule performs data migration operations. The QoS control module collects device load information and adjusts the access request rate of compute nodes. The fault tolerance module creates redundant memory images and ensures data consistency and fault recovery through atomic operation protocols.

[0015] The beneficial effects of this invention are: (1) By building cross-node communication links, dividing heterogeneous memory functions, distinguishing data migration and building redundant images and consistency control, the centralized scheduling and sharing of cross-node memory resources can be realized, thereby improving the flexibility of resource adaptation. (2) By using machine learning to identify data access characteristics and dynamically allocate memory bandwidth and capacity, combined with data layering migration strategies, the efficiency of memory resource allocation can be optimized and access latency reduced; (3) Integrate redundant memory images, extend atomic operation protocols and node fault monitoring mechanisms to ensure data consistency when multiple nodes access concurrently and enhance system stability. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the steps of a cross-node heterogeneous memory pooling method based on the CXL protocol; Figure 2 The following is a flowchart illustrating the specific steps of a cross-node heterogeneous memory pooling method based on the CXL protocol, provided as an example. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1 A cross-node heterogeneous memory pooling method based on the CXL protocol is provided, which includes the following steps: S1. Establish communication links between multiple computing nodes and heterogeneous memory resource pools through CXL switching units, deploy FPGA-accelerated intelligent memory controllers, optimize cross-node memory access paths, and configure hot-swapping and hot-adding functions. S2. Based on the hardware configuration of the heterogeneous memory resource pool, the heterogeneous memory resource pool is divided into three categories: DRAM, CXL memory and HBM. The storage functions of each type of memory are clarified, a unified management mechanism is established to record the resource status and allocation, and centralized scheduling and sharing of cross-node memory resources are realized. S3. Based on the memory access data recorded by the unified management mechanism, distinguish between data with access frequency higher than the set threshold and data with access frequency lower than the set threshold, migrate different types of data to the corresponding memory areas according to the storage function of each type of memory, and dynamically adjust memory bandwidth and capacity allocation according to the real-time task requirements of computing nodes. S4. Based on the data classification information in the memory allocation record, determine the range of key data, build a redundant memory image for the key data, extend the atomic operation protocol based on the CXL.mem protocol, perform data consistency control on concurrent access by multiple nodes, and establish a node fault monitoring and recovery mechanism.

[0019] In some embodiments, step S1 includes: S1.1. Use CXL links to connect computing nodes and heterogeneous memory resource pools, and configure the CXL switching unit with multi-logical device functions and dynamic capacity device functions; S1.2. Based on the connection architecture formed by the CXL link, deploy an FPGA-accelerated intelligent memory controller to optimize cross-node memory access paths through hardware-level logic; S1.3. By leveraging the connection between the CXL switching unit and the heterogeneous memory resource pool, hot-swapping and hot-adding functions are enabled for both.

[0020] In some embodiments, step S2 includes: S2.1. Define the characteristics of DRAM, CXL memory, and HBM; S2.2. Based on the characteristics of various types of memory, define the storage function division of DRAM, CXL memory and HBM; S2.3. According to the defined storage function division, establish a memory resource registration and monitoring mechanism to record the usage status, remaining capacity and allocation of various types of memory, and form a resource management ledger; S2.4. Extract record information from the resource management ledger and synchronize the memory resource view of each computing node.

[0021] In some embodiments, the process of distinguishing data in step S3 includes: S3.1. Construct a machine learning model. The model includes an input layer, a feature extraction layer, a classification layer, and an output layer. The input layer receives memory access logs and read / write record data. The feature extraction layer extracts data access frequency, access interval, and access duration features through convolution and pooling operations. The classification layer uses a fully connected network to process the features. The output layer outputs the classification results. S3.2. Divide the time window to collect memory access logs and read / write records, normalize the collected data, divide the data into training set, validation set and test set, initialize the weight parameters and bias parameters of the machine learning model, set the learning rate, number of iterations and batch size hyperparameters, input the training set data into the constructed machine learning model, update the model parameters through the backpropagation algorithm, and iterate until the model's classification accuracy on the validation set reaches the preset standard. S3.3. Call the trained machine learning model to process the test set data, statistically analyze the distribution of access frequency and access interval, set an access frequency threshold, and use multi-dimensional features to determine data with access frequency higher than the set threshold and data with access frequency lower than the set threshold.

[0022] In some embodiments, step S3 further includes: S3.4. Based on the division of storage functions and data judgment results, perform data migration operations to migrate data with access frequency higher than the set threshold, data with access frequency lower than the set threshold, and high-performance computing data to the corresponding memory. S3.5. Collect the running status of computing node tasks, memory usage, and access request queue length after the data migration operation. Based on the collected node-related information, adjust the memory bandwidth allocation ratio and capacity scale, and update the memory allocation record.

[0023] In some embodiments, step S4 includes: S4.1. Extract data classification information from memory allocation records, determine the key data range of core parameters, intermediate results and configuration information of computing tasks, and formulate a hierarchical redundant storage strategy; S4.2. Based on the hierarchical redundancy storage strategy and the storage layout of the heterogeneous memory resource pool, create redundant memory images of key data in different physical storage areas; S4.3. Based on the storage method of redundant memory mirroring, the CXL.mem protocol is extended to form an atomic operation protocol to sort and mutually exclude concurrent read and write requests from multiple nodes; S4.4. Based on the communication link between the computing node and the heterogeneous memory resource pool, a node fault monitoring mechanism is established. When a node fault is detected, redundant memory image data is called to migrate the data to the normal node.

[0024] In some embodiments, in step S3, a two-level memory allocation strategy is adopted, which combines historical task memory usage data, the current total amount of free memory in the system and task expansion estimates to pre-allocate multiple large blocks of memory of fixed size, and divide each large block of memory into small blocks of memory of uniform size; when the small blocks of memory are released, the free status of adjacent memory blocks is detected, adjacent free memory blocks are merged, and the merged memory blocks are managed according to the system memory request scale.

[0025] In some embodiments, in step S3, based on the memory blocks divided by the two-level memory allocation strategy, the LRU-K strategy is used to maintain a memory block access history list, recording the access time, access count, and access interval of each memory block; the list data is updated periodically, invalid records are eliminated, and an initial K value is set based on the access information recorded in the list; during the memory reclamation phase, the frequency of the most recent K accesses of each memory block is counted, and memory blocks with access frequencies lower than a set threshold are released first; the system load, memory utilization, and task access characteristics are monitored, and the K value is adjusted accordingly.

[0026] In some embodiments, in step S3, based on the memory resource view of each computing node, an independent virtual memory mapping table is configured for each computing node to record the correspondence between local virtual addresses and remote physical addresses, the mapping validity status, and access permissions; the cache consistency support function of the CXL protocol is enabled, an address mapping validity detection mechanism is established, and the accuracy of the mapping relationship is periodically verified; the mapping table is updated according to the verification result and synchronized to the corresponding computing node; the computing node locates the remote physical address and accesses the remote memory data through the virtual memory mapping table.

[0027] In some embodiments, a cross-node heterogeneous memory pooling system based on the CXL protocol is provided. The system includes a heterogeneous memory resource pool, a CXL switching unit, an intelligent memory controller, a dynamic management engine, an operating system kernel module, a cold and hot data tiering algorithm module, a QoS control module, and a fault tolerance module. The heterogeneous memory resource pool includes DRAM, CXL memory, and HBM, with each type of memory providing storage services according to its preset functional positioning. The CXL switching unit connects the compute nodes to the heterogeneous memory resource pool via CXL links, and is configured with multi-logic device functions, dynamic capacity device functions, and hot-swapping and hot-adding functions. The intelligent memory controller adopts an FPGA-accelerated design, optimizes access paths, and establishes an instruction interaction channel with the CXL switching unit. The dynamic management engine receives memory allocation data, migration status, and load information from each module and issues adjustment instructions. The operating system kernel module integrates the memory management engine to realize dynamic memory allocation and hot-swapping related operations. The cold and hot data stratification algorithm module includes a data acquisition submodule, a model training submodule, and a data migration submodule. The data acquisition submodule collects memory access data, the model training submodule builds and trains machine learning models, and the data migration submodule performs data migration operations. The QoS control module collects device load information and adjusts the access request rate of compute nodes. The fault tolerance module creates redundant memory images and ensures data consistency and fault recovery through atomic operation protocols.

[0028] Example 2 This embodiment provides a specific implementation process for a cross-node heterogeneous memory pooling method based on the CXL protocol, such as... Figure 2 As shown, the specific implementation process is as follows: S1. Establish cross-node communication links, configure the FPGA memory controller, and organize access paths: S1.1. Use CXL links to connect compute nodes and heterogeneous memory resource pools, and configure the CXL switching unit with multi-logical device functionality and dynamic capacity device functionality: As the core network switching device, the CXL switching unit establishes stable connections with multiple compute nodes and heterogeneous memory resource pools via CXL links, forming a complete cross-node memory access architecture. The CXL switching unit supports the CXL 3.1 protocol, providing a low-latency memory access path and laying the foundation for cross-node memory sharing. Configuring the multi-logical device function of the CXL switching unit allows a single physical CXL switching unit to be divided into multiple independent logical devices, each of which can provide memory access services to different compute nodes independently, achieving logical partitioning and efficient reuse of physical resources. Simultaneously, enabling the dynamic capacity device function of the CXL switching unit allows it to flexibly adjust the memory capacity allocated to each compute node according to the real-time memory requirements of each node, meeting the dynamic memory capacity changes of compute nodes at different task stages and avoiding idle or insufficient memory resources.

[0029] S1.2. Based on the connection architecture formed by CXL links, deploy an FPGA-accelerated intelligent memory controller to optimize cross-node memory access paths through hardware-level logic: The system utilizes a connection architecture built upon the CXL link between compute nodes and a heterogeneous memory resource pool, deploying an FPGA-accelerated intelligent memory controller. This intelligent memory controller implements memory access optimization logic through FPGA hardware, directly optimizing cross-node memory access paths at the hardware level, reducing performance overhead from software intervention, and further lowering latency. The intelligent memory controller supports priority scheduling of memory access, assigning priorities to different memory access requests based on the importance of the compute tasks, ensuring that critical tasks receive priority response and processing. Simultaneously, a collaborative mechanism is established between the intelligent memory controller and the CXL switching unit, achieving seamless cooperation in data transmission and command interaction. The intelligent memory controller receives memory access requests forwarded by the CXL switching unit, optimizes them, and sends them to the heterogeneous memory resource pool. The response results are then fed back to the compute nodes through the CXL switching unit, improving the overall collaborative efficiency of memory access.

[0030] S1.3. Leveraging the connection between the CXL switching unit and the heterogeneous memory resource pool, enable hot-swapping and hot-adding capabilities for both: Leveraging the established stable connection between the CXL switching unit and the heterogeneous memory resource pool, hot-swapping and hot-adding capabilities are configured for all types of memory modules in both the CXL switching unit and the heterogeneous memory resource pool. Hot-swapping allows faulty or replaceable CXL switching unit modules and memory modules to be removed from the system during normal operation without interrupting overall system services, while simultaneously allowing new modules to be added, ensuring continuous system operation. Hot-adding supports adding new memory modules to the heterogeneous memory resource pool or new port modules to the CXL switching unit as memory demand increases during system operation. This enables dynamic expansion of hardware resources, flexibly adapting to changes in system load and improving system scalability and availability.

[0031] S2. Separate heterogeneous memory types, define storage functions, and establish a unified management mechanism: S2.1. Define the characteristics of DRAM, CXL memory, and HBM: Based on the hardware configuration of the heterogeneous memory resource pool, the memory is categorized and analyzed, clarifying the hardware characteristics of DRAM, CXL memory, and HBM. DRAM, as traditional local memory, features low access latency and high data transfer bandwidth, enabling rapid response to memory read / write requests from computing nodes. CXL memory, as extended memory, boasts large storage capacity and strong scalability, meeting the needs of large-capacity data storage. HBM, or High Bandwidth Memory, possesses extremely high bandwidth and low latency, belonging to the high-performance memory type, and can match the memory access requirements of high-performance computing scenarios. Clarifying the characteristics of these three types of memory provides a foundation for subsequent functional division and resource allocation.

[0032] S2.2. Based on the characteristics of various types of memory, define the storage function division of DRAM, CXL memory, and HBM: Based on the characteristics of DRAM, CXL memory, and HBM, the storage functions of the three types of memory are rationally assigned. DRAM is designated as the storage area for data accessed more frequently than a set threshold, specifically for storing data that requires frequent read and write operations during computation, fully leveraging its low latency and high bandwidth advantages to ensure fast access to frequently accessed data. CXL memory is designated as the storage area for data accessed less frequently than the set threshold and for large-capacity data, used to store data with lower access frequency but larger storage space requirements, utilizing its large capacity and scalability to improve the overall utilization of memory resources. HBM is designated as the storage area for high-performance computing data, specifically providing storage support for intensive computing tasks and high-performance computation tasks on computing nodes, matching the stringent requirements of high-performance computing tasks for memory bandwidth and latency, and ensuring the efficient execution of high-performance computing tasks.

[0033] S2.3. Establish a memory resource registration and monitoring mechanism according to the defined storage function division, record the usage status, remaining capacity and allocation of various types of memory, and form a resource management ledger: Based on the established division of labor among the three types of memory storage functions, a memory resource registration and monitoring mechanism covering the entire heterogeneous memory resource pool is established. This mechanism, through a monitoring module deployed in the system, collects real-time resource data from DRAM, CXL memory, and HBM, including the usage status of each type of memory (e.g., whether it is idle, occupied, or faulty), remaining capacity (i.e., the amount of currently unallocated memory space), and allocation status (e.g., allocated memory regions, the computing node to which the allocation was made, allocation time, and allocation purpose). This collected resource data is registered in the system and compiled into a standardized resource management ledger. The resource management ledger is updated periodically to ensure that the recorded information accurately reflects the real-time status of the heterogeneous memory resource pool, providing data support for memory resource scheduling, allocation, and optimization.

[0034] S2.4. Extract record information from the resource management ledger and synchronize the memory resource views of each computing node: Key information such as the usage status, remaining capacity, and allocation of various types of memory is extracted from the resource management ledger and synchronized to each compute node via a communication link built by the CXL switching unit. Upon receiving the synchronization information, each compute node updates its locally stored memory resource view, ensuring that all compute nodes have consistent information on the heterogeneous memory resource pool status. The memory resource views of each compute node are kept in real-time synchronized with the resource management ledger, enabling compute nodes to make decisions based on accurate and unified resource information when initiating memory access or allocation requests. This avoids memory access conflicts or unreasonable resource allocation caused by information asymmetry, providing a guarantee for centralized scheduling and sharing of cross-node memory resources.

[0035] S3. Identify data access frequency, migrate data to corresponding memory, and dynamically allocate memory resources: S3.1. Construct a machine learning model. The model includes an input layer, a feature extraction layer, a classification layer, and an output layer. The input layer receives memory access logs and read / write record data. The feature extraction layer extracts data access frequency, access interval, and access duration features through convolution and pooling operations. The classification layer uses a fully connected network to process the features. The output layer outputs the classification result. Based on memory access data recorded by a unified management mechanism, a machine learning model is constructed to distinguish data access frequency categories. This machine learning model adopts a hierarchical architecture design, including four core layers: input layer, feature extraction layer, classification layer, and output layer. Each layer is connected to the others through a data transmission channel to ensure orderly data processing. The core function of the input layer is to receive data, specifically memory access logs and read / write records recorded by a unified management mechanism. This data covers key information such as the time, address, and read / write type of each memory access, providing raw data support for model analysis. After receiving the raw data transmitted from the input layer, the feature extraction layer extracts features through convolution operations, uncovering hidden local correlation features in the data. Then, it performs dimensionality reduction processing on the extracted features through pooling operations, retaining key feature information, and finally extracting three core features: data access frequency, access interval, and access duration, providing a valid basis for subsequent classification. The classification layer adopts a fully connected network structure, receives the three core features output by the feature extraction layer, and performs nonlinear transformation and integration processing on the features through multi-layer neurons of the fully connected network to achieve in-depth feature analysis. The output layer is connected to the output of the classification layer, receives the processing results of the classification layer, and finally outputs the classification result of the data access frequency, that is, initially determining whether the data belongs to the type with an access frequency higher than a set threshold or a type with an access frequency lower than a set threshold.

[0036] In some embodiments, the convolution operation of the feature extraction layer uses a 3×3 convolution kernel, the pooling operation uses max pooling, the classification layer contains two fully connected layers, the first fully connected layer contains 64 neurons, the second fully connected layer contains 32 neurons, and the output layer contains 2 neurons, corresponding to the output of the two data access frequency types respectively.

[0037] S3.2. Collect memory access logs and read / write records within a time window, normalize the collected data, divide it into training, validation, and test sets, initialize the weight and bias parameters of the machine learning model, set the learning rate, number of iterations, and batch size hyperparameters, input the training set data into the constructed machine learning model, update the model parameters through the backpropagation algorithm, and iterate until the model's classification accuracy on the validation set reaches the preset standard. Time windows are divided at fixed intervals. Within each time window, memory access logs and read / write records from a unified management mechanism are collected to ensure that the collected data covers memory access patterns across different time periods, guaranteeing data comprehensiveness and timeliness. The collected raw data is normalized to map the numerical range of the data to a unified interval, eliminating dimensional differences between different dimensions of data and preventing interference with model training due to inconsistent data magnitudes, thus improving the stability and accuracy of model training. The normalized data is then divided into training, validation, and test sets according to a preset ratio. The training set is used for learning and optimizing model parameters, the validation set is used for adjusting model hyperparameters and preliminary evaluation of model performance, and the test set is used for validating the final model performance.

[0038] Initialize the weights and biases of the machine learning model. Weights are randomly initialized, with values ​​ranging from -0.01 to 0.01. Bias parameters are initialized to 0. Set the hyperparameters for model training, including the learning rate, number of iterations, and batch size. The learning rate controls the magnitude of each parameter update, the number of iterations sets the total number of training epochs, and the batch size sets the number of samples input to the model each time. Input the training set data into the built machine learning model in batches according to the batch size. The model extracts features from the input data, performs classification processing, and outputs prediction results. Calculate the loss value between the prediction results and the actual data type labels. Use the backpropagation algorithm to calculate the gradient of the loss value with respect to each weight and bias parameter along the model's hierarchy. Update the model's parameters based on the gradient information and the set learning rate. After each iteration of training, input the validation set data into the model and calculate the model's classification accuracy on the validation set. Repeat the above training process, continuously iterating and updating the model parameters until the model's classification accuracy on the validation set reaches the preset standard. Stop model training to obtain the trained machine learning model.

[0039] In some embodiments, the time window interval is set to 1 hour, the ratio of training set, validation set and test set is 7:2:1, the learning rate is set to 0.001, the number of iterations is set to 100 rounds, the batch size is set to 32, and the preset classification accuracy standard is 90%.

[0040] S3.3. Call the trained machine learning model to process the test set data, statistically analyze the distribution of access frequency and access interval, set an access frequency threshold, and use multi-dimensional features to determine data with access frequency higher than the set threshold and data with access frequency lower than the set threshold: The trained machine learning model is invoked, and the test set data is input into the model for processing. Based on the feature patterns learned during training, the model outputs a classification prediction result for the access frequency of the test set data. Based on the model's prediction results and the original access records in the test set data, the distribution of access frequency and access interval is statistically analyzed. The distribution characteristics of data with different access frequencies and access intervals are analyzed to determine the overall distribution range and concentration interval of data access frequency. Combining the statistically obtained distribution, a reasonable access frequency threshold is set, which serves as the critical standard for distinguishing data with different access frequencies. Based on the set access frequency threshold, and combined with multi-dimensional features such as data access interval and access duration, all memory access data is comprehensively judged, ultimately clearly distinguishing data with access frequencies higher than the set threshold and data with access frequencies lower than the set threshold, providing a clear basis for subsequent data migration operations.

[0041] In some embodiments, the statistically obtained data access frequency distribution is concentrated between 10 times / hour and 1000 times / hour, and the access interval distribution is concentrated between 1 second and 100 seconds. Based on this, the access frequency threshold is set to 200 times / hour. Data with an access frequency higher than 200 times / hour and an access interval less than 30 seconds is determined to be data with an access frequency higher than the set threshold, and data with an access frequency lower than 200 times / hour and an access interval greater than 30 seconds is determined to be data with an access frequency lower than the set threshold.

[0042] S3.4. Based on the storage function division and data judgment results, perform data migration operations, migrating data with access frequency higher than the set threshold, data with access frequency lower than the set threshold, and high-performance computing data to the corresponding memory: Based on the defined memory storage functions and data assessment results, the data migration operation is initiated. For data whose access frequency exceeds a set threshold, the data migration module moves it from its original storage location to DRAM, leveraging DRAM's low latency and high bandwidth to ensure fast access. For data whose access frequency is below the set threshold, it is migrated to CXL memory, fully utilizing CXL's large capacity and saving DRAM storage space. For high-performance computing data generated by high-performance computing tasks, it is migrated to HBM according to the storage function allocation, utilizing HBM's high bandwidth and low latency to meet the needs of high-performance computing. During the data migration process, data is transmitted via the CXL link to ensure stability and efficiency. Key information such as the source address, destination address, data volume, and migration time for each migration is recorded, providing a basis for subsequent migration status tracking and memory allocation updates.

[0043] S3.5. Collect the running status of computing node tasks, memory usage, and access request queue length after the data migration operation. Based on the collected node-related information, adjust the memory bandwidth allocation ratio and capacity scale, and update the memory allocation record: After the data migration operation is completed, the monitoring module in the system collects relevant operational information of each computing node, including the current task running status of the computing node (such as task execution progress, task type, task priority, etc.), memory utilization rate (i.e., the proportion of memory capacity used by the computing node to the total memory capacity allocated to that node), and access request queue length (i.e., the number of memory access requests currently waiting to be processed by the computing node). This collected node-related information is summarized and analyzed to determine the real-time memory bandwidth and memory capacity requirements of each computing node: computing nodes with busy task execution, high memory utilization rate, and long access request queue lengths indicate a high demand for memory resources; computing nodes with smooth task execution, low memory utilization rate, and short access request queue lengths indicate a low demand for memory resources. Based on the analysis results, the allocation ratio of memory bandwidth among different computing nodes is dynamically adjusted, increasing the memory bandwidth allocation to high-demand computing nodes and decreasing the memory bandwidth allocation to low-demand computing nodes; simultaneously, the available memory capacity of each computing node is adjusted, tilting memory capacity resources towards high-demand nodes to ensure that memory resources are concentrated on high-value tasks. Update the memory allocation records in the resource management ledger according to the adjusted memory bandwidth allocation ratio and capacity scale to ensure that the memory allocation records are consistent with the actual allocation.

[0044] S3.6. A two-level memory allocation strategy is adopted, combining historical task memory usage data, the current total amount of free memory in the system, and task expansion estimates to pre-allocate multiple large blocks of memory of fixed size. Each large block of memory is then divided into smaller blocks of memory of uniform size. When a small block of memory is released, the free status of adjacent memory blocks is checked, adjacent free memory blocks are merged, and the merged memory blocks are managed according to the system's memory request scale. During memory allocation, a two-level memory allocation strategy is employed to optimize the process. First, based on historical memory usage data from similar tasks, the current total amount of free memory in the system, and anticipated future task expansion, a reasonable pre-allocation size for large memory blocks is determined. Multiple fixed-size large memory blocks are pre-allocated during system initialization or when memory resources are sufficient. Each pre-allocated large memory block is further divided into multiple smaller memory blocks of uniform size, forming a small memory pool to meet the frequent small memory allocation needs of compute nodes. When a compute node requests a small memory block allocation, the corresponding number of small memory blocks are directly extracted from the corresponding small memory pool for allocation, avoiding the memory management overhead caused by frequent creation and release of small memory blocks. When a small memory block is released after use, the system automatically checks the status of adjacent memory blocks. If adjacent memory blocks are also idle, these adjacent idle small memory blocks are merged into a larger memory block. Based on the current memory request scale of the system, the merged memory blocks are managed flexibly: if the system currently has a large memory allocation requirement, the merged memory blocks are included in the large memory management scope to respond to large memory allocation requests; if the system currently has a primary need for small memory allocation, the merged memory blocks are retained as medium-sized memory blocks, or further divided into small memory blocks and included in the small memory pool management. In this way, memory fragmentation is reduced and the overall utilization of memory resources is improved.

[0045] S3.7. Based on the two-level memory allocation strategy, memory blocks are partitioned using an LRU-K strategy to maintain a memory block access history list, recording the access time, access count, and access interval for each memory block; the list data is updated periodically, invalid records are evicted, and an initial K value is set based on the access information recorded in the list; during the memory reclamation phase, the frequency of the last K accesses of each memory block is counted, and memory blocks with access frequencies below a set threshold are released first; changes in system load, memory utilization, and task access characteristics are monitored, and the K value is adjusted accordingly. Based on the various memory blocks created by the two-level memory allocation strategy, an LRU-K strategy is used to maintain a memory block access history list, recording the access activity of each memory block in its entirety. The information recorded in the memory block access history list includes the access time (i.e., the specific moment each access occurred), the number of accesses (i.e., the total number of times the memory block has been accessed since its allocation), and the access interval (i.e., the time difference between two consecutive accesses). The data in the memory block access history list is updated at fixed intervals, and invalid records exceeding the set statistical period are deleted to ensure that the information recorded in the list accurately reflects the recent access activity of the memory blocks. Based on the memory block access information recorded in the list, combined with the system memory size and the type of computing task, an initial K value for the LRU-K strategy is set. The K value is used to determine the range of memory block access frequencies for statistical analysis.

[0046] When the system needs to reclaim memory to release idle memory, based on the LRU-K strategy, it counts the K most recent access frequencies of each memory block, i.e., the number of times the memory block has been accessed in the K most recent memory access cycles. The counted K most recent access frequencies are compared with a set access frequency threshold. Memory blocks with access frequencies below the threshold are prioritized for reclamation, releasing the memory resources occupied by these blocks. This ensures that the memory reclamation process does not frequently reclaim frequently accessed memory blocks, reducing performance loss caused by unreasonable reclamation. Simultaneously, the system monitors changes in system load, memory utilization, and task access characteristics in real time: when system load increases, memory utilization rises, and task access characteristics become more frequent, the value of K is appropriately increased to extend the statistical range of memory block access frequencies, reducing the probability of frequently accessed memory blocks being reclaimed; when system load decreases, memory utilization drops, and task access characteristics level off, the value of K is appropriately decreased to shorten the statistical range of memory block access frequencies, improving the flexibility of memory reclamation and enabling the LRU-K strategy to dynamically adapt to the system's operating state and optimize memory reclamation effectiveness.

[0047] S3.8. Based on the memory resource view of each compute node, configure an independent virtual memory mapping table for each compute node to record the correspondence between local virtual addresses and remote physical addresses, mapping validity status, and access permissions; enable the cache coherency support function of the CXL protocol, establish an address mapping validity detection mechanism, and periodically verify the accuracy of the mapping relationship; update the mapping table according to the verification results and synchronize it to the corresponding compute node; compute nodes locate remote physical addresses and access remote memory data through the virtual memory mapping table. Based on the synchronized memory resource view of each compute node, an independent virtual memory mapping table is configured for each compute node. This mapping table is specifically used to record the correspondence between the compute node's local virtual addresses and remote physical addresses in the heterogeneous memory resource pool. The virtual memory mapping table records three core pieces of information in detail: the correspondence between local virtual addresses and remote physical addresses (i.e., the specific remote physical memory location corresponding to each local virtual address), the mapping validity status (i.e., whether the mapping relationship is in a valid state; if the mapping relationship becomes invalid due to memory reclamation, data migration, or other operations, it is marked as invalid in a timely manner), and access permissions (i.e., the access permissions that the compute node has for the memory region corresponding to the remote physical address, such as read-only permissions, read-write permissions, etc.).

[0048] Enable cache consistency support in the CXL protocol, treating remote memory in the heterogeneous memory resource pool as an extension of the compute node's local cache. Maintain consistency between the local cache and remote memory data through the CXL protocol's cache consistency mechanism, ensuring that compute nodes obtain accurate and up-to-date data when accessing remote memory, avoiding access errors caused by data inconsistency. Establish an address mapping validity detection mechanism, periodically verifying the mapping relationships in the virtual memory mapping table. Check if the remote physical address corresponding to the local virtual address exists, if data has been migrated, and if access permissions have changed, determining the validity of the mapping relationship. Update the virtual memory mapping table based on the verification results: invalid mapping relationships are marked as invalid and removed from the mapping table; mapping relationships where the remote physical address has changed due to data migration or other operations are updated with the new remote physical address; mapping relationships with changed access permissions are synchronously updated with access permission information. Synchronize the updated virtual memory mapping table to the corresponding compute nodes, ensuring that the mapping table information used by the compute nodes is always accurate and valid. When a compute node needs to access data in remote memory, it can quickly locate the corresponding remote physical address by querying the local virtual memory mapping table, and directly access the memory data corresponding to the remote physical address through the CXL link. This eliminates the need for data copying and transmission, enabling direct access to remote memory and reducing overhead and latency during data transmission.

[0049] S3.9. Embed service quality control logic in the CXL switching unit and intelligent memory controller. The detection module collects load information such as device link occupancy, processing pressure, and memory usage, encapsulates it into a device load field, and feeds it back to the compute nodes. Based on the feedback data from the device load field, a device load threshold range is set, and the memory access request rate of each compute node is adjusted according to the load, while retaining the request priority of preset priority tasks. A direct data transmission channel is established using the [CXL.io] (CXL.io) protocol, supporting asynchronous data transmission mode. Service quality control logic is embedded in the CXL switching unit and intelligent memory controller to build a comprehensive service quality control mechanism. A dedicated detection module collects device load information in real time, including the link occupancy rate of the CXL switching unit (the proportion of bandwidth currently used by the CXL link to the total bandwidth), the processing pressure of the intelligent memory controller (the proportion of access requests currently being processed by the intelligent memory controller to its maximum processing capacity), and the memory utilization rate of the heterogeneous memory resource pool (the proportion of used memory capacity to the total memory capacity). This collected load information is integrated and encapsulated into a device load field, which is fed back to each computing node at fixed intervals, enabling the computing nodes to monitor the current load status of the devices in real time.

[0050] Based on feedback data from the device load field, a device load threshold range is set, including an upper and lower load threshold. When the device load is detected to be higher than the upper load threshold, it indicates that the device is currently under high load. In this case, the memory access request rate of each compute node is reduced proportionally to decrease the number of memory access requests sent by the compute nodes, preventing increased response latency or service interruption due to excessive load. When the device load is detected to be lower than the lower load threshold, it indicates that the device has idle resources. In this case, the memory access request rate of each compute node is gradually increased to fully utilize the idle resources and improve memory access efficiency. Simultaneously, during the adjustment of access request rates, the request priority of preset priority tasks is preserved. For high-priority critical tasks, their memory access request rates are not reduced or only slightly adjusted to ensure the normal execution of critical tasks and achieve fair allocation and efficient utilization of memory resources.

[0051] By leveraging the direct memory access functionality of the CXL.io protocol, a direct data transfer channel is established. This channel enables direct data transfer between compute nodes and heterogeneous memory resource pools, eliminating the need for CPU intermediary processing. It also supports asynchronous data transfer mode, where compute nodes can continue executing other tasks immediately after initiating a data transfer request, without waiting for the transfer to complete. The data transfer process is handled automatically by the hardware, which returns a completion notification to the compute node upon completion. This data transfer method reduces CPU latency, lowers CPU load, and improves data transfer efficiency and overall system processing capacity.

[0052] S4. Define the scope of critical data, build redundant mirrors, and ensure data consistency and fault recovery: S4.1. Extract data classification information from memory allocation records, determine the key data range of core parameters, intermediate results, and configuration information for the computation task, and formulate a hierarchical redundancy storage strategy: Data classification information is extracted from memory allocation records in the resource management ledger, including the storage location, data type, and access frequency level of each type of data. Based on this data classification information and the characteristics of the computing task, the scope of critical data is defined. Critical data specifically includes core parameters of the computing task (such as key configuration parameters for task execution, core algorithm parameters, etc.), incomplete intermediate results of computation (such as data generated during task execution that requires further processing), and important configuration information (such as system operation configuration, node connection configuration, etc.). Based on the importance and access frequency of the critical data, a hierarchical redundancy storage strategy is formulated, dividing the critical data into different redundancy levels: for the most important and frequently accessed critical data, a dual redundancy storage strategy is adopted, creating two independent redundant mirrors; for moderately important critical data, a single redundancy storage strategy is adopted, creating one redundant mirror; for critical data with lower importance but still requiring security, a periodic redundancy storage strategy is adopted, creating redundant mirrors at fixed intervals to ensure the security and recoverability of the critical data.

[0053] S4.2. Based on the hierarchical redundancy storage strategy and the storage layout of the heterogeneous memory resource pool, create redundant memory mirrors of critical data in different physical storage areas: Based on the established tiered redundancy storage strategy and the storage layout of the heterogeneous memory resource pool, redundant memory images are created for critical data at different levels. When selecting the storage location for redundant images, the principle of physical isolation is followed, storing the original critical data and the redundant memory images in different physical storage areas of the heterogeneous memory resource pool. This ensures that if the original data storage area fails, the storage area containing the redundant memory images remains unaffected. For critical data employing a dual redundancy storage strategy, the two redundant memory images are stored in different types of memory (e.g., one in DRAM and the other in CXL memory) to further enhance the security of redundant data. For critical data employing a single redundancy storage strategy or a periodic redundancy storage strategy, the redundant memory images are stored in different physical memory modules than the original data. When creating redundant memory images, a data synchronization mechanism ensures consistency between the redundant memory images and the original data. When the original data is updated, the redundant memory images are updated synchronously, ensuring that the redundant memory images always remain consistent with the original data.

[0054] S4.3. Based on the redundant memory mirroring storage method, the CXL.mem protocol is extended to form an atomic operation protocol to perform sorting and mutual exclusion control on concurrent read and write requests from multiple nodes: Based on the redundant memory mirroring storage method and the requirement for concurrent access by multiple nodes, the CXL.mem protocol is extended to design a dedicated atomic operation protocol. This atomic operation protocol can effectively control memory read and write requests initiated concurrently by multiple nodes, ensuring that access operations on the same data by multiple nodes do not cause data conflicts or inconsistencies. The core functions of the atomic operation protocol include request ordering and mutual exclusion control: the request ordering function sorts multiple concurrent read and write requests according to preset rules (such as request initiation time, task priority, etc.) to form an ordered request queue, so that read and write requests are executed sequentially; the mutual exclusion control function sets an access lock for each data block. When a node is performing a read or write operation on a data block, it locks the data block, prohibiting other nodes from performing read or write operations on the data block at the same time. After the current node's read or write operation is completed, the access lock is released, allowing other nodes to access the data block. By combining request ordering and mutual exclusion control, data consistency during concurrent access by multiple nodes is guaranteed, avoiding data errors or data loss caused by concurrent access.

[0055] S4.4. Based on the communication link between the compute nodes and the heterogeneous memory resource pool, establish a node fault monitoring mechanism. When a node fault is detected, call the redundant memory image to migrate data to the normal node. Based on the existing CXL link communication architecture between compute nodes and the heterogeneous memory resource pool, a node fault monitoring mechanism is established. This mechanism uses heartbeat detection to monitor node faults. Each compute node sends a heartbeat signal to the CXL switching unit at a fixed period. The heartbeat signal contains the compute node's operating status information (such as CPU utilization, memory utilization, task execution status, etc.). The CXL switching unit receives the heartbeat signals from each compute node and monitors them in real time. If no heartbeat signal is received from a compute node within a preset time, or if the received heartbeat signal indicates that the compute node's operating status is abnormal, then the compute node is determined to have failed.

[0056] Upon detecting a node failure, a data recovery process is immediately triggered. Critical data associated with the failed node is locked using atomic operation protocols to prevent other nodes from reading or writing this data, thus preventing inconsistencies. A previously created redundant memory image of critical data is invoked, and the data in the redundant memory image is quickly migrated to a normally functioning standby node or other idle computing node via the CXL link. After the data migration is complete, the memory allocation record and virtual memory mapping table are updated, transferring the task-related data and access permissions of the original failed node to the normal node. The normal node then takes over the unfinished tasks of the failed node and continues subsequent computational operations, ensuring the continuous execution of computational tasks and preventing data loss or task interruption due to node failure, thus guaranteeing the stable operation of the entire system.

[0057] This embodiment achieves efficient pooling and management of heterogeneous memory resources across nodes through a complete technical solution. Firstly, a stable cross-node communication architecture is built using CXL switching units and CXL links. An FPGA-accelerated intelligent memory controller optimizes access paths, providing a solid foundation for cross-node memory resource sharing. Secondly, by classifying and functionally dividing heterogeneous memory resources, precise matching and efficient utilization of memory resources with different characteristics are achieved. Thirdly, machine learning models enable precise differentiation of data access frequencies, and a data migration mechanism ensures reasonable data layout. Fourthly, two-level memory allocation and LRU-K strategies effectively suppress memory fragmentation and improve memory resource utilization. Fifthly, low-latency direct access to remote memory is achieved through virtual memory mapping tables and the cache consistency support of the CXL protocol. Sixthly, redundant memory mirroring and extended atomic operation protocols ensure data consistency and fault recovery capabilities for concurrent access across multiple nodes. Finally, a service quality control mechanism ensures fair allocation and efficient scheduling of memory resources. The overall solution enables centralized and dynamic management of cross-node memory resources, effectively improving memory resource utilization and access efficiency, ensuring system stability, scalability, and data security, and providing strong support for the efficient execution of various computing tasks.

[0058] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A cross-node heterogeneous memory pooling method based on the CXL protocol, characterized in that, Includes the following steps: S1. Establish communication links between multiple computing nodes and heterogeneous memory resource pools through CXL switching units, deploy FPGA-accelerated intelligent memory controllers, optimize cross-node memory access paths, and configure hot-swapping and hot-adding functions. S2. Based on the hardware configuration of the heterogeneous memory resource pool, the heterogeneous memory resource pool is divided into three categories: DRAM, CXL memory and HBM. The storage functions of each type of memory are clarified, a unified management mechanism is established to record the resource status and allocation, and centralized scheduling and sharing of cross-node memory resources are realized. S3. Based on the memory access data recorded by the unified management mechanism, distinguish between data with access frequency higher than the set threshold and data with access frequency lower than the set threshold, migrate different types of data to the corresponding memory areas according to the storage function of each type of memory, and dynamically adjust memory bandwidth and capacity allocation according to the real-time task requirements of computing nodes. S4. Based on the data classification information in the memory allocation record, determine the range of key data, build a redundant memory image for the key data, extend the atomic operation protocol based on the CXL.mem protocol, perform data consistency control on concurrent access by multiple nodes, and establish a node fault monitoring and recovery mechanism.

2. The method according to claim 1, characterized in that, Step S1 includes: S1.

1. Use CXL links to connect computing nodes and heterogeneous memory resource pools, and configure the CXL switching unit with multi-logical device functions and dynamic capacity device functions; S1.

2. Based on the connection architecture formed by the CXL link, deploy an FPGA-accelerated intelligent memory controller to optimize cross-node memory access paths through hardware-level logic; S1.

3. By leveraging the connection between the CXL switching unit and the heterogeneous memory resource pool, hot-swapping and hot-adding functions are enabled for both.

3. The method according to claim 1, characterized in that, Step S2 includes: S2.

1. Define the characteristics of DRAM, CXL memory, and HBM; S2.

2. Based on the characteristics of various types of memory, define the storage function division of DRAM, CXL memory and HBM; S2.

3. According to the defined storage function division, establish a memory resource registration and monitoring mechanism to record the usage status, remaining capacity and allocation of various types of memory, and form a resource management ledger; S2.

4. Extract record information from the resource management ledger and synchronize the memory resource view of each computing node.

4. The method according to claim 1, characterized in that, The process of distinguishing data in step S3 includes: S3.

1. Construct a machine learning model. The model includes an input layer, a feature extraction layer, a classification layer, and an output layer. The input layer receives memory access logs and read / write record data. The feature extraction layer extracts data access frequency, access interval, and access duration features through convolution and pooling operations. The classification layer uses a fully connected network to process the features. The output layer outputs the classification results. S3.

2. Divide the time window to collect memory access logs and read / write records, normalize the collected data, divide the data into training set, validation set and test set, initialize the weight parameters and bias parameters of the machine learning model, set the learning rate, number of iterations and batch size hyperparameters, input the training set data into the constructed machine learning model, update the model parameters through the backpropagation algorithm, and iterate until the model's classification accuracy on the validation set reaches the preset standard. S3.

3. Call the trained machine learning model to process the test set data, statistically analyze the distribution of access frequency and access interval, set an access frequency threshold, and use multi-dimensional features to determine data with access frequency higher than the set threshold and data with access frequency lower than the set threshold.

5. The method according to claim 1, characterized in that, Step S3 also includes: S3.

4. Based on the division of storage functions and data judgment results, perform data migration operations to migrate data with access frequency higher than the set threshold, data with access frequency lower than the set threshold, and high-performance computing data to the corresponding memory. S3.

5. Collect the running status of computing node tasks, memory usage, and access request queue length after the data migration operation. Based on the collected node-related information, adjust the memory bandwidth allocation ratio and capacity scale, and update the memory allocation record.

6. The method according to claim 1, characterized in that, Step S4 includes: S4.

1. Extract data classification information from memory allocation records, determine the key data range of core parameters, intermediate results and configuration information of computing tasks, and formulate a hierarchical redundant storage strategy; S4.

2. Based on the hierarchical redundancy storage strategy and the storage layout of the heterogeneous memory resource pool, create redundant memory images of key data in different physical storage areas; S4.

3. Based on the storage method of redundant memory mirroring, the CXL.mem protocol is extended to form an atomic operation protocol to sort and mutually exclude concurrent read and write requests from multiple nodes; S4.

4. Based on the communication link between the computing node and the heterogeneous memory resource pool, a node fault monitoring mechanism is established. When a node fault is detected, redundant memory image data is called to migrate the data to the normal node.

7. The method according to claim 1, characterized in that, In step S3, a two-level memory allocation strategy is adopted, which combines historical task memory usage data, the current total amount of free memory in the system and the task expansion estimate to pre-allocate multiple large blocks of memory of fixed size, and divide each large block of memory into small blocks of memory of uniform size. When a small block of memory is released, the free status of adjacent memory blocks is detected, adjacent free memory blocks are merged, and the merged memory blocks are managed according to the system memory request scale.

8. The method according to claim 7, characterized in that, In step S3, based on the memory blocks divided by the two-level memory allocation strategy, the LRU-K strategy is used to maintain the memory block access history list, recording the access time, access count and access interval of each memory block; the list data is updated periodically, invalid records are eliminated, and the initial K value is set based on the access information recorded in the list; During the memory reclamation phase, the frequency of the last K accesses of each memory block is counted, and memory blocks with access frequencies lower than a set threshold are released first. Monitor changes in system load, memory usage, and task access characteristics, and adjust the K value accordingly.

9. The method according to claim 1, characterized in that, In step S3, based on the memory resource view of each computing node, an independent virtual memory mapping table is configured for each computing node to record the correspondence between local virtual addresses and remote physical addresses, mapping validity status, and access permissions; the cache consistency support function of the CXL protocol is enabled, an address mapping validity detection mechanism is established, and the accuracy of the mapping relationship is periodically verified; Update the mapping table based on the verification results and synchronize it to the corresponding computing nodes; Compute nodes locate remote physical addresses and access remote memory data through virtual memory mapping tables.

10. A cross-node heterogeneous memory pooling system based on the CXL protocol, used to execute the method according to any one of claims 1-9, characterized in that, It includes a heterogeneous memory resource pool, CXL switching unit, intelligent memory controller, dynamic management engine, operating system kernel module, cold and hot data tiering algorithm module, QoS control module, and fault tolerance module; The heterogeneous memory resource pool includes DRAM, CXL memory, and HBM. Each type of memory provides storage services according to its preset functional positioning. The CXL switching unit connects the computing nodes and the heterogeneous memory resource pool through the CXL link and is configured with multiple logical device functions, dynamic capacity device functions, and hot-swapping and hot-adding functions. The intelligent memory controller adopts an FPGA-accelerated design, optimizes the access path, and establishes an instruction interaction channel with the CXL switching unit; the dynamic management engine receives memory allocation data, migration status, and load information from each module and issues adjustment instructions; the operating system kernel module integrates the memory management engine to realize dynamic memory allocation and hot-plug related operations. The hot and cold data stratification algorithm module includes a data acquisition submodule, a model training submodule, and a data migration submodule. The data acquisition submodule collects memory access data, the model training submodule builds and trains machine learning models, and the data migration submodule performs data migration operations. The QoS control module collects device load information and adjusts the access request rate of computing nodes. The fault-tolerant module creates redundant memory images and ensures data consistency and fault recovery through atomic operation protocols.

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