Design method of memory computing integrated high-speed external interface of memory unit buffer

Abstract

The application relates to the technical field of integrated circuits and storage-computing integrated architecture, and particularly discloses a storage unit buffering storage-computing integrated high-speed external interface design method. The method deploys an event sensing logic unit in a storage unit buffer area, monitors data changes in real time, and triggers address-event representation data packet generation; high-speed transmission without clock driving is realized through an asynchronous handshake protocol; after the receiving end analyzes the data packet, the address information is written into an external unit, and a confirmation signal is returned to release the buffering resources. The application starts transmission only when data substantially changes through an event driving mechanism, reduces invalid communication overhead, eliminates the influence of clock skew, simplifies wiring complexity, and realizes the unification of high bandwidth, low delay and ultra-low power consumption while ensuring reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and in-memory computing architecture technology, specifically relating to a design method for a high-speed external interface for in-memory computing with a storage unit buffer. Background Technology

[0002] With the explosive growth in demand for artificial intelligence and large-scale data processing, in-memory computing architecture has become a research hotspot in high-performance computing and edge intelligence due to its ability to overcome the memory wall problem inherent in the von Neumann architecture, improving computing efficiency and reducing energy consumption. By integrating computing logic within the storage array, in-memory computing technology enables in-situ fusion of data processing and storage, providing underlying hardware support for the efficient deployment of deep neural networks. As microelectronic systems evolve towards higher integration and lower power consumption, the overall performance of in-memory computing chips depends not only on the improvement of internal computing power but also on efficient and stable data interaction with the external environment.

[0003] The high-speed external interface design with memory cell buffers is a crucial step in enabling information exchange between the in-memory computing array and external systems. This high-speed external interface, by constructing a buffer mechanism between the physical link and the memory core, coordinates the speed difference between the internal high-parallel computing flow and the external serial transmission link, aiming to ensure the real-time performance of instruction issuance and computation result feedback. Efficient interface protocols and circuit structures ensure accurate data routing within the complex chip bus architecture, maintaining the overall operating efficiency and throughput of the in-memory computing system.

[0004] Current interface designs generally follow traditional clock-driven patterns. Even when processing highly sparse and redundant data, high-frequency read and write operations must be maintained, resulting in a high proportion of invalid data transmission in bus energy consumption and limiting the overall energy efficiency of in-memory computing systems. In large-scale array layouts, the complexity of the global clock distribution network increases exponentially with scale. The resulting clock skew and synchronization overhead not only occupy a large amount of chip area but also limit the physical bandwidth of data transmission. Traditional linear data flow representation methods lack the ability to adaptively capture dynamic computing states, making it difficult to implement on-demand driving based on the data change characteristics within the storage unit. This results in insufficient flexibility and response latency when dealing with non-stationary data flows. Therefore, a storage unit-buffered, high-speed external interface design method for in-memory computing is desired. Summary of the Invention

[0005] The purpose of this invention is to provide a design method for a high-speed external interface for in-memory computing with storage unit buffer, which can solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a design method for a high-speed external interface for in-memory computing with storage unit buffering, comprising the following specific steps:

[0007] Step 1: Deploy event-aware logic units in the storage unit buffer of the in-memory computing architecture to monitor the changes in the data state within the buffer in real time and determine whether the changes exceed a preset threshold.

[0008] Step 2: When the change exceeds a preset threshold, the address-event representation generation mechanism is triggered to bind the physical address of the current storage unit with the corresponding data event type to form a structured address-event representation data packet;

[0009] Step 3: The asynchronous handshake protocol is used to control the transmission process of the address-event characterization data packet. The clockless transmission of the data packet on the high-speed external interface is completed through the interaction of request and response signals.

[0010] Step 4: Configure the event decoding and reconstruction module at the receiving end to parse the received address-event representation data packet and write the event data into the corresponding external storage or processing unit according to the address information;

[0011] Step 5: After the data transmission is completed, the receiving end returns an acknowledgment signal to the sending end to release local buffer resources and prepare for the next event-driven transmission.

[0012] Preferably, the event-aware logic unit is constructed based on an integral-issuance mechanism, which includes a dynamic accumulator for accumulating and summing the data differences output by the storage unit over multiple consecutive periods. When the accumulation result reaches a preset threshold, a valid event trigger signal is generated.

[0013] Preferably, the address-event representation data packet adopts a fixed-length field structure, including an address identifier field, an event type field, and a check field. The address identifier field is used to uniquely identify the storage unit location where the event occurred, and the event type field is used to distinguish different event categories such as data update, calculation completion, or abnormal interruption.

[0014] Preferably, the asynchronous handshake protocol is implemented using a four-phase dual-track encoding method, which transmits the status information of logic zero and logic one through two independent data lines, and completes the synchronous interaction of request and response with two control lines, ensuring that the integrity and timing consistency of data transmission can still be maintained even in the absence of a global clock.

[0015] Preferably, the event decoding and reconstruction module has a built-in address mapping table, which can quickly locate the target external storage area based on the received address identifier field, and convert the operation instructions indicated by the event type field into standard read and write commands to perform corresponding data writing or status update operations.

[0016] Preferably, the generation of the acknowledgment signal depends on the receiving end's verification result of the address-event characterization data packet integrity. The acknowledgment signal is only sent to the sending end after the verification is successful and the data has been correctly written, in order to prevent the buffer resources from being released accidentally due to transmission errors.

[0017] Preferably, the storage unit buffer is divided into multiple independent sub-regions, each sub-region is equipped with a dedicated event-aware logic unit and a local asynchronous transmission channel, so that multiple events can be detected and transmitted in parallel, thereby improving the overall interface throughput.

[0018] Preferably, the preset threshold can be dynamically adjusted according to the application scenario. In high-precision calculation mode, it can be set to a smaller value to improve event sensitivity, while in low-power operation mode, it can be set to a larger value to reduce the frequency of invalid event triggering.

[0019] Preferably, the high-speed external interface supports a multi-level cascaded topology, allowing multiple in-memory computing chips to be connected sequentially via an event-driven link. The event output port of the previous-level chip can be directly used as the event input port of the next-level chip, thereby realizing efficient event flow transmission in a large-scale system.

[0020] Preferably, the event type field includes a priority flag to distinguish between critical events and ordinary events. The receiving end allocates different processing queues and response delay limits to events of different priorities based on the flag, ensuring the real-time requirements of critical tasks.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. By introducing an event-driven mechanism, this invention completely eliminates the energy-consuming mode of relying on a high-frequency global clock for continuous data refresh in traditional interfaces. The transmission process is only started when the data in the storage unit buffer changes substantially, reducing the invalid communication overhead caused by sparse data or zero-value activation, and achieving the energy efficiency optimization goal of zero computation and zero transmission.

[0023] 2. The asynchronous handshake protocol replaces the global clock distribution network, eliminating the constraint of clock skew on the performance of high-speed interfaces, greatly simplifying the complexity of physical layout and routing, and saving valuable chip area resources.

[0024] 3. The address-event-based data encapsulation method endows the interface with adaptive awareness of dynamic computing states, enabling it to flexibly respond to sudden events under non-stationary data flows, thus improving the real-time performance and robustness of in-memory computing systems in complex intelligent application scenarios. The entire design scheme, without sacrificing transmission reliability, balances the three core indicators of high bandwidth, low latency, and ultra-low power consumption, providing interconnect technology support for next-generation high-performance edge intelligent chips. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the overall technical solution architecture according to the present invention;

[0026] Figure 2 This is a schematic diagram of the core principle framework of the event-aware logic unit-based integration-issuance mechanism in the present invention, which accumulates data differences in storage units to trigger the generation of address-event representations.

[0027] Figure 3 This is a flowchart illustrating the logic of the asynchronous handshake protocol using four-phase dual-track coding according to the present invention, which achieves clock-free transmission through the interaction of request and response signals.

[0028] Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow between the sending end storage unit buffer and the receiving end event decoding and reconstruction module according to the present invention;

[0029] Figure 5 This is a logical flowchart illustrating the process of allocating processing queues for different events based on an address mapping table and priority flag bits, according to the present invention, to achieve efficient event flow transmission in a multi-level cascaded topology. Detailed Implementation

[0030] Example 1: Please refer to the appendix Figure 1 To be continued Figure 5 To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0031] In the hardware implementation of in-memory computing architecture, to achieve efficient interconnection between the storage unit buffer and the external system, this embodiment provides a design method for a high-speed external interface for in-memory computing with a storage unit buffer. This method deeply integrates the pulse coding mechanism from neuroscience with the address-event representation technology in asynchronous circuit design, replacing the traditional clock-driven data transmission mode with an event-driven approach.

[0032] In the above design method, step 1 involves deploying an event-aware logic unit in the storage unit buffer of the in-memory computing architecture to monitor the changes in the data state within the buffer in real time and determine whether the changes exceed a preset threshold.

[0033] Specifically, the storage unit buffer is not managed as a single unit, but is divided into multiple independent sub-regions. Each independent sub-region integrates a dedicated event-aware logic unit. This distributed architecture ensures the parallelization of the sensing process. The storage space of each sub-region can be set to a fixed size according to hardware specifications, for example, each sub-region contains 1024 storage bits. The event-aware logic unit is built based on an integration-issuance mechanism. In terms of hardware implementation, it integrates a high-precision dynamic accumulator and a differential comparator.

[0034] Within each sampling period, the event-aware logic unit first acquires the output data of the storage unit at the current moment and performs a difference operation between it and the reference data saved at the previous sampling moment. The sampling period here is not defined by a global clock, but is driven by a short pulse sequence generated by a local self-oscillating circuit. The resulting difference represents the instantaneous change of the data in the time dimension. The dynamic accumulator accumulates and sums these data differences generated over multiple consecutive periods. When the accumulated result, i.e., the cumulative change in the data state, reaches or exceeds a preset threshold, the output state of the differential comparator flips, generating a valid time trigger signal.

[0035] The preset threshold is a configurable parameter stored in a configuration register within the sensing unit. This preset threshold can be dynamically adjusted according to different application requirements. In modes requiring high-precision calculations, the system sets the preset threshold to a smaller value. Even slight fluctuations in the data stored in the unit will be detected by the event-aware logic unit and trigger subsequent transmissions, ensuring the sensitivity and accuracy of the calculation results. In low-power operation mode, the system adjusts the preset threshold to a larger value through the configuration interface. This filters out most data changes caused by noise or unimportant computational fluctuations, initiating interface transmission only when data is updated, reducing unnecessary communication overhead and lowering the system's dynamic power consumption.

[0036] In the above design method, in step 2, when the change exceeds a preset threshold, the address-event representation generation mechanism is triggered to bind the physical address of the current storage unit with the corresponding data event type to form a structured address-event representation data packet.

[0037] Specifically, once the event trigger signal generated in step 1 is captured, the encoding logic within the interface immediately begins. The address-event representation data packet employs a rigorous fixed-length field structure to ensure alignment and parsing efficiency on the asynchronous transmission link. The data packet specifically includes an address identifier field, an event type field, a priority identifier bit, and a checksum field.

[0038] The address identifier field uniquely identifies the physical location of the storage unit where data changes have occurred within the entire in-memory array. To support large-scale in-memory computing chips, the width of this address identifier field is designed to cover millions of storage units. Using a hierarchical encoding method, the address identifier field includes row index, column index, and subarray number information.

[0039] The event type field is a multi-bit data segment used to distinguish the specific trigger for the current transmission. In this embodiment, the event type is further subdivided into data update events, computation completion events, abnormal interruption events, and resource warning events. For example, if the accumulated result inside the storage unit is caused by a normal storage and computation logic update, it is marked as a data update type; if the change represents the completion of loading a set of neural network weights, it is marked as a computation completion type.

[0040] The priority flag is used to distinguish between critical events and ordinary events. In complex task flows, certain events with extremely high real-time requirements (such as system resets or emergency control commands) need to be processed with priority. When parsing data packets, the receiving end will prioritize identifying this flag. If the flag indicates a high priority, the data packet will be sent to the receiving end's fast processing queue and will receive a minimum response latency guarantee.

[0041] The check field typically employs cyclic redundancy check (CRC) bits or parity check bits to monitor the integrity of data packets in real time during transmission. During encapsulation, the encoding logic calculates a checksum based on the contents of the address identifier field and the event type field, following a preset linear mapping rule, and appends it to the end of the data packet.

[0042] In the above design method, step 3 uses an asynchronous handshake protocol to control the transmission process of the address-event characterization data packet, and completes the clockless transmission of the data packet on the high-speed external interface through the interaction of request signals and response signals.

[0043] Specifically, the asynchronous handshake protocol in this embodiment is implemented using a four-phase dual-track encoding method. Dual-track encoding means that for each logic bit, two independent physical data lines are used for transmission: a logic zero transmission line and a logic one transmission line. This encoding method ensures that the data itself contains timing information. When the logic zero transmission line is high and the logic one transmission line is low, it represents the transmission of Boolean logic zero; conversely, when the logic one transmission line is high and the logic zero transmission line is low, it represents the transmission of Boolean logic one. If both lines are simultaneously low, it indicates that the bus is in an idle or intermittent state. Simultaneous high levels on both lines are strictly prohibited and are considered an illegal error state.

[0044] The four-phase handshake protocol's operation comprises four distinct phases: In the first phase, the sending end loads the prepared address-event representation data packet onto the dual-track data lines and pulls the request signal line high to send a transmission request to the receiving end. Due to the use of dual-track encoding, the receiving end can confirm the validity of the data by monitoring the state of the data lines. In the second phase, after detecting a high-level request signal and that the signal on the data lines has stabilized, the receiving end begins reading and processing the data packet. After processing, the receiving end pulls the acknowledgment signal line high to send feedback to the sending end indicating successful reception. In the third phase, after receiving a high-level acknowledgment signal, the sending end pulls the request signal line low and restores the dual-track data lines to an all-zero idle state, marking the end of the current data transmission process. In the fourth phase, after detecting that the request signal has gone low, the receiving end also pulls the acknowledgment signal line low, restoring the entire interface circuit to its initial listening state, preparing for the next handshake.

[0045] This global clock-free design completely eliminates the limitation on transmission rate caused by clock skew in large-scale circuits. The signal transmission speed depends only on the physical delay of the wires and the toggling speed of the logic gates, achieving extremely high instantaneous bandwidth.

[0046] In the above design method, step 4 involves configuring an event decoding and reconstruction module at the receiving end to parse the received address-event representation data packet and write the event data into the corresponding external storage or processing unit based on the address information.

[0047] Specifically, the event decoding and reconstruction module incorporates a high-performance address mapping table. This mapping table is implemented using content-addressable memory or a high-speed hash table structure, recording the correspondence between the addresses of internal storage units of the in-memory computing chip and external storage areas (such as system memory or specific register groups).

[0048] Once the receiving end receives the complete address-event representation data packet via the asynchronous handshake protocol, the decoding logic first extracts the address identifier field. By consulting the address mapping table, the module can locate the target external storage location corresponding to the event at extremely high speed. The decoding logic then parses the event type field. If the event type indicates a standard data update, the reconstruction module converts the calculation results (either attached to the data packet or obtained through specific pulse density conversion) into a standard read / write command format. This read / write command format conforms to an external bus protocol (such as an advanced microcontroller bus architecture protocol). If the event type contains a priority flag, the receiving end's scheduling logic distributes the parsed operation tasks to different levels of processing queues. Higher priority queues have higher arbitration privileges and can preempt bus resources to ensure the real-time performance of critical tasks.

[0049] The high-speed external interface also supports multi-level cascaded topologies. In a typical cascaded scenario, multiple in-memory computing chips are connected sequentially via event-driven links. The event output port of the preceding chip directly serves as the event input port of the following chip. In this structure, the event decoding and reconstruction module also undertakes routing and forwarding functions. If the received address identifier field indicates that the destination address of the event is not within the external region governed by this chip, the reconstruction module will automatically forward the data packet to the next chip as is, achieving efficient event flow transmission in large-scale distributed systems.

[0050] In the above design method, in step 5, after the data transmission is completed, the receiving end returns an acknowledgment signal to the sending end to release local buffer resources and prepare for the next event-driven transmission.

[0051] Specifically, the generation of the acknowledgment signal has strict logical triggering conditions. After completing the address resolution and data writing operations, the receiving end will perform integrity verification on the received data packet again. Only when the verification result shows that no errors occurred during data transmission, and the external storage or processing unit has returned a successful write acknowledgment signal, will the receiving end send the final acknowledgment signal to the sending end.

[0052] At the sending end, the storage unit buffer is designed with a temporary storage mechanism. During the data transmission in step 3, to prevent data loss, the triggered storage unit data is not immediately overwritten or cleared, but is retained in the local buffer. Only when the sending end receives an acknowledgment signal from the receiving end will the relevant local buffer resources be officially released and marked as overwriteable.

[0053] This closed-loop feedback-based resource release mechanism effectively prevents the accidental release of buffer resources due to sudden errors or congestion in asynchronous transmission. If the sending end does not receive an acknowledgment signal within a preset time threshold, it will trigger a retransmission mechanism to restart the asynchronous handshake process in step 3, thereby improving the robustness of the entire interface system.

[0054] To further enhance the interface's throughput, each independent sub-region of the storage unit buffer is equipped with a local asynchronous transmission channel. This means that multiple sub-regions can independently handshake and interact with the receiving end simultaneously. At the hardware level, by introducing multiplexers or arbitration logic, the system can handle multiple concurrent event streams simultaneously, avoiding the blocking risk of a single global channel under high-concurrency data loads.

[0055] In practical engineering implementation, the integration-issuance mechanism of the event-aware logic unit can also be perfectly integrated with analog in-memory computing circuits. When the memory unit uses current-mode or voltage-mode calculations, the dynamic accumulator can be implemented as a capacitor integrator. The voltage across the capacitor rises as the calculation results accumulate, and when the voltage reaches a reference level (i.e., a preset threshold), the comparator generates a pulse. This design directly encodes the computational intensity in the analog domain into the pulse frequency or interval in the digital domain, achieving natural analog-to-digital conversion and interface encapsulation integration.

[0056] The address-event representation interface not only responds to static data changes but also possesses the ability to perceive dynamic computational trends. By adjusting the accumulator's attenuation coefficient (i.e., subtracting a certain percentage from the accumulated value in each micro-cycle), it can sensitively capture high-frequency burst events while effectively suppressing low-frequency background noise. This characteristic demonstrates energy efficiency advantages in AI applications with highly sparsity and dynamic characteristics, such as visual processing and speech recognition.

[0057] This embodiment also relates to a flow control strategy under a multi-chip cascaded topology. In the event type field, the system reserves a congestion indicator bit. When the receiving end's processing queue is close to full, it embeds a congestion flag in the returned acknowledgment or confirmation signal. After receiving this congestion flag, the sending end automatically and temporarily increases the preset threshold in step 1. In this way, the sending end can adaptively reduce the event triggering frequency, alleviate network congestion, and prevent data packet overflow.

[0058] Considering the physical design of large-scale integrated circuits, this invention employs an asynchronous circuit design, eliminating the need to construct a large clock distribution network within the interface module. This not only saves significant metal wiring resources but also substantially reduces static power consumption caused by clock tree flipping. During the physical placement and routing phase, since strict clock convergence constraints are not required, the design cycle is shortened, and the chip area utilization is significantly improved.

[0059] The event decoding and reconstruction module at the receiving end also includes a timing recalibration unit. Although the transmission process is asynchronous, to ensure compatibility with traditional synchronous external processors, the reconstruction module can realign the received asynchronous event stream according to a predetermined timing template, outputting a standard data stream that meets the requirements of the synchronous clock domain. This asynchronous-to-synchronous conversion logic enables the high-speed interface of this invention to seamlessly integrate into the existing high-performance computing ecosystem.

[0060] This embodiment constructs a complete high-speed external interface solution for in-memory computing by deploying intelligent event-aware logic at the storage unit buffer, combined with an efficient address-event representation encapsulation method and a highly reliable asynchronous handshake protocol. This solution ensures real-time data transmission while achieving a high degree of decoupling between transmission energy consumption and data validity.

[0061] Example 2: Based on Example 1, this example further refines the specific implementation of the event-aware logic unit when processing nonlinear data streams, and describes in detail the routing logic of address-event representation data packets in complex topologies.

[0062] In step 1, to address the complexity of data fluctuations in certain application scenarios, the event-aware logic unit introduces a bidirectional integration mechanism. The dynamic accumulator is designed to handle both positive and negative increments simultaneously. When the data output by the storage unit changes positively relative to the previous period, the accumulator performs addition; when the change is negative, the accumulator performs subtraction.

[0063] In this embodiment, the preset threshold is set as a numerical range, including an upper threshold and a lower threshold. An event trigger signal is generated when the accumulator value exceeds the upper threshold or the lower threshold. This design allows the interface to accurately capture the bidirectional evolution trend of the signal, which is of great significance for applications that need to monitor the range of signal fluctuations.

[0064] In step 2, a data compression mapping layer is added to the construction process of the address-event representation data packet. To further reduce the size of the data packet and improve transmission efficiency, the address identifier field employs incremental encoding technology. In the same continuous event stream, if the addresses of consecutively triggered memory cells have high locality, the encoder only records the starting address, and subsequent data packets only contain the offset relative to the starting address. This approach can reduce the average width of the address field when handling large-scale continuous array accesses.

[0065] In this embodiment, the event type field is given richer meanings. In addition to basic data operations, performance monitoring events and security audit events are added. When the interface detects an abnormally high event triggering frequency in a certain area, exceeding a preset security frequency threshold, a security audit event will be generated to alert the receiving end to possible abnormal access behavior or hardware failure.

[0066] In the above design method, the asynchronous handshake protocol in step 3 further introduces an adaptive delay matching mechanism. Because signal transmission delays differ at different physical locations within the chip, the asynchronous logic circuit can automatically adjust the hold time of the request signal based on the return speed of the response signal. In long-distance cascaded links, this mechanism ensures the integrity of the handshake signal and prevents signal integrity problems caused by wire resistance and capacitance.

[0067] In step 4, the address mapping table of the event decoding and reconstruction module supports dynamic updates. During system operation, external processors can modify the contents of the mapping table through a dedicated configuration channel. This means that the system can dynamically redirect data from storage units in different regions to different processing resources based on the current load, thus achieving virtualized management of storage resources.

[0068] For multi-level cascaded topologies, this embodiment employs a geographic coordinate-based routing algorithm. Each address-event representation data packet implicitly contains the coordinates of a target chip. When a data packet arrives at the interface of an intermediate chip, the routing logic compares these coordinates with the coordinates of the current chip. If they do not match, the routing logic selects the optimal direction (such as horizontal or vertical) to forward the data packet based on the coordinate difference. This two-dimensional grid-like cascading method enhances the system's scalability, supporting the construction of ultra-large-scale computing clusters containing hundreds or thousands of in-memory computing units.

[0069] In the above design method, the acknowledgment signal in step 5 also includes transmission quality feedback information. After successfully receiving data, the receiving end calculates a transmission quality score based on the average delay and the number of error correction attempts during transmission. This transmission quality score is fed back to the sending end via the acknowledgment signal. Based on this score, the sending end can dynamically adjust the drive current intensity or handshake frequency in step 3. For example, when a degradation in transmission quality is detected, the sending end increases the aspect ratio of the output drive transistor to enhance the signal's anti-interference capability and ensure data transmission reliability in complex electromagnetic environments.

[0070] The storage unit buffer in this embodiment employs a hierarchical management strategy. In addition to the local buffers provided in each sub-region, a large-capacity global buffer pool is also set up at the interface. When local asynchronous transmission channels become congested, address-event representation data packets to be sent can be temporarily stored in the global buffer pool and asynchronously overflowed using idle channels. This hierarchical buffer structure effectively smooths burst traffic and improves the interface's peak processing capacity under extreme load conditions.

[0071] To further optimize energy efficiency, the event-aware logic unit also integrates zero-value suppression logic. In artificial intelligence applications, a large number of calculation results are 0 or close to 0. This embodiment sets specific zero-value judgment logic in step 1, directly blocking the event trigger signal when the data fluctuates within a small range near zero. This zero-value non-triggering strategy, combined with the action-free and energy-efficient characteristics of asynchronous interfaces, enables the in-memory computing system to achieve near-theoretical energy efficiency performance when processing sparse neural networks.

[0072] At the physical implementation level, this embodiment recommends using polycrystalline silicon nanowires or advanced finned transistor (FMT) technology to construct the asynchronous handshake control circuit. Utilizing the high switching speed and low leakage current characteristics of these advanced processes, the control overhead of the asynchronous logic can be further reduced. In terms of routing, address lines and data lines employ differential routing, coupled with appropriate shielding layers, to reduce electromagnetic radiation generated by high-speed data transmission and improve immunity to external power fluctuations.

[0073] The event decoding and reconstruction module at the receiving end also features data aggregation capabilities. In certain scenarios, multiple fragmented events can be aggregated into a large data block for batch writing to external storage. The reconstruction module monitors the status of the receive queue, and when it detects multiple small update events targeting consecutive addresses, it automatically merges these events and initiates a burst write operation. This strategy significantly reduces the frequency of external bus accesses, improving the overall I / O efficiency of the system.

[0074] In summary, Example 2 further enhances the flexibility, reliability, and scalability of the in-memory computing high-speed external interface in complex application scenarios by introducing advanced features such as bidirectional integral sensing, incremental address coding, adaptive latency matching, and hierarchical buffer routing.

[0075] Example 3: This example focuses on describing the application of the storage unit buffer in a high-speed external interface design method for in-memory computing in a heterogeneous computing environment, as well as the high reliability guarantee mechanism for extreme environments.

[0076] In step 1, for certain applications with extremely high time sensitivity, the event-aware logic unit adds a rate-aware component. The accumulator not only accumulates the absolute differences in the data but also calculates the rate of data change, i.e., an approximation of the first derivative. When a drastic change occurs in the data, even if the total accumulated amount has not yet reached a preset threshold, the rate-aware component will force the event generation. This predictive mechanism ensures the system's rapid response to sudden abnormal states; for example, in autonomous driving obstacle avoidance calculations, this mechanism can detect dangerous changes ahead before conventional logic.

[0077] In step 2, to enhance data transmission security, a lightweight hardware-level encryption mechanism is introduced during the generation of the address-event representation data packet. The encoding logic performs an XOR operation on the address identifier field and the event type field based on a dynamically generated pseudo-random sequence. Only the receiving end holding the corresponding decryption key can correctly parse the data packet. This mechanism effectively protects the computational privacy and data structure security within the in-memory array without increasing transmission latency.

[0078] Regarding step 3, this embodiment proposes a redundant dual-track handshake protocol. Two sets of parallel asynchronous handshake logic are deployed on the critical data link. When one link detects physical damage or severe level jitter, the system can instantly switch to the backup link and use an acknowledgment signal to notify the sending end for fault diagnosis. This redundancy design is crucial for high-reliability industrial and aerospace applications.

[0079] In step 4, the decoding and reconstruction module at the receiving end integrates an online performance evaluation unit. This online performance evaluation unit statistically analyzes the frequency distribution of events triggered in each storage sub-region in real time. By analyzing this address-event hotspot map, the system firmware can identify computational load imbalances in the in-memory array and adjust task allocation strategies accordingly. For example, overly computationally intensive tasks can be migrated to less demanding storage regions to avoid localized overheating and extend the overall lifespan of the chip.

[0080] In step 5, the return link of the acknowledgment signal is given reverse control functionality. Besides acknowledging receipt, the receiver can use this return link to send simple flow control commands, such as pausing transmission, reducing precision, or entering standby. This bidirectional asynchronous interaction mechanism enables the sender and receiver to form an organic dynamic game balance, ensuring an optimal solution is found between changing computational demands and limited resource supply.

[0081] This embodiment also details the deadlock prevention mechanism in a multi-level cascaded system. Since asynchronous transmission lacks global synchronization, uncontrolled circular cascading can lead to packets being transmitted indefinitely within a loop. This embodiment adds a lifecycle field to the address-event representation of the data packet. The value of this field is decremented by 1 each time the packet passes through a different chip level. When the value reaches zero, the packet is forcibly dropped, triggering an abnormal interrupt. This approach eliminates deadlock and routing loops at the protocol level.

[0082] For the physical interface portion of the high-speed external interface, this embodiment recommends using low-power differential signaling technology. This technology utilizes two complementary voltage signals to transmit one bit of data, providing extremely strong immunity to common-mode interference. On the physical cable of the asynchronous handshake signal, by adding matching resistors and capacitor compensation circuits, the rising and falling edge slopes of the signal are further optimized, enabling the maintenance of an event stream transmission with an extremely low bit error rate even on board-level interconnects several centimeters long.

[0083] Regarding the structural optimization of the storage unit buffer, this embodiment proposes a three-dimensional stacked caching scheme. Event-aware logic units and asynchronous transmission channels are deployed in a dedicated logic layer, while the storage unit array is deployed in the storage layer. The two layers are vertically interconnected via through-silicon vias (TSVs). This vertical architecture significantly shortens the physical distance between the sensing logic and the storage bits, reducing sensing latency and power consumption in step 1, while also enabling higher-density in-memory computing integration.

[0084] In the event decoding and reconstruction module, to address the varying data bit width requirements of heterogeneous processors, this embodiment introduces a flexible bit width adapter. The adapter can automatically split or merge fixed-length address-event representation data packets into outputs of different bit widths based on the configuration of the receiving processing unit. For example, for 8-bit microcontrollers and 64-bit general-purpose processors, the adapter automatically adjusts the alignment of the reconstructed data, ensuring broad interface compatibility.

[0085] Finally, to address the testing requirements of large-scale systems, the interface design method also includes a built-in self-test subsystem. During system startup or idle phases, this built-in self-test subsystem can simulate and generate pseudo-random event sequences and inject them into the asynchronous transmission link. By comparing the parsing results at the receiving end with the original simulated sequence, logical errors or physical overhead in the link can be quickly located, improving the maintainability of the system.

[0086] In summary, by introducing mechanisms such as rate awareness, hardware encryption, redundant handshake, online performance evaluation, and deadlock prevention, Example 3 pushes the design of in-memory computing high-speed external interfaces to a higher level of security and a wider range of applications.

[0087] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for designing a high-speed external interface for in-memory computing with a storage unit buffer, characterized in that, Includes the following steps: An event-aware logic unit is deployed in the storage unit buffer of the in-memory computing architecture. The event-aware logic unit is used to monitor the amount of data state changes in the storage units within the storage unit buffer in real time and determine whether the amount of data state changes exceeds a preset threshold. When the amount of data state change exceeds a preset threshold, the address and event representation generation mechanism is triggered, which binds the physical address of the current storage unit with the corresponding data event type and encapsulates it into a structured address and event representation data packet. An asynchronous handshake protocol is used to control the transmission process of the address and event representation data packets. The clockless transmission of the address and event representation data packets on the high-speed external interface is completed through the interaction of request and response signals. The receiving end is configured with an event decoding and reconstruction module to parse the received address and event representation data packet, and write the event data into the corresponding external storage unit or processing unit according to the physical address. After the data transmission is completed, the receiving end returns an acknowledgment signal to the sending end, and the sending end releases its local buffer resources after receiving the acknowledgment signal. The step of deploying event-aware logic units in the storage unit buffer of the in-memory computing architecture includes: The storage unit buffer is divided into multiple independent sub-regions, and each independent sub-region is configured with a dedicated event-aware logic unit and a local asynchronous transmission channel. Each event-aware logic unit integrates a dynamic accumulator and a differential comparator, and generates a driving pulse sequence using a local self-excited oscillation circuit. Within each sampling period, the event-aware logic unit acquires the current output data of the storage unit and calculates the numerical difference between the current output data and the reference data of the previous sampling time. The numerical difference represents the instantaneous change of the data in the time dimension. The dynamic accumulator accumulates and sums the numerical differences generated over multiple consecutive periods to obtain the cumulative change in the data state. When the cumulative change reaches or exceeds a preset threshold in value, the output state of the differential comparator flips, generating a valid event trigger signal. The steps for configuring the event decoding and reconstruction module at the receiving end include: An address mapping table based on a content-addressable memory structure is constructed inside the receiving end. The address mapping table records the correspondence between the physical addresses of the internal storage units of the memory chip and the external storage areas. Extract the address identifier field from the address and event representation data packet, and locate the target external storage location by searching the address mapping table; Parse the event type field. When the event type is data update, convert the data carried in the packet into a read / write command format that conforms to the external bus protocol standard. The priority flag bits in the address and event representation data packets are identified, and the scheduling logic distributes the parsed operation tasks to the corresponding level of processing queues, where the high-priority queues have arbitration rights to preempt bus resources.

2. The in-memory computing high-speed external interface design method for storage unit buffers according to claim 1, characterized in that, The steps of encapsulating a structured address and event representation data packet include: constructing a data packet with a fixed-length field structure, wherein the data packet includes, in sequence, an address identifier field, an event type field, a priority identifier bit, and a check field; in the address identifier field, encapsulating the physical location information of the storage unit in the storage array where data changes have occurred using a hierarchical encoding method, wherein the physical location information consists of row index information, column index information, and subarray number information; in the event type field, using a preset multi-bit width data segment to identify the specific trigger for transmission, wherein the trigger includes data update events, computation completion events, abnormal interruption events, and resource warning events; and calculating a check code according to a preset linear mapping rule based on the contents of the address identifier field and the event type field, and filling the check code into the check field.

3. The method for designing a high-speed external interface for in-memory computing with a storage unit buffer according to claim 2, characterized in that, The asynchronous handshake protocol adopts a four-phase dual-track encoding method, and its data transmission control steps include: Each logic bit is configured with a logic zero transmission line and a logic one transmission line. When the logic zero transmission line is high and the logic one transmission line is low, it represents logic zero. When the logic one transmission line is high and the logic zero transmission line is low, it represents logic one. When both the logic zero transmission line and the logic one transmission line are low, it represents the bus idle state. In the first phase, the sending end loads the address and event representation data packet onto the dual-rail data line and pulls the request signal line high; In the second phase, after the receiving end detects that the request signal line is high and the signal on the dual-rail data line is stable, it reads the address and event characterization data packet, processes it, and then pulls the response signal line high. In the third phase, after receiving a high-level response signal, the transmitting end pulls the request signal line low and restores the dual-rail data lines to a completely zero idle state. In the fourth phase, after the receiving end detects that the request signal line has gone low, it pulls the response signal line low, so that the interface circuit returns to the initial listening state.

4. The in-memory computing high-speed external interface design method for storage unit buffers according to claim 3, characterized in that, The preset threshold supports dynamic adjustment, and the adjustment steps include: A configuration register is set inside the sensing unit to store preset threshold parameters; When the system is in high-precision calculation mode, the preset threshold in the configuration register is adjusted to the first threshold through the configuration interface; When the system is in a low-power operating mode, the preset threshold in the configuration register is adjusted to a second threshold through the configuration interface. The second threshold is numerically greater than the first threshold. During system operation, the processing queue load status of the receiving end is monitored in real time. When the receiving end responds with a congestion indicator, the sending end automatically increases the preset threshold in the configuration register to reduce the event triggering frequency.

5. The in-memory computing high-speed external interface design method for storage unit buffers according to claim 4, characterized in that, The dynamic accumulator performs a bidirectional integration mechanism, the steps of which include: When the change in the output data of the storage unit relative to the previous cycle is positive, the dynamic accumulator performs an addition operation; When the change in the output data of the storage unit relative to the previous cycle is negative, the dynamic accumulator performs a subtraction operation; A numerical range including an upper threshold and a lower threshold is set. When the accumulated value of the dynamic accumulator exceeds the upper threshold or the lower threshold, an event trigger signal is generated. When encapsulating data packets, the locality association between the current trigger address and the previous trigger address is determined. If the addresses are continuous, only the starting address is recorded in the address identifier field, and subsequent data packets only encapsulate the offset value relative to the starting address.

6. The method for designing a high-speed external interface for in-memory computing with a storage unit buffer according to claim 5, characterized in that, The high-speed external interface supports multi-level cascaded topology structures, and its routing control steps include: Multiple in-memory computing chips are connected sequentially via an event-driven link, so that the event output port of the previous stage chip is connected to the event input port of the next stage chip; The geographic coordinates field and lifecycle field of the target chip are set in the address and event representation data packet; When a data packet arrives at the intermediate chip, the routing logic compares the geographic coordinate field with the chip's own coordinates. If the coordinates do not match, the data packet is forwarded in either the horizontal or vertical direction based on the coordinate difference. Each time a data packet is forwarded through a first-level chip, the value of the lifecycle field is reduced by a fixed step size. When the value of the lifecycle field decreases to zero, the data packet representing the address and event is forcibly discarded and an abnormal interruption alarm is triggered.

7. The method for designing a high-speed external interface for in-memory computing with a storage unit buffer according to claim 6, characterized in that, The confirmation signal return and resource release steps include: After completing the address resolution and data writing operations, the receiving end performs an integrity check on the address and event representation data packet; The receiver determines whether the verification result is successful and whether the external storage unit returns a write success acknowledgment. Only when both verification and write are successful, the receiver sends a final acknowledgment signal to the sender. Set up a temporary storage mechanism at the sending end to retain the data of the triggered storage unit during the asynchronous handshake transmission process; The sending end monitors the reception status of the acknowledgment signal. If the acknowledgment signal is received within a preset time range, the corresponding local buffer resource is marked as overwhelmable. If the sending end does not receive the confirmation signal within the preset time range, it restarts the asynchronous handshake protocol to retransmit the data.

8. The method for designing a high-speed external interface for in-memory computing with a storage unit buffer according to claim 7, characterized in that, The method also includes the following optimization steps: The event-aware logic unit integrates a rate-aware component to calculate an approximate first-order derivative of the data change output by the storage unit. When the approximate first-order derivative exceeds a preset rate of change threshold, the event generation mechanism is forcibly triggered. A hierarchical buffer structure is set between the storage unit buffer and the high-speed external interface. The hierarchical buffer structure includes a local buffer and a global buffer pool. When the local asynchronous transmission channel is congested, the address and event characterization data packets are temporarily stored in the global buffer pool. Zero-value determination logic is set in the event-aware logic unit. When the calculation result of the storage unit fluctuates within the preset deviation range of zero value, the event trigger signal is blocked. During the generation of the address and event representation data packet, the address identifier field and the event type field are encrypted by XOR operation using a dynamically generated pseudo-random sequence; A bit-width adapter is configured at the receiving end, and the fixed-length address and event representation data packet are split or merged according to the hardware requirements of the receiving end processing unit.

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