A low-latency FPGA acceleration method for graph neural network inference

Abstract

The application relates to the field of artificial intelligence hardware acceleration and wireless communication technology, and particularly discloses a low-delay FPGA acceleration method for graph neural network inference, which comprises the following steps: initializing FPGA hardware resources, loading satellite communication channel data and weight and bias parameters of a graph neural network model from an off-chip memory to an on-chip memory, and initializing each calculation module in a calculation engine; performing matrix operation in the graph neural network by using a parallel calculation engine in the FPGA, wherein the parallel calculation engine comprises a plurality of contraction arrays, each contraction array is composed of a plurality of processing elements, and is used for performing matrix multiplication calculation of a full connection layer in parallel; parallel operation is realized between data processing and data transmission by adopting a double-buffering technology, and a plurality of calculation layers are merged into a calculation group by using a layer fusion technology, so that the storage and transmission of intermediate data are reduced; and the calculated beamforming data is output to the off-chip memory, so that the acceleration task is completed.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence hardware acceleration and wireless communication technology, specifically to a low-latency FPGA acceleration method for graph neural network inference. Background Technology

[0002] With the significant reduction in the production and launch costs of low Earth orbit (LEO) satellites, direct satellite-to-ground communication technology has become an important research direction for achieving seamless global coverage and enhancing network flexibility and resilience. Among these technologies, a distributed antenna system composed of multiple LEO satellites coordinating communication with ground users to form a space-based multiple-input multiple-output (MIMO) system is an effective way to improve communication capacity and quality. In such systems, achieving distributed cooperative beamforming across multiple satellites is the core of high-performance communication; its essence is solving a non-convex optimization problem of maximizing the weighted sum and rate under satellite transmit power constraints.

[0003] Traditional optimization methods, such as alternating optimization based on Lagrange dual transformation, are not only computationally complex but also prone to getting trapped in local optima, making them unsuitable for the stringent real-time requirements of spaceborne environments. In recent years, graph neural networks (GNNs) have offered a new solution to these distributed optimization problems due to their powerful representation and reasoning capabilities for graph-structured data. By mapping the communication network to a graph structure and deploying a lightweight GNN model on each satellite, it is possible to perform efficient reasoning based on local channel information, thereby generating beamforming vectors in real time.

[0004] However, the practical deployment of GNN models on satellite platforms faces significant challenges. Satellite platforms have strict constraints on power consumption, hardware resources, and real-time performance, while GNN inference typically involves a large number of parameters and complex neighborhood aggregation operations, leading to significant computational latency and energy consumption. Field-programmable gate arrays (FPGAs) are often used as acceleration platforms for deep learning inference due to their low power consumption, reconfigurability, and strong parallel computing capabilities. However, existing general-purpose or traditional GNN-oriented FPGA accelerator architectures have obvious limitations: First, most architectures employ non-pipelined designs that frequently access off-chip memory, or only optimize pipelines for sequential layer-by-layer processing, resulting in insufficient resource utilization and throughput; second, they fail to provide customized optimization for the multi-layer graph convolutional network structure with fully connected layers at its core, which is unique to satellite-ground collaborative communication scenarios, leading to low computational efficiency; third, they lack in-depth optimization in data flow scheduling, inter-layer fusion, and memory bandwidth utilization, making the overall inference process limited by memory access bottlenecks, and the latency cannot meet the real-time requirements of highly dynamic satellite communication.

[0005] Therefore, designing a dedicated, low-latency FPGA accelerator architecture for the specific computational mode and performance constraints of GNN inference tasks in LEO multi-star collaborative communication scenarios, in order to achieve efficient utilization of hardware resources and extreme acceleration of the inference process, has important theoretical value and urgent practical significance. Summary of the Invention

[0006] To achieve the objectives of this invention, this application provides a low-latency FPGA acceleration method for graph neural network inference, comprising: Step S1: Initialize FPGA hardware resources, load satellite communication channel data and the weights and bias parameters of the graph neural network model from off-chip memory to on-chip memory, and initialize each computing module in the computing engine; Step S2: Utilize the parallel computing engine in the FPGA to perform matrix operations in the graph neural network. The parallel computing engine includes multiple shrink arrays, each consisting of multiple processing elements, for parallel execution of matrix multiplication calculations in the fully connected layer. Step S3: Use double buffering technology to achieve parallel operation between data processing and data transmission, and use layer fusion technology to merge multiple computing layers into computing groups to reduce the storage and transmission of intermediate data; Step S4: Output the calculated beamforming data to off-chip memory to complete the acceleration task.

[0007] In some specific embodiments, step S1 includes: A double-buffering technique is used to achieve ping-pong buffered transmission of channel data, weight parameters, and bias parameters from off-chip memory to on-chip memory.

[0008] In some specific embodiments, step S2 includes: Step S21: Perform preliminary processing on the features of the input nodes through a multi-layer perceptron layer; Step S22: Perform an aggregation operation to gather the feature information of adjacent nodes; Step S23: Perform a combination operation to combine the aggregated features with the features of the current node; Step S24: Process the nodes again through the multilayer perceptron layer to generate updated node features.

[0009] In some specific embodiments, step S2 further includes: During matrix operations, partial product accumulation and transmission are achieved between processing elements through pulse-style data transfer.

[0010] In some specific embodiments, step S3 includes the double buffering technique: Double buffers are used to store the output data of the current layer as the input data of the next layer, so as to achieve seamless connection of data flow between layers.

[0011] In some specific embodiments, step S3 includes the layer fusion technique: Multiple graph convolutional layers are combined into a computation group, and the computation of each layer is performed sequentially within the group, reducing the number of data exchanges between on-chip and off-chip memory.

[0012] In some specific embodiments, it also includes: Before performing matrix operations in the graph neural network, the weights and bias parameters are quantized to convert high-precision data into low-precision fixed-point or integer formats.

[0013] In some specific embodiments, it also includes: The large-scale computation is decomposed into multiple tiles using a cyclic tiling technique, which are then sequentially input into the FPGA accelerator for processing.

[0014] In some specific embodiments, it also includes: Finite state machines are used to control the computation sequence and data access location, and to manage the execution state and data flow scheduling of each computation module.

[0015] In some specific embodiments, in step S4, all calculations are performed in on-chip memory to avoid external memory access during inference and reduce latency.

[0016] The beneficial effects of the above technical solution are as follows: Compared with existing technologies, the low-latency FPGA accelerator architecture for graph neural network inference provided by this invention has the following significant advantages: 1. Significantly reduced inference latency to meet real-time requirements: By employing a highly parallel computing engine based on a shrinking array, double buffering technology to achieve overlap between computation and transmission, and layer fusion technology to reduce intermediate data access, this invention significantly shortens the single inference time of the GNN model. This enables near real-time calculation of beamforming vectors even under harsh conditions of high-speed motion of low-Earth orbit satellites and rapid channel changes, effectively ensuring the performance of space multi-input multi-output communication systems.

[0017] 2. Significantly Improved Hardware Resource Utilization and Computational Energy Efficiency: A customized design was implemented specifically for the computational characteristics of the target GNN, which is centered around fully connected layers, eliminating redundant logic in the general architecture. Through optimization strategies such as cyclic tiling, quantization, and code refactoring (e.g., reducing the number of MLP calls), computational density was maximized within limited FPGA logic and storage resources. Simultaneously, optimized dataflow reduced unnecessary off-chip memory accesses, significantly lowering dynamic power consumption and meeting the stringent power budget constraints of the spaceborne platform.

[0018] 3. Effectively alleviates memory bandwidth bottleneck: This invention identifies that GNN inference on FPGAs is mainly limited by memory bandwidth. By comprehensively applying multiple techniques such as quantization (reducing data bit width), double buffering (smoothing data flow), and layer fusion (reducing intermediate result write-back), the demand for off-chip memory bandwidth is significantly reduced, shifting the computational bottleneck from I / O to the computing unit itself, thereby fully leveraging the parallel computing potential of the FPGA.

[0019] 4. Enhanced System Reliability and Deployment Flexibility: Employing finite state machines for centralized, deterministic process control reduces the complexity of control logic and improves the stability and predictability of accelerator operation. Furthermore, this dedicated accelerator architecture is deeply optimized for specific GNN models, featuring a compact structure that is easy to integrate and deploy in resource-constrained onboard computing modules, providing an efficient implementation paradigm for the co-design of algorithms and hardware.

[0020] 5. Improve overall communication system performance: This method enables the distributed cooperative beamforming algorithm based on GNN to be executed efficiently on the satellite, thereby helping multi-satellite systems generate beamforming vectors faster and more accurately, improving the weighted sum rate and communication quality of the system, and enhancing the capacity and robustness of the entire LEO satellite communication network. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating a low-latency FPGA acceleration method for graph neural network inference, as provided in one embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0024] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the invention, and should not be construed as limiting the invention.

[0025] Example 1 One embodiment of the present invention provides a low-latency FPGA acceleration method for graph neural network inference, referring to... Figure 1 As shown, it includes: Step S1: Initialize FPGA hardware resources, load satellite communication channel data and the weights and bias parameters of the graph neural network model from off-chip memory to on-chip memory, and initialize each computing module in the computing engine; In a specific embodiment of the present invention, step S1 includes: A double-buffering technique is used to achieve ping-pong buffered transmission of channel data, weight parameters, and bias parameters from off-chip memory to on-chip memory.

[0026] Step S2: Utilize the parallel computing engine in the FPGA to perform matrix operations in the graph neural network. The parallel computing engine includes multiple shrink arrays, each consisting of multiple processing elements, for parallel execution of matrix multiplication calculations in the fully connected layer. In one specific embodiment of the present invention, step S2 includes: Step S21: Perform preliminary processing on the features of the input nodes through a multi-layer perceptron layer; Step S22: Perform an aggregation operation to gather the feature information of adjacent nodes; Step S23: Perform a combination operation to combine the aggregated features with the features of the current node; Step S24: Process the nodes again through the multilayer perceptron layer to generate updated node features.

[0027] In one specific embodiment of the present invention, step S2 further includes: During matrix operations, partial product accumulation and transmission are achieved between processing elements through pulse-style data transfer.

[0028] Step S3: Use double buffering technology to achieve parallel operation between data processing and data transmission, and use layer fusion technology to merge multiple computing layers into computing groups to reduce the storage and transmission of intermediate data; In a specific embodiment of the present invention, step S3 includes the double buffering technique: Double buffers are used to store the output data of the current layer as the input data of the next layer, so as to achieve seamless connection of data flow between layers.

[0029] In a specific embodiment of the present invention, step S3 includes the layer fusion technique: Multiple graph convolutional layers are combined into a computation group, and the computation of each layer is performed sequentially within the group, reducing the number of data exchanges between on-chip and off-chip memory.

[0030] Step S4: Output the calculated beamforming data to off-chip memory to complete the acceleration task.

[0031] In one specific embodiment of the present invention, in step S4, all calculations are performed in the on-chip memory to avoid external memory access during the inference process and reduce latency.

[0032] In one specific embodiment of the present invention, it further includes: Before performing matrix operations in the graph neural network, the weights and bias parameters are quantized to convert high-precision data into low-precision fixed-point or integer formats.

[0033] In one specific embodiment of the present invention, it further includes: The large-scale computation is decomposed into multiple tiles using a cyclic tiling technique, which are then sequentially input into the FPGA accelerator for processing.

[0034] In one specific embodiment of the present invention, it further includes: Finite state machines are used to control the computation sequence and data access location, and to manage the execution state and data flow scheduling of each computation module.

[0035] This invention provides a low-latency FPGA accelerator architecture for graph neural network inference, in order to solve the problems of low resource utilization and high latency in existing FPGA accelerators due to their incompatibility with specific graph neural network architectures.

[0036] In the adopted GNN, all layers are associated with fully connected (FC) networks, and their computation relies on large matrix multiplications. With this in mind, multiple shrinking arrays (SAs) are used as the core components of the computation engine. An SA is a specialized hardware architecture consisting of a grid of processing elements (PEs). Each PE is responsible for computing partial products, accumulating the results, and passing data to neighboring PEs in a rhythmic, pulsed manner. This structure allows for efficient parallel processing, making SAs particularly suitable for tasks involving repetitive computations, such as matrix operations. In addition to SAs, the computation engine includes other computational modules, including rectified linear units (ReLU), aggregation, and combination operations.

[0037] The algorithm implementation of the graph convolutional layer is the core part of the technical solution of this invention. The goal of this algorithm is to generate the optimal beamforming vector by processing the features of each user terminal (UT) node in the communication network using a graph neural network (GNN). The algorithm first performs preliminary processing on the features of each node through a multilayer perceptron (MLP) layer, then aggregates the information of neighboring nodes through graph convolution operations, and finally generates updated features for each node through a combination operation. This process progressively optimizes the node features through multiple graph convolutions, ensuring that the final generated beamforming vector effectively improves the performance of the communication system.

[0038] In the specific implementation process, the input data is the feature vector of each user terminal. After processing by the graph neural network, these node features are updated and optimized layer by layer. Each graph convolutional layer first performs feature transformation through an MLP, then aggregates the features of neighboring nodes through an aggregation operation, and then combines the aggregated result with the features of the current node through a combination operation. Finally, after processing by the second MLP layer, the final output features of the node are used to calculate the optimal beamforming vector. The formula is as follows: Step 1: Initialize the MLP layer (first layer), for each input feature Processing is performed to generate intermediate results: Step 2: Aggregation operation, aggregating from adjacent nodes. Information is used to generate new aggregated features: here, It is an aggregation function, usually a combination of MLP and element-wise max pooling. Step 3: Combination operation, which combines the aggregated information with the features of the current node to generate new features for the node: For memory access, a double-buffering technique, specifically ping-pong buffering, is employed to enable parallel operations between data processing and data transfer, thereby improving system efficiency and reducing latency. Furthermore, double buffering is also applied to store the output of one layer as the input of the next, facilitating layer fusion and merging multiple layers into a single group. This technique minimizes intermediate data transfers between on-chip and off-chip memory, thereby reducing latency and minimizing energy consumption associated with excessive data movement.

[0039] The control unit employs a finite state machine (FSM) to manage the calculation count and data access locations. By using an FSM, the control module can systematically and efficiently manage the calculation count and data access locations, ensuring that operations are executed in the correct sequence and that data is accessed precisely when needed. This structured approach reduces the complexity of the control logic and improves the overall performance of the system.

[0040] According to the Roofline model, computation and communication between on-chip and off-chip memory are two major constraints on FPGA inference latency. Since the GNNs under consideration involve a large number of weights and bias parameters, the inference latency of FPGA-based GNN accelerators depends more on the I / O bandwidth for accessing off-chip memory. In other words, the accelerator implementation is memory-constrained. To address this, four key techniques are employed: quantization, cyclic tiling, double buffering, and layer fusion. Quantization involves reducing the bit width of the data, typically by converting from a higher-precision format (such as floating-point) to a lower-precision format (such as fixed-point or integer). This approach significantly reduces communication latency between on-chip and off-chip memory, improving computational efficiency on resource-constrained hardware platforms. However, quantization can also lead to potential precision loss. Overall, balancing precision and efficiency during quantization is crucial. Cyclic tiling aims to break down large loops into smaller blocks. For FPGA-based accelerators, only one tile can be processed at a time; therefore, all tiles are input sequentially into the FPGA-based accelerator for computation. This means that the accelerator can only begin computation on the next tile after completing the processing of the current tile. By tiling the loop, the loop is divided into on-chip and off-chip parts, thereby increasing the on-chip data throughput.

[0041] In the FPGA implementation, the code was refactored to improve computational efficiency. Specifically, to reduce the computational burden of each MLP layer call and minimize hardware resource consumption, the refactored code optimized the number of MLP calls in the graph convolutional layer. Furthermore, memory usage in the FPGA architecture also needed optimization, employing double buffering to improve data transmission efficiency and reduce latency. This optimization strategy ensures that graph convolution operations can still be performed efficiently even with limited FPGA hardware resources, thereby improving the overall system performance.

[0042] The FPGA accelerator design further optimizes computational latency and resource utilization. The computation engine employs streaming arrays (SAs) to accelerate matrix operations, processing computational tasks in parallel through multiple processing elements (PEs), thus improving the efficiency of graph convolution operations. The memory section utilizes double buffering technology to reduce data transfer latency between on-chip and off-chip memory, ensuring smooth data transfer and avoiding delays caused by data waiting. Furthermore, the control unit manages data access and computation order through a finite state machine (FSM), ensuring that computational tasks are executed in a predetermined order, thereby avoiding performance bottlenecks caused by complex control logic.

[0043] The computation flow of the FPGA-based GNN accelerator consists of three steps. First, channel data of the local communication network, weight parameters of the associated GNN model, and bias parameter memory are obtained from off-chip memory and converted to on-chip memory using a dual-buffer. Then, computation is performed, outputting beamforming data of the local communication network. During computation, the code for the two-layer graph convolution in the GNN is reconstructed, and the number of calls to the MLP layer is reduced by adapting to the size of the SA (Self-Assessment). Finally, the output is returned to off-chip memory. In this process, all computations are performed on-chip, eliminating external memory access.

[0044] This application employs a highly parallel computing engine based on a shrinking array, double buffering technology to achieve overlap between computation and transmission, and layer fusion technology to reduce intermediate data access. These techniques significantly shorten the single inference time of the GNN model. This enables near real-time beamforming vector calculation even under harsh conditions of high-speed low-Earth orbit satellite motion and rapidly changing channels, effectively ensuring the performance of space multi-input multi-output communication systems.

[0045] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0046] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes. Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the invention. Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0047] The methods and apparatus provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0048] In the description of this specification, references to terms such as "an embodiment," "some embodiments," "example," "specific example," or "a specific embodiment" or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A low-latency FPGA acceleration method for graph neural network inference, characterized in that, include: Step S1: Initialize FPGA hardware resources, load satellite communication channel data and the weights and bias parameters of the graph neural network model from off-chip memory to on-chip memory, and initialize each computing module in the computing engine; Step S2: Utilize the parallel computing engine in the FPGA to perform matrix operations in the graph neural network. The parallel computing engine includes multiple shrink arrays, each consisting of multiple processing elements, for parallel execution of matrix multiplication calculations in the fully connected layer. Step S3: Use double buffering technology to achieve parallel operation between data processing and data transmission, and use layer fusion technology to merge multiple computing layers into computing groups to reduce the storage and transmission of intermediate data; Step S4: Output the calculated beamforming data to off-chip memory to complete the acceleration task.

2. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Step S1 includes: A double-buffering technique is used to achieve ping-pong buffered transmission of channel data, weight parameters, and bias parameters from off-chip memory to on-chip memory.

3. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Step S2 includes: Step S21: Perform preliminary processing on the features of the input nodes through a multi-layer perceptron layer; Step S22: Perform an aggregation operation to gather the feature information of adjacent nodes; Step S23: Perform a combination operation to combine the aggregated features with the features of the current node; Step S24: Process the nodes again through the multilayer perceptron layer to generate updated node features.

4. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Step S2 also includes: During matrix operations, partial product accumulation and transmission are achieved between processing elements through pulse-style data transfer.

5. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, In step S3, the double buffering technology includes: Double buffers are used to store the output data of the current layer as the input data of the next layer, so as to achieve seamless connection of data flow between layers.

6. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, In step S3, the layer fusion technology includes: Multiple graph convolutional layers are combined into a computation group, and the computation of each layer is performed sequentially within the group, reducing the number of data exchanges between on-chip and off-chip memory.

7. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Also includes: Before performing matrix operations in the graph neural network, the weights and bias parameters are quantized to convert high-precision data into low-precision fixed-point or integer formats.

8. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Also includes: The large-scale computation is decomposed into multiple tiles using a cyclic tiling technique, which are then sequentially input into the FPGA accelerator for processing.

9. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, Also includes: Finite state machines are used to control the computation sequence and data access location, and to manage the execution state and data flow scheduling of each computation module.

10. The low-latency FPGA acceleration method for graph neural network inference according to claim 1, characterized in that, In step S4, all calculations are performed in on-chip memory, avoiding external memory access during inference to reduce latency.

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