Msi address translation emulation system and method

Abstract

The application provides an MSI address translation simulation system and method, and relates to the technical field of integrated circuit design and verification. The system comprises an MSI transaction generation module, which is used for generating MSI transactions based on an interrupt target semantic model; a synchronous interface module, which is used for synchronizing configuration information, running states and transaction semantics between the MSI address translation simulation system and a device under test; an MSI transaction identification module, which is used for identifying MSI transactions in a mixed transaction flow; a translation result collection and path fingerprint extraction module, which is used for collecting translation results of the MSI transactions after address translation by the device under test and constructing translation path fingerprints; and a verification module, which is used for performing consistency verification on the translation results and the translation path fingerprints output by the device under test. The system provided in the application embodiment can realize structured simulation and consistency verification of the MSI address translation process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and verification technology, and in particular to an MSI address translation simulation system and method. Background Technology

[0002] In related technologies, the verification work on the RISC-V Input / Output Memory Management Unit (IOMMU) mainly focuses on Direct Memory Access (DMA) address translation and cache hit path verification. Typically, Message Signaled Interrupt (MSI) write transactions and ordinary DMA write transactions are modeled in the same way, without distinguishing the essential differences between the two in address semantics and interrupt triggering characteristics, resulting in insufficient verification granularity. Summary of the Invention

[0003] This invention provides an MSI address translation simulation system and method. Driven by the semantics of interrupt targets, it constructs a semantic, end-to-end, closed-loop simulation verification process. It can accurately distinguish between MSI and ordinary DMA transactions, and achieve dual verification from the result to the translation path fingerprint. It comprehensively covers complex scenarios such as single / multi-stage, normal / abnormal, multi-address space, and multi-interrupt targets, significantly improving the verification granularity, completeness, and automation level. It effectively reduces the cost of manual comparison, improves fault location efficiency and verification credibility, and efficiently and reliably realizes MSI address translation simulation.

[0004] This invention provides an MSI address translation simulation system, comprising: The MSI transaction generation module is used to generate MSI transactions based on the interrupt target semantic model; the interrupt target semantic model includes interrupt target semantic information and the mapping relationship between the interrupt target semantic information and MSI address and data field; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority and address space type; The synchronization interface module is used to synchronize configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test. The MSI transaction identification module is used to identify MSI transactions in mixed transaction streams; The translation result acquisition and path fingerprint extraction module is used to acquire the translation result of the MSI transaction execution address translated by the device under test and construct the translation path fingerprint; The verification module is used to perform consistency verification on the translation results and translation path fingerprints output by the device under test based on the expected translation results and expected translation path fingerprints generated by the reference model unit.

[0005] According to an MSI address translation simulation system provided by the present invention, the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority, and address space type.

[0006] According to an MSI address translation simulation system provided by the present invention, the step of identifying MSI transactions in a mixed transaction stream includes: The MSI address range is determined by scanning the DeviceContext and / or resolving MSI-PT entries; Based on the MSI address range, MSI transactions are identified in the mixed transaction flow.

[0007] According to the MSI address translation simulation system provided by the present invention, the MSI transaction identification module is further used for: The identified MSI transactions are semantically decomposed to obtain physical attributes and interrupt semantic attributes; wherein, the physical attributes include address, data and transaction length, and the interrupt semantic attributes include interrupt file number, interrupt vector number and interrupt priority.

[0008] According to an MSI address translation simulation system provided by the present invention, the construction of the translation path fingerprint includes: A translation path fingerprint is constructed based on the state information during the translation process; the state information during the translation process includes at least one of the following: page table traversal level, translation stage trigger state, IOTLB hit state, and MSI-PT participation state encoding.

[0009] According to the MSI address translation simulation system provided by the present invention, the expected translation result and the expected translation path fingerprint are obtained independently based on the RISC-VIOMMU specification and the AIA interrupt remapping rule.

[0010] According to the MSI address translation simulation system provided by the present invention, the verification module is further used to perform consistency verification on the exception type and interrupt target, and output the verification result.

[0011] According to the present invention, an MSI address translation simulation system further includes: The abnormal path construction module is used to modify page table entries, permission bits, and MSI-PT table entries to construct abnormal scenarios without changing the MSI transaction semantics.

[0012] According to the present invention, an MSI address translation simulation system further includes: The association coverage modeling and feedback module is used to construct a multi-dimensional association coverage matrix based on translation path fingerprints, exception types, and interruption targets, determine unverified translation scenarios based on the multi-dimensional association coverage matrix, and feed back the unverified translation scenarios to the MSI transaction generation module.

[0013] This invention also provides an MSI address translation simulation method, comprising the following steps: MSI transactions are generated based on the interrupt target semantic model; the interrupt target semantic model includes interrupt target semantic information and the mapping relationship between the interrupt target semantic information and MSI address and data field; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority and address space type; Synchronize the configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test; Identify MSI transactions in mixed transaction flows; Collect the translation results of the MSI transaction execution address translation by the device under test and construct the translation path fingerprint; Based on the expected translation result and the expected translation path fingerprint, the translation result and translation path fingerprint output by the device under test are verified.

[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the MSI address translation simulation methods described above.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the MSI address translation simulation method as described above.

[0016] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the MSI address translation simulation method as described above.

[0017] This invention provides an MSI address translation simulation system and method, driven by interrupt target semantics, constructing a semantic, end-to-end, closed-loop simulation verification process. It can accurately distinguish between MSI and ordinary DMA transactions, achieve dual verification from the result to the translation path fingerprint, and comprehensively cover complex scenarios such as single / multi-stage, normal / abnormal, multi-address space, and multi-interrupt target. It significantly improves the verification granularity, completeness, and automation, effectively reduces the cost of manual comparison, improves fault location efficiency and verification credibility, and efficiently and reliably realizes MSI address translation simulation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is one of the schematic diagrams of the MSI address translation simulation system provided by the present invention.

[0020] Figure 2 This is a flowchart illustrating the MSI address translation simulation method provided by the present invention.

[0021] Figure 3 This is the second schematic diagram of the MSI address translation simulation system provided by the present invention.

[0022] Figure 4 This is the third schematic diagram of the MSI address translation simulation system provided by the present invention.

[0023] Figure 5 This is the fourth schematic diagram of the MSI address translation simulation system provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] The following is combined Figures 1 to 5 The present invention describes the MSI address translation simulation system and method.

[0026] To facilitate a clearer understanding of the technical solutions of the various embodiments of this application, some technical content related to the various embodiments of this application will be introduced first.

[0027] As the IOMMU specification released by RISC-V International has been gradually improved, the IOMMU module in the RISC-V architecture now supports address translation and redirection processing for MSI write transactions initiated by peripherals.

[0028] Under this mechanism, peripherals trigger an interrupt request by initiating a write operation to a specific address. The IOMMU needs to perform address validity verification, page table traversal, permission checks and exception handling on the write transaction, and perform interrupt remapping when necessary.

[0029] Compared with ordinary DMA data access transactions, MSI write transactions have the characteristics of small transaction granularity, sensitive triggering timing, and tight coupling with the interrupt controller. The translation result not only affects the correctness of address mapping, but also directly affects the accuracy of interrupt dispatch target.

[0030] In the existing verification system, the verification work for RISC-VIOMMU mainly focuses on DMA address translation and cache hit path verification, while a dedicated verification mechanism for MSI address translation function is lacking, specifically the following problems exist: (1) Lack of a dedicated modeling mechanism for MSI write transactions.

[0031] Existing verification environments typically model MSI write transactions and ordinary DMA write transactions in the same way, without distinguishing their address semantics and interrupt triggering characteristics, resulting in insufficient verification granularity.

[0032] (2) There is a lack of an automated consistency verification mechanism between the translation results and the interrupted target.

[0033] Existing verification methods mostly rely on log analysis or manual comparison of translation results, lacking a closed-loop automatic checking mechanism, making it difficult to systematically verify the correctness of interruption redirection.

[0034] (3) Insufficient ability to construct abnormal paths.

[0035] For abnormal scenarios such as missing page tables, abnormal permissions, out-of-bounds addresses, and translation failures, there is a lack of systematic combined testing strategies, making it difficult to cover boundary conditions.

[0036] (4) The verification link is incomplete in a multi-address space environment.

[0037] In multi-address space or multi-stage translation scenarios, existing verification platforms struggle to establish a complete verification chain from transaction input to interrupt output.

[0038] Figure 1 This is one of the schematic diagrams of the MSI address translation simulation system provided by the present invention, such as... Figure 1 As shown, the system includes the following: The MSI transaction generation module is used to generate MSI transactions based on the interrupt target semantic model. The interrupt target semantic model includes interrupt target semantic information and the mapping relationship between interrupt target semantic information and MSI address and data fields. The interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority, and address space type. The synchronization interface module is used to synchronize configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test. The MSI transaction identification module is used to identify MSI transactions in mixed transaction streams; The translation result acquisition and path fingerprint extraction module is used to acquire the translation results of the MSI transaction execution address translation by the device under test and construct the translation path fingerprint. The verification module is used to verify the consistency of the translation results and translation path fingerprints output by the device under test based on the expected translation results and expected translation path fingerprints generated by the reference model units.

[0039] Specifically, in this embodiment of the application, the MSI address translation simulation system includes an MSI transaction generation module, a synchronization interface module, an MSI transaction identification module, a translation result acquisition and path fingerprint extraction module, and a verification module.

[0040] Optionally, the MSI transaction generation module can generate MSI transactions conforming to the RISC-VIOMMU and AIA specifications based on a pre-built interrupt target semantic model. This model incorporates interrupt target semantic information and establishes a mapping relationship between the semantic information and MSI addresses and data fields. Optionally, the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority, and address space type, used to construct a complete and accurate interrupt target semantic model, thereby providing clear semantic constraints and parameter sources for MSI transaction generation.

[0041] For example, the MSI transaction generation module constructs interrupt-triggered write transactions conforming to the RISC-VIOMMU specification and RISC-VAIA architecture constraints in the following manner. Optionally, during the initialization phase, the MSI transaction generation module reads the IMSIC interrupt file structure information, including the interrupt file number, supported vector number range, priority encoding range, and client-host file mapping relationship. Based on the above information, it constructs an interrupt target semantic model, ensuring that the generated MSI address and write data field logically correspond to different interrupt file instances, thus ensuring coverage of multiple interrupt files and multiple priority ranges. Optionally, the MSI transaction generation module supports constructing MSI target addresses in the form of client virtual address (GVA), client physical address (GPA), and host physical address (HPA), and combines them with device identifier (DeviceID) and process address space identifier (PASID) for joint constraints, which can trigger single-stage translation path fingerprints, two-stage translation path fingerprints, and MSI-PT independent translation path fingerprints. Optionally, the MSI transaction generation module can introduce a multi-dimensional parameter matrix generator to construct a multi-dimensional parameter combination space based on device identifier, process address space identifier, translation mode, interrupt file number, interrupt vector number and priority, and guide test cases to cover unverified scenarios through a dynamic weight adjustment mechanism.

[0042] In other words, this application generates dedicated MSI transactions driven by interrupt semantics, which can accurately match different interrupt files, interrupt vector numbers, and priority targets. This differs from the general modeling method of ordinary DMA transactions, ensuring that simulation stimuli can effectively trigger various MSI address translation scenarios. The MSI address and data fields generated based on this semantic constraint can be directly mapped to real interrupt targets, making the simulation stimuli strictly aligned with hardware behavior and improving the realism and accuracy of verification. At the same time, it supports the configuration of semantic items individually or in combination, which can flexibly cover complex scenarios such as single / multiple interrupt files, different priorities, and multiple address spaces, enhancing the comprehensiveness of verification coverage. In addition, this semantic information can also provide a unified and quantifiable basis for subsequent MSI transaction identification, semantic decomposition, and translation result verification, further improving the accuracy and traceability of verification.

[0043] Optionally, the synchronization interface module is used to synchronize and align configuration information, operating status, and transaction semantics in real time between the MSI address translation simulation system and the device under test (DUT). This ensures the consistency of the context between the simulation environment and the DUT, effectively preventing verification failures due to configuration asynchrony or inconsistent states between the simulation reference model and the DUT. It ensures the translation process executes under unified conditions, improving the stability and reliability of the entire simulation system. Optionally, the state consistency between the DUT and the verification platform specifically includes a software behavior simulation synchronization mechanism and an out-of-order transaction association support mechanism. Specifically, the software behavior simulation synchronization mechanism automatically sends a state refresh notification to the reference model and synchronously updates the page table cache within the model when the page table or device context is updated, preventing state mismatch between the reference model and the DUT. The out-of-order transaction association support mechanism addresses potential out-of-order write-back scenarios by assigning a unique transaction ID to each transaction, establishing an input queue and an output reordering buffer, and achieving precise input / output association based on the transaction ID, ensuring the correctness and orderliness of transaction processing.

[0044] Optionally, the MSI transaction identification module can automatically identify and filter out MSI type transactions in mixed transaction flows containing various types such as ordinary DMA transactions and MSI transactions. It can accurately distinguish between MSI and ordinary DMA transactions without manual configuration and intervention, effectively separating MSI transactions from other transactions and effectively solving the problem that traditional verification methods cannot specifically handle MSI translation processes.

[0045] Optionally, the translation result acquisition and path fingerprint extraction module can acquire the final output result of the device under test after translating the address of the MSI transaction execution. At the same time, it can construct the corresponding translation path fingerprint based on the internal state information during the translation process, forming complete data containing result and process characteristics. Thus, it can not only obtain the final result such as the translated address and data, but also restore the complete execution link and path characteristics of the address translation, realizing the upgrade from the traditional "result verification" to "result + execution path" dual verification, which greatly improves the verification depth and completeness.

[0046] Optionally, the verification module can compare the expected translation result and expected translation path fingerprint obtained by independent calculation with the actual output translation result and translation path fingerprint of the device under test, forming a closed-loop automated verification mechanism to ensure that the translation result of the device under test is correct and the translation path fingerprint meets the specification requirements. This effectively avoids errors and omissions caused by manual comparison and improves the efficiency of fault location and the accuracy of verification.

[0047] For example, such as Figure 2 As shown, this application provides an MSI address translation simulation method, which specifically includes the following steps: Step 1: Dynamic MSI address range learning and semantic model construction.

[0048] During the simulation initialization and page table update phases, the system automatically identifies the valid MSI remapping target space by scanning the DeviceContext and parsing MSI-PT entries, thereby constructing an IMSIC valid address database. At the same time, it extracts the interrupt file number, vector range, and priority interval to construct an interrupt file semantic model.

[0049] Step 2: Semantic-driven MSI transaction generation.

[0050] Based on the semantic model constructed in step 1, an MSI write transaction containing DeviceID, PASID, and multi-stage nested addresses (GVA / GPA / HPA) is constructed using a parameter combination optimization engine. The generated address and data fields must be constrained by the interrupt file structure to ensure that the stimuli can directionally cover specific translation path fingerprints.

[0051] Step 3: Transaction identification and semantic decoupling.

[0052] The system monitors the input transaction flow in real time, matches the request address with the address database maintained in step 1, and automatically identifies MSI type transactions. Semantic decomposition is performed on the identified transactions, decoupling their physical attributes (address / data) from their interrupt semantic attributes (target file / vector / priority) to create structured dedicated data objects.

[0053] Step 4: IOMMU translation execution and path state extraction.

[0054] The driver performs address translation for the IOMMU under test and monitors and records the page table traversal level, First-stage / Second-stage (G / S-stage) trigger flags, and IOTLB status in real time during execution. This multi-dimensional status information is encoded into a translation path fingerprint to characterize the structural features of the hardware execution process.

[0055] Step 5: Progressive exception scenario injection and priority verification.

[0056] A hierarchical approach is adopted to sequentially inject single-phase faults, nested two-phase faults, and MSI-PT superimposed faults. By simulating extreme scenarios with multiple faults coexisting, the internal fault decision-making logic of the IOMMU is verified to conform to the priority reporting rules defined in the specification.

[0057] Step 6: Derivation of the reference model structure and expected results.

[0058] The reference model unit synchronously reads the configuration status and performs independent calculations on transactions with the same transaction identifier (ID). In addition to calculating the expected translation results and deriving the theoretical anomaly priority, the model also needs to generate corresponding theoretical path fingerprints to provide a reference benchmark for subsequent structural-level comparisons.

[0059] Step 7: Automated verification of structural closed-loop consistency.

[0060] Based on transaction identifiers, the actual RTL output is compared with the model's expected results across multiple dimensions. Verification includes address consistency, data consistency, exception type consistency, and path fingerprint consistency. By comparing fingerprint codes, it is ensured that the hardware translation process logic fully matches the specification semantics.

[0061] Step 8: Multidimensional correlation coverage statistics and feedback optimization.

[0062] Establish a coverage matrix that associates "translation path fingerprint × interrupted file" and "anomaly type × translation stage". Identify areas with missing coverage and input them as feedback vectors into the generation module in step 2. Dynamically adjust the excitation distribution weights until the coverage reaches a preset threshold or all anomaly paths are verified.

[0063] The system described above is driven by the semantics of the interrupt target, constructing a semantic, full-link, closed-loop simulation verification process. It can accurately distinguish between MSI and ordinary DMA transactions, realize dual verification from the result to the translation path fingerprint, and comprehensively cover complex scenarios such as single / multi-stage, normal / abnormal, multi-address space, and multi-interrupt target. It significantly improves the verification granularity, completeness, and automation, effectively reduces the cost of manual comparison, improves the efficiency of fault location and the credibility of verification, and efficiently and reliably realizes MSI address translation simulation.

[0064] In some embodiments, identifying MSI transactions in a mixed transaction stream includes: The MSI address range is determined by scanning the DeviceContext and / or resolving MSI-PT entries; Identify MSI transactions in mixed transaction streams based on MSI address ranges.

[0065] Specifically, in this embodiment, the MSI transaction identification module can determine the legitimate MSI address range by scanning the DeviceContext and / or parsing the MSI-PT. Based on the determined MSI address range, it can accurately identify transactions of the MSI type in a mixed transaction flow containing multiple transactions such as DMA and MSI, avoiding misjudgments or missed detections, and ensuring that subsequent translation, acquisition, and verification processes only target valid MSI transactions. Optionally, when the page table or device context is updated, the MSI address range can be refreshed synchronously to adapt to changes in system runtime configuration, ensuring that the identification logic always remains consistent with the hardware configuration.

[0066] The system described in the above embodiment dynamically determines the legitimate MSI address range by scanning the device context and parsing MSI-PT entries. Based on this, it accurately identifies MSI transactions in mixed transaction flows. It can automatically obtain the effective address range without manual preset configuration, effectively avoiding transaction misjudgment and missed detection, and ensuring that subsequent translation, collection and verification processes are only executed for valid MSI transactions. At the same time, it supports dynamic refreshing of the address range at runtime, always keeping it synchronized with the hardware configuration, which improves the accuracy, stability and environmental adaptability of MSI transaction identification.

[0067] In some embodiments, the MSI transaction identification module is also used for: The identified MSI transactions are semantically decomposed to obtain physical attributes and interrupt semantic attributes. The physical attributes include address, data, and transaction length, while the interrupt semantic attributes include interrupt file number, interrupt vector number, and interrupt priority.

[0068] Specifically, in this embodiment, after identifying an MSI transaction, the MSI transaction identification module can also perform semantic decomposition processing on the MSI transaction, that is, split the MSI transaction into two parts: physical attributes and interrupt semantic attributes. The physical attributes include address, data, and transaction length; the interrupt semantic attributes include interrupt file number, interrupt vector number, and interrupt priority. This provides a directly comparable semantic basis for subsequent translation result verification, interrupt target consistency verification, and anomaly correctness verification, so that the MSI transaction changes from a simple address write operation to an understandable and verifiable structured interrupt behavior, improving verification accuracy and traceability.

[0069] The system described in the above embodiment can transform low-level address write operations into resolvable and verifiable high-level interrupt behaviors by structurally decomposing the identified MSI transactions into physical attributes and interrupt semantic attributes. This provides clear and direct semantic basis for subsequent translation result verification, interrupt target consistency verification, and anomaly correctness verification, significantly improving verification depth, verification accuracy, and problem traceability. It upgrades MSI address translation verification from physical layer comparison to semantic layer closed-loop verification.

[0070] In some embodiments, constructing a translation path fingerprint includes: A translation path fingerprint is constructed based on the state information during the translation process; the state information during the translation process includes at least one of the following: page table traversal level, translation stage trigger state, IOTLB hit state, and MSI-PT participation state encoding.

[0071] Specifically, in this embodiment, the translation result acquisition and path fingerprint extraction module can construct a translation path fingerprint based on real-time status information such as page table traversal level, translation stage trigger status, IOTLB hit status, and MSI-PT participation status encoding during the MSI address translation process. This transforms the originally invisible internal translation process into an extractable and comparable path fingerprint, realizing dual verification from "result verification" to "result + process". This not only makes the verification results more comprehensive and significantly improves the verification depth and completeness, but also allows for quick differentiation between result errors and path logic errors, significantly improving debugging efficiency and traceability.

[0072] For example, the translation result acquisition and path fingerprint extraction module in this embodiment can not only acquire address translation results, but also extract the structural features of the translation path fingerprint. Specifically, the result acquisition stage obtains the final host physical address (HPA), the updated MSI data field, and fault output information; the translation path fingerprint generation stage extracts the internal state of the device under test during the translation process, including page table traversal level, G-stage / S-stage trigger flags, IOTLB hit or missing status, and whether MSI-PT participates in the translation. This state is then encoded into a multi-dimensional feature vector form of the translation path fingerprint code, which is used for structural comparison with the derived path, thereby improving the verification dimension from result consistency to process consistency.

[0073] The system described in the above embodiment constructs an enable and comparable translation path fingerprint based on multidimensional state information during the translation process. It transforms the internally invisible address translation process into quantifiable feature information, achieving a complete representation of the execution path while completing result collection. Through dual verification of results and process, it significantly improves the verification depth and completeness, can quickly distinguish between result errors and path logic errors, significantly improves debugging efficiency and problem traceability, and realizes the improvement of verification dimension from result consistency to process consistency.

[0074] In some embodiments, the expected translation result and the expected translation path fingerprint are obtained independently based on the RISC-VIOMMU specification and the AIA interrupt remapping rule.

[0075] Specifically, in this embodiment, the verification module is used to perform consistency verification on the translation results and translation path fingerprints output by the device under test based on the expected translation results and expected translation path fingerprints generated by the reference model unit. Optionally, in this embodiment, the expected translation results and expected translation path fingerprints required for verification are not obtained from the device under test, nor are they simply configured. Instead, they are generated entirely according to the RISC-VIOMMU official specification and AIA interrupt remapping rules, through independent algorithms and independent logical operations. They are completely isolated from the implementation path of the device under test, thereby enabling objective and impartial detection of whether the RTL design is compliant, and significantly improving the verification credibility.

[0076] For example, it can follow the RISC-VIOMMU specification and AIA interrupt remapping rules to maintain semantic consistency with the hardware design, but it can be built using independent algorithms and independent implementation paths, without relying on the logic code of the device under test.

[0077] The system described above generates expected translation results and expected translation path fingerprints independently based on the RISC-VIOMMU specification and AIA interrupt remapping rules. This enables it to objectively and fairly detect whether the RTL design is compliant, effectively avoid the propagation of common source errors, and significantly improve the accuracy, authority, and credibility of the verification.

[0078] In some embodiments, the verification module is also used to perform consistency verification on the exception type and interrupt target, and output the verification result.

[0079] Specifically, in this embodiment, the verification module can not only verify the translation results and translation path fingerprints output by the device under test based on the expected translation results and expected translation path fingerprints, but also perform consistency verification on the exception type and interrupt target. Optionally, the exception type consistency verification compares the exception type output by the device under test with the inferred theoretical exception type to ensure that the exception capture and error code definition conform to the specifications. Optionally, the interrupt target consistency verification checks whether the interrupt target ultimately pointed to by the device under test completely matches the inferred expected target. This expands the verification dimension from traditional address data to the exception semantics and interrupt target level, ensuring that the RTL design not only has correct results, but its exception handling logic and interrupt intent also fully comply with the RISC-VIOMMU and AIA specifications, making the verification dimension more complete. In addition, through accurate comparison of exception type and interrupt target, it is possible to quickly distinguish whether it is a translation logic error, an exception judgment error, or an interrupt target mapping error, achieving accurate problem location, significantly reducing debugging complexity and time cost, and improving fault location accuracy.

[0080] The system described in the above embodiment performs consistency verification between the exception type and the interruption target through the verification module, expanding the verification dimension from traditional address data to the exception semantics and interruption business intent level, which significantly improves the verification integrity and design reliability. At the same time, through accurate comparison of exception type and interruption target, error type can be accurately distinguished, the root cause of the problem can be quickly located, the debugging complexity can be effectively reduced, and the verification efficiency and fault location accuracy can be improved.

[0081] In some embodiments, the MSI address translation emulation system further includes: The abnormal path construction module is used to modify page table entries, permission bits, and MSI-PT table entries to construct abnormal scenarios without changing the MSI transaction semantics.

[0082] Specifically, the MSI address translation simulation system in this embodiment also includes an abnormal path construction module. Optionally, the abnormal path construction module can actively construct various address translation abnormal scenarios by modifying configuration information such as page table entries, permission control bits, and MSI-PT entries, while maintaining the original interrupt semantics of MSI transactions, to achieve full verification of the abnormal handling logic. That is, the abnormal path construction module can flexibly construct various abnormal paths, such as page table abnormalities, permission violations, illegal addresses, and MSI-PT mapping errors, without changing the core interrupt semantics such as interrupt file number, interrupt vector number, and interrupt priority, by only modifying address translation-related configurations such as page table entries, permission control bits, and MSI-PT entries, to simulate various boundary and extreme fault scenarios. Since the original interrupt semantics of MSI transactions are maintained throughout the construction process, it can ensure that verification can still be completed based on the original semantic benchmark after an abnormality is triggered, achieving full coverage of IOMMU abnormal judgment, priority reporting, and fault handling logic, fully verifying the stability and correctness of the design under abnormal conditions, and improving the operational reliability of the chip in real complex environments.

[0083] For example, in this embodiment, the abnormal path construction module can adopt a hierarchical progressive fault injection strategy, injecting faults step by step in the order of single-stage faults, double-stage nested faults, and MSI-PT superimposed faults, focusing on verifying the consistency between IOMMU abnormal priority determination and abnormal reporting. Optionally, the abnormal path construction module can also support the construction of conflict-type fault scenarios, simulating typical boundary scenarios such as valid addresses but invalid MSI-PT permissions, to accurately verify the accuracy of IOMMU abnormal determination. Optionally, the abnormal path construction module maintains the original interrupt semantics of MSI transactions unchanged throughout the construction of abnormal scenarios, ensuring that after an abnormality is triggered, the system can still rely on the original interrupt semantic benchmark to complete subsequent verification work, without disrupting the coherence and accuracy of the verification logic due to scenario construction. At the same time, it can comprehensively cover the verification scenarios of core logic such as IOMMU abnormal judgment, abnormal priority reporting, and fault response processing, fully verifying the compliance and operational stability of the processing logic of the device under test under various abnormal conditions, and further improving the operational reliability of the chip in actual complex application environments.

[0084] The system described in the above embodiment modifies page table entries, permission bits, and MSI-PT entries to construct abnormal scenarios without changing the MSI transaction semantics through the abnormal path construction module. This comprehensively covers various translation anomalies and priority determination scenarios, fully verifying the IOMMU anomaly handling mechanism without disrupting the continuity of the verification logic, and significantly improving the stability, robustness, and design reliability of the chip in complex environments.

[0085] In some embodiments, the MSI address translation emulation system further includes: The association coverage modeling and feedback module is used to construct a multi-dimensional association coverage matrix based on translation path fingerprints, exception types, and interruption targets. Based on the multi-dimensional association coverage matrix, unverified translation scenarios are identified, and the unverified translation scenarios are fed back to the MSI transaction generation module.

[0086] Specifically, in this embodiment, the MSI address translation simulation system further includes an association coverage modeling and feedback module. Optionally, the association coverage modeling and feedback module constructs a multi-dimensional association coverage matrix using translation path fingerprints, anomaly types, and interruption targets as dimensions; then, based on the constructed multi-dimensional association coverage matrix, it accurately identifies translation scenarios that have not yet been covered or verified, and feeds back the missing scenario information to the MSI transaction generation module to guide subsequent stimulus generation, thereby effectively improving coverage and verification completeness and avoiding verification omissions.

[0087] For example, in this embodiment of the application, the association coverage modeling and feedback module constructs a two-dimensional coverage matrix model of translation path fingerprints and interruption targets, which is used to statistically analyze the combined coverage of different interruption file numbers corresponding to different translation path fingerprint types; at the same time, it constructs a multi-dimensional association coverage matrix such as exception type and translation stage, IOTLB status and interrupt priority, and transforms the uncovered feature space into constraint weights of the incentive generation module through feedback loop, and adopts a weighted random evolution strategy to realize automatic traversal and fast convergence of the verification space.

[0088] The system described in the above embodiment can accurately identify unverified translation scenarios and feed them back to the MSI transaction generation module to optimize stimulus generation by constructing a multi-dimensional association coverage matrix that combines translation path fingerprints, exception types, and interruption targets. This effectively improves coverage and verification completeness and avoids verification omissions.

[0089] For example, the overall framework diagram and workflow of the MSI address translation simulation system in this application embodiment are as follows: Figure 3 , Figure 4 and Figure 5 As shown, by establishing a dedicated MSI transaction modeling mechanism, the verification granularity is effectively refined. Simultaneously, an automated closed-loop verification mechanism between the translation result and the interrupt target is constructed. Coupled with a systematic scheme for constructing abnormal path combination scenarios, the verification coverage and completeness of the MSI address translation function are comprehensively improved. At the same time, the cost of manual analysis and debugging is significantly reduced, and the overall verification efficiency is significantly improved. Unlike general DMA address translation verification systems, its core lies in constructing a semantically driven transaction generation, dynamic identification, path modeling, and consistency closed-loop verification system based on the coupled translation characteristics between the MSI address and the interrupt target. Optionally, Figure 4The semantic-driven MSI transaction generation module is the MSI transaction generation module; the transaction identification and semantic decoupling module is the MSI transaction identification module; the IOMMU simulation interface module is the synchronization interface module; and the consistency verification module is the verification module.

[0090] This invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the MSI address translation simulation method provided by the above methods. The method includes: generating MSI transactions based on an interrupt target semantic model; the interrupt target semantic model includes interrupt target semantic information and a mapping relationship between the interrupt target semantic information and MSI addresses and data fields; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority, and address space type; synchronizing the configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test; identifying MSI transactions in a mixed transaction flow; collecting the translation results after the device under test performs address translation on the MSI transactions and constructing a translation path fingerprint; and verifying the translation results and translation path fingerprint output by the device under test based on the expected translation results and the expected translation path fingerprint.

[0091] This invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program performs the MSI address translation simulation method provided by the above methods. The method includes: generating an MSI transaction based on an interrupt target semantic model; the interrupt target semantic model includes interrupt target semantic information and a mapping relationship between the interrupt target semantic information and MSI addresses and data fields; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority, and address space type; synchronizing the configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test; identifying MSI transactions in a mixed transaction flow; collecting the translation results after the device under test performs address translation on the MSI transactions and constructing a translation path fingerprint; and verifying the translation results and translation path fingerprint output by the device under test based on the expected translation results and the expected translation path fingerprint.

[0092] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A message signal interrupt MSI address translation simulation system, characterized in that, include: The message signal interruption MSI transaction generation module is used to generate MSI transactions based on the interruption target semantic model; The interrupt target semantic model includes interrupt target semantic information and the mapping relationship between the interrupt target semantic information and MSI address and data field; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority and address space type; The synchronization interface module is used to synchronize configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test. The MSI transaction identification module is used to identify MSI transactions in mixed transaction streams; The translation result acquisition and path fingerprint extraction module is used to acquire the translation result of the MSI transaction execution address translated by the device under test and construct the translation path fingerprint; The verification module includes a reference model unit, which is used to perform consistency verification on the translation results and translation path fingerprints output by the device under test based on the expected translation results and expected translation path fingerprints generated by the reference model unit.

2. The MSI address translation simulation system according to claim 1, characterized in that, The identification of MSI transactions in a mixed transaction stream includes: The MSI address range is dynamically determined by scanning the DeviceContext and / or parsing the MSI-PT entries of the interrupt page table. Based on the MSI address range, MSI transactions are identified in the mixed transaction flow.

3. The MSI address translation simulation system according to claim 1, characterized in that, The MSI transaction identification module is also used for: The identified MSI transactions are semantically decomposed to obtain physical attributes and interrupt semantic attributes; wherein, the physical attributes include address, data and transaction length, and the interrupt semantic attributes include interrupt file number, interrupt vector number and interrupt priority.

4. The MSI address translation simulation system according to claim 1, characterized in that, The translation path fingerprint is obtained based on state information during the translation process; the state information includes at least one of the following: Page table traversal level, translation phase trigger state, input / output conversion backup buffer (IOTLB) hit state, and MSI-PT participation state.

5. The MSI address translation simulation system according to claim 1, characterized in that, The expected translation result and the expected translation path fingerprint are obtained independently based on the Reduced Instruction Set Computer Input / Output Memory Management Unit (RISC-VIOMMU) specification and the Advanced Interrupt Architecture (AIA) interrupt remapping rules, and are independent of the implementation structure of the device under test.

6. The MSI address translation simulation system according to claim 1, characterized in that, The verification module is also used to perform consistency verification on exception types and interrupt targets, and output the verification results.

7. The MSI address translation simulation system according to any one of claims 1-6, characterized in that, The MSI address translation simulation system also includes: The abnormal path construction module is used to modify page table entries, permission bits, and MSI-PT table entries to construct abnormal scenarios without changing the MSI transaction semantics.

8. The MSI address translation simulation system according to any one of claims 1-6, characterized in that, The MSI address translation simulation system also includes: The association coverage modeling and feedback module is used to construct a multi-dimensional association coverage matrix based on translation path fingerprint, anomaly type and interruption target, determine unverified translation scenarios based on the multi-dimensional association coverage matrix, and feed back the unverified translation scenarios to the MSI transaction generation module to drive subsequent MSI transaction generation.

9. An MSI address translation simulation method, characterized in that, include: Generate MSI transactions based on the interruption target semantic model; The interrupt target semantic model includes interrupt target semantic information and the mapping relationship between the interrupt target semantic information and MSI address and data field; the interrupt target semantic information includes at least one of the following: interrupt file number, interrupt vector number, priority and address space type; Synchronize the configuration information, operating status, and transaction semantics between the MSI address translation simulation system and the device under test; Identify MSI transactions in mixed transaction flows; Collect the translation results of the MSI transaction execution address translation by the device under test and construct the translation path fingerprint; Based on the reference model unit, the expected translation result and the expected translation path fingerprint are generated, and the consistency of the translation result and the translation path fingerprint output by the device under test is verified.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the MSI address translation simulation method as described in claim 9.

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