An interactive circuit experiment simulation method, system and computer program product

Abstract

The application belongs to the field of computer-aided teaching, and discloses a simulation method and system of interactive circuit experiment and a computer program product, comprising: randomly generating the number of circuit nodes, and planning the circuit layout according to the number of nodes; forming an initial node full connection matrix according to the circuit layout by adopting the three-short principle; eliminating the cross connection in the grid in the node full connection matrix, and randomly removing part of the connection between the nodes connected to each other with a preset probability, thereby forming different node connection matrices; generating different circuit topology graphs according to the circuit layout and the different node connection matrices; adding circuit components to the circuit topology graphs to obtain circuit diagrams; and generating an interactive experiment interface for users to conduct independent experiments according to the circuit topology graphs or the circuit diagrams in combination with the knowledge points related to the circuit simulation experiment, so as to overcome the problem that the existing circuit simulation teaching platform cannot meet the personalized experiment or interactive exploration of students due to the fixed circuit diagram.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided instruction, specifically relating to a simulation method, system, and computer program product for interactive circuit experiments. Background Technology

[0002] In the study of electrical engineering, students need to deepen their understanding of circuit theory through circuit simulation and enhance their learning through practical operation. Traditionally, these experiments usually rely on physical experiment kits, which not only require the purchase of a large amount of equipment, but each kit can often only serve 1 to 3 students at a time. Students are also restricted to conducting experiments in specific locations, making it difficult to conduct experiment preparation and review at any time.

[0003] Circuit simulation platforms allow users to freely build and test circuits in a virtual environment, significantly reducing experimental costs and space limitations. However, currently common online professional circuit simulation software, such as SPICE, LTspice, Multisim, and PSpice, while providing powerful analysis functions and professional component libraries, are designed with professional applications in mind and are not suitable for teaching beginners. When using these software programs, students can usually only build circuits based on known circuit structures, easily becoming confined to fixed patterns in textbooks or lab manuals, which is not conducive to cultivating students' active exploration of circuit topologies and systematic design capabilities.

[0004] Among existing teaching-oriented simulation software, CN113011120A discloses an electronic circuit simulation system, which consists of two parts: a circuit simulation platform and a computing engine. The computing engine is deployed on the server as a plug-in, while the simulation platform has built-in typical experimental scripts, instructions, and component descriptions. Users can build target circuits on the platform, automatically generate SPICE scripts and send them to the server, and the computing engine completes the simulation and returns the results.

[0005] However, the aforementioned system essentially merely migrates the traditional manual, fixed-case simulation model online. While it provides convenient simulation tools and teaching resources, it doesn't change the passive learning mode of students imitating known circuits. Students still operate within known circuit structures or under explicit guidance, easily falling into fixed mindsets and lacking the ability to explore and analyze the circuit topology itself, resulting in poor teaching quality. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a simulation method, system, and computer program product for interactive circuit experiments.

[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a simulation method for interactive circuit experiments, comprising: Step 1: In response to the user's command to start the circuit simulation experiment, randomly generate the number of circuit nodes and plan the circuit layout according to the number of circuit nodes; in the circuit layout, the nodes are distributed in a matrix so that four adjacent nodes form a grid. Step 2: Based on the circuit layout, form an initial fully connected node matrix using the three short principles; the three short principles mean that each node can only be connected to its adjacent nodes and diagonal nodes. Step 3: Eliminate the cross connections within the grid in the initial fully connected node matrix to obtain a node connection matrix without cross connections; Step 4: For the non-intersecting node connection matrix, randomly remove some connections between interconnected nodes with a preset probability, and constrain each node to have at least two connections, thereby forming different node connection matrices. Step 5: Generate different circuit topology diagrams based on the circuit layout and different node connection matrices; Step 6: Add circuit components to the circuit topology diagram to obtain the circuit diagram; Step 7: Based on the circuit topology or circuit diagram, and in conjunction with the relevant knowledge points of the circuit simulation experiment, generate a corresponding interactive experimental interface for users to conduct experiments.

[0008] Optionally, the step of planning the circuit layout according to the number of circuit nodes includes: Take the square root of the number of circuit nodes and round up to obtain the initial number N of each row and column in the circuit layout. If N*(N-1) is less than the number of circuit nodes, a square circuit layout is adopted; in the square circuit layout, the number of nodes in each row and each column is N; If N*(N-1) is not less than the number of circuit nodes, a rectangular circuit layout is adopted; in the rectangular circuit layout, the number of nodes in each row is N-1 and the number of nodes in each column is N.

[0009] Optionally, step 2 specifically includes: Step 2-1: Construct a node connection matrix based on the circuit layout. First, initialize all elements of the node connection matrix to 0. The value of the element in the p-th row and q-th column of the node connection matrix represents the number of connections between the p-th node and the q-th node in the circuit layout; p∈[1,2,…,num], q∈[1,2,…,num], and num is the number of circuit nodes. Step 2.2: Traverse the elements of the node connection matrix based on the three shortest principle to form an initial fully connected node matrix; wherein, when traversing each element, if the two nodes corresponding to its row and column are horizontally adjacent or vertically adjacent, then the element is reassigned a value of 2; if the two nodes corresponding to its row and column are located in the same grid and are diagonally adjacent, then the element is reassigned a value of 1.

[0010] Optionally, step 3 specifically includes: Traverse all nodes in the circuit layout, find all pairs of nodes with a row difference and a column difference of 1, find diagonally adjacent pairs of nodes, and determine whether each pair of nodes is connected based on the current node connection matrix. Using a grid as a unit, determine whether there are multiple oblique connections in each grid of the circuit layout; if so, update the current node connection matrix to delete the redundant oblique connections in the grid, and randomly retain only one oblique connection.

[0011] Optionally, in step 4, randomly removing some connections between interconnected nodes with a preset probability includes: for two interconnected nodes in the circuit layout, randomly generating a number between 0 and 1; if the number is greater than the preset probability, updating the current node connection matrix to delete 1-2 connections between the two nodes.

[0012] Optionally, in step 4, constraining each node to be connected to at least two nodes includes: based on the current node connection matrix, finding a node with fewer than 2 connected nodes, and randomly selecting 1-2 nodes from the nodes adjacent to that node that have not been connected to it for connection.

[0013] Optionally, before generating different circuit topology diagrams based on the circuit layout and different node connection matrices, the method further includes: checking whether there are unconnected adjacent boundary nodes in the node connection matrix; the adjacent boundary nodes are nodes located on the boundary of the circuit layout and adjacent to each other; if there are unconnected pairs of adjacent boundary nodes, then adding a connection between the pairs of adjacent boundary nodes in the node connection matrix so that the boundary of the circuit layout forms a closed connection.

[0014] Secondly, the present invention provides an interactive circuit experiment simulation system, comprising: multiple experimental modules and a random circuit topology generation module; each experimental module conducts circuit simulation experiment teaching for a specific circuit knowledge point; The experimental module is used to respond to the user's command to start the circuit simulation experiment and call the random circuit topology generation module. The random circuit topology generation module is used to randomly generate the number of circuit nodes and plan the circuit layout according to the number of circuit nodes; the number of circuit nodes is randomly generated according to a preset numerical range; in the circuit layout, the nodes are distributed in a matrix, so that four adjacent nodes form a grid. The random circuit topology generation module is further configured to: form an initial fully connected node matrix based on the circuit layout using the "three shorts" principle; eliminate cross connections within the grid in the initial fully connected node matrix to obtain a non-crossing node connection matrix; for the non-crossing node connection matrix, randomly remove connections between interconnected nodes with a preset probability, and constrain each node to be connected to at least two other nodes, thereby forming different node connection matrices; and generate different circuit topologies based on the circuit layout and the different node connection matrices; wherein, the "three shorts" principle means that each node can only be connected to its adjacent nodes and diagonal nodes; The experimental module includes: an experimental circuit generation unit and an interactive experimental unit; The experimental circuit generation unit includes a circuit topology generation subunit and a circuit component addition subunit; the circuit topology generation subunit is used to call the random circuit topology generation module to generate a random circuit topology diagram, and the circuit component addition subunit is used to add circuit components to the circuit topology diagram to obtain a circuit diagram. The interactive experimental unit is used to generate a corresponding interactive experimental interface based on the circuit topology diagram or circuit diagram and the knowledge points related to the circuit simulation experiment, so that users can conduct experiments.

[0015] Optionally, the multiple experimental modules include three main categories of experimental modules: component verification experiments, circuit law and theorem verification experiments, and circuit analysis method verification experiments. The component verification experiments include: ideal voltage source experiment, ideal current source experiment, voltage-controlled voltage source experiment, voltage-controlled current source experiment, current-controlled voltage source experiment, current-controlled current source experiment, resistor VAR experiment, resistor series-parallel experiment, resistor Y-type-Δ equivalent transformation experiment, equivalent resistance experiment, capacitor VAR experiment, capacitor series-parallel experiment, capacitor Y-type-Δ equivalent transformation experiment, equivalent inductance experiment, capacitor breakdown experiment, capacitor charge-discharge experiment, inductor VAR experiment, inductor series-parallel experiment, inductor Y-type-Δ equivalent transformation experiment, equivalent inductance experiment, inductive coupling experiment, AC to DC conversion experiment, impedance VAR experiment, impedance series-parallel experiment, impedance Y-type-Δ equivalent transformation experiment, and equivalent impedance experiment. The circuit law and theorem verification experiments include: energy conservation law verification experiment, charge conservation law verification experiment, magnetic flux conservation law verification experiment, OL verification experiment, KCL verification experiment, KVL verification experiment, switching law verification experiment, homogeneity theorem verification experiment, superposition theorem verification experiment, substitution theorem verification experiment, Thevenin theorem verification experiment, Norton theorem verification experiment, maximum power transfer theorem verification experiment, Tellegen theorem verification experiment, reciprocity theorem verification experiment, complex power conservation theorem verification experiment, and maximum power product theorem verification experiment. The circuit analysis method verification experiments include: external power supply method experiment, volt-ampere relationship method experiment, open circuit and short circuit method experiment, three-element method experiment, zero input response experiment, zero state response experiment, full response experiment, phasor method experiment, T-type decoupling experiment, three-phase circuit experiment, network function experiment, quality factor experiment, resonant circuit experiment, filter circuit experiment, two-port circuit experiment, and characteristic impedance experiment.

[0016] Thirdly, the present invention provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps of the simulation method for the interactive circuit experiment described above.

[0017] The interactive circuit experiment simulation method, system, and computer program product provided by this invention transforms the starting point of circuit learning from a known, fixed circuit structure to a randomly generated, unknown circuit topology. It randomly generates a large number of circuit topology diagrams with different structures but neat and readable layouts (thanks to circuit layout, the three shortest principles, and elimination of wiring intersections). This ensures that students encounter a new circuit diagram each time, requiring active analysis and identification, rather than memorization or copying. This forces students to observe and understand circuits from the most basic node and branch relationships, thereby stimulating their exploration of circuit topology itself, cultivating their analytical thinking, and improving teaching quality. Based on this, this invention generates corresponding interactive experimental interfaces for users to conduct experiments according to the circuit topology diagram or circuit diagram and the relevant knowledge points of the circuit experiment. Students do not need to start building from basic components, thus lowering the operational threshold and allowing them to focus their attention on the core exploration process of observing circuit phenomena, analyzing parameter effects, and understanding the underlying principles. This not only ensures a close alignment between the learning process and teaching objectives but also effectively cultivates students' systematic circuit design and analysis abilities while stimulating their interest in exploration. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a simulation method for an interactive circuit experiment provided by the present invention; Figure 2 The diagram illustrates the relationship between the node connection matrix and the actual connections between nodes. Figure 3The overall process of randomly generating circuit topology diagrams is schematically shown in the diagram. Figure 4 The diagram illustrates the process of adding components to a circuit topology. Figure 5 The interactive experimental interface for KCL verification is illustrated schematically in the figure; Figure 6 The diagram illustrates an extended experiment in the KCL verification experiment. Figure 7 The interactive experimental interface for KVL verification experiments is illustrated schematically in the figure; Figure 8 The diagram illustrates an extended experiment in the KVL verification experiment. Figure 9 The interactive experimental interface of the resistance VAR experiment is schematically shown in the figure. Figure 10 The interactive experimental interface of the capacitance VAR experiment is schematically shown in the figure. Figure 11 The interactive experimental interface of the inductor VAR experiment is schematically shown in the figure. Figure 12 The interactive experimental interface for the series and parallel resistor experiment is shown schematically in the figure. Figure 13 The interactive experimental interface of the Y-type to Δ-type equivalent transformation experiment of resistance is schematically shown in the figure; Figure 14 The interactive experimental interface of the impedance Y-type to Δ-type equivalent transformation experiment is schematically shown in the figure; Figure 15 The interactive experimental interface for the equivalent resistance experiment is shown schematically in the figure. Figure 16 The interactive experimental interface for the equivalent impedance experiment is schematically shown in the figure. Figure 17 The diagram illustrates a Y-type to Δ-type circuit conversion schematic. Figure 18 The diagram illustrates the Y-type to Δ-type circuit conversion formula. Figure 19 The diagram illustrates the specific code implementation of the formulas related to the Y-type to Δ-type circuit conversion; Figure 20 The diagram illustrates the current response displayed on the interactive experimental interface in the three-element method experiment of the basic mode. Figure 21 The diagram illustrates the voltage response displayed on the interactive experimental interface in the three-element method experiment of the basic mode. Figure 22The diagram schematically illustrates the interactive experimental interface of the three-element method experiment in the extended mode; Figure 23 The diagram schematically illustrates the simulation platform interface of an interactive circuit experiment simulation system provided by the present invention; Figure 24 The diagram schematically illustrates the classification of circuit experiments covered by the simulation system for interactive circuit experiments provided by this invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] To overcome the problem that existing circuit simulation teaching platforms only allow students to passively imitate and verify circuit structures under fixed conditions, failing to cultivate their ability to actively explore and analyze circuit topologies, this invention provides an interactive circuit experiment simulation method. (See below) Figure 1 As shown, the method includes the following steps: Step 1: In response to the user's command to start the circuit simulation experiment, randomly generate the number of circuit nodes and plan the circuit layout according to the number of circuit nodes.

[0021] The number of circuit nodes, num, is randomly generated based on a preset numerical range. For example, in the basic simulation mode, the number of circuit nodes, num, can be randomly set to 7~9, and in the extended simulation mode, the number of circuit nodes can be randomly set to 7~200.

[0022] Step 1 involves planning the circuit layout based on the number of circuit nodes. This includes: taking the square root of the number of circuit nodes (num) and rounding it up to obtain the initial number of nodes (N) in each row and column of the circuit layout; if N*(N-1) is less than the number of circuit nodes, a square circuit layout is used, where each row and column has N nodes; if N*(N-1) is not less than the number of circuit nodes, a rectangular circuit layout is used, where each row has N-1 nodes and each column has N nodes. Thus, in the planned circuit layout, the nodes are distributed in a matrix, so that four adjacent nodes form a grid.

[0023] Step 2: Based on the circuit layout, form the initial fully connected node matrix using the three short principles; the three short principles mean that each node can only be connected to its adjacent nodes and diagonal nodes.

[0024] Here, the three-short principle is used to form the initial fully connected node matrix, which can ensure that there are no long connecting lines in the generated circuit topology.

[0025] In one implementation, step 2 can specifically include: Step 2-1: Construct a node connection matrix based on the circuit layout. First, initialize all elements of the node connection matrix to 0. The values ​​of the p-th row and q-th column elements of the node connection matrix represent the number of connections between the p-th node and the q-th node in the circuit layout; p∈[1,2,…,num], q∈[1,2,…,num], and num is the number of circuit nodes. Figure 2 The diagram illustrates the relationship between the node connection matrix and the actual connections between nodes.

[0026] Step 2-2: Traverse the elements of the node connection matrix based on the three short principles to form the initial fully connected node matrix. When traversing each element, if the two nodes corresponding to its row and column are horizontally or vertically adjacent, the element is reassigned a value of 2. If the two nodes corresponding to its row and column are in the same grid and are diagonally adjacent, the element is reassigned a value of 1. This part of the operation reflects the three short principles mentioned above.

[0027] In another implementation, a randomization generation strategy (such as randomly assigning initial values ​​to the node connection matrix) or other graph theory algorithms can be used to generate the initial node connection matrix, and then the "three short principles" can be applied to filter and constrain it.

[0028] Step 3: Eliminate the cross connections within the grid in the initial fully connected node matrix to obtain a node connection matrix without cross connections.

[0029] In one implementation, step 3 can specifically include: Step 3-1: Traverse all nodes in the circuit layout. Find all pairs of nodes with a row difference (difference between row numbers) and a column difference (difference between column numbers) of 1 to find diagonally adjacent pairs of nodes. Then, based on the current node connection matrix (i.e., the node connection matrix after the elements in Step 2-2 have been reassigned), determine whether each pair of nodes is connected (i.e., find connected and diagonally adjacent pairs of nodes). Step 3-2: On a grid-by-grid basis, determine if multiple diagonal connections exist in each grid cell. If so, update the current node connection matrix to remove redundant diagonal connections from that grid, randomly retaining only one diagonal connection. This eliminates cross connections within the grid. To determine if multiple diagonal connections exist in a grid, the diagonal connections can be grouped based on the grids containing the two nodes of the diagonal connection (using the top-left corner coordinates of each grid cell as the key). Diagonal connections belonging to the same grid are grouped together, and then it is determined whether multiple diagonal connections exist in each grid cell.

[0030] Step 4: For the above non-intersecting node connection matrix, randomly remove some connections between interconnected nodes with a preset probability, and constrain each node to have at least two connections, thereby forming different node connection matrices.

[0031] In one implementation, randomly removing some connections between interconnected nodes with a preset probability may include: for two interconnected nodes in the circuit layout, randomly generating a number between 0 and 1; if the number is greater than the preset probability, updating the current node connection matrix to delete 1-2 connections between the two nodes.

[0032] In one implementation, constraining each node to be connected to at least two other nodes can include: based on the current node connection matrix, finding nodes with fewer than 2 connected nodes, and randomly selecting 1-2 nodes from those adjacent nodes that are not currently connected to the node to make a connection.

[0033] In one implementation, after forming the node connection matrix in step 4, it is possible to further check whether there are any unconnected adjacent boundary nodes in the node connection matrix. It is understood that adjacent boundary nodes are nodes located at the boundaries of the circuit layout and are adjacent to each other. If there are pairs of unconnected adjacent boundary nodes, then the connection of the pair of adjacent boundary nodes is added to the node connection matrix so that the boundaries of the circuit layout form a closed connection.

[0034] Specifically, the statement `[rows, cols] = ind2sub(gridsize, 1:num)` is used to convert the node indices of the circuit layout into row and column indices. A clockwise traversal strategy is used to traverse the nodes of the circuit layout. First, the node with row index 1 is found and stored in the boundary array in ascending order of column index. Then, the node in the rightmost column, i.e., the node with row index greater than 1 and column index of gridsize(2) (to avoid adding the node with row index 1 repeatedly), is found and stored in the boundary array in ascending order of row index. The search method for the remaining boundary nodes is the same. Then, according to the order of the node indices in the boundary array, the connection status of each pair of adjacent boundary nodes (including the first and last node pairs to form a closed loop) in the node connection matrix is ​​checked in turn. If there is no connection between a pair of adjacent boundary nodes (i.e., the value of the corresponding element in the node connection matrix is ​​0), the value of the corresponding element in the node connection matrix is ​​modified to 1 to connect the pair of adjacent boundary nodes, thereby ensuring that the boundary of the circuit layout forms a closed connection. Figure 3 The diagram schematically illustrates the overall process of randomly generating circuit topology.

[0035] Step 5: Generate different circuit topologies based on the circuit layout and different node connection matrices.

[0036] Understandably, the circuit layout determines the coordinate position of each node, and the node connection matrix represents the connection relationship between all nodes. Based on these coordinate positions and connection relationships, a circuit topology diagram consisting of nodes and branches can be obtained through graphical processing.

[0037] Step 6: Add circuit components to the circuit topology diagram to obtain the circuit diagram.

[0038] Specifically, when adding circuit components to a circuit topology diagram, the components can be represented by simple graphics, and then these graphical representations are added to the connection lines between two nodes in the circuit topology diagram. This invention does not limit the graphical representation of components. For example, a resistor can be composed of a rectangle and its internal resistance value; a current source can be composed of a circle and a straight line perpendicular to the circuit line; a voltage source can be composed of a circle and a straight line parallel to the circuit line; a controlled current source can be composed of a rhombus and a straight line perpendicular to the circuit line; a controlled voltage source can be composed of a rhombus and a straight line parallel to the circuit line; an inductor is represented by the absolute value of a sine wave; a capacitor is represented by two parallel lines perpendicular to the circuit line; a switch is composed of a small circle and a diagonal line; and a black box is composed of a slightly larger rectangle and the symbol "N" in the center.

[0039] It is understandable that different circuit simulation experiments have different teaching objectives, and therefore require different types and quantities of components. Component configuration information can be defined for each circuit simulation experiment, allowing components to be added to the circuit topology based on this configuration. For example, the configuration information may include: a component list, specifying the types, quantities, positional constraints (such as "randomly select a branch" or "connected in series with the power supply"), and parameter generation ranges (such as resistance and voltage ranges) of components to be added to the circuit topology of the simulation experiment; and addition order and dependency constraint rules, defining the order in which components are added and the dependency constraint rules (such as controlled sources requiring a control branch, switches requiring series connection with the power supply, etc.). Thus, components can be placed sequentially on the connection lines of the circuit topology according to the configured order and rules, and reasonable circuit parameter values ​​(such as node voltage values) can be calculated using circuit theorems.

[0040] Taking the three-element method experiment as an example, the flowchart is as follows: Figure 4As shown. The experimental circuit requires the following components: voltage source, current source, four types of controlled sources (including voltage-controlled current source, current-controlled current source, voltage-controlled voltage source, and current-controlled voltage source), switch, inductor, and capacitor. The steps to generate the circuit diagram are as follows: First, randomly select a circuit line in the circuit topology diagram and add a voltage source (or current source) and a switch. Then, randomly select one of the remaining circuit lines and add an inductor (or capacitor). Next, randomly select a circuit line with a 50% probability and add a controlled voltage source (or controlled current source). Finally, add resistors to all the remaining circuit lines. Here, the operation of randomly adding a controlled source with a 50% probability is the same as the method of randomly removing the connection between any two nodes in step 4 above. A random number is generated first, and then compared with 50%. If the random number exceeds 50%, a controlled voltage source (or controlled current source) is added; otherwise, it is not added. All the above components are stored using the containers.Map data structure. The stored parameters include: the type of the component, such as "voltage" for a voltage source; the parameter value of the component, such as 4V for a voltage source; and the location of the component, such as "P3-P4-1" for a voltage source located on the first line between nodes P3 and P4. This data is stored in the key of the data structure. In addition, describing a controlled source requires two additional parameters: one is the location of the control quantity, such as "P3-P4-1", which indicates that the control quantity is located on the first connection line between nodes P3 and P4; the other is the type of control quantity, such as current control or voltage control.

[0041] Step 7: Based on the circuit topology or circuit diagram, and combined with the relevant knowledge points of circuit simulation experiments, generate the corresponding interactive experimental interface for users to conduct experiments.

[0042] Specifically, the interactive experimental interface can have two interactive modes: First, randomly cover a key parameter in the circuit (such as the current or voltage value of a branch) and provide an input window for students to calculate and fill in the answer. Students can press the check button to judge the correctness of the answer and receive feedback. Second, provide different function buttons for different circuit simulation experiments (such as "solve equivalent resistance", "switch switch state", "view response curve") to support students in analyzing or operating the current circuit, thereby deepening their understanding of knowledge points through active exploration.

[0043] For example, in the equivalent resistance experiment, such as Figure 15 As shown, the simplification steps after pressing the "Solve Equivalent Resistance" button are as follows: First, simplify the parallel resistors to equivalent resistance; then, simplify the series resistors to equivalent resistance; finally, use Y-type to Δ simplification theory to find the Y-type structure in the circuit and convert it to a Δ structure, performing series and parallel simplification after each conversion until the simplest circuit is obtained. A schematic diagram of the Y-type to Δ circuit conversion is shown below. Figure 17As shown, the conversion formula is as follows: Figure 18 As shown, the specific code implementation is as follows: Figure 19 As shown. The denominator variable in line 680 stores... Figure 18 The numerator in the formula. When a Y-type circuit is converted to a delta circuit, the connections change, such as... Figure 17 As shown, it is necessary to determine whether there is a connecting resistor between the nodes involved in the transformation (line 683). If so, the transformed resistor newZ and the original resistor existingZ are connected in parallel using the parallel formula to simplify them into a single resistor (lines 689-692). Figure 18 In the code implementation of the formula shown (corresponding to the calculation of newZ on line 690), the equivalent resistance value between nodes A and B is obtained by dividing the value of the denominator by the resistance value of C. The code logic for calculating the other equivalent resistances is similar.

[0044] For example, in the KCL experiment, such as Figure 5 , 6 As shown, a method combining random assignment and KCL constraints is used to assign current values ​​to each branch in the circuit topology diagram, and the current value of one circuit line is randomly masked for student input and interaction. For example, in the three-element method experiment, in the basic mode, such as... Figure 20 , 21 As shown, the solution addresses the response of dynamic components (capacitors and inductors). The experimental circuit diagram includes the initial steady-state circuit diagram (inductors are equivalent to short circuits, and capacitors are equivalent to open circuits), the equivalent resistance solution circuit diagram (replacing dynamic components with current sources), the zero-state steady-state circuit diagram (the switching state is the opposite of the initial state, inductors are equivalent to short circuits, and capacitors are equivalent to open circuits), and the solution result curves (including three response curves: zero-state response curve, zero-input response curve, and full response curve). Extended modes, such as... Figure 22 As shown, this solution addresses the voltage or current response of any component in a circuit diagram. Compared to the basic mode, it adds a zero-state transient circuit diagram (inductors are equivalent to open circuits, capacitors to short circuits) and a zero-input transient circuit diagram (voltage sources are equivalent to short circuits, current sources to open circuits, inductors to current sources, and capacitors to voltage sources). The voltage and current parameters in the circuit are solved using the nodal voltage method to obtain the desired response values.

[0045] The core of the interactive circuit experiment simulation method provided by this invention lies in its ability to automatically generate arbitrary circuit topologies containing over 100 nodes, forming a universal foundation supporting all circuit experiments. Based on this, the unique "three shorts" principle (i.e., nodes can only connect to adjacent and diagonal nodes) effectively ensures the regularity and aesthetics of the generated circuit topology. Theoretically, cross-node connections can be obtained by simplifying equipotential points, thus guaranteeing that the randomly generated circuit topology includes all possible circuit scenarios. Based on this universal topology, designed component patterns can be randomly added to any circuit line under certain constraints, thereby efficiently generating a rich variety of circuit diagrams.

[0046] Furthermore, this invention designs an extended mode aimed at expanding students' cognitive boundaries and covering various circuit scenarios that may occur in circuit experiments, simulating situations that knowledge points may encounter in real-world applications. At the interactive level, two interactive modes are provided: a) by covering a certain parameter of the circuit, a window is provided for students to calculate and input answers, and to judge their correctness; b) buttons are provided for students to process the circuit accordingly and observe the experimental results. These technical features collectively make this invention suitable for circuit course experimental teaching scenarios. Specifically, on the one hand, this invention supports the generation of circuit topologies with over 100 nodes, ensuring the breadth of students' knowledge in terms of circuit scale; on the other hand, the interactive modes guide students to explore each important circuit knowledge point in depth; in addition, the platform visualizes the experimental simulation results in a graphical way, transforming abstract formulas into intuitive physical images, aligning with engineering thinking, and effectively helping students build a cognitive bridge from theory to practice, deeply understanding the essence of circuits.

[0047] The method provided in this embodiment of the invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc., and is not limited thereto.

[0048] Based on the same inventive concept, the present invention also provides an interactive circuit experiment simulation system, including: multiple experimental modules and a random circuit topology generation module; each experimental module conducts circuit simulation experiment teaching for a specific circuit knowledge point.

[0049] The experiment module is used to respond to the user's command to start a circuit simulation experiment and call the random circuit topology generation module. The random circuit topology generation module is used to randomly generate the number of circuit nodes and plan the circuit layout based on the number of circuit nodes. The number of circuit nodes is randomly generated according to a preset numerical range. In the circuit layout, the nodes are distributed in a matrix, so that four adjacent nodes form a grid.

[0050] The random circuit topology generation module is also used to form an initial fully connected node matrix based on the circuit layout using the three short principles; eliminate cross connections within the grid in the initial fully connected node matrix to obtain a non-crossing node connection matrix; for the non-crossing node connection matrix, randomly remove some connections between interconnected nodes with a preset probability, and constrain each node to be connected to at least two nodes, thereby forming different node connection matrices; generate different circuit topologies based on the circuit layout and different node connection matrices; where the three short principles mean that each node can only be connected to its adjacent nodes and diagonal nodes.

[0051] The experimental module includes: an experimental circuit generation unit and an interactive experimental unit; The experimental circuit generation unit includes a circuit topology generation subunit and a circuit component addition subunit. The circuit topology generation subunit is used to call the random circuit topology generation module to generate a random circuit topology diagram, and the circuit component addition subunit is used to add circuit components to each circuit topology diagram to obtain multiple circuit diagrams. The interactive experimental unit is used to generate a corresponding interactive experimental interface based on the circuit topology diagram or circuit diagram and the knowledge points related to circuit simulation experiments, so that users can conduct experiments.

[0052] In practical applications, the interactive circuit experiment simulation system provided by this invention can be a desktop application containing multiple experimental modules. These modules all generate circuit topology diagrams by calling a random circuit topology generation module. As this system embodiment is fundamentally similar to the method embodiment described above, the description is relatively simple. For the specific implementation methods of each module, please refer to the relevant descriptions in the method embodiment described above, which will not be repeated here.

[0053] The system described above can be developed using the MATLAB App Designer integrated environment to form a desktop application. Therefore, there is no need to deploy and maintain a separate server; the main development cost is the initial manpower cost, while maintenance costs are low. Furthermore, the platform's interface is intuitive and user-friendly, with a clear functional layout and a detailed user manual. Students can quickly get started without prior software training, achieving a "zero adaptation period" and allowing them to focus on the circuit experiments themselves, thus effectively improving learning efficiency.

[0054] The aforementioned system has undergone systematic validation, demonstrating its high feasibility and effectiveness across various teaching scenarios. Specifically, Figure 23 The simulation platform interface of the system is illustrated schematically. The system covers three main categories of circuit experiments, such as... Figure 24As shown, the system includes component verification experiments, circuit law and theorem verification experiments, and circuit analysis method verification experiments. The entire system covers 58 typical experimental cases, including: ideal voltage source experiment, ideal current source experiment, voltage-controlled voltage source experiment, voltage-controlled current source experiment, current-controlled voltage source experiment, current-controlled current source experiment, resistor VAR experiment, resistor series-parallel experiment, resistor Y-type-Δ type equivalent transformation experiment, equivalent resistance experiment, capacitor VAR experiment, capacitor series-parallel experiment, capacitor Y-type-Δ type equivalent transformation experiment, equivalent inductance experiment, capacitor breakdown experiment, capacitor charging and discharging experiment, inductor VAR experiment, inductor series-parallel experiment, inductor Y-type-Δ type equivalent transformation experiment, equivalent inductance experiment, inductive coupling experiment, AC to DC conversion experiment, impedance VAR experiment, impedance series-parallel experiment, impedance Y... The experiments include: type-Δ equivalent transformation experiment, equivalent impedance experiment, energy conservation law verification experiment, charge conservation law verification experiment, magnetic flux conservation law verification experiment, OL verification experiment, KCL verification experiment, KVL verification experiment, switching law verification experiment, homogeneity theorem verification experiment, superposition theorem verification experiment, substitution theorem verification experiment, Thevenin's theorem verification experiment, Norton's theorem verification experiment, maximum power transfer theorem verification experiment, Tellegen's theorem verification experiment, reciprocity theorem verification experiment, complex power conservation theorem verification experiment, maximum power product theorem verification experiment, external power supply method experiment, volt-ampere relationship method experiment, open circuit and short circuit method experiment, three-element method experiment, zero-input response experiment, zero-state response experiment, total response experiment, phasor method experiment, T-type decoupling experiment, three-phase circuit experiment, network function experiment, quality factor experiment, resonant circuit experiment, filter circuit experiment, two-port circuit experiment, and characteristic impedance experiment.

[0055] Each experiment targets a key knowledge point, and students can enter the corresponding experimental environment simply by clicking the relevant experiment button. Within this environment, the platform generates a wide variety of random circuit topologies or circuit diagrams related to the knowledge point. Students do not need to start building from basic components, thus lowering the operational threshold and allowing them to focus on the core exploration process of observing circuit phenomena, analyzing parameter effects, and understanding the underlying principles. This invention not only ensures a close alignment between the learning process and teaching objectives but also effectively cultivates students' systematic circuit design and analysis abilities while stimulating their interest in exploration.

[0056] Figure 5 The diagram illustrates the interactive experimental interface for the KCL verification experiment. Figure 6 The diagram illustrates an extended experiment in the KCL verification experiment. Figure 7 The diagram illustrates the interactive experimental interface for KVL verification experiments. Figure 8 The diagram illustrates an extended experiment in this KVL verification experiment. Figure 9The interactive experimental interface of the resistance VAR experiment is shown schematically. Figure 10 The interactive experimental interface of the capacitance VAR experiment is schematically shown in the figure. Figure 11 The interactive experimental interface of the inductive VAR experiment is shown schematically. Figure 12 The diagram schematically illustrates the interactive experimental interface for the series and parallel resistor experiment. Figure 13 The interactive experimental interface for the Y-type to Δ-type equivalent transformation experiment of resistance is schematically shown in the figure. Figure 14 The interactive experimental interface for the impedance Y-type to Δ-type equivalent transformation experiment is schematically shown in the figure. Figure 15 The diagram schematically illustrates the interactive experimental interface for the equivalent resistance experiment. Figure 16 The interactive experimental interface for the equivalent impedance experiment is shown schematically in the figure.

[0057] The simulation system for interactive circuit experiments provided by this invention can also be applied in the following scenarios: (1) Application in educational assessment: One of the core application scenarios of this system is to realize the automated and personalized generation of circuit analysis exercises in online education or examination systems. By randomly generating unique circuit diagrams and automatically calculating standard answers, customized exercises and test questions can be provided for each student, realizing personalized teaching assessment.

[0058] (2) Application in scientific research and advanced teaching: This system can provide an efficient tool for circuit reliability research. By generating different topologies on a large scale and injecting typical faults (such as open circuits and short circuits), the robustness and reliability of various circuit architectures can be systematically and quantitatively evaluated.

[0059] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, executes the steps of the simulation method for the above-described interactive circuit experiment by the computer.

[0060] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0062] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0063] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus (devices), or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects, all of which are collectively referred to herein as "modules" or "systems." Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The computer program may be stored / distributed in a suitable medium, provided with or as part of other hardware, or may take other distribution forms, such as via the Internet or other wired or wireless telecommunications systems.

[0064] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0065] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0066] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0067] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A simulation method for interactive circuit experiments, characterized in that, include: Step 1: In response to the user's command to start the circuit simulation experiment, randomly generate the number of circuit nodes and plan the circuit layout according to the number of circuit nodes; In the circuit layout, the nodes are distributed in a matrix, so that four adjacent nodes form a grid. Step 2: Based on the circuit layout, form an initial fully connected node matrix using the three short principles; the three short principles mean that each node can only be connected to its adjacent nodes and diagonal nodes. Step 3: Eliminate the cross connections within the grid in the initial fully connected node matrix to obtain a node connection matrix without cross connections; Step 4: For the non-intersecting node connection matrix, randomly remove some connections between interconnected nodes with a preset probability, and constrain each node to have at least two connections, thereby forming different node connection matrices. Step 5: Generate different circuit topology diagrams based on the circuit layout and different node connection matrices; Step 6: Add circuit components to the circuit topology diagram to obtain the circuit diagram; Step 7: Based on the circuit topology or circuit diagram, and in conjunction with the relevant knowledge points of the circuit simulation experiment, generate a corresponding interactive experimental interface for users to conduct experiments.

2. The simulation method for interactive circuit experiments according to claim 1, characterized in that, The step of planning the circuit layout based on the number of circuit nodes includes: Take the square root of the number of circuit nodes and round up to obtain the initial number N of each row and column in the circuit layout. If N*(N-1) is less than the number of circuit nodes, a square circuit layout is adopted; in the square circuit layout, the number of nodes in each row and each column is N; If N*(N-1) is not less than the number of circuit nodes, a rectangular circuit layout is adopted; in the rectangular circuit layout, the number of nodes in each row is N-1 and the number of nodes in each column is N.

3. The simulation method for interactive circuit experiments according to claim 1, characterized in that, Step 2 specifically includes: Step 2-1: Construct a node connection matrix based on the circuit layout. First, initialize all elements of the node connection matrix to 0. The value of the element in the p-th row and q-th column of the node connection matrix represents the number of connections between the p-th node and the q-th node in the circuit layout; p∈[1,2,…,num], q∈[1,2,…,num], and num is the number of circuit nodes. Step 2.2: Traverse the elements of the node connection matrix based on the three shortest principle to form an initial fully connected node matrix; wherein, when traversing each element, if the two nodes corresponding to its row and column are horizontally adjacent or vertically adjacent, then the element is reassigned a value of 2; if the two nodes corresponding to its row and column are located in the same grid and are diagonally adjacent, then the element is reassigned a value of 1.

4. The simulation method for interactive circuit experiments according to claim 3, characterized in that, Step 3 specifically includes: Traverse all nodes in the circuit layout, find all pairs of nodes with a row difference and a column difference of 1, find diagonally adjacent pairs of nodes, and determine whether each pair of nodes is connected based on the current node connection matrix. Using a grid as a unit, determine whether there are multiple oblique connections in each grid of the circuit layout; if so, update the current node connection matrix to delete the redundant oblique connections in the grid, and randomly retain only one oblique connection.

5. The simulation method for interactive circuit experiments according to claim 3, characterized in that, In step 4, some connections between interconnected nodes are randomly removed with a preset probability. This includes: for two interconnected nodes in the circuit layout, a number between 0 and 1 is randomly generated. If the number is greater than the preset probability, the current node connection matrix is ​​updated to delete 1-2 connections between the two nodes.

6. The simulation method for interactive circuit experiments according to claim 5, characterized in that, In step 4, constraining each node to be connected to at least two nodes includes: based on the current node connection matrix, finding nodes with fewer than 2 connected nodes, and randomly selecting 1-2 nodes from those adjacent nodes that are not connected to the node to make a connection.

7. The simulation method for interactive circuit experiments according to claim 1, characterized in that, Before generating different circuit topology diagrams based on the circuit layout and different node connection matrices, the method further includes: checking whether there are unconnected adjacent boundary nodes in the node connection matrix; the adjacent boundary nodes are nodes located on and adjacent to the boundaries of the circuit layout; if there are unconnected pairs of adjacent boundary nodes, then adding a connection between the pairs of adjacent boundary nodes in the node connection matrix so that the boundaries of the circuit layout form a closed connection.

8. A simulation system for interactive circuit experiments, characterized in that, It includes multiple experimental modules and a random circuit topology generation module; each experimental module focuses on circuit simulation experiments for teaching a specific circuit knowledge point. The experimental module is used to respond to the user's command to start the circuit simulation experiment and call the random circuit topology generation module. The random circuit topology generation module is used to randomly generate the number of circuit nodes and plan the circuit layout according to the number of circuit nodes; the number of circuit nodes is randomly generated according to a preset numerical range; in the circuit layout, the nodes are distributed in a matrix, so that four adjacent nodes form a grid. The random circuit topology generation module is further configured to form an initial node full connection matrix based on the circuit layout using the three short principles; and to eliminate the cross connections located within the grid in the initial node full connection matrix to obtain a node connection matrix without cross connections. For the non-intersecting node connection matrix, connections between interconnected nodes are randomly removed with a preset probability, and each node is constrained to be connected to at least two other nodes, thereby forming different node connection matrices; different circuit topologies are generated based on the circuit layout and the different node connection matrices; wherein, the three short principles mean that each node can only be connected to its adjacent nodes and diagonal nodes. The experimental module includes: an experimental circuit generation unit and an interactive experimental unit; The experimental circuit generation unit includes a circuit topology generation subunit and a circuit component addition subunit; the circuit topology generation subunit is used to call the random circuit topology generation module to generate a random circuit topology diagram, and the circuit component addition subunit is used to add circuit components to the circuit topology diagram to obtain a circuit diagram. The interactive experimental unit is used to generate a corresponding interactive experimental interface based on the circuit topology diagram or circuit diagram and the knowledge points related to the circuit simulation experiment, so that users can conduct experiments.

9. The simulation system for interactive circuit experiments according to claim 8, characterized in that, The multiple experimental modules include three main categories: component verification experiments, circuit law and theorem verification experiments, and circuit analysis method verification experiments. The component verification experiments include: ideal voltage source experiment, ideal current source experiment, voltage-controlled voltage source experiment, voltage-controlled current source experiment, current-controlled voltage source experiment, current-controlled current source experiment, resistor VAR experiment, resistor series-parallel experiment, resistor Y-type-Δ type equivalent transformation experiment, equivalent resistance experiment, capacitor VAR experiment, capacitor series-parallel experiment, capacitor Y-type-Δ type equivalent transformation experiment, equivalent inductance experiment, capacitor breakdown experiment, capacitor charge-discharge experiment, inductor VAR experiment, inductor series-parallel experiment, inductor Y-type-Δ type equivalent transformation experiment, equivalent inductance experiment, inductive coupling experiment, AC to DC conversion experiment, impedance VAR experiment, impedance series-parallel experiment, impedance Y-type-Δ type equivalent transformation experiment, and equivalent impedance experiment. The circuit law and theorem verification experiments include: energy conservation law verification experiment, charge conservation law verification experiment, magnetic flux conservation law verification experiment, OL verification experiment, KCL verification experiment, KVL verification experiment, switching law verification experiment, homogeneity theorem verification experiment, superposition theorem verification experiment, substitution theorem verification experiment, Thevenin theorem verification experiment, Norton theorem verification experiment, maximum power transfer theorem verification experiment, Tellegen theorem verification experiment, reciprocity theorem verification experiment, complex power conservation theorem verification experiment, and maximum power product theorem verification experiment. The circuit analysis method verification experiments include: external power supply method experiment, volt-ampere relationship method experiment, open circuit and short circuit method experiment, three-element method experiment, zero input response experiment, zero state response experiment, full response experiment, phasor method experiment, T-type decoupling experiment, three-phase circuit experiment, network function experiment, quality factor experiment, resonant circuit experiment, filter circuit experiment, two-port circuit experiment, and characteristic impedance experiment.

10. A computer program product containing instructions, characterized in that, When it is run on a computer, it causes the computer to perform the steps of the simulation method for the interactive circuit experiment as described in any one of claims 1 to 7.

Images