A computing device, chip, and method
CN122114027APending Publication Date: 2026-05-29HUAWEI TECH CO LTD
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Patent Information
- Application Number
- CN202411723827.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
AI Technical Summary
Technical Problem
Existing ternary neural network hardware designs have high overhead and poor circuit performance, making it difficult to meet the needs of complex models on mobile devices and edge computing devices.
Method used
By employing compression and multiplication units, and utilizing carry and sum logic gates to process ternary signals, the maximum delay path length of the circuit is reduced, thereby improving circuit performance.
Benefits of technology
By optimizing the circuit structure, signal processing efficiency and system utilization have been improved, meeting the operational requirements of ternary neural networks on mobile devices and edge computing devices.
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Smart Images
Figure CN122114027A_ABST
Abstract
The application provides a computing device, a chip and a method. The computing device comprises at least one compression unit, which is used for summing four-way input signals to obtain a first carry signal and a first sum signal; the compression unit comprises a carry logic gate and a sum logic gate; wherein the carry logic gate is used for summing two-way carry input signals to obtain a carry value, and inverting the carry value to obtain one-way carry output signal; the sum logic gate is used for summing two-way sum input signals to obtain a first sum value, and obtaining one-way sum output signal according to the size of the first sum value. By introducing the carry logic gate and the sum logic gate required for carry calculation, the maximum delay path length of the circuit is reduced, the power delay product of the compression unit is reduced, and the circuit performance is improved.
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