A quantum circuit cutting method and related apparatus
By using a quantum bit interaction graph and a recursive subgraph construction method, quantum circuit cutting is optimized, which solves the decoherence error problem caused by the neglect of hardware information in the existing technology and improves the fidelity of quantum circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BENYUAN TIANGONG (ZHENGZHOU) QUANTUM TECH CO LTD
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
AI Technical Summary
Existing quantum circuit cutting methods ignore hardware information, resulting in excessively long routing paths, increased decoherence errors, and reduced fidelity of execution results.
By obtaining the quantum bit interaction graph, the target subgraph with the minimum cutting cost is determined based on the recursive construction of subgraphs, and the routing overhead is reduced by utilizing hardware layout to optimize quantum circuit cutting.
Minimize the number of cut points, reduce line depth, and improve the fidelity of execution results.
Smart Images
Figure CN122114216A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of quantum computing technology, specifically a quantum circuit cutting method and related apparatus. Background Technology
[0002] Quantum circuit dicing is a promising technique that overcomes the limitation of a few physical qubits in recent quantum hardware by cutting large quantum circuits into smaller sub-circuits. Recent research in this field focuses on reducing the sampling overhead of sub-circuits.
[0003] Existing methods for quantum circuit segmentation represent the quantum circuit as a directed graph, where nodes represent quantum logic gates used in the circuit, and directed edges represent the dependencies of quantum logic gates on the quantum state evolution timeline of qubits. A graph partitioning algorithm is then used to divide the directed graph into several subgraphs, each corresponding to a sub-circuit. However, this segmentation process ignores hardware information. Directly compiling and executing these sub-circuits may lead to decoherence errors due to excessively long routing paths, resulting in low-fidelity results. Summary of the Invention
[0004] The purpose of this application is to provide a quantum circuit cutting method and related apparatus, which aims to improve the fidelity of the execution results.
[0005] One embodiment of this application provides a quantum circuit cutting method, the method comprising:
[0006] A qubit interaction diagram of a quantum circuit to be cut is obtained, wherein nodes in the qubit interaction diagram represent logical bits and edges represent two-bit logic gates that interact between corresponding two logical bits.
[0007] Based on the quantum bit interaction graph, a preset number of target subgraphs and corresponding cutting costs are obtained by recursively constructing subgraphs. The number of nodes in the target subgraph is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the quantum bit interaction graph. The cutting cost is determined by the cutting cost and the routing cost. The cutting cost is determined by the number of cutting points, and the routing cost is determined by the similarity between the corresponding subgraph and the physical bit layout of the target quantum hardware.
[0008] The quantum circuit to be cut is cut based on the target subgraph with the minimum cutting cost.
[0009] Optionally, the step of obtaining a preset number of target subgraphs and their corresponding cutting costs based on the qubit interaction graph by recursively constructing subgraphs includes:
[0010] Based on the quantum bit interaction graph, by recursively constructing subgraphs, all subgraphs corresponding to one iteration and the routing cost corresponding to each subgraph are obtained. In one iteration, the number of nodes in each level subgraph is the second number, which is determined by the number of nodes in the corresponding upper level graph and is less than the number of nodes in the upper level graph. When the upper level is the first level, the upper level graph is the quantum bit interaction graph.
[0011] By determining the target subgraph corresponding to one iteration based on the routing cost of one iteration, and obtaining the cutting cost of the target subgraph, the process returns to execute the steps of obtaining all subgraphs corresponding to one iteration and the routing cost of each subgraph by recursively constructing subgraphs based on the quantum bit interaction graph, until the number of iterations reaches a preset number.
[0012] Optionally, the step of obtaining all subgraphs corresponding to one iteration by recursively constructing subgraphs based on the qubit interaction graph includes:
[0013] For each iteration, nodes and edges are selected from the specified graph to construct a subgraph of the specified graph until the number of nodes in the constructed subgraph is the second number. When a subgraph is constructed for the first time, the specified graph is a qubit interaction graph; otherwise, the specified graph is a subgraph constructed in the previous iteration.
[0014] Each subgraph of the constructed specified graph is used as a new specified graph. Then, nodes and edges are selected from the specified graph to construct subgraphs of the specified graph, and so on, until the number of nodes in the constructed subgraphs is the second number.
[0015] Optionally, the step of selecting nodes and edges from a specified graph for each iteration, and constructing a subgraph of the specified graph until the number of nodes in the constructed subgraph is the second number, includes:
[0016] Determine the set of edges and the set of nodes corresponding to a specified graph, wherein the number of edges in the set of edges is less than the number of edges in the specified graph, and the specified graph has no isolated nodes;
[0017] By selecting nodes and edges from the node set and the edge set, a subgraph is gradually constructed until the number of unselected nodes in the node set is less than or equal to a third quantity, thus obtaining a subgraph of the specified graph. The third quantity is determined by the difference between the number of nodes in the specified graph and the second quantity.
[0018] Optionally, the target subgraph for each iteration can be determined based on the routing cost of that iteration, including:
[0019] For each iteration, the target subgraph is determined by backtracking from bottom to top, using the routing overhead of the corresponding next-level subgraph.
[0020] Optionally, the step of determining the target subgraph for a single iteration by backtracking from bottom to top and utilizing the routing cost of the corresponding next-level subgraph includes:
[0021] For each iteration, using the minimum routing cost of the subgraphs constructed from the same specified graph at the next level, a subgraph is determined from the subgraphs constructed from the same specified graph at the previous level as a candidate subgraph. This process is repeated up the hierarchy, and the candidate subgraph determined at the highest level is taken as the target subgraph.
[0022] Optionally, the routing overhead is the cost of graphics editing.
[0023] Optionally, the cost of the graph editing is determined by the topological distance between the physical bits corresponding to the edge to be added and the fidelity between the physical bits, wherein the edge to be added is determined by the layout of the corresponding subgraph and the physical bits of the target quantum hardware.
[0024] Optionally, the cost of graphic editing is obtained by multiplying and summing the topological distance between the physical bits corresponding to the edges to be added and the fidelity between the physical bits.
[0025] Optionally, the cutting cost is:
[0026] C = Cuts + α∑C GED
[0027] Where C represents the cutting cost, Cuts represents the number of cutting points, α represents the parameter, α∈(0,1], C GED Characterizes the cost of graphic editing.
[0028] Another embodiment of this application provides a quantum circuit cutting device, the device comprising:
[0029] The first obtaining module is used to obtain the qubit interaction diagram of the quantum circuit to be cut, wherein nodes in the qubit interaction diagram represent logical bits, and edges represent two-bit logic gates that interact between corresponding two logical bits.
[0030] The second acquisition module is used to obtain a preset number of target subgraphs and corresponding cutting cost overheads based on the quantum bit interaction graph by recursively constructing subgraphs. The number of nodes in the target subgraphs is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the quantum bit interaction graph. The cutting cost overhead is determined by the cutting overhead and the routing overhead. The cutting overhead is determined by the number of cutting points and the routing overhead is determined by the similarity between the corresponding subgraph and the physical bit layout of the target quantum hardware.
[0031] The cutting module is used to cut the quantum circuit to be cut based on the target subgraph with the lowest cutting cost.
[0032] Another embodiment of this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the quantum circuit cutting method described in any of the above embodiments.
[0033] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit cutting method in any of the above embodiments.
[0034] Compared with existing technologies, in this application, the present application first obtains a qubit interaction graph and represents the quantum circuit in a more abstract way, which enables modeling of the circuit cutting problem. Based on the qubit interaction graph, the optimal cutting scheme can be better inferred. Then, the target subgraph is determined by recursively constructing a subgraph. The corresponding cutting cost is determined by the cutting cost and routing cost, and the routing cost is determined by the similarity between the corresponding subgraph and the physical qubit layout of the target quantum hardware. The quantum circuit to be cut is then cut based on the target subgraph with the minimum cutting cost, which can minimize the number of cutting points. At the same time, by utilizing the hardware layout to reduce the routing cost, the circuit depth is reduced, thereby improving the fidelity of the execution result. Attached Figure Description
[0035] Figure 1 A network block diagram of a quantum circuit cutting system provided in an embodiment of this application;
[0036] Figure 2 A flowchart of a quantum circuit cutting method provided in this application embodiment;
[0037] Figure 3 A schematic diagram illustrating the relationship between sub-graphs at different levels, provided as an embodiment of this application;
[0038] Figure 4 A structural diagram of a quantum circuit cutting device provided in an embodiment of this application;
[0039] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0040] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0041] Figure 1This is a network block diagram of a quantum circuit cutting system provided in an embodiment of this application. The system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170 (including target quantum hardware), and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.
[0042] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit cutting system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.
[0043] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.
[0044] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled according to the quantum circuit cutting method provided in the embodiments of this application.
[0045] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.
[0046] It should be noted that a true quantum computing platform has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.
[0047] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.
[0048] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.
[0049] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects. Quantum computing...
[0050] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.
[0051] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.
[0052] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.
[0053] See Figure 2 , Figure 2 A quantum circuit cutting method provided in this application includes the following steps:
[0054] S201: Obtain the qubit interaction diagram of the quantum circuit to be cut, wherein nodes in the qubit interaction diagram represent logical bits, and edges represent two-bit logic gates that interact between corresponding two logical bits.
[0055] In the quantum bit interaction diagram, only two-bit logic gates are considered. Cutting a quantum circuit will not cut a single-bit quantum logic gate. If there are quantum logic gates with more than two qubits in the original quantum circuit to be cut, they are split into single-bit logic gates and / or equivalent combinations of two-bit logic gates to generate the quantum circuit to be cut.
[0056] S202: Based on the qubit interaction graph, a preset number of target subgraphs and corresponding cutting cost overheads are obtained by recursively constructing subgraphs. The number of nodes in the target subgraphs is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the qubit interaction graph. The cutting cost overhead is determined by the cutting overhead and the routing overhead. The cutting overhead is determined by the number of cutting points, and the routing overhead is determined by the similarity between the corresponding qubit interaction subgraph and the target quantum hardware physical bit layout.
[0057] Subgraphs are constructed using qubit interaction graphs. The number of nodes in a subgraph is determined by a first set of parameters and is less than the first set of parameters. Recursive subgraph construction involves building new subgraphs based on the previous subgraph. As subgraphs are constructed, the number of nodes in each new subgraph decreases. Because the cutting costs of the target subgraphs need to be compared, and these cutting costs must be comparable, a predetermined number of target subgraphs must correspond to subgraphs at the same level.
[0058] In this embodiment, the specific subgraph in which a level is selected as the target subgraph can be determined based on the number of physical bits in the quantum hardware. It can be that the number of nodes in the subgraph of that level is less than the number of physical bits.
[0059] There are no isolated nodes in the qubit interaction graph. The target subgraph is a subgraph of the qubit interaction graph. To obtain the target subgraph from the qubit interaction graph, some edges need to be cut. The number of cut edges determines the number of cut points. The number of cut points can be determined by the cut edges and their weights. The weight of the cut edges can be determined by the number of two-bit logic gates that interact between the two connected logic bits.
[0060] When a logic bit that functions as a two-bit logic gate in a quantum circuit is mapped to a physical bit, the mapped physical bits are not directly connected. A routing mechanism is needed to establish a connection between the two mapped physical bits, achieving the same effect as the two-bit logic gate in the quantum circuit. This routing can be implemented using quantum logic gates capable of quantum state swapping, such as SWAP gates. Routing incurs overhead, which is related to the number of quantum logic gates used for pure insertion to achieve quantum state swapping.
[0061] Finding the cutting scheme with the minimum number of cutting points and the minimum routing cost is not easy when cutting quantum circuits. The routing cost is determined by the number of quantum logic gates that can realize quantum state swapping. Taking SWAP gates as an example, it is usually impossible to deduce the number of SWAP gates that need to be inserted during cutting unless the cut quantum circuit is compiled first. However, compiling all sub-circuits for each possible cutting scheme is impractical because the decomposition and compilation of the two-bit logic gates for cutting is very time-consuming. That is, the number of SWAP gates inserted is still unknown before the quantum bit mapping and routing are completed. In addition, the number of SWAP gates cannot be defined as a linear function on the quantum circuit. Therefore, it is impossible to integrate it into a similar mathematical optimization solver and then use the solver to solve it. Therefore, this application uses graph similarity to estimate the routing cost. There are many methods to measure graph similarity, such as graph edit distance (GED), maximum common subgraph (MCS), graph isomorphism, etc., which quantify the degree of graph similarity.
[0062] S203: Cut the quantum circuit to be cut based on the target subgraph with the minimum cutting cost.
[0063] Minimizing the cutting cost indicates that the routing cost and cutting cost are minimized together. Low cutting cost means fewer cutting points, and low routing cost means fewer quantum logic gates are inserted. The number of cutting points and the number of inserted quantum logic gates are related to the depth of the quantum circuit. The more cutting points there are, the deeper the circuit is, and the more quantum logic gates are inserted, the deeper the circuit is. Therefore, the size of the cutting cost reflects the depth of the circuit. That is, low cutting cost means that the depth of the sub-circuit after cutting is relatively shallow.
[0064] In this embodiment, a qubit interaction graph is first obtained, and the quantum circuit is represented in a more abstract way, which enables modeling of the circuit cutting problem. Based on the qubit interaction graph, the optimal cutting scheme can be better inferred. Then, the target subgraph is determined by recursively constructing a subgraph. The corresponding cutting cost is determined by the cutting cost and the routing cost, and the routing cost is determined by the similarity between the corresponding subgraph and the physical qubit layout of the target quantum hardware. The quantum circuit to be cut is then cut based on the target subgraph with the minimum cutting cost, which can minimize the number of cutting points. At the same time, by utilizing the hardware layout to reduce the routing cost, the circuit depth is reduced, thereby improving the fidelity of the execution result.
[0065] In some embodiments of this application, obtaining a preset number of target subgraphs and their corresponding cutting costs based on the qubit interaction graph by recursively constructing subgraphs includes:
[0066] Based on the quantum bit interaction graph, by recursively constructing subgraphs, all subgraphs corresponding to one iteration and the routing cost corresponding to each subgraph are obtained. In one iteration, the number of nodes in each level subgraph is the second number, which is determined by the number of nodes in the corresponding upper level graph and is less than the number of nodes in the upper level graph. When the upper level is the first level, the upper level graph is the quantum bit interaction graph.
[0067] By using all the routing costs corresponding to one iteration, the target subgraph corresponding to one iteration is determined and the cutting cost cost corresponding to the target subgraph is obtained. Then, the process is returned to execute the steps of obtaining all the subgraphs corresponding to one iteration and the routing cost corresponding to each subgraph by recursively constructing subgraphs based on the quantum bit interaction graph, until the number of iterations reaches a preset number.
[0068] It should be noted that the number of iterations is pre-set, and the specific number can be determined according to the actual situation. When the subgraph is a first-level subgraph, the upper-level graph is a qubit interaction graph. When the subgraph is not a first-level subgraph, the upper-level graph is a subgraph. Furthermore, except for the level where the qubit interaction graph is located, each level has at least two subgraphs. One graph in the upper-level graph can construct at least two subgraphs. When two subgraphs are constructed, the relationship between the qubit interaction graph and the subgraphs at each level can be represented as a binary tree structure, with the qubit interaction graph as the root node. The number of subgraphs at each level increases, but the number of nodes in each subgraph decreases. "Level" refers to the graph's current level. For example, based on the qubit interaction graph, the number of iterations is... Figure 1 Based on sub Figure 1 Constructing sub Figure 2 The quantum bit interaction diagram is the first level. Figure 1 It is the second level, sub-level. Figure 2 It is the third level. When the subgraph is at the second level, the second quantity is the first quantity.
[0069] Once the subgraph is constructed, the routing cost corresponding to the subgraph can also be calculated. Using the routing cost obtained in this iteration, the target subgraph is determined, and the cutting cost corresponding to the target subgraph is calculated.
[0070] In some embodiments of this application, the methods for obtaining all subgraphs corresponding to one iteration and the routing cost corresponding to each subgraph can be:
[0071] For each iteration, nodes and edges are selected from the specified graph to construct a subgraph of the specified graph until the number of nodes in the constructed subgraph is the second number. When a subgraph is constructed for the first time, the specified graph is a qubit interaction graph; otherwise, the specified graph is a subgraph constructed in the previous iteration.
[0072] Each subgraph of the constructed specified graph is used as a new specified graph. Then, nodes and edges are selected from the specified graph to construct subgraphs of the specified graph, and so on, until the number of nodes in the constructed subgraphs is the second number.
[0073] When constructing a subgraph, two nodes are first selected, and edges are added between them. Then, another node is selected, and edges are added between them, until the number of nodes in the constructed subgraph reaches the second threshold. Node selection is random, and the constructed subgraph contains no isolated nodes. The specific subgraph construction process can be as follows: First, determine the edge set and node set corresponding to the specified graph. The number of edges in the edge set is less than the number of edges in the specified graph, ensuring that the specified graph contains no isolated nodes. Then, by selecting nodes and edges from the node set and edge set, the subgraph is constructed step by step until the number of unselected nodes in the node set is less than or equal to the third threshold, obtaining the subgraph of the specified graph. The third threshold is determined by the difference between the number of nodes in the specified graph and the second threshold. In one iteration, when constructing the subgraph for the first time, the specified graph is the qubit interaction graph. Otherwise, the specified graph is the subgraph constructed at the previous level. When multiple subgraphs exist at a level, the subgraphs of that level are used as the specified graphs to construct the subgraphs of the next level.
[0074] The node set consists of all nodes in the specified graph, and the edge set satisfies two constraints: the number of edges is less than the number of edges in the specified graph, and the nodes in the node set are connected, with no independent nodes. In this embodiment, the third constraint can be... or The rounded value can also be The rounded value, where 'n' is the number of nodes in the corresponding subgraph at the next higher level, and the second number can be... In the lowest level subgraph, the number of nodes can be 1, meaning there are no edges. To determine whether an iteration of subgraph construction has terminated, we can check if the edge set is empty. When the edge set is empty, subgraph construction stops, and the operation to determine the target subgraph is performed. In this embodiment, the Merge_Nodes function can be used to construct the subgraph.
[0075] In some possible implementations of this application, the target subgraph corresponding to one iteration is determined by using all routing costs corresponding to one iteration, including:
[0076] For each iteration, the target subgraph is determined by backtracking from bottom to top, using the routing overhead of the corresponding next-level subgraph.
[0077] The target subgraph is determined using a backtracking approach. This involves using the routing cost of the corresponding next-level subgraph to select a subgraph from the current-level subgraph to determine the next-level subgraph. Based on the routing cost of the selected subgraph, the next-level subgraph is then determined. One iteration determines one target subgraph. If there are many subgraphs at the same level as the determined target subgraph, multiple target subgraphs can be determined in a single iteration. Specifically, the process for determining the target subgraph is as follows: For each iteration, using the minimum routing cost of the subgraphs constructed from the same specified graph at the next level, a subgraph constructed from the same specified graph at the next level is selected as the undetermined subgraph. This process is repeated backtracking upwards, with the undetermined subgraph determined at the highest level being used as the target subgraph.
[0078] by Figure 3 Taking an example, let's illustrate the process of determining the target subgraph. 1 is the qubit interaction graph, located at the first level. 2 and 3 are subgraphs constructed based on the qubit interaction graph, located at the second level. When constructing 2 and 3, 1 is the designated graph; when constructing 4 and 5, 2 is the designated graph; when constructing 6 and 7, 3 is the designated graph, and so on, until we obtain the fourth level where 8 and 9 are located. Backtracking upwards, we calculate the routing costs of 8 and 9, assigning the smaller one to 4; calculate the routing costs of 10 and 11, assigning the smaller one to 5; calculate the routing costs of 12 and 13, assigning the smaller one to 5; calculate the routing costs of 14 and 15, assigning the smaller one to 7; compare the values of 4 and 5 after assignment, assuming 5 is smaller, calculate the routing cost of 5 and assign it to 2. Similarly, compare the values of 6 and 7 after assignment, assuming 7 is smaller, calculate the routing cost of 7 and assign it to 3. Similarly, compare the values of 2 and 3 after assignment. Assuming that 3 is smaller, calculate the cutting cost of 3 and use 3 as the target subgraph.
[0079] In some embodiments of this application, the routing overhead can be the graph editing cost. The similarity between graphs can be measured by the graph editing distance, as the graph editing distance clearly describes the difficulty of qubit routing on NISQ (Noisy Intermediate Scale Quantum) scale lines. Graph editing refers to the edge or node addition or deletion operations required to transform graph A into graph B, and the editing distance refers to the number of operations. Specifically, the routing overhead can be measured from the physical bit layout T of the target quantum hardware to the subgraph G. sub The edit distance, denoted as C GED (G subThe graph edit distance calculation function (T) is used to estimate the insertion of SWAP gates. SWAP gates are inserted because the physical qubits in the target quantum hardware have limited connectivity. If more edges must be added to edit the physical qubit layout of the target quantum hardware into the subgraph (higher edit distance), the lack of connectivity becomes more severe, thus requiring more SWAP gates to fill the gaps. The graph edit distance calculation function only sets the cost of adding edges to the physical qubit layout graph of the target quantum hardware; deleting edges or nodes incurs no cost.
[0080] In this embodiment, the graph editing cost is a heuristic cost function designed to optimize the search for circuit cutting solutions. Specifically, the graph editing cost is determined by the topological distance between the physical bits corresponding to the edge to be added and the fidelity between the physical bits, where the edge to be added is determined by the corresponding subgraph and the physical bit layout of the target quantum hardware. The topological distance (denoted as dist(pi, pj)) measures the shortest path between two physical qubits pi and pj, with each edge in the physical bit topology of the target quantum hardware assigned a distance of 1. dist(pi, pj) describes the number of edges in the shortest path connecting these physical bits. Then, the graph editing cost is calculated using the edge weight Wij of the edge to be added and dist(pi, pj), where the edge weight Wij is determined by the fidelity between the physical bits. The graph editing cost is obtained by multiplying and summing the topological distance between the physical bits corresponding to the edge to be added and the fidelity between the physical bits, and can be expressed as:
[0081]
[0082] Among them, E add Edges to be added.
[0083] Calculating the similarity between two graphs reveals that graph A has one more edge than graph B. Therefore, the editing cost of this extra edge needs to be calculated; the extra edge is the one to be added. In this embodiment, the physical bit layout T of the target quantum hardware is compared to the corresponding subgraph G. sub The extra edges are the edges to be added. Calculate the physical bit layout T of the target quantum hardware compared to the corresponding subgraph G. sub The cost of editing multiple edges is used as the graphic editing cost corresponding to that subgraph.
[0084] Based on the above graphic editing costs, the cutting cost can be expressed as:
[0085] C = Cuts + α∑C GED
[0086] Where C represents the cutting cost, Cuts represents the number of cutting points, α represents the parameter, α∈(0,1], C GED Characterizes the cost of graphic editing.
[0087] The parameter α is uniquely set according to the characteristics of each circuit (e.g., quantum logic gate density) and can be adjusted to meet different levels of overhead trade-offs. The specific settings can be made according to the actual situation.
[0088] See Figure 4 , Figure 4 A quantum circuit cutting device provided in this application embodiment may include:
[0089] The first obtaining module is used to obtain the qubit interaction diagram of the quantum circuit to be cut, wherein nodes in the qubit interaction diagram represent logical bits, and edges represent two-bit logic gates that interact between corresponding two logical bits.
[0090] The second acquisition module is used to obtain a preset number of target subgraphs and corresponding cutting cost overheads based on the qubit interaction graph by recursively constructing subgraphs. The number of nodes in the target subgraphs is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the qubit interaction graph. The cutting cost overhead is determined by the cutting overhead and the routing overhead. The cutting overhead is determined by the number of cutting points, and the routing overhead is determined by the similarity between the corresponding qubit interaction subgraph and the target quantum hardware physical bit layout.
[0091] The cutting module is used to cut the quantum circuit to be cut based on the target subgraph with the lowest cutting cost.
[0092] The specific functions and effects of the aforementioned quantum circuit cutting device can be explained by referring to other embodiments of this application, and will not be repeated here. Each module in the quantum circuit cutting device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0093] Please see Figure 5 This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit cutting method in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 5 The computer device can be a classical computer or a quantum computer.
[0094] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit cutting method in any of the above embodiments.
[0095] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the quantum circuit cutting method in any of the above embodiments.
[0096] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.
[0097] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.
[0098] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0099] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.
[0100] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0101] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0102] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.
[0103] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0105] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0106] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0107] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for cutting quantum circuits, characterized in that, The method includes: A qubit interaction diagram of a quantum circuit to be cut is obtained, wherein nodes in the qubit interaction diagram represent logical bits and edges represent two-bit logic gates that interact between corresponding two logical bits. Based on the quantum bit interaction graph, a preset number of target subgraphs and corresponding cutting costs are obtained by recursively constructing subgraphs. The number of nodes in the target subgraph is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the quantum bit interaction graph. The cutting cost is determined by the cutting cost and the routing cost. The cutting cost is determined by the number of cutting points, and the routing cost is determined by the similarity between the corresponding subgraph and the physical bit layout of the target quantum hardware. The quantum circuit to be cut is cut based on the target subgraph with the minimum cutting cost.
2. The method as described in claim 1, characterized in that, The method of obtaining a preset number of target subgraphs and their corresponding cutting costs based on the quantum bit interaction graph by recursively constructing subgraphs includes: Based on the quantum bit interaction graph, by recursively constructing subgraphs, all subgraphs corresponding to one iteration and the routing cost corresponding to each subgraph are obtained. In one iteration, the number of nodes in each level subgraph is the second number, which is determined by the number of nodes in the corresponding upper level graph and is less than the number of nodes in the upper level graph. When the upper level is the first level, the upper level graph is the quantum bit interaction graph. By determining the target subgraph corresponding to one iteration based on the routing cost of one iteration, and obtaining the cutting cost of the target subgraph, the process returns to execute the steps of obtaining all subgraphs corresponding to one iteration and the routing cost of each subgraph by recursively constructing subgraphs based on the quantum bit interaction graph, until the number of iterations reaches a preset number.
3. The method as described in claim 2, characterized in that, Based on the qubit interaction graph, all subgraphs corresponding to one iteration are obtained by recursively constructing subgraphs, including: For each iteration, nodes and edges are selected from the specified graph to construct a subgraph of the specified graph until the number of nodes in the constructed subgraph is the second number. When a subgraph is constructed for the first time, the specified graph is a qubit interaction graph; otherwise, the specified graph is a subgraph constructed in the previous iteration. Each subgraph of the constructed specified graph is used as a new specified graph. Then, nodes and edges are selected from the specified graph to construct subgraphs of the specified graph, and so on, until the number of nodes in the constructed subgraphs is the second number.
4. The method as described in claim 3, characterized in that, For each iteration, selecting nodes and edges from a specified graph and constructing a subgraph of the specified graph until the number of nodes in the constructed subgraph is the second number includes: Determine the set of edges and the set of nodes corresponding to a specified graph, wherein the number of edges in the set of edges is less than the number of edges in the specified graph, and the specified graph has no isolated nodes; By selecting nodes and edges from the node set and the edge set, a subgraph is gradually constructed until the number of unselected nodes in the node set is less than or equal to a third quantity, thus obtaining a subgraph of the specified graph. The third quantity is determined by the difference between the number of nodes in the specified graph and the second quantity.
5. The method as described in claim 3, characterized in that, The target subgraph for each iteration is determined by the routing cost of that iteration, including: For each iteration, the target subgraph is determined by backtracking from bottom to top, using the routing overhead of the corresponding next-level subgraph.
6. The method as described in claim 5, characterized in that, The process of determining the target subgraph for a single iteration, by backtracking from bottom to top and utilizing the routing cost of the corresponding next-level subgraph, includes: For each iteration, using the minimum routing cost of the subgraphs constructed from the same specified graph at the next level, a subgraph is determined from the subgraphs constructed from the same specified graph at the previous level as a candidate subgraph. This process is repeated up the hierarchy, and the candidate subgraph determined at the highest level is taken as the target subgraph.
7. The method as described in claim 3, characterized in that, The routing overhead refers to the cost of graphic editing.
8. The method as described in claim 7, characterized in that, The cost of the graph editing is determined by the topological distance between the physical bits corresponding to the edge to be added and the fidelity between the physical bits, wherein the edge to be added is determined by the layout of the corresponding subgraph and the physical bits of the target quantum hardware.
9. The method as described in claim 8, characterized in that, The cost of graphic editing is obtained by multiplying and summing the topological distance between the physical bits corresponding to the edges to be added and the fidelity between the physical bits.
10. The method as described in claim 7, characterized in that, The cutting cost is as follows: C=Cuts+αΣC GED Where C represents the cutting cost, Cuts represents the number of cutting points, α represents the parameter, α∈(0,1], C GED Characterizes the cost of graphic editing.
11. A quantum circuit cutting device, characterized in that, The device includes: The first obtaining module is used to obtain the qubit interaction diagram of the quantum circuit to be cut, wherein nodes in the qubit interaction diagram represent logical bits, and edges represent two-bit logic gates that interact between corresponding two logical bits. The second acquisition module is used to obtain a preset number of target subgraphs and corresponding cutting cost overheads based on the quantum bit interaction graph by recursively constructing subgraphs. The number of nodes in the target subgraphs is determined by a first quantity and is less than the first quantity, where the first quantity is the number of nodes in the quantum bit interaction graph. The cutting cost overhead is determined by the cutting overhead and the routing overhead. The cutting overhead is determined by the number of cutting points and the routing overhead is determined by the similarity between the corresponding subgraph and the physical bit layout of the target quantum hardware. The cutting module is used to cut the quantum circuit to be cut based on the target subgraph with the lowest cutting cost.
12. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the quantum circuit cutting method of any one of claims 1-10.
13. A computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit cutting method of any one of claims 1-10.