Chip welding quality comprehensive detection method and system

Abstract

The application discloses a kind of welding quality comprehensive detection method and system of chip, it is related to semiconductor technical field, solve the problem of inaccurate chip welding quality detection, method includes respectively collecting the image of target chip before and after welding operation and processing, extract the actual welding range corresponding to target chip;The coordinate distribution of endpoint in actual welding range is analyzed, in combination with the coordinate distribution corresponding to estimated welding area and the overlap of actual welding range, generate abnormal signal or do not carry out any operation;Chip welding area is analyzed and extracted to obtain a plurality of weld spots, identify the weld spot coordinates corresponding to each weld spot;According to weld spot coordinates, the weld spot connectivity of target chip is analyzed, and an abnormal signal or no operation is generated;Extract the abnormal signal corresponding to target chip and display based on abnormal signal, the present application is tested by welding offset condition and weld spot quality, realize accurate evaluation to target chip welding quality.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing technology, specifically a comprehensive testing method and system for chip welding quality. Background Technology

[0002] Chips are a general term for microelectronic devices, which are items that achieve specific functions by integrating a large number of transistors, resistors, capacitors and other components onto a semiconductor material. Chip soldering specifically refers to the process of connecting chips and packaging bases in semiconductor manufacturing. The core is to use solder to combine the cut individual chips with the base to form an electrical and mechanical connection.

[0003] However, at present, when conducting welding quality inspection, the quality of welding is often only evaluated and inspected based on the geometry of the welding area, without taking into account factors such as welding range deviation, the presence of weld points, and weld point quality. This results in inaccurate welding quality inspection.

[0004] Therefore, this invention proposes a comprehensive testing method and system for chip welding quality. Summary of the Invention

[0005] The purpose of this invention is to provide a comprehensive inspection method and system for chip welding quality, in order to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A comprehensive inspection method for chip soldering quality, the method comprising:

[0008] Step S1: Collect and process images of the target chip before and after the welding operation, and extract the actual welding range corresponding to the target chip.

[0009] Step S2: Analyze the coordinate distribution of the endpoints in the actual welding range, and combine the overlap between the estimated coordinate distribution of the welding area and the actual welding range to generate an abnormal signal or perform no operation.

[0010] Step S3: Analyze and extract multiple solder joints from the chip soldering area, and identify the coordinates of each solder joint.

[0011] Step S4: Analyze the solder joint connectivity of the target chip based on the solder joint coordinates, and generate an abnormal signal or perform no operation.

[0012] Step S5: Extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal.

[0013] Further, step S1 includes the following sub-steps:

[0014] Step S11: Before the soldering operation, place the target chip on the base and acquire an image of the target chip before soldering using an image acquisition device.

[0015] Step S12: Solder the target chip onto the base in the same orientation, place the soldered target chip on a flat surface, and acquire the soldered image of the target chip using an image acquisition device.

[0016] Step S13: Extract the pixel value of each pixel in the image before welding, and separate the pixel value into R value component, G value component and B value component.

[0017] Step S14: Calculate the pixel grayscale value corresponding to each pixel in the image before welding based on the R value component, G value component and B value component. Calculate the pixel grayscale value of each pixel in the image after welding of the target chip based on the same grayscale value calculation operation.

[0018] Furthermore, step S1 also includes the following sub-steps:

[0019] Step S15: Subtract the grayscale value of each pixel at the same position in the image after welding from the grayscale value of each pixel in the image before welding;

[0020] Step S16: Take the absolute value of the grayscale difference value and compare it with the preset grayscale difference threshold. If the absolute value of the grayscale difference value is less than the grayscale difference threshold, no operation is performed. If the absolute value of the grayscale difference value is greater than or equal to the grayscale difference threshold, the corresponding pixel is recorded as a changed pixel.

[0021] Step S17: Discard isolated variable pixels and connect the remaining variable pixels with the outermost boundary to obtain the actual welding range of the target chip.

[0022] Further, step S2 includes the following sub-steps:

[0023] Step S21: Establish a Cartesian coordinate system corresponding to the target chip, with any corner of the target chip as the origin;

[0024] Step S22: Obtain the actual welding range of the target chip, extract the area of ​​the actual welding range in the post-welding image and record it as the chip welding area, record each endpoint of the chip welding area as the welding endpoint, and read the endpoint coordinates of each welding endpoint.

[0025] Step S23: Obtain the estimated welding area corresponding to the target chip, and read the estimated endpoint coordinates of the estimated welding area in the Cartesian coordinate system corresponding to the target chip.

[0026] Step S24: Construct an overlapping polygon between the chip welding area and the estimated welding area.

[0027] Furthermore, step S2 also includes the following sub-steps:

[0028] Step S25: Calculate the overlapping area of ​​the overlapping polygons using the polygon calculation formula, and then calculate the area of ​​the estimated welding area using the rectangle calculation formula. The welding area ratio is obtained by dividing the overlapping area by the area of ​​the estimated welding area.

[0029] Step S26: Calculate the area of ​​the chip welding area using the polygon calculation formula; subtract the estimated area of ​​the welding area from the area of ​​the chip welding area to obtain the welding overflow area; divide the welding overflow area by the estimated area of ​​the welding area to obtain the overflow area ratio.

[0030] Step S27: Compare the welding area ratio and overflow area ratio with the preset area ratio thresholds in sequence. If the welding area ratio is greater than or equal to the welding area ratio threshold and the overflow area ratio is less than or equal to the overflow area ratio threshold, then execute step S3; otherwise, generate an abnormal signal.

[0031] Furthermore, the construction process of the overlapping polygons is as follows:

[0032] Step S241: Traverse the four edges of the estimated welding area and the z edges of the chip welding area, determine the intersection by the line segment addition condition, and record the corresponding intersection point as the common intersection point;

[0033] Step S242: For any endpoint of the estimated welding area, draw a ray to the right from the location of the endpoint, count the number of intersections between the ray and the chip welding area. If the number of intersections is even, discard the corresponding endpoint. If the number of intersections is odd, the corresponding endpoint is located in the common area.

[0034] Step S243: For any endpoint of the chip bonding area, identify the endpoint located in the common area using the same operation as in step S242;

[0035] Step S244: Connect the common intersection point and the endpoints of the common area in a clockwise order to construct the overlapping polygon of the chip welding area and the estimated welding area.

[0036] Further, step S3 includes the following sub-steps:

[0037] Step S31: Obtain the chip welding area of ​​the target chip;

[0038] Step S32: Extract the pixel value of each pixel in the chip welding area and calculate the pixel grayscale value of each pixel in the chip welding area corresponding to the target chip.

[0039] Step S33: Sum the pixel gray values ​​of all pixels in the chip welding area and take the average to obtain the pixel gray mean; calculate the pixel gray standard deviation based on the pixel gray mean and the pixel gray values ​​of the pixels.

[0040] Step S34: Traverse the pixels in the chip welding area, record each pixel as a selected pixel, calculate the difference between the pixel grayscale value of the selected pixel and all its neighboring pixels, and take the absolute value to obtain the grayscale difference value.

[0041] The grayscale difference value is compared with the standard deviation of pixel grayscale. If the grayscale difference value between the selected pixel and all its neighboring pixels is greater than the standard deviation of pixel grayscale, the selected pixel is recorded as a solder joint; otherwise, no operation is performed.

[0042] Step S35: Extract the coordinates of the solder joints. Calculate the solder joint spacing between any two solder joints according to the distance formula between two points. If the solder joint spacing is less than or equal to the minimum spacing, randomly discard one of the two solder joints and keep only one solder joint. If the solder joint spacing is greater than the minimum spacing, keep both solder joints.

[0043] Further, step S4 includes the following sub-steps:

[0044] Step S41: Obtain multiple solder joints and their corresponding coordinates;

[0045] Step S42: Obtain the chip welding area, and obtain multiple closed areas based on the color depiction within the chip welding area;

[0046] Step S43: Identify the geometric center of the closed area and read the coordinates of the geometric center. Calculate the distance between the geometric center and the solder joint. If there is only one solder joint whose distance between the geometric center and the solder joint is less than the preset distance, then the corresponding closed area is recorded as the solder joint radial profile of the corresponding solder joint.

[0047] Furthermore, step S4 also includes the following sub-steps:

[0048] Step S44: If there are multiple solder joints whose distances from the geometric center to the solder joints are less than a preset distance, then the corresponding closed areas are recorded as continuous welding areas; if the distances between all solder joints and the geometric center are greater than the preset distances, then the corresponding closed areas are discarded.

[0049] Step S45: Using the coordinates of any solder joint as the center and the radius length r as the radius, construct the corresponding solder joint radiation area.

[0050] Step S46: Calculate the area of ​​the solder joint radiation region and the area of ​​the solder joint radiation profile respectively. Divide the area of ​​the solder joint radiation profile by the area of ​​the solder joint radiation region to obtain the solder joint area ratio of the corresponding solder joint. If the solder joint area ratio is greater than or equal to the area ratio threshold, the corresponding solder joint radiation profile is regarded as normal and no operation is performed. If the solder joint area ratio is less than the area ratio threshold, the corresponding solder joint radiation profile is regarded as a cold solder joint area and an abnormal signal is generated.

[0051] On the other hand, a comprehensive welding quality inspection system for chips executes a comprehensive welding quality inspection method. The system includes a data acquisition module, an image analysis module, an offset recognition module, a solder joint extraction module, a solder joint analysis module, and a display terminal.

[0052] The data acquisition module is used to acquire images of the target chip before and after the welding operation and send them to the image analysis module; the image analysis module is used to analyze the images of the target chip before and after the welding operation, obtain the actual welding range of the target chip and send it to the offset recognition module and the solder joint extraction module; the offset recognition module is used to analyze the coordinate distribution of the endpoints in the actual welding range, obtain the chip welding area of ​​the target chip and send it to the solder joint extraction module, generate an abnormal signal and send it to the display terminal or do not perform any operation;

[0053] The solder joint extraction module is used to analyze the chip soldering area and extract multiple solder joints and their corresponding coordinates; the solder joint extraction module sends each solder joint and its corresponding coordinates to the solder joint analysis module; the solder joint analysis module is used to analyze the solder joint connectivity of the target chip based on the solder joint coordinates, generate an abnormal signal and send it to the display terminal or perform no operation; the display terminal is used to extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal.

[0054] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0055] 1. This invention acquires and processes images of the target chip before and after the welding operation, extracts the actual welding range corresponding to the target chip, analyzes the coordinate distribution of the endpoints in the actual welding range, and generates an abnormal signal or performs no operation based on the overlap between the coordinate distribution of the estimated welding area and the actual welding range, thereby realizing the analysis of the welding offset of the target chip.

[0056] 2. This invention analyzes and extracts multiple solder joints from the chip welding area, identifies the coordinates of each solder joint, analyzes the connectivity of the solder joints on the target chip based on the solder joint coordinates, generates an abnormal signal or performs no operation, extracts the abnormal signal corresponding to the target chip and displays it based on the abnormal signal, and achieves accurate evaluation of the welding quality of the target chip by comprehensively testing the welding offset, the presence of solder joints and the quality of solder joints. Attached Figure Description

[0057] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0058] Figure 1 This is a flowchart of the method of the present invention;

[0059] Figure 2 This is a schematic diagram of an isolated pixel in this invention;

[0060] Figure 3 This is a schematic diagram of the solder joint radiation area in this invention;

[0061] Figure 4 This is a schematic diagram of the system in this invention. Detailed Implementation

[0062] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] A chip is a general term for microelectronic devices, which are items that achieve specific functions by integrating a large number of transistors, resistors, capacitors and other components onto a semiconductor material. Chip soldering specifically refers to the process of connecting chips and packaging substrates in semiconductor manufacturing. The core is to use solder to combine the cut individual chips with the substrate to form an electrical and mechanical connection. However, in the actual soldering process, the two ends of the metal are soldered to a designated area on the wafer and the substrate respectively. However, because this area is small and shadows can appear during the soldering process under light, errors can occur, leading to short circuits in the chip. This invention analyzes this situation. This invention also refers to the chip that needs to be combined with the substrate as the target chip and analyzes the soldering image of the target chip.

[0064] Example 1: Please refer to Figures 1-3As shown, the technical solution provided by the present invention is: a comprehensive inspection method for chip welding quality, which involves acquiring images of the target chip before and after the welding operation, processing them, and identifying the actual welding range in the original image; and determining the actual welding offset based on the actual welding range.

[0065] Then, multiple solder joints are identified based on the actual welding range; by combining the solder joints with the corresponding solder joint radiation profile, a comprehensive inspection of the chip welding quality can be achieved.

[0066] In this invention, the comprehensive welding quality inspection method is specifically as follows:

[0067] Step S1: Collect and process images of the target chip before and after the welding operation, and extract the actual welding range corresponding to the target chip.

[0068] In this invention, step S1 includes the following sub-steps:

[0069] Step S11: Before the soldering operation, place the target chip on the base and acquire an image of the target chip before soldering using an image acquisition device.

[0070] Step S12: Solder the target chip onto the base in the same orientation, place the soldered target chip on a flat surface, and acquire the soldered image of the target chip using an image acquisition device.

[0071] It should be noted that the image acquisition device is selected based on the package type of the target chip during the soldering process. If the package type is ball grid array or leadless flat package (the solder joints will be blocked after soldering), the image of the target chip after soldering is acquired by an XRay device; if the package type is other types, the image of the target chip after soldering is acquired by a camera.

[0072] Step S13: Extract the pixel value of each pixel in the image before welding, and separate the pixel value into R value component, G value component and B value component.

[0073] Step S14: Calculate the pixel grayscale value corresponding to each pixel in the image before welding based on the R value component, G value component and B value component. Calculate the pixel grayscale value of each pixel in the image after welding corresponding to the target chip based on the same grayscale value calculation operation.

[0074] Step S15: Subtract the grayscale value of each pixel at the same position in the image after welding from the grayscale value of each pixel in the image before welding;

[0075] Step S16: Take the absolute value of the grayscale difference value and compare it with the preset grayscale difference threshold. If the absolute value of the grayscale difference value is less than the grayscale difference threshold, no operation is performed. If the absolute value of the grayscale difference value is greater than or equal to the grayscale difference threshold, the corresponding pixel is recorded as a changed pixel.

[0076] Step S17, as follows Figure 2 As shown, isolated changing pixels are discarded, and the remaining changing pixels are connected by the outermost boundary to obtain the actual welding range of the target chip.

[0077] It should be noted that this step identifies the total soldering range of the target chip during the soldering operation.

[0078] Step S2: Analyze the coordinate distribution of the endpoints in the actual welding range, and combine the overlap between the estimated coordinate distribution of the welding area and the actual welding range to generate an abnormal signal or perform no operation.

[0079] In this invention, step S2 includes the following sub-steps:

[0080] Step S21: Establish a Cartesian coordinate system corresponding to the target chip, with any corner of the target chip as the origin;

[0081] Step S22: Obtain the actual welding range of the target chip, extract the area of ​​the actual welding range in the post-welding image and record it as the chip welding area, record each endpoint of the chip welding area as the welding endpoint, and read the endpoint coordinates (Xi, Yi) of each welding endpoint; where i is the number of the endpoint corresponding to the actual welding range, i=1,2,...,z, and z is a positive integer;

[0082] Step S23: Obtain the estimated welding area corresponding to the target chip, and read the estimated endpoint coordinates (x1, y1), (x2, y2), (x3, y3) and (x4, y4) of the estimated welding area in the Cartesian coordinate system corresponding to the target chip.

[0083] It should be noted that the estimated soldering area is the specific area that needs to be soldered. In practice, the estimated soldering area is directly marked on the target chip, and the color of the estimated soldering area is different from the color of other areas of the target chip.

[0084] Step S24: Construct the overlapping polygon between the chip welding area and the estimated welding area. The specific construction process is as follows:

[0085] Step S241: Traverse the four edges of the estimated welding area and the z edges of the chip welding area, determine the intersection by the line segment addition condition, record the corresponding intersection point as the common intersection point, and record the coordinates of the common intersection point;

[0086] The specific conditions for line segment intersection are as follows:

[0087] In the formula, (X1, Y1) and (X2, Y2) are the coordinates of any two adjacent endpoints in the chip welding area; (x1, y1) and (x2, y2) are the coordinates of any two adjacent endpoints in the estimated welding area.

[0088] Step S242: For any endpoint of the estimated welding area, draw a ray to the right from the location of the endpoint, count the number of intersections between the ray and the chip welding area. If the number of intersections is even, discard the corresponding endpoint. If the number of intersections is odd, the corresponding endpoint is located in the common area.

[0089] Step S243: For any endpoint of the chip bonding area, identify the endpoint located in the common area using the same operation as in step S242;

[0090] Step S244: Connect the common intersection point and the endpoints of the common area in a clockwise order to construct the overlapping polygon of the chip welding area and the estimated welding area;

[0091] Step S25: Calculate the overlapping area of ​​the overlapping polygons using the polygon calculation formula, and then calculate the area of ​​the estimated welding area using the rectangle calculation formula. The welding area ratio is obtained by dividing the overlapping area by the area of ​​the estimated welding area.

[0092] Step S26: Calculate the area of ​​the chip welding area using the polygon calculation formula; subtract the estimated area of ​​the welding area from the area of ​​the chip welding area to obtain the welding overflow area; divide the welding overflow area by the estimated area of ​​the welding area to obtain the overflow area ratio.

[0093] Step S27: Compare the welding area ratio and overflow area ratio with the preset area ratio thresholds in sequence. If the welding area ratio is greater than or equal to the welding area ratio threshold and the overflow area ratio is less than or equal to the overflow area ratio threshold, then execute step S3; otherwise, generate an abnormal signal.

[0094] It should be noted that both the overflow area percentage threshold and the welding area percentage threshold are empirical values. In practice, the overflow area percentage threshold can be 120%, and the welding area percentage threshold can be 80%.

[0095] This step is used to analyze the welding offset during the welding process.

[0096] Step S3: Analyze and extract multiple solder joints from the chip soldering area, and identify the coordinates of each solder joint.

[0097] In this invention, step S3 includes the following sub-steps:

[0098] Step S31: Obtain the chip welding area of ​​the target chip;

[0099] Step S32: Extract the pixel value of each pixel in the chip welding area, and calculate the pixel grayscale value of each pixel in the chip welding area corresponding to the target chip according to the process of steps S13-S14.

[0100] Step S33: Sum the pixel gray values ​​of all pixels in the chip welding area and take the average to obtain the pixel gray mean; calculate the pixel gray standard deviation based on the pixel gray mean and the pixel gray values ​​of the pixels.

[0101] Step S34: Traverse the pixels in the chip welding area, record each pixel as a selected pixel, calculate the difference between the pixel grayscale value of the selected pixel and all its neighboring pixels, and take the absolute value to obtain the grayscale difference value.

[0102] The grayscale difference value is compared with the standard deviation of pixel grayscale. If the grayscale difference value between the selected pixel and all its neighboring pixels is greater than the standard deviation of pixel grayscale, the selected pixel is recorded as a solder joint; otherwise, no operation is performed.

[0103] It should be noted that during welding, there is a significant difference in brightness between the weld point and its surroundings. Depending on the imaging conditions, the weld point may be brighter or darker than the surrounding area.

[0104] Step S35: Extract the coordinates of the solder joints. Calculate the solder joint spacing between any two solder joints according to the distance formula between two points. If the solder joint spacing is less than or equal to the minimum spacing, randomly discard one of the two solder joints and keep only one solder joint. If the solder joint spacing is greater than the minimum spacing, keep both solder joints.

[0105] Among them, the minimum spacing is a constant, which is actually a pre-set distance threshold;

[0106] It should be noted that this step is used to extract the location and coordinates of the solder joints on the target chip during the soldering operation.

[0107] Step S4: Analyze the solder joint connectivity of the target chip based on the solder joint coordinates, and generate an abnormal signal or perform no operation.

[0108] In this invention, step S4 includes the following sub-steps:

[0109] Step S41: Obtain multiple solder joints and their corresponding coordinates;

[0110] Step S42: Obtain the chip welding area, and obtain multiple closed areas based on the color depiction within the chip welding area;

[0111] Step S43: Identify the geometric center of the closed area and read the coordinates of the geometric center. Calculate the distance between the geometric center and the solder joint. If there is only one solder joint whose distance between the geometric center and the solder joint is less than the preset distance, then the corresponding closed area is recorded as the solder joint radial profile of the corresponding solder joint.

[0112] Step S44: If there are multiple solder joints whose distances from the geometric center to the solder joints are less than a preset distance, then the corresponding closed areas are recorded as continuous welding areas; if the distances between all solder joints and the geometric center are greater than the preset distances, then the corresponding closed areas are discarded.

[0113] Step S45, as follows Figure 3 As shown, the solder joint radiation area of ​​any solder joint is constructed with the solder joint coordinates as the center and the radius length r as the radius.

[0114] Step S46: Calculate the area of ​​the solder joint radiation region and the area of ​​the solder joint radiation profile respectively. Divide the area of ​​the solder joint radiation profile by the area of ​​the solder joint radiation region to obtain the solder joint area ratio of the corresponding solder joint. If the solder joint area ratio is greater than or equal to the area ratio threshold, the corresponding solder joint radiation profile is regarded as normal and no operation is performed. If the solder joint area ratio is less than the area ratio threshold, the corresponding solder joint radiation profile is regarded as a cold solder joint area and an abnormal signal is generated.

[0115] It should be noted that since the total amount of solder metal used in each welding is fixed, the area corresponding to the radiating profile of the solder joint is not particularly large.

[0116] This step is used to evaluate the solder joint quality of each solder joint.

[0117] Step S5: Extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal; specifically, if an abnormal signal is extracted, the welding quality of the target chip is deemed unqualified; if no abnormal signal is extracted, the welding quality of the target chip is deemed qualified.

[0118] Example 2: Please refer to Figure 4 As shown, based on another concept of the same invention, a comprehensive chip welding quality inspection system is proposed, including a data acquisition module, an image analysis module, an offset recognition module, a solder joint extraction module, a solder joint analysis module, and a display terminal.

[0119] The data acquisition module is used to acquire images of the target chip before and after the welding operation and send them to the image analysis module; the image analysis module is used to analyze the images of the target chip before and after the welding operation, obtain the actual welding range of the target chip and send it to the offset recognition module and the solder joint extraction module; the offset recognition module is used to analyze the coordinate distribution of the endpoints in the actual welding range, obtain the chip welding area of ​​the target chip and send it to the solder joint extraction module, generate an abnormal signal and send it to the display terminal or do not perform any operation;

[0120] The solder joint extraction module is used to analyze the chip soldering area and extract multiple solder joints and their corresponding coordinates; the solder joint extraction module sends each solder joint and its corresponding coordinates to the solder joint analysis module; the solder joint analysis module is used to analyze the solder joint connectivity of the target chip based on the solder joint coordinates, generate an abnormal signal and send it to the display terminal or perform no operation; the display terminal is used to extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal.

[0121] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A comprehensive inspection method for chip welding quality, characterized in that, The methods include: Step S1: Collect and process images of the target chip before and after the welding operation, and extract the actual welding range corresponding to the target chip. Step S2: Analyze the coordinate distribution of the endpoints in the actual welding range, and combine the overlap between the estimated coordinate distribution of the welding area and the actual welding range to generate an abnormal signal or perform no operation. Step S3: Analyze and extract multiple solder joints from the chip soldering area, and identify the coordinates of each solder joint. Step S4: Analyze the solder joint connectivity of the target chip based on the solder joint coordinates, and generate an abnormal signal or perform no operation. Step S5: Extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal.

2. The comprehensive inspection method for chip welding quality according to claim 1, characterized in that, Step S1 includes the following sub-steps: Step S11: Before the soldering operation, place the target chip on the base and acquire an image of the target chip before soldering using an image acquisition device. Step S12: Solder the target chip onto the base in the same orientation, place the soldered target chip on a flat surface, and acquire the soldered image of the target chip using an image acquisition device. Step S13: Extract the pixel value of each pixel in the image before welding, and separate the pixel value into R value component, G value component and B value component. Step S14: Calculate the pixel grayscale value corresponding to each pixel in the image before welding based on the R value component, G value component and B value component. Calculate the pixel grayscale value of each pixel in the image after welding of the target chip based on the same grayscale value calculation operation.

3. The comprehensive inspection method for chip welding quality according to claim 2, characterized in that, Step S1 further includes the following sub-steps: Step S15: Subtract the grayscale value of each pixel at the same position in the image after welding from the grayscale value of each pixel in the image before welding; Step S16: Take the absolute value of the grayscale difference value and compare it with the preset grayscale difference threshold. If the absolute value of the grayscale difference value is less than the grayscale difference threshold, no operation is performed. If the absolute value of the grayscale difference value is greater than or equal to the grayscale difference threshold, the corresponding pixel is recorded as a changed pixel. Step S17: Discard isolated variable pixels and connect the remaining variable pixels with the outermost boundary to obtain the actual welding range of the target chip.

4. The comprehensive inspection method for chip welding quality according to claim 1, characterized in that, Step S2 includes the following sub-steps: Step S21: Establish a Cartesian coordinate system corresponding to the target chip, with any corner of the target chip as the origin; Step S22: Obtain the actual welding range of the target chip, extract the area of ​​the actual welding range in the post-welding image and record it as the chip welding area, record each endpoint of the chip welding area as the welding endpoint, and read the endpoint coordinates of each welding endpoint. Step S23: Obtain the estimated welding area corresponding to the target chip, and read the estimated endpoint coordinates of the estimated welding area in the Cartesian coordinate system corresponding to the target chip. Step S24: Construct an overlapping polygon between the chip welding area and the estimated welding area.

5. The comprehensive inspection method for chip welding quality according to claim 4, characterized in that, Step S2 further includes the following sub-steps: Step S25: Calculate the overlapping area of ​​the overlapping polygons using the polygon calculation formula, and then calculate the area of ​​the estimated welding area using the rectangle calculation formula. The welding area ratio is obtained by dividing the overlapping area by the area of ​​the estimated welding area. Step S26: Calculate the area of ​​the chip welding area using the polygon calculation formula; subtract the estimated area of ​​the welding area from the area of ​​the chip welding area to obtain the welding overflow area; divide the welding overflow area by the estimated area of ​​the welding area to obtain the overflow area ratio. Step S27: Compare the welding area ratio and overflow area ratio with the preset area ratio thresholds in sequence. If the welding area ratio is greater than or equal to the welding area ratio threshold and the overflow area ratio is less than or equal to the overflow area ratio threshold, then execute step S3; otherwise, generate an abnormal signal.

6. The comprehensive inspection method for chip welding quality according to claim 4, characterized in that, The process of constructing the overlapping polygons is as follows: Step S241: Traverse the four edges of the estimated welding area and the z edges of the chip welding area, determine the intersection by the line segment addition condition, and record the corresponding intersection point as the common intersection point; Step S242: For any endpoint of the estimated welding area, draw a ray to the right from the location of the endpoint, count the number of intersections between the ray and the chip welding area. If the number of intersections is even, discard the corresponding endpoint. If the number of intersections is odd, the corresponding endpoint is located in the common area. Step S243: For any endpoint of the chip bonding area, identify the endpoint located in the common area using the same operation as in step S242; Step S244: Connect the common intersection point and the endpoints of the common area in a clockwise order to construct the overlapping polygon of the chip welding area and the estimated welding area.

7. The comprehensive inspection method for chip welding quality according to claim 1, characterized in that, Step S3 includes the following sub-steps: Step S31: Obtain the chip welding area of ​​the target chip; Step S32: Extract the pixel value of each pixel in the chip welding area and calculate the pixel grayscale value of each pixel in the chip welding area corresponding to the target chip. Step S33: Sum the pixel gray values ​​of all pixels in the chip welding area and take the average to obtain the pixel gray mean; calculate the pixel gray standard deviation based on the pixel gray mean and the pixel gray values ​​of the pixels. Step S34: Traverse the pixels in the chip welding area, record each pixel as a selected pixel, calculate the difference between the pixel grayscale value of the selected pixel and all its neighboring pixels, and take the absolute value to obtain the grayscale difference value. The grayscale difference value is compared with the standard deviation of pixel grayscale. If the grayscale difference value between the selected pixel and all its neighboring pixels is greater than the standard deviation of pixel grayscale, the selected pixel is recorded as a solder joint; otherwise, no operation is performed. Step S35: Extract the coordinates of the solder joints. Calculate the solder joint spacing between any two solder joints according to the distance formula between two points. If the solder joint spacing is less than or equal to the minimum spacing, randomly discard one of the two solder joints and keep only one solder joint. If the solder joint spacing is greater than the minimum spacing, keep both solder joints.

8. The comprehensive inspection method for chip welding quality according to claim 1, characterized in that, Step S4 includes the following sub-steps: Step S41: Obtain multiple solder joints and their corresponding coordinates; Step S42: Obtain the chip welding area, and obtain multiple closed areas based on the color depiction within the chip welding area; Step S43: Identify the geometric center of the closed area and read the coordinates of the geometric center. Calculate the distance between the geometric center and the solder joint. If there is only one solder joint whose distance between the geometric center and the solder joint is less than the preset distance, then the corresponding closed area is recorded as the solder joint radial profile of the corresponding solder joint.

9. The comprehensive inspection method for chip welding quality according to claim 8, characterized in that, Step S4 further includes the following sub-steps: Step S44: If there are multiple solder joints whose distances from the geometric center to the solder joints are less than a preset distance, then the corresponding closed areas are recorded as continuous welding areas; if the distances between all solder joints and the geometric center are greater than the preset distances, then the corresponding closed areas are discarded. Step S45: Using the coordinates of any solder joint as the center and the radius length r as the radius, construct the corresponding solder joint radiation area. Step S46: Calculate the area of ​​the solder joint radiation region and the area of ​​the solder joint radiation profile respectively. Divide the area of ​​the solder joint radiation profile by the area of ​​the solder joint radiation region to obtain the solder joint area ratio of the corresponding solder joint. If the solder joint area ratio is greater than or equal to the area ratio threshold, the corresponding solder joint radiation profile is regarded as normal and no operation is performed. If the solder joint area ratio is less than the area ratio threshold, the corresponding solder joint radiation profile is regarded as a cold solder joint area and an abnormal signal is generated.

10. A comprehensive inspection system for chip welding quality, characterized in that, The chip welding quality comprehensive inspection method according to any one of claims 1-9 includes a data acquisition module, an image analysis module, an offset recognition module, a solder joint extraction module, a solder joint analysis module, and a display terminal. The data acquisition module is used to acquire images of the target chip before and after the welding operation and send them to the image analysis module; the image analysis module is used to analyze the images of the target chip before and after the welding operation, obtain the actual welding range of the target chip and send it to the offset recognition module and the solder joint extraction module; the offset recognition module is used to analyze the coordinate distribution of the endpoints in the actual welding range, obtain the chip welding area of ​​the target chip and send it to the solder joint extraction module, generate an abnormal signal and send it to the display terminal or do not perform any operation; The solder joint extraction module is used to analyze the chip soldering area and extract multiple solder joints and their corresponding coordinates; the solder joint extraction module sends each solder joint and its corresponding coordinates to the solder joint analysis module; the solder joint analysis module is used to analyze the solder joint connectivity of the target chip based on the solder joint coordinates, generate an abnormal signal and send it to the display terminal or perform no operation; the display terminal is used to extract the abnormal signal corresponding to the target chip and display it based on the abnormal signal.

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