Detection protection circuit and display device

Abstract

The application provides a detection protection circuit and a display device. The detection protection circuit is applied to a spliced display screen of a chip-on-board module. The detection protection circuit comprises a detection circuit and a power supply path. The detection circuit comprises a detection unit and outputs a detection signal based on a resistance value change of the detection unit. The detection unit is arranged at a splicing position of the spliced display screen to sense a packaging state of the splicing position. The power supply path receives the detection signal and provides different driving voltages to the spliced display screen according to the detection signal. The detection unit is arranged at the splicing position and outputs the detection signal based on the resistance value change, so that the abnormal packaging state of the splicing position can be detected in real time.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a detection protection circuit and a display device. Background Technology

[0002] As the display market evolves towards multi-dimensionality and scenario-based applications, modular assembly and splicing technology has become the mainstream solution to meet the demands for massive display effects in scenarios such as large advertising screens and commercial venues. This technology achieves large-size displays by splicing multiple small-sized display modules, supports rapid replacement of individual modules, and significantly improves maintenance efficiency.

[0003] Currently, COB (Chip on Board) direct-view modules are widely used in large-scale outdoor display systems due to their advantages such as high contrast, high resolution, and compact structure. Outdoor large screens rely on COB module splicing technology to achieve giant displays; however, the epoxy resin encapsulation is sensitive to humidity, and the splicing edges are prone to damage and corrosion under harsh environments (temperature differences, rain, snow, vibration). Initial micro-cracks can accelerate their propagation due to stress concentration, leading to large-area failures and high repair costs. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a detection and protection circuit and a display device that can detect abnormalities in the encapsulation status at the splicing point in real time.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: a detection and protection circuit applied to a modular chip-on-board splicing display screen, comprising: The detection circuit includes a detection unit and outputs a detection signal based on the resistance change of the detection unit; the detection unit is disposed at the splicing point of the splicing display to sense the packaging status at the splicing point. The power supply path receives detection signals and provides different driving voltages to the splicing display screen according to the detection signals.

[0006] In some embodiments, the detection unit is a sensitive resistor; the detection circuit includes a voltage divider resistor connected in series with the sensitive resistor, the sensitive resistor being a humidity-sensitive resistor or a force-sensitive resistor; the connection node between the voltage divider resistor and the sensitive resistor is a voltage divider node, and the detection signal is output through the voltage divider node.

[0007] In some embodiments, the detection protection circuit further includes a main power supply and a backup power supply; the power supply path includes a first power supply path and a second power supply path. In response to the splicing point being in the first encapsulation state, the main power supply provides a first driving voltage to the splicing display screen through the first power supply path; In response to the second encapsulation state at the splicing point, the backup power supply provides a second driving voltage to the splicing display screen through the second power supply path; The first driving voltage is greater than the second driving voltage.

[0008] In some embodiments, the first power supply path includes a first transistor, a first terminal of the first transistor is connected to the main power supply, a second terminal of the first transistor is connected to the video wall display, and a control terminal of the first transistor is connected to a voltage divider node for receiving detection signals to control the on / off state of the first power supply path. The second power supply path includes a second transistor, the first end of which is connected to a backup power supply, the second end of which is connected to the splicing display screen, and the control end of which is connected to a voltage divider node to receive detection signals and control the on / off state of the second power supply path. The first transistor has the opposite conductivity type to the second transistor.

[0009] In some embodiments, the voltage divider resistor is connected between the main power supply and the voltage divider node, one end of the sensitive resistor is connected to the voltage divider node, and the other end of the sensitive resistor is grounded. The first power supply path also includes a first operational amplifier, the non-inverting input of the first operational amplifier is connected to the main power supply, the inverting input of the first operational amplifier is connected to the backup power supply, and the output of the first operational amplifier is connected to the first terminal of the first transistor. The second power supply path also includes a second operational amplifier, the non-inverting input of which is connected to the backup power supply, the inverting input of which is connected to the main power supply, and the output of which is connected to the first terminal of the second transistor. In response to the splicing point being in the first encapsulation state and the main power supply being in a normal state, power is supplied to the splicing display screen through the first power supply path; In response to the second encapsulation state at the splicing point, the main power supply is in an undervoltage state, and the actual output voltage of the main power supply is less than the power supply voltage of the backup power supply, power is supplied to the splicing display screen through the second power supply path.

[0010] In some embodiments, the detection protection circuit further includes a display control module for receiving control signals to control the display mode of the splicing display screen; wherein the detection signal is multiplexed as a control signal, or the control signal is output through a power supply path; The display control module includes a first switching unit, a second switching unit, a third transistor, and a fourth transistor; The first terminal of the third transistor is connected to the first switching unit, and the second terminal of the third transistor is connected to the splicing display screen. The first terminal of the fourth transistor is connected to the second switching unit, the second terminal of the fourth transistor is connected to the splicing display screen, and the control terminal of the fourth transistor is connected to the control terminal of the third transistor and is used to receive control signals; the third transistor and the fourth transistor have opposite conduction types. In response to the splicing point being in the first encapsulation state, the first switching unit controls the display area of ​​the splicing display screen to work in the first display mode; In response to the splicing area being in the second encapsulation state, the second switching unit controls the display area of ​​the splicing display screen to operate in the second display mode.

[0011] In some embodiments, the detection protection circuit further includes a display control module for receiving control signals to control the display mode of the splicing display screen; wherein the detection signal is multiplexed as a control signal, or the control signal is output through a power supply path; The display control module is connected between the drive circuit and multiple display zones of the splicing display screen, and is configured to establish or cut off the transmission path of the drive signal between the drive circuit and the display zones; wherein the drive circuit is a gate drive circuit or a source drive circuit.

[0012] In some embodiments, the display control module includes a first switch and a second switch, and the driving circuit includes a first gate driving circuit and a second gate driving circuit. The first terminal of the first switch is connected to the first gate driving circuit and to the display partition corresponding to the first gate driving circuit. The first terminal of the second switch is connected to the second gate driving circuit; the second terminal of the second switch is connected to the display partition corresponding to the second gate driving circuit, and is also connected to the second terminal of the first switch; the control terminal of the second switch is connected to the control terminal of the first switch and is used to receive control signals. The first switch and the second switch have opposite conductivity types; In response to the splicing point being in the first encapsulation state, the first gate driving circuit controls multiple display zones to refresh the display at the first refresh rate; In response to the splicing point being in the second packaged state, the second gate driving circuit controls the corresponding display partition to display at a second refresh rate different from the first refresh rate.

[0013] In some embodiments, the display control module is configured to correspond one-to-one with the display partition; the driving circuit includes a first gate driving circuit and a second gate driving circuit. The display control module includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; The first terminal of the first control transistor is connected to the first gate driving circuit, the second terminal of the first control transistor is connected to the corresponding display partition, and the control terminal of the first control transistor receives the control signal. The control terminal of the second control transistor receives the control signal; The first terminal of the third control transistor is connected to the first gate drive circuit, the second terminal of the third control transistor is connected to the corresponding display partition, and the control terminal of the third control transistor is used to receive the screen detection signal of the corresponding display partition. The first terminal of the fourth control transistor is connected to the second gate drive circuit, and the second terminal of the fourth control transistor is connected to the corresponding display partition. In this configuration, the control terminal of the third control transistor receives the screen detection signal through the second control transistor; or the second terminal of the third control transistor is connected to the corresponding display partition through the second control transistor. In response to the splicing point being in the first encapsulation state, the first gate driving circuit controls the corresponding display partition to refresh the display at the first refresh rate; In response to the splicing point being in the second encapsulation state and the display partition displaying dynamic images, the first gate driving circuit controls the corresponding display partition to refresh the display at the first refresh rate; In response to the splicing point being in the second encapsulation state and the display partition displaying a static or repeating image, the second gate driving circuit controls the corresponding display partition to refresh the display at a second refresh rate different from the first refresh rate.

[0014] In some embodiments, the display control module includes two control switches connected in parallel, and the control terminals of both control switches receive control signals. The display control module is configured to correspond one-to-one with the display partition; the display control module is connected between the corresponding display partition and the source drive circuit, or the display control module is connected between the corresponding display partition and the gate drive circuit. The display partition where the splicing location is not located is the first display partition. In the display control module corresponding to the first display partition, the two control switches have opposite conductivity types. The display zone where the splicing point is located is the second display zone. In the display control module corresponding to the second display zone, the two control switches have the same conductivity type. When the splicing area is in the first encapsulation state, each display zone displays normally; When the splicing area is in the second encapsulation state, the first display partition displays normally, while the second display partition displays a black screen.

[0015] In some embodiments, the detection and protection circuit includes a main power supply and a display control module. A voltage divider resistor is connected between the main power supply and the voltage divider node. One end of a sensitive resistor is connected to the voltage divider node, and the other end of the sensitive resistor is grounded. A power supply path is connected between the voltage divider node and the video wall display screen. The display control module is used to receive control signals to control the display mode of the video wall display screen. The display control module is connected between the voltage divider node and the video wall display to multiplex the detection signal into a control signal; or, The detection and protection circuit also includes a third operational amplifier and a fourth operational amplifier. The non-inverting input of the third operational amplifier is connected to the main power supply, the inverting input of the third operational amplifier is connected to the voltage divider node, and the output of the third operational amplifier is connected to the inverting input of the fourth operational amplifier, and is used to output the difference between the output voltage of the main power supply and the voltage of the voltage divider node to the fourth operational amplifier. The non-inverting input of the fourth operational amplifier receives the threshold voltage, and the output of the fourth operational amplifier is connected to the display control module so that the output signal of the fourth operational amplifier is used as a control signal.

[0016] To solve the above-mentioned technical problems, the second technical solution provided by this application is: to provide a display device, which includes a splicing display screen and the above-mentioned detection and protection circuit.

[0017] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a detection protection circuit and a display device. The detection protection circuit is applied to a modular chip-on-board splicing display screen. The detection protection circuit includes a detection circuit and a power supply path. The detection circuit includes a detection unit and outputs a detection signal based on the resistance change of the detection unit. The detection unit is disposed at the splicing point of the splicing display screen to sense the packaging state at the splicing point. The power supply path receives the detection signal and provides different driving voltages to the splicing display screen according to the detection signal. By placing the detection unit at the splicing point and outputting a detection signal based on the resistance change, abnormal packaging states at the splicing point can be detected in real time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an embodiment of the display device provided in this application; Figure 2 This is a schematic diagram of the structure of the first embodiment of the detection and protection circuit provided in this application; Figure 3 This is a schematic diagram of the second embodiment of the detection and protection circuit provided in this application; Figure 4 This is a schematic diagram of the third embodiment of the detection and protection circuit provided in this application; Figure 5 This is a schematic diagram of the structure of the first embodiment of the display control module and display partition provided in this application; Figure 6This is a schematic diagram of the structure of the second embodiment of the display control module and display partition provided in this application; Figure 7 This is a schematic diagram of the structure of the display control module and display partition in the third embodiment provided in this application; Figure 8 This is a schematic diagram of the structure of the display control module and display partition in the fourth embodiment provided in this application; Figure 9 This is a schematic diagram of the structure of the first embodiment of the detection module provided in this application; Figure 10 This is a schematic diagram of the structure of the second embodiment of the detection module provided in this application; Figure 11 This is a schematic diagram of the structure of the third embodiment of the detection module provided in this application; Figure 12 This is a schematic diagram of the fourth embodiment of the detection module provided in this application; Figure 13 This is a schematic diagram of the structure of the fifth embodiment of the display control module and display partition provided in this application in the first packaged state; Figure 14 This is a schematic diagram of the display control module and display partition fifth embodiment provided in this application in the second packaged state; Figure 15 This is a schematic diagram of the structure of the sixth embodiment of the display control module and display partition provided in this application; Figure 16 This is a schematic diagram of the structure of the seventh embodiment of the display control module and display partition provided in this application; Figure 17 This is a schematic diagram of the fourth embodiment of the detection and protection circuit provided in this application; Figure 18 This is a schematic diagram of the fifth embodiment of the detection and protection circuit provided in this application; Figure 19 This is a schematic diagram of an embodiment of the display control module provided in this application.

[0020] Explanation of icon numbers: 100. Detection and protection circuit; 10. Detection circuit; 11. Detection unit; R1. Voltage divider resistor; R2. Sensitive resistor; a. Voltage divider node; 20. Power supply path; 21. First power supply path; 22. Second power supply path; V1. Main power supply; V2. Backup power supply; U1. First operational amplifier; U2. Second operational amplifier; U3. Third operational amplifier; U4. Fourth operational amplifier; +. Non-inverting input terminal; -. Inverting input terminal; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; S. Control signal; 30. Display control module; 31. First switching unit; 32. Second switching unit; T1. First switch; T2. Second switch; T3. First control switch; T4. Second control switch; 301. The... 1. AND gate; 302. Second AND gate; 303. Third AND gate; 304. Fourth AND gate; 305. NOT gate; 306. OR gate; Q1. First control transistor; Q2. Second control transistor; Q3. Third control transistor; Q4. Fourth control transistor; Q5. Fifth control transistor; Q6. Sixth control transistor; Q7. Seventh control transistor; Q8. Eighth control transistor; Q9. Ninth control transistor; Q10. Tenth control transistor; Vdd. High-level signal terminal; 40. Electrostatic discharge protection module; 50. Anti-backflow module; 1. Display device; 200. Splicing display screen; 60. Display zone; 61. First display zone; 62. Second display zone; 70. Detection module; 71. XNOR gate; Vt1. First data voltage; Vt2. Second data voltage. Detailed Implementation

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of an embodiment of the display device provided in this application. Figure 2 This is a schematic diagram of the first embodiment of the detection and protection circuit provided in this application.

[0027] This application provides a display device 1, which includes a video wall display 200 and a detection and protection circuit 100.

[0028] The detection and protection circuit 100 is used to drive the splicing display screen 200.

[0029] The splicing display screen 200 is a modular splicing display screen 200 with chips on the board.

[0030] The on-board chip modular splicing display 200 refers to an independent display module made based on on-board chip (COB) packaging technology, which forms a continuous display surface through physical splicing.

[0031] In some embodiments, the splicing display screen 200 is a large-size display screen and supports the replacement of individual display modules. For example, the splicing display screen 200 can be a large screen such as an advertising screen, a large screen in a command and dispatch center, or an integrated screen in a conference room / exhibition hall.

[0032] This application provides a detection protection circuit 100 applied to a modular chip-on-board splicing display screen 200. The detection protection circuit 100 includes a detection circuit 10 and a power supply path 20. The detection circuit 10 includes a detection unit 11 and outputs a detection signal based on the resistance change of the detection unit 11. The detection unit 11 is disposed at the splicing point of the splicing display screen 200 to sense the packaging state at the splicing point. The power supply path 20 receives the detection signal and provides different driving voltages to the splicing display screen 200 according to the detection signal.

[0033] By setting the detection unit 11 at the splicing point and outputting a detection signal based on the resistance change, abnormal packaging status at the splicing point can be detected in real time.

[0034] The splicing point of the splicing display screen 200 refers to the physical contact surface between the edges of two adjacent display modules (i.e., COB modules) in the splicing display screen 200.

[0035] The power supply path 20 provides different driving voltages according to the detection signal, thereby avoiding high voltage driving from further accelerating corrosion and helping to extend the service life of the module.

[0036] In some embodiments, the detection unit 11 is a sensitive resistor R2; the detection circuit 10 includes a voltage divider resistor R1 connected in series with the sensitive resistor R2, and the sensitive resistor R2 is a humidity-sensitive resistor or a force-sensitive resistor; the connection node between the voltage divider resistor R1 and the sensitive resistor R2 is a voltage divider node a, and the detection signal is output through the voltage divider node a.

[0037] The voltage divider resistor R1 and the sensitive resistor R2 are connected in series in the detection circuit 10. The sensitive resistor R2 is directly set at the splicing point of the splicing display screen 200 to sense the packaging status at the splicing point.

[0038] In some specific embodiments, a humidity-sensitive resistor is used as the sensing resistor R2. Its resistance can reach the megaohm level in a dry environment, and its resistance decreases exponentially as humidity increases. Specifically, when the encapsulation at the splice is intact, the humidity is low, and the resistance of the humidity-sensitive resistor is relatively large; when the encapsulation at the splice is damaged, moisture can enter, resulting in high humidity, and the resistance of the humidity-sensitive resistor decreases rapidly.

[0039] In some other specific embodiments, a force-sensitive resistor is used as the sensing resistor R2, whose resistance changes significantly when affected by pressure. Specifically, when the encapsulation at the splice is damaged, the pressure on the force-sensitive resistor decreases, and the resistance of the force-sensitive resistor increases.

[0040] The resistance value of the voltage divider resistor R1 is fixed, and the voltage divider resistor R1 can be composed of one or more voltage divider sub-resistors connected in series and parallel.

[0041] For example, this application uses the example of a voltage divider resistor R1 consisting of a single resistor for illustration.

[0042] In some embodiments, the voltage of voltage divider node a decreases as the resistance of sensitive resistor R2 decreases. If sensitive resistor R2 is a humidity-sensitive resistor, one end of the humidity-sensitive resistor is connected to voltage divider node a and the other end is grounded. Voltage divider resistor R1 is connected between the high-level signal terminal Vdd and voltage divider node a. If sensitive resistor R2 is a force-sensitive resistor, one end of voltage divider resistor R1 is connected to voltage divider node a and the other end is grounded. Force-sensitive resistor is connected between the high-level signal terminal Vdd and voltage divider node a.

[0043] In other embodiments, the voltage at voltage divider node a increases as the resistance of sensitive resistor R2 decreases. If sensitive resistor R2 is a humidity-sensitive resistor, one end of voltage divider resistor R1 is connected to voltage divider node a, and the other end is grounded. The humidity-sensitive resistor is connected between the high-level signal terminal Vdd and voltage divider node a. If sensitive resistor R2 is a force-sensitive resistor, one end of force-sensitive resistor is connected to voltage divider node a, and the other end is grounded. The voltage divider resistor R1 is connected between the high-level signal terminal Vdd and voltage divider node a.

[0044] By connecting the voltage divider resistor R1 and the sensitive resistor R2 in series, the voltage change at voltage divider node a is correlated with the resistance change of the sensitive resistor R2, thereby realizing the output of the detection signal, which is beneficial for accurately reflecting the packaging status. By setting the sensitive resistor R2 as a humidity-sensitive resistor or a force-sensitive resistor, the change in packaging status is converted into a change in electrical signal, which makes it easier for the power supply path 20 to provide different driving voltages to the splicing display screen 200 based on the voltage change of the detection signal, thereby avoiding high voltage driving from continuing to accelerate corrosion and extending the module's service life.

[0045] This application mainly uses the example of a sensitive resistor R2 being a humidity-sensitive resistor, with one end of the humidity-sensitive resistor connected to voltage divider node a and the other end grounded.

[0046] In some embodiments, such as Figure 1 As shown, the detection and protection circuit 100 also includes a main power supply V1 and a backup power supply V2; the power supply path 20 includes a first power supply path 21 and a second power supply path 22. In response to the first encapsulation state at the splicing point, the main power supply V1 provides a first driving voltage to the splicing display screen 200 through the first power supply path 21; in response to the second encapsulation state at the splicing point, the backup power supply V2 provides a second driving voltage to the splicing display screen 200 through the second power supply path 22; the first driving voltage is greater than the second driving voltage.

[0047] The main power supply V1 and the backup power supply V2 are connected to the input terminal of the splicing display screen 200 through the first power supply path 21 and the second power supply path 22, respectively. The first power supply path 21 is turned on when the splicing point is in the first encapsulation state, and the second power supply path 22 is turned on when the splicing point is in the second encapsulation state.

[0048] The first packaging state refers to the joint being intact and undamaged, while the second packaging state refers to the joint being damaged, leading to moisture intrusion.

[0049] By introducing a backup power supply V2 and providing a lower second driving voltage in the second packaging state, the driving voltage of the splicing display screen 200 is reduced in the abnormal packaging state (i.e., the second packaging state), thereby reducing current and heat generation and avoiding high voltage driving that accelerates the corrosion of epoxy resin.

[0050] By configuring the main power supply V1 and the backup power supply V2, the system automatically switches to low-voltage drive when damage occurs at the splicing point, thus avoiding the accelerated corrosion of epoxy resin by high voltage. The design of the first drive voltage being greater than the second drive voltage reduces the current after the second drive voltage is lowered, which helps to slow down the aging of the module. The display brightness is reduced by using low-voltage drive, which helps to detect abnormal conditions in a timely manner. This further improves the system's emergency display capability (i.e., some important information can still be displayed without delaying emergency use) and service life in the event of packaging abnormalities.

[0051] In some embodiments, the first power supply path 21 includes a first transistor M1, the first end of the first transistor M1 is connected to the main power supply V1, the second end of the first transistor M1 is connected to the splicing display screen 200, and the control end of the first transistor M1 is connected to the voltage divider node a for receiving detection signals to control the on / off state of the first power supply path 21. The second power supply path 22 includes a second transistor M2. The first end of the second transistor M2 is connected to the backup power supply V2, the second end of the second transistor M2 is connected to the splicing display screen 200, and the control end of the second transistor M2 is connected to the voltage divider node a to receive detection signals and control the on / off state of the second power supply path 22. The first transistor M1 has the opposite conductivity type to the second transistor M2.

[0052] One of the first transistor M1 and the second transistor M2 is of N-type conductivity, and the other is of P-type conductivity. They operate complementaryly to avoid simultaneous conduction. Specifically, in the first package state, when the detection signal is at a first level, the first transistor M1 is turned on while the second transistor M2 is turned off; in the second package state, when the detection signal is at a second level, the first transistor M1 is turned off while the second transistor M2 is turned on.

[0053] One of the first level and the second level is high, and the other is low.

[0054] The first voltage level determines the conduction type of the first transistor M1, and the second voltage level determines the conduction type of the second transistor M2.

[0055] In this embodiment, the first transistor M1 is N-type and the second transistor M2 is P-type, as an example for illustration.

[0056] For example, an N-MOS (Metal-Oxide-Semiconductor) transistor can be used as the first transistor M1, and a P-MOS transistor as the second transistor M2. In other embodiments, the first transistor M1 and the second transistor M2 can be other types of transistors, which are not limited here.

[0057] For example, when the splicing joint is intact, the resistance of the humidity-sensitive resistor is high, the voltage of the voltage divider node a is high, the first transistor M1 is turned on while the second transistor M2 is turned off, and the main power supply V1 provides high voltage drive to the splicing display screen 200 through the first power supply path 21; when the splicing joint is damaged and moisture enters, the resistance of the humidity-sensitive resistor decreases, the voltage of the voltage divider node a is low, the first transistor M1 is turned off while the second transistor M2 is turned on, and the backup power supply V2 provides low voltage drive to the splicing display screen 200 through the second power supply path 22.

[0058] In this embodiment, the voltage divider resistor R1 is connected between the high-level signal terminal Vdd and the voltage divider node a. The high-level signal terminal Vdd can be the main power supply V1, the backup power supply V2, or other power supplies.

[0059] By setting the first transistor M1 and the second transistor M2 to have opposite conduction types, the two transistors are ensured to be in a complementary conduction state when the voltage of the voltage divider node a changes, thereby avoiding the risk of short circuit during power switching and helping to prevent circuit damage. The stable switching driven by low voltage helps to maintain the basic display function of the splicing display screen 200 in abnormal packaging state, while reducing current and heat generation, and effectively slowing down the corrosion rate of epoxy resin.

[0060] Please see Figure 2 and Figure 3 , Figure 3 This is a schematic diagram of the second embodiment of the detection and protection circuit provided in this application.

[0061] In some embodiments, the voltage divider resistor R1 is connected between the main power supply V1 and the voltage divider node a, one end of the sensitive resistor R2 is connected to the voltage divider node a, and the other end of the sensitive resistor R2 is grounded.

[0062] The first power supply path 21 also includes a first operational amplifier U1, the non-inverting input terminal + of the first operational amplifier U1 is connected to the main power supply V1, the inverting input terminal - of the first operational amplifier U1 is connected to the backup power supply V2, and the output terminal of the first operational amplifier U1 is connected to the first terminal of the first transistor M1.

[0063] The second power supply path 22 also includes a second operational amplifier U2. The non-inverting input terminal + of the second operational amplifier U2 is connected to the backup power supply V2, the inverting input terminal - of the second operational amplifier U2 is connected to the main power supply V1, and the output terminal of the second operational amplifier U2 is connected to the first terminal of the second transistor M2.

[0064] In response to the first encapsulation state at the splicing point and the main power supply V1 being in a normal state, power is supplied to the splicing display screen 200 through the first power supply path 21; in response to the second encapsulation state at the splicing point, the main power supply V1 being in an undervoltage state and the actual output voltage of the main power supply V1 being less than the power supply voltage of the backup power supply V2, power is supplied to the splicing display screen 200 through the second power supply path 22.

[0065] For ease of description, the power supply voltage output by the main power supply V1 is referred to as the main power supply V1 voltage, and the power supply voltage output by the backup power supply V2 is referred to as the backup power supply V2 voltage.

[0066] For example, when the splicing point is properly encapsulated (first encapsulation state), the voltage of voltage divider node a is high, the main power supply V1 voltage is normal and higher than the backup power supply V2 voltage, the first operational amplifier U1 outputs a high level (i.e., Vout1=V1), the first transistor M1 is turned on, and power is supplied through the first power supply path 21 so that the main power supply V1 voltage is transmitted to the splicing display screen 200 through the first transistor M1; at the same time, the second operational amplifier U2 outputs a low level (i.e., Vout2=0), and the second transistor M2 is turned off.

[0067] When the splicing joint is damaged (second encapsulation state), the voltage of voltage divider node a decreases, the main power supply V1 is undervoltage and the output voltage is lower than the backup power supply V2 voltage, the second operational amplifier U2 outputs a high level (i.e., Vout2=V2), the second transistor M2 is turned on, and power is supplied through the second power supply path 22 so that the backup power supply V2 voltage is transmitted to the splicing display screen 200 through the second transistor M2; at the same time, the first operational amplifier U1 outputs a low level (i.e., Vout1=0), and the first transistor M1 is turned off.

[0068] When the splicing point is in the first encapsulation state and the main power supply V1 is normal, the main power supply V1 is used first to ensure efficient system operation; when the splicing point is in the second encapsulation state and the main power supply V1 is undervoltage, and the output voltage of the main power supply V1 is less than the voltage of the backup power supply V2, the system automatically switches to the backup power supply V2 to ensure emergency operation of the equipment.

[0069] In some embodiments, such as Figure 3 As shown, the detection and protection circuit 100 also includes an electrostatic discharge (ESD) protection module 40, which includes a first diode and a capacitor connected in parallel. One end of the ESD protection module 40 is connected to the power supply module, and the other end is grounded. The power supply module includes a main power supply V1 or a backup power supply V2.

[0070] For example, in the electrostatic discharge protection module 40, the anode of the first diode is connected to the power supply module, and the cathode of the first diode is grounded; one end of the capacitor is connected to the power supply module, and the other end is grounded. D1 and D2 represent different first diodes, and C1 and C2 represent different capacitors.

[0071] Specifically, one end of an electrostatic discharge protection module 40 is connected to the main power supply V1, and the other end is grounded; one end of another electrostatic discharge protection module 40 is connected to the backup power supply V2, and the other end is grounded.

[0072] By setting an electrostatic protection module 40 at the rear end of the power module, the AC components in the power module are filtered out, and the power module is protected from electrostatic interference.

[0073] In some embodiments, the power supply path 20 further includes an anti-backflow module 50, one end of which is connected to the second end of the first transistor M1 and / or the second end of the second transistor M2, and the other end of which is connected to the splicing display screen 200.

[0074] For example, the anti-backflow module 50 includes two branches arranged in parallel, each branch including a protective resistor and a second diode arranged in series. R3 to R6 represent different protective resistors, and D3 to D6 represent different second diodes.

[0075] For example, one end of an anti-backflow module 50 is connected to the second end of the first transistor M1, and the other end is connected to the splicing display screen 200; one end of another anti-backflow module 50 is connected to the second end of the second transistor M2, and the other end is connected to the splicing display screen 200.

[0076] By incorporating an anti-backflow module 50, voltage backflow from the splicing display screen 200 is prevented from damaging the circuit. In one branch, a protective resistor is connected in series with the second diode to act as a voltage divider, preventing high voltage from damaging the second diode. The two branches are connected in parallel to protect the circuit and prevent large currents from damaging components or the circuitry.

[0077] Please see Figure 3 and Figure 4 , Figure 4 This is a schematic diagram of the third embodiment of the detection and protection circuit provided in this application.

[0078] In some embodiments, the detection protection circuit 100 further includes a display control module 30, which receives a control signal S to control the display mode of the splicing display screen 200; wherein the detection signal is multiplexed as the control signal S, or the control signal S is output through the power supply path 20.

[0079] The display control module 30 includes a first switching unit 31, a second switching unit 32, a third transistor M3, and a fourth transistor M4.

[0080] The first terminal of the third transistor M3 is connected to the first switching unit 31, and the second terminal of the third transistor M3 is connected to the splicing display screen 200.

[0081] The first terminal of the fourth transistor M4 is connected to the second switching unit 32, the second terminal of the fourth transistor M4 is connected to the splicing display screen 200, and the control terminal of the fourth transistor M4 is connected to the control terminal of the third transistor M3 and is used to receive the control signal S; the conductivity type of the third transistor M3 and the fourth transistor M4 is opposite.

[0082] In response to the splicing area being in the first encapsulation state, the first switching unit 31 controls the display area of ​​the splicing display screen 200 to work in the first display mode; in response to the splicing area being in the second encapsulation state, the second switching unit 32 controls the display area of ​​the splicing display screen 200 to work in the second display mode.

[0083] The first display mode is the normal display mode, and the second display mode is the low-power display mode.

[0084] In the first package state, the third transistor M3 is turned on and the fourth transistor M4 is turned off; in the second package state, the third transistor M3 is turned off and the fourth transistor M4 is turned on.

[0085] In some embodiments, such as Figure 4 As shown, in the second power supply path 22, the output terminal of the second operational amplifier U2 is connected to the control terminal of the third transistor M3, so that the output signal of the second operational amplifier U2 is used as the control signal S. Specifically, the third transistor M3 is a P-MOS transistor, and the fourth transistor M4 is an N-MOS transistor. In the first package state, the second operational amplifier U2 outputs a low level (i.e., Vout2=0) to drive the third transistor M3 to conduct and the fourth transistor M4 to turn off, and the first switching unit 31 enables the splicing display screen 200 to operate in the first display mode; in the second package state, the second operational amplifier U2 outputs a high level (i.e., Vout2=V2) to drive the third transistor M3 to turn off and the fourth transistor M4 to conduct, and the second switching unit 32 enables the splicing display screen 200 to operate in the second display mode. For example, a protective resistor R7 can be set between the output of the second operational amplifier U2 and the display control module to avoid damage to components or circuits by large current.

[0086] In some other embodiments, in the first power supply path 21, the output terminal of the first operational amplifier U1 is connected to the control terminal of the third transistor M3 so that the output signal of the first operational amplifier U1 is used as the control signal S. At this time, the fourth transistor M4 is a P-MOS transistor and the third transistor M3 is an N-MOS transistor.

[0087] In other embodiments, the detection signal is multiplexed as a control signal S. Specifically, the voltage divider node a in the detection protection circuit 100 is connected to the control terminal of the fourth transistor M4.

[0088] By configuring the third transistor M3 and the fourth transistor M4 with opposite conduction types, the system automatically switches to a low-power display mode in case of abnormal encapsulation at the splicing point, thereby reducing circuit current and heat generation. The structural design of the display control module 30 allows the display area of ​​the splicing display screen 200 to adopt a second display mode in the second encapsulation state, which helps reduce power consumption and slow down epoxy resin corrosion. The mechanism of multiplexing the detection signal into a control signal S, or outputting the control signal S through the power supply path 20, avoids additional signal processing circuitry, improving system integration and reliability. The switching logic between the first and second display modes reduces display brightness in abnormal encapsulation states, facilitating timely detection of module malfunctions. This further improves the system's display duration and maintenance response efficiency in emergency situations.

[0089] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the structure of the display control module and display partition according to the first embodiment of this application. Figure 6 This is a schematic diagram of the structure of the second embodiment of the display control module and display partition provided in this application.

[0090] In some other embodiments, the detection protection circuit 100 further includes a display control module 30 for receiving a control signal S to control the display mode of the splicing display screen 200; wherein the detection signal is multiplexed as the control signal S, or the control signal S is output through the power supply path 20; the display control module 30 is connected between the driving circuit and multiple display zones 60 of the splicing display screen 200, and is configured to establish or disconnect the transmission path of the driving signal between the driving circuit and the display zone 60; wherein the driving circuit is a gate driving circuit or a source driving circuit.

[0091] In some embodiments, the display modes include a high refresh rate mode and a low refresh rate mode. In other embodiments, the display modes include a partitioned refresh display and a global refresh display.

[0092] In the first encapsulation state, the display control module 30 controls the splicing display screen 200 to perform global refresh display or high refresh rate mode display. In the second encapsulation state, the display control module 30 controls the splicing display screen 200 to perform zone refresh display or low refresh rate display, which reduces the driving current of the splicing display screen 200, reduces heat generation, and helps to delay the accelerated corrosion of epoxy resin caused by the current thermal effect; through the dynamic zone refresh mechanism, the display load demand is reduced, further reducing panel current and voltage, which helps to extend the emergency use time of the module in abnormal encapsulation state.

[0093] In some embodiments, such as Figure 5 As shown, the display control module 30 includes a first switch T1 and a second switch T2, and the driving circuit includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2. The first terminal of the first switch T1 is connected to the first gate driving circuit GOA1 and to the display partition 60 corresponding to the first gate driving circuit GOA1. The first terminal of the second switch T2 is connected to the second gate driving circuit GOA2. The second terminal of the second switch T2 is connected to the display partition 60 corresponding to the second gate driving circuit GOA2 and to the second terminal of the first switch T1. The control terminal of the second switch T2 is connected to the control terminal of the first switch T1 and is used to receive the control signal S. The first switch T1 and the second switch T2 have opposite conductivity types; In response to the splicing point being in the first encapsulation state, the first gate driving circuit GOA1 controls multiple display zones 60 to refresh and display at the first refresh rate; In response to the splicing point being in the second packaged state, the second gate drive circuit GOA2 controls the corresponding display partition 60 to display at a second refresh rate different from the first refresh rate.

[0094] For example, display partition 60 is divided into a first display partition 61 and a second display partition 62. The display partition 60 corresponding to the first gate driving circuit GOA1 is the first display partition 61, and the display partition 60 corresponding to the second gate driving circuit GOA2 is the second display partition 62. There can be multiple second gate driving circuits GOA2. Each second gate driving circuit GOA2 is configured to correspond one-to-one with a second display partition 62.

[0095] It should be noted that the second gate drive circuit GOA2 is only distinguished from the first gate drive circuit GOA1.

[0096] The layout of the first display partition 61 and the second display partition 62 is not limited and can be selected according to actual needs. For ease of understanding, an example is given where the display area includes two display partitions 60. In some embodiments, such as... Figure 5As shown, the first display partition 61 and the second display partition 62 are arranged horizontally side by side. In other embodiments, such as... Figure 6 As shown, the first display partition 61 and the second display partition 62 are arranged side by side vertically.

[0097] The first refresh rate is greater than the second refresh rate.

[0098] In the first packaged state, the first switch T1 is turned on and the second switch T2 is turned off. At this time, the first gate driving circuit GOA1 drives all display partitions 60 to perform global high refresh rate display at the first refresh rate. In the second packaged state, the first switch T1 is turned off and the second switch T2 is turned on. At this time, the first gate driving circuit GOA1 drives the first display partition 61 to perform high refresh rate display at the first refresh rate, and the second gate driving circuit GOA2 drives the corresponding second display partition 62 to perform low refresh rate display at the second refresh rate, thereby reducing the power consumption of some display partitions 60.

[0099] For example, the description will be given with the detection signal at a high level in the first packaged state. In some embodiments, the detection signal is multiplexed as a control signal S, and the conductivity type of the first switch T1 is N-type (i.e., high-level conduction type). In other embodiments, the control signal S is output via the power supply path 20, for example, the control signal S is output via... Figure 3 The output of the first operational amplifier U1 is output, and the first switch T1 has a P-type conductivity (i.e., low-level conduction). For example, the control signal S is transmitted via... Figure 3 The output of the second operational amplifier U2 is output, and the first switch T1 is of type N (i.e., high-level conduction type).

[0100] By having the first switch T1 and the second switch T2 have opposite conductivity types, the two switches will not conduct simultaneously when the control signal S changes, thereby avoiding short circuits and further improving the reliability of system switching. The driving circuit includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2, so that in abnormal packaging conditions, the second gate driving circuit GOA2 specifically controls the low refresh rate display, thereby reducing the driving current, further reducing panel heating, and slowing down the module corrosion rate.

[0101] Please see Figures 5 to 8 , Figure 7 This is a schematic diagram of the structure of the display control module and display partition in the third embodiment provided in this application. Figure 8 This is a structural schematic diagram of the fourth embodiment of the display control module and display partition provided in this application.

[0102] In other embodiments, the display control module 30 is configured in a one-to-one correspondence with the display partitions 60; the driving circuit includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2; the display control module 30 includes a first control transistor Q1, a second control transistor Q2, a third control transistor Q3, and a fourth control transistor Q4; the first terminal of the first control transistor Q1 is connected to the first gate driving circuit GOA1, the second terminal of the first control transistor Q1 is connected to the corresponding display partition 60, and the control terminal of the first control transistor Q1 receives a control signal S; the control terminal of the second control transistor Q2 receives the control signal S; the first terminal of the third control transistor Q3 is connected to the first gate driving circuit GOA1, the second terminal of the third control transistor Q3 is connected to the corresponding display partition 60, and the control terminal of the third control transistor Q3 is used to receive the screen detection signal Y1 of the corresponding display partition 60; the first terminal of the fourth control transistor Q4 is connected to the second gate driving circuit GOA2, and the second terminal of the fourth control transistor Q4 is connected to the corresponding display partition 60; Among them, the control terminal of the third control transistor Q3 receives the screen detection signal Y1 through the second control transistor Q2; or the second terminal of the third control transistor Q3 is connected to the corresponding display partition 60 through the second control transistor Q2. In response to the splicing area being in the first encapsulation state, the first gate driving circuit GOA1 controls the corresponding display partition 60 to refresh the display at the first refresh rate; in response to the splicing area being in the second encapsulation state and the display partition 60 displaying dynamic images, the first gate driving circuit GOA1 controls the corresponding display partition 60 to refresh the display at the first refresh rate; in response to the splicing area being in the second encapsulation state and the display partition 60 displaying static or repetitive images, the second gate driving circuit GOA2 controls the corresponding display partition 60 to refresh the display at a second refresh rate different from the first refresh rate.

[0103] The first control transistor Q1 and the second control transistor Q2 have opposite conduction types, and the third control transistor Q3 and the fourth control transistor Q4 have opposite conduction types. Specifically, in the first package state, the first control transistor Q1 is turned on, while the second control transistor Q2, the third control transistor Q3, and the fourth control transistor Q4 are turned off. The first gate drive circuit GOA1 controls the corresponding display partition 60 to display at a high refresh rate using the first refresh rate. In the second package state, the first control transistor Q1 is turned off, and the second control transistor Q2 is turned on. If the display partition 60 displays a dynamic image, the third control transistor Q3 is turned on, and the fourth control transistor Q4 is turned off. The first gate drive circuit GOA1 controls the corresponding display partition 60 to display at a high refresh rate using the first refresh rate. If the display partition 60 displays a static or repetitive image, the third control transistor Q3 is turned off, and the fourth control transistor Q4 is turned on. The second gate drive circuit GOA2 controls the corresponding display partition 60 to display at a low refresh rate using a second refresh rate different from the first refresh rate. This reduces panel heat generation, which helps to delay the accelerated corrosion of epoxy resin caused by the current thermal effect and extends the duration of the module in emergency use.

[0104] For example, in the first packaged state, both the control signal S and the screen detection signal Y1 are at a high level. The first control transistor Q1 and the third control transistor Q3 are both N-type.

[0105] In one specific embodiment, such as Figure 7 As shown, the first terminal of the second control transistor Q2 is connected to the control terminal of the third control transistor Q3, and the second terminal of the second control transistor Q2 is connected to the corresponding display partition 60 to receive the image detection signal; the second terminal of the third control transistor Q3 is also connected to the corresponding display partition 60. Figure 8 As shown, in another specific embodiment, the control terminal of the third control transistor Q3 directly receives the screen detection signal, the second terminal of the third control transistor Q3 is connected to the first terminal of the second control transistor Q2, and the second terminal of the second control transistor Q2 is connected to the corresponding display partition 60.

[0106] The screen detection signal Y1 is received by the control terminal of the third control transistor Q3, which automatically switches to the second gate drive circuit GOA2 when displaying static or repeating images, thereby achieving a low refresh rate display and further reducing the drive current of the display partition 60. The high refresh rate of the first gate drive circuit GOA1 is maintained by the dynamic image, so that the display quality is not affected and the readability of the emergency display is maintained. The signal transmission mechanism of the second control transistor Q2 ensures that the screen detection signal Y1 accurately triggers the refresh rate switching and avoids display abnormalities caused by signal interference.

[0107] Please see Figures 5 to 12 , Figure 9 This is a schematic diagram of the structure of the first embodiment of the detection module provided in this application. Figure 10 This is a schematic diagram of the structure of the second embodiment of the detection module provided in this application. Figure 11 This is a schematic diagram of the structure of the third embodiment of the detection module provided in this application. Figure 12 This is a structural schematic diagram of the fourth embodiment of the detection module provided in this application.

[0108] In some embodiments, the detection protection circuit 100 further includes a detection module 70, which is used to detect the display screen of the splicing display screen and output a screen detection signal Y1 according to the display screen. Specifically, the detection module 70 receives a first data voltage Vt1 and a second data voltage Vt2; the first data voltage Vt1 and the second data voltage Vt2 correspond to the pixel driving voltage of the same display partition 60 in two consecutive frames.

[0109] In different detection modules 70, the screen detection signal Y1 output when displaying a static or repeating image can be either high or low. The conductivity type of the corresponding third control transistor Q3 and fourth control transistor Q4 is selected based on the screen detection signal Y1.

[0110] In some specific embodiments, such as Figure 9 As shown, the detection module 70 includes a XOR gate 71.

[0111] In other specific embodiments, such as Figure 10 As shown, the detection module 70 includes a fifth control transistor Q5, a sixth control transistor Q6, a seventh control transistor Q7, and an eighth control transistor Q8. The first terminal of the fifth control transistor Q5 is connected to a high-level signal terminal Vdd, and the second terminal of the fifth control transistor Q5 is connected to the first terminal of the seventh control transistor Q7. The control terminal of the fifth control transistor Q5 receives a first data voltage Vt1. The first terminal of the sixth control transistor Q6 is connected to a high-level signal terminal Vdd, and the second terminal of the sixth control transistor Q6 is connected to the second terminal of the fifth control transistor Q5. The control terminal of the sixth control transistor Q6 receives a second data voltage Vt2. The first terminal of the seventh control transistor Q7 is connected to the second terminal of the sixth control transistor Q6, serving as the output terminal of the detection module 70 and connected to the display control module 30. The second terminal of the seventh control transistor Q7 is connected to the first terminal of the eighth control transistor Q8, and the second terminal of the eighth control transistor Q8 is grounded. The control terminal of the seventh control transistor Q7 receives the first data voltage Vt1, and the control terminal of the eighth control transistor Q8 receives the second data voltage Vt2.

[0112] In response to both the first data voltage Vt1 and the second data voltage Vt2 being high or both being low (i.e., display partition 60 displays a static or repeating image), the detection module 70 outputs a high-level image detection signal Y1. In response to one of the first data voltage Vt1 and the second data voltage Vt2 being high and the other low (i.e., display partition 60 displays a real-time dynamic image), the detection module 70 outputs a low-level image detection signal Y1.

[0113] Among them, the seventh control transistor Q7 and the fifth control transistor Q5 have the same conduction type, the eighth control transistor Q8 and the sixth control transistor Q6 have the same conduction type, and the fifth control transistor Q5 and the sixth control transistor Q6 have opposite conduction types.

[0114] For example, the seventh control transistor Q7 and the fifth control transistor Q5 are both P-MOS transistors, and the eighth control transistor Q8 and the sixth control transistor Q6 are both N-MOS transistors.

[0115] In this embodiment, the truth table of the detection module 70 is shown in Table 1.

[0116]

[0117] In some other specific embodiments, such as Figure 11 As shown, the detection module 70 also includes a ninth control transistor Q9 and a tenth control transistor Q10. The ninth and tenth control transistors Q9 and Q10 are connected in series between the high-level signal terminal Vdd and the ground terminal. The control terminals of both the ninth and tenth control transistors Q9 and Q10 are connected to the second terminal of the sixth control transistor Q6. The connection point between the ninth and tenth control transistors Q9 and Q10 serves as the output terminal of the detection module 70 and is connected to the splicing display screen 200. The ninth and tenth control transistors Q9 have opposite conductivity types and the same conductivity type as the fifth control transistor Q5.

[0118] In response to both the first data voltage Vt1 and the second data voltage Vt2 being high or both being low (i.e., display partition 60 displays a static or repeating image), the detection module 70 outputs a low-level image detection signal Y1. In response to one of the first data voltage Vt1 and the second data voltage Vt2 being high and the other low (i.e., display partition 60 displays a real-time dynamic image), the detection module 70 outputs a high-level image detection signal Y1.

[0119] For example, the seventh control transistor Q7, the fifth control transistor Q5, and the ninth control transistor Q9 are all P-MOS transistors, while the eighth control transistor Q8, the sixth control transistor Q6, and the tenth control transistor Q10 are all N-MOS transistors.

[0120] In this embodiment, the truth table of the detection module 70 is shown in Table 2.

[0121]

[0122] In some other embodiments, such as Figure 12 As shown, the detection module 70 includes four AND gates, namely the first AND gate 301, the second AND gate 302, the third AND gate 303 and the fourth AND gate 304.

[0123] The first input terminal of the first AND gate 301 receives the first data voltage Vt1, and the second input terminal of the first AND gate 301 receives the second data voltage Vt2. The output terminal of the first AND gate 301 is connected to the first input terminal of the second AND gate 302 and the first input terminal of the third AND gate 303. The second input terminal of the second AND gate 302 receives the first data voltage Vt1, and the output terminal of the second AND gate 302 is connected to the first input terminal of the fourth AND gate 304. The second input terminal of the third AND gate 303 receives the second data voltage Vt2, and the output terminal of the third AND gate 303 is connected to the second input terminal of the fourth AND gate 304. The output terminal of the fourth AND gate 304 is connected to the splicing display screen 200.

[0124] Please see Figures 5 to 16 , Figure 13 This is a schematic diagram of the structure of the fifth embodiment of the display control module and display partition provided in this application in the first packaged state. Figure 14 This is a schematic diagram of the display control module and display partition fifth embodiment provided in this application in the second packaged state. Figure 15 This is a schematic diagram of the structure of the display control module and display partition according to the sixth embodiment of this application. Figure 16 This is a structural schematic diagram of the seventh embodiment of the display control module and display partition provided in this application.

[0125] In other embodiments, the display control module 30 includes two control switches connected in parallel, and the control terminals of both control switches receive control signals S.

[0126] The display control module 30 is configured in a one-to-one correspondence with the display partition 60; the display control module 30 is connected between the corresponding display partition 60 and the source drive circuit, or the display control module 30 is connected between the corresponding display partition 60 and the gate drive circuit. GD represents the source drive circuit, and GOA represents the gate drive circuit.

[0127] The display partition 60 where the splicing location is not located is the first display partition 61. In the display control module 30 corresponding to the first display partition 61, the two control switches have opposite conductivity types.

[0128] The display partition 60 where the splicing point is located is the second display partition 62. In the display control module 30 corresponding to the second display partition 62, the two control switches have the same conductivity type.

[0129] When the splicing area is in the first encapsulation state, each display partition 60 displays normally; when the splicing area is in the second encapsulation state, the first display partition 61 displays normally, and the second display partition 62 displays a black screen.

[0130] The two control switches in the display control module 30 are the first control switch T3 and the second control switch T4.

[0131] For the display partition 60, i.e. the first display partition 61, where the splicing point is not present, the two control switches adopt a structure with opposite conductivity types, such as one using an N-type MOSFET and the other using a P-type MOSFET, so that the first display partition 61 can be displayed normally regardless of whether the control signal S is high or low.

[0132] For the display partition 60, i.e., the second display partition 62, where the splicing point is located, the two control switches adopt the same conductivity type structure, such as both using N-type MOSFETs or both using P-type MOSFETs. This allows the second display partition 62 to display normally in the first package state. In the second package state, the second display partition 62 completely cuts off signal transmission, realizing a black screen display, avoiding current passing through the damaged area, thereby reducing heat generation. This ensures that when the splicing point is abnormally packaged, only the second display partition 62 displays a black screen, making it easier for users to identify local damage in a timely manner, reducing maintenance time, and further improving emergency use time.

[0133] The display device 1 further includes a gate driving circuit and a source driving circuit. The gate driving circuit supplies driving signals to the display area through gate lines; the source driving circuit supplies driving signals to the display area through data lines. Gate represents a scan line, and Data represents a data line.

[0134] In some specific embodiments, such as Figure 13 and Figure 14 As shown, the display control module 30 is connected between the corresponding display partition 60 and the source drive circuit, and the first display partition 61 and the second display partition 62 are arranged along the extension direction of the scan line. Figure 15 and Figure 16 As shown, in some other embodiments, the display control module 30 is connected between the corresponding display partition 60 and the gate driving circuit. For example, the first display partition 61 and the second display partition 62 are arranged in an array.

[0135] It should be understood that the first display partition 61 and the second display partition 62 are pre-defined.

[0136] Please see Figures 17 to 19 , Figure 17 This is a schematic diagram of the fourth embodiment of the detection and protection circuit provided in this application. Figure 18 This is a schematic diagram of the fifth embodiment of the detection and protection circuit provided in this application. Figure 19 This is a schematic diagram of an embodiment of the display control module provided in this application.

[0137] In some embodiments, such as Figure 17 As shown, the detection and protection circuit 100 includes a main power supply V1 and a display control module 30. A voltage divider resistor R1 is connected between the main power supply V1 and voltage divider node a. One end of the sensitive resistor R2 is connected to voltage divider node a, and the other end of the sensitive resistor R2 is grounded. The power supply path 20 is connected between voltage divider node a and the video wall display 200. The display control module 30 receives a control signal S to control the display mode of the video wall display 200. The display control module 30 is connected between voltage divider node a and the video wall display 200 to multiplex the detection signal into the control signal S.

[0138] The main power supply V1 provides the base voltage. A voltage divider network is formed by connecting the voltage divider resistor R1 and the sensitive resistor R2 in series. The sensitive resistor R2 is directly set at the splicing point of the video wall display 200 to sense environmental changes. When the splicing point is intact, the resistance of the sensitive resistor R2 is relatively large (e.g., the resistance of a humidity-sensitive resistor reaches the megohm level in a dry environment), and the voltage at voltage divider node a is relatively high. At this time, the display control module 30 directly reuses this high voltage detection signal as the control signal S to drive the video wall display 200 to work in a high refresh rate mode. At the same time, the voltage at voltage divider node a is directly used as the driving voltage of the video wall display 200. When the splicing point is damaged, the resistance of the sensitive resistor R2 decreases rapidly, and the voltage at voltage divider node a decreases. At this time, the display control module 30 directly reuses this low voltage detection signal as the control signal S to drive the video wall display 200 to work in a low refresh rate mode. At the same time, the voltage at voltage divider node a is directly used as the driving voltage of the video wall display 200.

[0139] By directly reusing the detection signal of voltage divider node a through the display control module 30, the system response speed is further improved, which is conducive to realizing the real-time synchronization of packaging state changes and display mode switching.

[0140] In other embodiments, such as Figure 18As shown, the detection and protection circuit 100 includes a main power supply V1 and a display control module 30. A voltage divider resistor R1 is connected between the main power supply V1 and the voltage divider node a. One end of the sensitive resistor R2 is connected to the voltage divider node a, and the other end of the sensitive resistor R2 is grounded. The power supply path 20 is connected between the voltage divider node a and the splicing display screen 200. The display control module 30 is used to receive control signals S to control the display mode of the splicing display screen 200. The detection and protection circuit 100 also includes a third operational amplifier U3 and a fourth operational amplifier U4. The non-inverting input terminal + of the third operational amplifier U3 is connected to the main power supply V1, the inverting input terminal - of the third operational amplifier U3 is connected to the voltage divider node a, and the output terminal of the third operational amplifier U3 is connected to the inverting input terminal - of the fourth operational amplifier U4, and is used to output the difference between the output voltage of the main power supply V1 and the voltage of the voltage divider node a to the fourth operational amplifier U4. The non-inverting input terminal + of the fourth operational amplifier U4 receives the threshold voltage, and the output terminal of the fourth operational amplifier U4 is connected to the display control module 30 to use the output signal of the fourth operational amplifier U4 as the control signal S.

[0141] The main power supply V1 provides the base voltage. A voltage divider network is formed by connecting the voltage divider resistor R1 and the sensitive resistor R2 in series. The sensitive resistor R2 is directly placed at the splicing point of the video wall display 200 to sense environmental changes. When the splicing point is properly encapsulated, the resistance of the sensitive resistor R2 is relatively large (e.g., the resistance of a humidity-sensitive resistor reaches the megaohm level in a dry environment), resulting in a higher voltage at voltage divider node a. The third operational amplifier U3 calculates the difference between the output voltage of the main power supply V1 and the voltage at voltage divider node a (i.e., Δ1 = V1 - Va; where Va is the voltage at voltage divider node a). The difference is output through the third operational amplifier U3 to the inverting input of the fourth operational amplifier U4, and compared with the threshold voltage V0 (i.e., the normal allowable voltage difference). If the difference (i.e., Δ2=V0-Δ1) is small, the splicing area is well packaged or only slightly damaged, and the fourth operational amplifier U4 outputs a low level, maintaining the normal display mode. If the difference (i.e., Δ2=V0-Δ1) is large, the splicing area is severely damaged, and the fourth operational amplifier U4 outputs a high level, requiring switching to the low-power display mode.

[0142] A two-stage operational amplifier circuit is adopted to improve anti-interference capability through difference detection and threshold voltage comparison, avoid false triggering caused by environmental fluctuations, and thus accurately trigger low-power mode when there is an abnormality in the splicing.

[0143] In some embodiments, such as Figure 19 As shown, the display control module 30 includes a selection module, a first switching unit 31, and a second switching unit 32.

[0144] The selection module includes a NOT gate 305, a first AND gate 301, a second AND gate 302, and an OR gate 306. The input of NOT gate 305 receives the control signal S, and its output is connected to the first input of the first AND gate 301. The second input of the first AND gate 301 is connected to the first switching unit 31, and its output is connected to the first input of the OR gate 306. The first input of the second AND gate 302 receives the control signal S, its second input is connected to the second switching unit 32, its output is connected to the second input of the OR gate 306, and its output is connected to the splicing display screen 200.

[0145] The logical function expression for selecting the module is: Y = ¬SP1 + SP2.

[0146] Where S represents the control signal S, P1 represents the normal display mode, and P2 represents the low power display mode.

[0147] In this embodiment, the truth table of the display control module 30 is shown in Table 3.

[0148]

[0149] That is, when the output of the fourth operational amplifier is high (i.e., 1), the output Y2 is P2 to select the low-power display mode. When the output of the fourth operational amplifier is low (i.e., 0), the output Y2 is P1 to select the normal display mode.

[0150] The display control modules 30 with different structures described above can be applied to the detection and protection circuits 100 in the above embodiments.

[0151] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0152] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A detection and protection circuit, applied to a modular chip-based splicing display screen, characterized in that, include: The detection circuit includes a detection unit and outputs a detection signal based on the resistance change of the detection unit; The detection unit is located at the splicing point of the splicing display screen to sense the encapsulation status at the splicing point; The power supply path receives the detection signal and provides different driving voltages to the splicing display screen according to the detection signal.

2. The detection and protection circuit according to claim 1, characterized in that, The detection unit is a sensitive resistor; the detection circuit includes a voltage divider resistor connected in series with the sensitive resistor, the sensitive resistor being a humidity-sensitive resistor or a force-sensitive resistor; the connection node between the voltage divider resistor and the sensitive resistor is a voltage divider node, and the detection signal is output through the voltage divider node.

3. The detection and protection circuit according to claim 2, characterized in that, The detection and protection circuit also includes a main power supply and a backup power supply; the power supply path includes a first power supply path and a second power supply path. In response to the splicing point being in a first encapsulation state, the main power supply provides a first driving voltage to the splicing display screen through the first power supply path; In response to the splicing point being in a second encapsulation state, the backup power supply provides a second driving voltage to the splicing display screen through the second power supply path; The first driving voltage is greater than the second driving voltage.

4. The detection and protection circuit according to claim 3, characterized in that, The first power supply path includes a first transistor, a first terminal of the first transistor is connected to the main power supply, a second terminal of the first transistor is connected to the splicing display screen, and a control terminal of the first transistor is connected to the voltage divider node to receive the detection signal and control the on / off state of the first power supply path. The second power supply path includes a second transistor, the first end of which is connected to the backup power supply, the second end of which is connected to the splicing display screen, and the control end of which is connected to the voltage divider node to receive the detection signal and control the on / off state of the second power supply path. The first transistor has the opposite conductivity type to the second transistor.

5. The detection and protection circuit according to claim 4, characterized in that, The voltage divider resistor is connected between the main power supply and the voltage divider node; one end of the sensitive resistor is connected to the voltage divider node, and the other end of the sensitive resistor is grounded. The first power supply path further includes a first operational amplifier, the non-inverting input terminal of the first operational amplifier is connected to the main power supply, the inverting input terminal of the first operational amplifier is connected to the backup power supply, and the output terminal of the first operational amplifier is connected to the first terminal of the first transistor. The second power supply path also includes a second operational amplifier, the non-inverting input of which is connected to the backup power supply, the inverting input of which is connected to the main power supply, and the output of which is connected to the first terminal of the second transistor. In response to the splicing point being in the first encapsulation state and the main power supply being in a normal state, power is supplied to the splicing display screen through the first power supply path; In response to the splicing point being in the second encapsulation state, the main power supply is in an undervoltage state, and the actual voltage output by the main power supply is less than the power supply voltage of the backup power supply, and power is supplied to the splicing display screen through the second power supply path.

6. The detection and protection circuit according to claim 2 or 3, characterized in that, The detection and protection circuit further includes a display control module for receiving control signals to control the display mode of the splicing display screen; wherein the detection signal is multiplexed as the control signal, or the control signal is output through the power supply path; The display control module includes a first switching unit, a second switching unit, a third transistor, and a fourth transistor; The first terminal of the third transistor is connected to the first switching unit, and the second terminal of the third transistor is connected to the splicing display screen; The first terminal of the fourth transistor is connected to the second switching unit, the second terminal of the fourth transistor is connected to the splicing display screen, and the control terminal of the fourth transistor is connected to the control terminal of the third transistor and is used to receive the control signal; the third transistor and the fourth transistor have opposite conductivity types. In response to the splicing point being in a first encapsulation state, the first switching unit controls the display area of ​​the splicing display screen to operate in a first display mode; In response to the splicing area being in the second encapsulation state, the second switching unit controls the display area of ​​the splicing display screen to operate in the second display mode.

7. The detection and protection circuit according to claim 2 or 3, characterized in that, The detection and protection circuit further includes a display control module for receiving control signals to control the display mode of the splicing display screen; wherein the detection signal is multiplexed as the control signal, or the control signal is output through the power supply path; The display control module is connected between the driving circuit and multiple display zones of the splicing display screen, and is configured to establish or disconnect the transmission path of the driving signal between the driving circuit and the display zone; wherein the driving circuit is a gate driving circuit or a source driving circuit.

8. The detection and protection circuit according to claim 7, characterized in that, The display control module includes a first switch and a second switch, and the driving circuit includes a first gate driving circuit and a second gate driving circuit. The first terminal of the first switch is connected to the first gate driving circuit and to the display partition corresponding to the first gate driving circuit; The first terminal of the second switch is connected to the second gate driving circuit; the second terminal of the second switch is connected to the display partition corresponding to the second gate driving circuit, and is also connected to the second terminal of the first switch; the control terminal of the second switch is connected to the control terminal of the first switch and is used to receive the control signal. The first switch and the second switch have opposite conductivity types; In response to the splicing point being in a first encapsulation state, the first gate driving circuit controls the plurality of display zones to refresh the display at a first refresh rate; In response to the splicing point being in a second encapsulation state, the second gate driving circuit controls the corresponding display partition to display at a second refresh rate different from the first refresh rate.

9. The detection and protection circuit according to claim 7, characterized in that, The display control module is configured in a one-to-one correspondence with the display partition; the driving circuit includes a first gate driving circuit and a second gate driving circuit. The display control module includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; The first terminal of the first control transistor is connected to the first gate driving circuit, the second terminal of the first control transistor is connected to the corresponding display partition, and the control terminal of the first control transistor receives the control signal. The control terminal of the second control transistor receives the control signal; The first terminal of the third control transistor is connected to the first gate driving circuit, the second terminal of the third control transistor is connected to the corresponding display partition, and the control terminal of the third control transistor is used to receive the screen detection signal of the corresponding display partition. The first terminal of the fourth control transistor is connected to the second gate driving circuit, and the second terminal of the fourth control transistor is connected to the corresponding display partition; Wherein, the control terminal of the third control transistor receives the screen detection signal through the second control transistor; or the second terminal of the third control transistor is connected to the corresponding display partition through the second control transistor; In response to the splicing point being in a first encapsulation state, the first gate driving circuit controls the corresponding display partition to refresh the display at a first refresh rate; In response to the splicing point being in the second encapsulation state and the display partition displaying dynamic images, the first gate driving circuit controls the corresponding display partition to refresh the display at a first refresh rate; In response to the splicing point being in a second encapsulation state and the display partition displaying a static or repeating image, the second gate driving circuit controls the corresponding display partition to refresh the display at a second refresh rate different from the first refresh rate.

10. The detection and protection circuit according to claim 7, characterized in that, The display control module includes two control switches connected in parallel, and the control terminals of both control switches receive the control signal. The display control module is configured in a one-to-one correspondence with the display partition; the display control module is connected between the corresponding display partition and the source driving circuit, or the display control module is connected between the corresponding display partition and the gate driving circuit. The display partition where the splicing point is not located is the first display partition, and in the display control module corresponding to the first display partition, the two control switches have opposite conductivity types; The display partition where the splicing point is located is the second display partition, and in the display control module corresponding to the second display partition, the two control switches have the same conductivity type; In response to the splicing point being in the first encapsulation state, each of the display partitions is displayed normally; In response to the splicing point being in the second encapsulation state, the first display partition displays normally, while the second display partition displays a black screen.

11. The detection and protection circuit according to claim 2, characterized in that, The detection and protection circuit includes a main power supply and a display control module. The voltage divider resistor is connected between the main power supply and the voltage divider node. One end of the sensitive resistor is connected to the voltage divider node, and the other end is grounded. The power supply path is connected between the voltage divider node and the splicing display screen. The display control module is used to receive control signals to control the display mode of the splicing display screen. The display control module is connected between the voltage divider node and the splicing display screen to multiplex the detection signal into the control signal; or, The detection and protection circuit further includes a third operational amplifier and a fourth operational amplifier. The non-inverting input of the third operational amplifier is connected to the main power supply, the inverting input of the third operational amplifier is connected to the voltage divider node, and the output of the third operational amplifier is connected to the inverting input of the fourth operational amplifier, and is used to output the difference between the output voltage of the main power supply and the voltage of the voltage divider node to the fourth operational amplifier. The non-inverting input of the fourth operational amplifier receives a threshold voltage, and the output of the fourth operational amplifier is connected to the display control module so that the output signal of the fourth operational amplifier is used as the control signal.

12. A display device, characterized in that, It includes a video wall display and a detection and protection circuit as described in any one of claims 1 to 11.

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