Display device and driving method thereof

Abstract

A display device includes a gate driving circuit including a Q node controller configured to charge or discharge a Q node to receive an input of a high potential voltage and output a scan signal, an inverter configured to change a voltage level of a Qb node according to a voltage level of the Q node, and a Q node stabilizing circuit configured to discharge the Q node to a low potential level in response to a voltage of the Qb node, a sensing circuit configured to sense a threshold voltage of at least one transistor included in the Q node stabilizing circuit, and a compensation circuit configured to generate a compensation value for compensating for the high potential voltage applied to the gate driving circuit according to a result of sensing the threshold voltage.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0173646, filed on November 28, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to a display device and a driving method thereof. Background Technology

[0003] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. Consequently, the use of display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0004] Each display device may include a display panel having subpixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates drive power. The driver includes a gate drive circuit that supplies gate signals (e.g., scan signals and light emission control signals) to the display panel and a data drive circuit that supplies data signals to the display panel.

[0005] The gate drive circuit of a display device may include multiple thin-film transistors (TFTs). Since the electrical characteristics of the TFTs change with driving time and driving stability deteriorates, it is necessary to compensate for the high-potential gate voltage GVDD based on the changes in the electrical characteristics of the TFTs. Therefore, a technique for accurately sensing the electrical characteristics of the TFTs included in the gate drive circuit is required. Summary of the Invention

[0006] Therefore, this disclosure relates to a display device and its driving method that substantially eliminate one or more problems caused by the limitations and disadvantages of related technologies.

[0007] The purpose of embodiments of this disclosure is to provide a display device and a driving method thereof, which can improve driving stability by accurately sensing and compensating for the electrical characteristics of the TFTs included in the gate driving circuit of the display device.

[0008] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon reading the following, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0009] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as embodied and generally described herein, a display device includes: a gate driving circuit comprising a Q-node controller, an inverter, and a Q-node stabilizing circuit, wherein the Q-node controller is configured to charge or discharge a Q-node to receive a high-potential voltage input and output a scan signal, the inverter is configured to change the voltage level of a Qb-node according to the voltage level of the Q-node, and the Q-node stabilizing circuit is configured to discharge the Q-node to a low-potential level in response to the voltage of the Qb-node; a sensing circuit configured to sense a threshold voltage of at least one transistor included in the Q-node stabilizing circuit; and a compensation circuit configured to generate a compensation value for compensating the high-potential voltage applied to the gate driving circuit based on the result of sensing the threshold voltage.

[0010] The Q-node stabilization circuit may include a transistor controlled by a voltage input to the gate of the Qb node to apply a low potential voltage input to the first electrode of the transistor to the Q-node connected to the second electrode of the transistor.

[0011] The sensing circuit may include: a first switch configured to connect a first electrode of a transistor to one of an initialization line transmitting an initialization voltage, a low-potential voltage line transmitting a low-potential voltage, and a sensing line acquiring a sensed value, or to electrically float the first electrode; and a second switch configured to electrically separate a Qb node into two Qb nodes.

[0012] The Qb node can be electrically separated into a first Qb node that remains in a floating state and a second Qb node whose voltage level is determined based on the inverter's output.

[0013] The sensing circuit can control the second switch in a sensing mode for sensing the threshold voltage of the transistor so that the voltage of the Qb node is floating at a high level, and then control the first switch so that the first electrode of the transistor is electrically floating when the voltage of the Q node connected to the second electrode of the transistor is high.

[0014] When a reference time has elapsed after the first electrode of the transistor has been electrically floated, the sensing circuit can connect the first electrode of the transistor to the sensing line.

[0015] The transistor can perform source follower operation based on the voltage of the Q node in sensing mode.

[0016] After the source follower operation of the transistor based on the Q-node voltage is completed, the sensing circuit can connect the first electrode of the transistor to the sensing line.

[0017] The Q-node controller can receive the gate start pulse or the carry signal from the previous stage as input, and charge the Q-node at a high level.

[0018] In another aspect of this disclosure, a driving method for a display device includes a gate driving circuit comprising: a Q-node controller configured to charge or discharge a Q-node to receive a high-potential voltage input and output a scan signal; an inverter configured to change the voltage level of a Qb node according to the voltage level of the Q-node; and a Q-node stabilizing circuit configured to discharge the Q-node to a low-potential level in response to the voltage of the Qb node, the method comprising: when the voltage of the Qb node to which the gate of the Q-node stabilizing transistor is connected is high... In the flat state, the Qb node is electrically separated into a first Qb node that remains in a floating state and a second Qb node whose voltage level is determined according to the inverter output; when the voltage of the Q node to which the second electrode of the Q node stabilizing transistor is connected switches to a high level state, the first electrode of the Q node stabilizing transistor is made to float; after a preset time, the voltage value of the first electrode of the Q node stabilizing transistor is sensed by connecting the first electrode of the Q node stabilizing transistor to a sensing line; the threshold voltage of the Q node stabilizing transistor is calculated based on the sensed voltage value; and a compensation value for compensating for high potential voltage is generated based on the threshold voltage.

[0019] The step of floating the first electrode of the Q-node stabilizing transistor may include performing a source follower operation based on the voltage of the Q-node through the Q-node stabilizing transistor.

[0020] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0021] This disclosure includes accompanying drawings to provide a further understanding of the disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate (multiple) embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is a system configuration diagram of a display device according to an embodiment of the present disclosure; Figure 2 This is an example system implementation diagram of a display device according to embodiments of the present disclosure; Figure 3 This is a diagram illustrating the configuration associated with the gate drive circuitry of a display device according to embodiments of the present disclosure; Figure 4 This is a schematic circuit configuration for illustrating the gate in-panel (GIP) and sensing circuitry of a display device according to embodiments of the present disclosure; Figures 5 to 7 This is a diagram illustrating a method for performing a sensing mode of sensing the threshold voltage of the Q-node stabilizing transistor T3 in a display device according to an embodiment of the present disclosure; and Figure 8 and Figure 9 It is used to describe Figure 4 The voltage curves show the main drive signals of the GIP and sensing circuits, as well as the voltage changes of each node. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of the embodiments and accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, and can be implemented in various different forms. These embodiments are provided merely to complete the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are illustrative, and therefore this disclosure is not limited to what is shown. Throughout the specification, the same reference numerals denote the same parts. When terms such as "comprising," "having," and "consisting of" are used in this disclosure, other parts may be added unless "only" is used. When a part is referred to in the singular, this includes cases where the parts are plural, unless specifically and explicitly described.

[0024] When interpreting a component, even without a separate explicit description, the component is interpreted as including a tolerance range.

[0025] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", "side", etc., one or more other parts may be located between the two parts unless "immediately following" or "directly" is used.

[0026] Although the terms first, second, etc., can be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can be a second component within the technical concept of this disclosure.

[0027] The display device according to this disclosure can be implemented as a television, video player, personal computer (PC), home theater, automotive electrical equipment, smartphone, etc. However, this disclosure is not limited thereto. The display device according to this disclosure can be implemented as a display device (light-emitting display device), quantum dot display device, liquid crystal display device, etc. However, for ease of description, a display device based on direct light emission from inorganic light-emitting diodes or organic light-emitting diodes will be used as an example below.

[0028] Throughout this specification, the same reference numerals denote substantially the same components. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In the following description, detailed descriptions will be omitted where it is determined that such detailed descriptions of known functions or configurations related to this disclosure might unnecessarily obscure the essential points of this disclosure.

[0029] Figure 1 This is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include an image supply circuit 150, a controller 140, a gate driving circuit 130, a data driving circuit 120, a display panel PNL, etc.

[0031] The image supply circuit 150 can supply image data signals from an external source or image data signals stored in internal memory, along with various drive signals, to the controller 140. The image supply circuit 150 can be any one of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0032] The controller 140 can output a gate control signal GCS for controlling the gate drive circuit 130 and a data control signal DCS for controlling the data drive circuit 120. The controller 140 can supply a data signal Data from the image supply circuit 150 together with the data control signal DCS to the data drive circuit 120. The controller 140 can be formed as an IC integrated circuit and mounted on a printed circuit board. However, this disclosure is not limited thereto.

[0033] The data driving circuit 120 can convert the data signal Data into an analog data voltage and output the analog data voltage in response to the data control signal DCS supplied from the controller 140. The data driving circuit 120 can supply data voltage to the sub-pixels SP included in the display panel PNL via data lines DL1 to DLn. The data driving circuit 120 can be formed as multiple source driver integrated circuits (SDICs). The source driver integrated circuits (SDICs) can be connected to the display panel PNL via tape-automated bonding (TAB), connected to the bonding pads of the display panel PNL via chip-on-glass (COG) or chip-on-panel (COP) methods, or implemented and connected to the display panel PNL using a chip-on-film (COF) method. When the data driving circuit 120 includes one or more source driver integrated circuits (SDICs) and is implemented in a COF manner, each source driver integrated circuit (SDIC) can be mounted on the source film SF connected to the non-display area NDA of the display panel PNL. Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter (DAC), output buffer, etc. Depending on the situation, each source driver integrated circuit (SDIC) may further include an analog-to-digital converter (ADC).

[0034] The gate driving circuit 130 can supply at least one scan signal to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The gate driving circuit 130 can be formed as an IC, or it can be formed directly on the display panel 150 in a GIP manner. The gate driving circuit 130 formed in a GIP manner can be arranged on one edge of the display panel 150, or it can be divided and arranged on both edges of the display panel 150.

[0035] The display panel PNL may include multiple data lines DL and multiple gate lines GL arranged in a matrix, and multiple sub-pixels SP arranged at the intersections of the data lines DL and the gate lines GL. The display panel PNL may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed. In the display area DA, multiple sub-pixels SP for displaying images are arranged. In the non-display area NDA, a gate driving circuit 130, a data driving circuit 120, and a controller 140 may be electrically connected or mounted, and pads for connection to integrated circuits or printed circuits may be arranged.

[0036] Figure 2 yes Figure 1 An example system implementation diagram of the display device.

[0037] Reference Figure 1and Figure 2 The source driver integrated circuit SDIC included in the data driver circuit 120 is implemented using the COF method among various methods (TAB, COG, COF, etc.), and the gate driver circuit 130 is implemented in the GIP form among various methods (TAB, COG, COF, GIP, etc.).

[0038] When the gate drive circuit 130 is implemented in GIP form, the multiple gate drive integrated circuits (GDICs) included in the gate drive circuit 130 can be directly formed in the non-display area NDA of the display panel PNL. In this case, the gate drive integrated circuits (GDICs) can be supplied with various signals (clock signal, gate high signal, gate low signal, etc.) required to generate scan signals through gate drive-related signal lines arranged in the non-display area NDA.

[0039] One or more source driver integrated circuits (SDICs) included in the data driver circuit 120 can be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel PNL. Additionally, lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel PNL can be arranged on the upper side of the source film SF.

[0040] The display device 100 may include: at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices; and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0041] The source film SF, on which the source driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB on the other side. That is, the source film SF, on which the source driver integrated circuit SDIC is mounted, can have one side electrically connected to the display panel PNL and the other side electrically connected to the source printed circuit board SPCB.

[0042] The controller 140 and the power management IC (PMIC) can be mounted on the control printed circuit board (CPCB). The controller 140 performs all control functions related to driving the display panel PNL and controls the operation of the data drive circuit 120 and the gate drive circuit 130. The PMIC can supply various voltages or currents to the data drive circuit 120 and the gate drive circuit 130, or control the various voltages or currents to be supplied. The PMIC can control the voltage or current to be supplied based on control signals applied from a control unit such as the controller 140.

[0043] At least one source printed circuit board (SPCB) and control printed circuit board (CPCB) can be connected by a connecting cable (CBL) formed using a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like. Therefore, power output from the PMIC mounted on the control printed circuit board (CPCB) can be applied to the display panel (PNL) via the connecting cable (CBL), the source printed circuit board (SPCB), and the source film (SF) on which the source driver integrated circuit (SDIC) is mounted.

[0044] Figure 3 This is a diagram illustrating the configuration associated with the gate drive circuitry of a display device according to embodiments of the present disclosure.

[0045] Reference Figure 3 The display device according to an embodiment of the present disclosure includes: a gate driving circuit 130; a high-potential gate voltage (GVDD) supply circuit 400 for supplying GVDD to the gate driving circuit 130; a sensing circuit 300 for sensing the electrical characteristics of the transistors included in the gate driving circuit 130; and a compensation circuit 410 for adjusting the voltage level of GVDD applied to the gate driving circuit 130 based on the sensing result of the sensing circuit 300.

[0046] The gate drive circuit 130 may include GIP logic circuitry and output buffer 138.

[0047] GIP logic circuits can be implemented as shift logic circuits comprising multiple transistors. GIP logic circuits can be driven by supplying DC voltages GVDD (high-level gate voltage) and GVSS (low-level gate voltage). GIP logic circuits can control the charging and discharging of the pull-up output voltage Q node Q and the pull-down output voltage Qb node Qb.

[0048] Output buffer 138 can output an output signal Vout, such as a scan signal (SCAN) or a carry signal, in response to the voltage levels of Q node Q and Qb node. Output buffer 138 may include a pull-up TFT TU whose gate is connected to Q node Q and a pull-down TFT TD whose gate is connected to Qb node Qb. The pull-up TFT TU can be turned on and output the output signal Vout, such as the scan signal (SCAN) or the carry signal, when the Q node voltage is high. The pull-down TFT TD can be turned on and output the low-level output signal Vout when Qb node Qb is high.

[0049] The sensing circuit 300 can sense the threshold voltage Vth of at least one transistor in the gate drive circuit 130 and provide the sensed value to the compensation circuit 410. Since the gate drive circuit 130 includes multiple transistors, the degradation and lifetime of the gate drive circuit 130 can be determined by the transistor with the greatest degradation. Typically, the Qb node Qb of the gate drive circuit 130 remains in a low voltage (negative voltage) state for all but one horizontal time period within a frame. Therefore, relatively large stress can be applied to the transistor controlled by the Qb node voltage, i.e., the transistor whose gate is connected to the Qb node Qb. Therefore, in order to extend the lifetime of the gate drive circuit 130, it is desirable to sense and compensate for the degradation of the transistor controlled by the Qb node voltage. Therefore, the sensing circuit 300 can sense the threshold voltage Vth of the transistor that inputs the Qb node voltage to its gate and provide the sensing result to the compensation circuit 410.

[0050] The compensation circuit 410 can generate a compensation value for the voltage level of GVDD based on the sensing result of the sensing circuit 300. The compensation circuit 410 may include a lookup table in which the voltage level of GVDD is set according to the threshold voltage Vth of the transistor sensed by the sensing circuit 300. The compensation circuit 410 may be built into the controller 140 or may be mounted on the CPCB.

[0051] The GVDD supply circuit 400 sets the GVDD voltage level by reflecting the compensation value output from the compensation circuit 410, and can supply GVDD power reflecting the compensation value to the gate drive circuit 130. The GVDD supply circuit 400 can be built into the PMIC or mounted on the CPCB.

[0052] Figure 4 This is a schematic circuit configuration illustrating the gate input (GIP) and sensing circuit 300 of a display device according to embodiments of the present disclosure. The GIP starts operating according to a gate start pulse (GSP) and can output a carry signal and a scan signal according to a clock signal. The scan signal output from the GIP is sequentially shifted and sequentially supplied through gate lines GL. The GIP includes multiple stages sequentially driven to output scan signals, and when a scan signal is output, the Nth stage can output the Nth carry signal CoutN to subsequent stages. Each stage of the GIP has the same TFT configuration. Figure 4 This is a schematic circuit configuration diagram showing the Nth stage and sensing circuit 300 included in the GIP.

[0053] Reference Figure 4The Nth stage of GIP may include a Q-node charging circuit 131, a Q-node discharging circuit 132, a Q-node stabilizing circuit 133, an inverter 135, an output buffer 138, and a sensing circuit 300.

[0054] Output buffer 138 can output a carry signal CoutN based on the voltage level of clock signal CLK or GVSS, depending on the Q node voltage or Qb node voltage. Output buffer 138 includes a pull-up transistor TU controlled according to the voltage level of Q node Q and a pull-down transistor TD controlled according to the voltage level of Qb node Qb, which is opposite to Q node Q.

[0055] The pull-up transistor TU may have a gate connected to Q node Q, a source connected to the output terminal of the output signal VoutN, and a drain connected to the input terminal of the clock signal CLK. The pull-up transistor TU can be turned on while Q node Q is high, and can output a high-level carry signal CoutN based on the clock signal CLK. The capacitor CB connected between the gate and source (output terminal) of the pull-up transistor TU can reduce the rise time of the carry signal CoutN by bootstrapping and amplifying the high voltage of Q node Q when the pull-up transistor TU is pulled up to output the gate on-state voltage of the clock signal CLK.

[0056] The pull-down transistor TD can have a gate connected to the Qb node Qb, a drain connected to the output terminal of the output signal VoutN, and a source connected to the power supply line of GVSS. The pull-down transistor TD can be turned on during the period when the Qb node voltage is high to transfer GVSS power to the output terminal. Therefore, a low-level carry signal CoutN can be output.

[0057] The Q-node charging circuit 131 can be supplied with a gate start pulse GSP or a carry signal Cout(N-3) from a preceding stage to charge the Q-node Q. The Q-node charging circuit 131 may include one or more Q-charging transistors T1, each having a gate and drain connected to the start terminal and a source connected to the Q-node Q. The Q-charging transistors T1 can be turned on when the gate start pulse GSP or the carry signal Cout(N-3) from the (N-3)th preceding stage is at a high voltage, thereby charging the Q-node Q with a high voltage.

[0058] Q-node discharge circuit 132 can discharge Q-node Q to GVSS (low gate voltage) in response to a reset signal RST applied to the reset terminal or a carry signal Cout(N+3) from a subsequent stage. Q-node discharge circuit 132 may include one or more Q-discharge transistors T2, each having a gate connected to the reset terminal, a source connected to the GVSS power supply line, and a drain connected to Q-node Q. Q-discharge transistor T2 can be turned on when the reset signal RST or the carry signal Cout(N+3) from a subsequent stage is high, to discharge Q-node Q to the low GVSS voltage.

[0059] The Q-node stabilization circuit 133 can discharge the Q-node voltage to the GVSS in response to a high-level Qb node voltage. The Q-node stabilization circuit 133 may include one or more Q-node stabilizing transistors T3, each having a gate connected to the Qb node Qb, a first electrode connected to the GVSS supply line, and a second electrode connected to the Q-node Q. Here, the Qb node Qb has a structure where a continuously low-level voltage is applied, thus relatively large stress can be applied to the Q-node stabilizing transistor T3. That is, since the Q-node stabilizing transistor T3 is the device among the transistors included in the GIP that is susceptible to fluctuations in the threshold voltage Vth, the stress on the GIP can be effectively reduced by adjusting the GVDD voltage based on the threshold voltage Vth of the Q-node stabilizing transistor T3.

[0060] Inverter 135 can change the Qb node voltage level based on the Q node voltage level. When the Q node voltage is high, inverter 135 can change the Qb node voltage to a low level. When the Q node voltage is low, inverter 135 can change the Qb node voltage to a high level.

[0061] The sensing circuit 300 can sense the threshold voltage Vth of the Q-node stabilizing transistor T3 and provide the sensed value to the compensation circuit 410. The sensing circuit 300 may include a first switch SW1 that operates by receiving an input of a first switching signal CSW1 and a second switch SW2 that operates by receiving an input of a second switching signal CSW2. The first switching signal CSW1 and the second switching signal CSW2 can be output from the compensation circuit 410. However, this disclosure is not limited thereto, and the switching signals can be output from a structure that controls the sensing mode for sensing the threshold voltage Vth of the Q-node stabilizing transistor T3.

[0062] One end of the first switch SW1 can be connected to the source node s connected to the first electrode of the Q-node stabilizing transistor T3, and the other end can be connected to any one of the GVSS line GVSSL, the initialization line INITIAL, and the sensing line (analog-to-digital converter ADC), or not connected to any of these lines. The first switch SW1 can be turned on by the first switch signal CSW1 to connect the source node s of the Q-node stabilizing transistor T3 to any one of the GVSS line GVSSL, the initialization line INITIAL, and the sensing line ADC, or the first switch SW1 can be turned off to float the source node s of the Q-node stabilizing transistor T3.

[0063] When the first switch SW1 is connected to the GVSS line GVSSL, GVSS is applied to the source node s of the Q-node stabilizing transistor T3. When GIP is operating in normal mode, the first switch SW1 can remain connected to the GVSS line GVSSL.

[0064] When the first switch SW1 is connected to the initialization line INITIAL, an initialization voltage is applied to the source node s of the Q-node stabilizing transistor T3. The initialization voltage can be applied to initialize the voltage at the source node s when the threshold voltage Vth of the Q-node stabilizing transistor T3 is sensed.

[0065] When the first switch SW1 is connected to the sensing line ADC, the voltage sensed value of the source node s of the Q-node stabilizing transistor T3 can be transmitted to the compensation circuit 410. The compensation circuit 410 can check the sensed value through the ADC. An ADC is a general structure that samples and holds a continuous analog signal and converts the analog signal into a digital signal. The ADC connected to the sensing line ADC can convert the voltage of the source node s of the Q-node stabilizing transistor T3 into a digital sensed value. Such an ADC can be included in the sensing circuit 300 or the compensation circuit 410 to generate the sensed value in the form of a digital signal.

[0066] When the first switch SW1 is open and not connected to any line, the source node s of the Q-node stabilizing transistor T3 can be electrically floated.

[0067] The second switch SW2 can be controlled by the second switch signal CSW2 to electrically separate the Qb node Qb into a first Qb node Qb1 and a second Qb node Qb2, or to connect the nodes. The first Qb node Qb1 can be the node to which the gate of the Q-node stabilizing transistor T3 is connected. The second Qb node Qb2 can be the node to which the output of the inverter 135 and the gate of the pull-down transistor TD are connected.

[0068] When the second switch SW2 is turned on, the first Qb node Qb1 and the second Qb node Qb2 are electrically interconnected to operate as a single Qb node Qb. The Qb node Qb can have a voltage level opposite to that of the Q node Q due to a signal applied from the inverter 135. When the second switch SW2 is turned off, the Qb nodes can be electrically separated into the first Qb node Qb1 and the second Qb node Qb2. When the first Qb node Qb1 and the second Qb node Qb2 are electrically separated from each other, the first Qb node Qb1 floats at the voltage level prior to separation, and the voltage level of the second Qb node Qb2 can be determined based on a signal applied from the inverter 135. For example, when the second switch SW2 is on and the voltage of Qb node Qb1+Qb2 is high, when the second switch SW2 is turned off, the first Qb node Qb1 floats at the high voltage level. The second Qb node Qb2 can be switched to a low voltage state by a signal applied from the inverter 135. In other words, when the Q-node voltage switches to a high level with the second switch SW2 open, the voltage of the second Qb node connected to the inverter 135 switches to a low level. However, the first Qb node voltage can remain at a high level.

[0069] The sensing circuit 300 with this structure can electrically disconnect the Qb node Qb, which is charged with a high-level voltage, apply a high-level signal to the gate of the Q-node stabilizing transistor T3, and float the source node s connected to the first electrode of the Q-node stabilizing transistor T3. Therefore, source follower drive can be performed based on the high-level Q-node voltage applied to the drain node d connected to the second electrode of the Q-node stabilizing transistor T3, thereby sensing the threshold voltage Vth.

[0070] Figures 5 to 7 This is a diagram illustrating a method for sensing the threshold voltage Vth of the Q-node stabilizing transistor T3 in a display device according to an embodiment of the present disclosure.

[0071] The sensing mode used to sense the threshold voltage Vth of the Q-node stabilizing transistor T3 may include a first time period P1, a second time period P2, and a third time period P3. Figures 5 to 7 The circuit operation of GIP and sensing circuit 300 is shown in the first time period P1 to the third time period P3.

[0072] Figure 5 The circuit operation of GIP and sensing circuit 300 during the first time period P1 is illustrated. The first time period P1 of the sensing mode is the Qb node voltage charging period, and the operation of the first time period P1 can be performed when the Qb node voltage is at a high level. For example, when GIP is in standby mode before starting operation for outputting the scan signal, the Q node voltage can be at a low level and the Qb node voltage can be at a high level.

[0073] In the first period P1 of the sensing mode, the first switch SW1 is connected to the GVSS line GVSSL and the second switch SW2 is turned on.

[0074] During the first time period P1, the first switch SW1 can connect the source node s of the Q-node stabilizing transistor T3 to the GVSS line GVSSL according to the first switch signal CSW1. When the first switch SW1 is connected to the GVSS line GVSSL, GVSS is applied to the source node s of the Q-node stabilizing transistor T3.

[0075] The second switch SW2 can be turned on according to the second switch signal CSW2 to electrically connect the first Qb node Qb1 and the second Qb node Qb2. Since the voltage of the Qb node is at a high level, both the first Qb node Qb1 and the second Qb node Qb2 can be charged at a high level.

[0076] Figure 6 The circuit operation of GIP and sensing circuit 300 in the second time period P2 is shown.

[0077] When the Q-node voltage switches to a high level, the second phase P2 of the sensing mode can be executed. For example, when the gate start pulse GSP or the carry signal Cout(N-3) from the preceding stage is applied to the Q-node charging circuit 131, the Q-node voltage can be charged at a high level. When the Q-node voltage is charging at a high level, the inverter 135 outputs a low-level voltage signal to the Qb node Qb. Therefore, the Q-node voltage and the Qb node voltage can be switched to opposite voltage level states in combination.

[0078] During the second period P2 of the sensing mode, the Q node voltage is charged at a high level, the first switch SW1 is turned off, and the second switch SW2 is turned on.

[0079] During the second time period P2, the first switch SW1 can be opened according to the first switch signal CSW1 and can be disconnected from any line. When the first switch SW1 is open and not connected to any line, the source node s of the Q-node stabilizing transistor T3 can be electrically floated.

[0080] The second switch SW2 can be opened according to the second switch signal CSW2. When the second switch SW2 is open, the Qb node Qb can be electrically separated into the first Qb node Qb1 and the second Qb node Qb2. The first Qb node Qb1 can float in a high-level state before separation. The second Qb node Qb2 can switch to a low-level state according to the low-level signal applied from the inverter 135.

[0081] According to the circuit operation described above, the voltage of the first Qb node Qb1 is reflected in the gate of the Q-node stabilizing transistor T3, and a high-level signal is applied to the gate of the Q-node stabilizing transistor T3. The voltage of Q node Q is applied to the drain node d of the Q-node stabilizing transistor T3, and the Q-node voltage can have a relatively higher voltage level than the voltage level of the first Qb node. The source node s of the Q-node stabilizing transistor T3 is in a floating state. With the first Qb node voltage at a high level applied to the gate of the Q-node stabilizing transistor T3, a Q-node voltage with a relatively higher potential than the first Qb node voltage is applied to the drain node d. Therefore, the Q-node stabilizing transistor T3 is driven by the source follower through the Q-node voltage at the drain node d, such that the voltage of the source node s fluctuates relative to the voltage fluctuation threshold voltage Vth of the gate. In other words, current flows from the drain node d to the source node s according to the gate-source voltage Vgs, causing the potential of the source node s to gradually increase. Current flow stops when the potential difference between the source node s and the gate becomes the threshold voltage Vth, thus the voltage of the source node s can be determined. Since the first Qb node voltage applied to the gate can be known in advance, the threshold voltage Vth of the Q-node stabilizing transistor T3 can be calculated by sensing the voltage of the source node s and calculating the difference between them.

[0082] Figure 8 The circuit operation of GIP and sensing circuit 300 in the third time period P3 is shown.

[0083] In the third time period P3 of the sensing mode, the first switch SW1 can be connected to the sensing line ADC according to the first switch signal CSW1. When the first switch SW1 is connected to the sensing line ADC, the voltage of the source node s of the Q-node stabilizing transistor T3 can be provided to the compensation circuit 410.

[0084] Figure 8 and Figure 9 It is used to describe Figure 4 The voltage curves of the GIP and the main drive signal of the sensing circuit 300, as well as the voltage changes of each node. Figure 8 This is a graph showing the changes in the Q-node voltage Qnode, the first Qb node voltage Qb1, the source node s voltage of the Q-node stabilizing transistor T3, and the voltages of the second switching signal CSW2 and the gate start pulse GSP. Figure 9 It is shown Figure 8 A magnified portion of the curve graph.

[0085] like Figure 8As shown in the graph of the Q-node voltage Qnode, when the GSP signal is input and the GIP operation starts, the Q-node voltage Qnode is charged at a high level. The scan signal is output sequentially, the Q-node voltage Qnode is discharged, and then the operation can end.

[0086] Before the GSP signal is input, the Qb node voltage remains high in standby mode. Before the GSP signal is input, when the second switch signal CSW2 is applied at a high level, the second switch SW2 is turned on, and the first Qb node Qb1 and the second Qb node Qb2 are electrically connected. Therefore, both the first Qb node voltage and the second Qb node voltage can be charged at a high level.

[0087] Subsequently, when the second switching signal CSW2 is applied at a low level, the second switch SW2 is turned off (SW2_OFF). The second switching signal CSW2 can be applied at a low level at any time when the Qb node voltage is high. When the second switch SW2 is turned off, the Qb node Qb is electrically separated into the first Qb node Qb1 and the second Qb node Qb2. Therefore, the first Qb node voltage can remain at the previously charged high level. The second Qb node voltage can switch to a low level according to the output of the inverter 135. That is, even during the period when the second switch SW2 is off (SW2_OFF), when the Q node voltage switches to a high level, the first Qb node voltage can float and remain at a high level.

[0088] Subsequently, when the GSP signal is input and the Q-node voltage Qnode is switched high, a source follower drive can be executed to sense the threshold voltage Vth of the Q-node stabilizing transistor T3. For example... Figure 9 As shown, during source follower drive, the source node s of the Q-node stabilizing transistor T3 remains in a floating state. Therefore, the voltage of the source node s of the Q-node stabilizing transistor T3 can rise to a voltage level that differs from the voltage of the first Qb node Qb1 input to the gate by a threshold voltage Vth. Therefore, the threshold voltage Vth can be calculated by sensing the voltage of the source node s of the Q-node stabilizing transistor T3.

[0089] As described above, the display device according to embodiments of this disclosure can perform control operations such that during any period when the Qb node voltage is in a high-level state, the Qb node is electrically disconnected and remains in a high-level state, the source of the Q-node stabilizing transistor T3 remains in a floating state, and when the Q node is charged with a high-level voltage, the Q-node stabilizing transistor T3 can be driven by source following based on the Q-node voltage. Therefore, the threshold voltage Vth of the Q-node stabilizing transistor T3, which is susceptible to GIP degradation, can be directly sensed to compensate for GVDD, thereby effectively reducing the stress applied to the GIP and improving drive reliability and drive stability.

[0090] The embodiments of this disclosure provide a display device and a driving method thereof that can improve driving stability.

[0091] Embodiments of this disclosure provide a display device and a driving method thereof, which can improve the driving reliability and driving stability of the gate driving circuit by accurately sensing the electrical characteristics of the TFT included in the gate driving circuit and adjusting the GVDD voltage.

[0092] Embodiments of this disclosure provide a display device and a driving method thereof, which can effectively reduce the stress applied to the gate driving circuit and ensure driving reliability and driving stability by directly and accurately sensing the threshold voltage of the Q-node stabilizing transistor included in the gate driving circuit and compensating for the GVDD voltage.

[0093] The effects of this disclosure are not limited to those shown above, and this disclosure covers a wider range of effects.

[0094] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from the spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A gate driving circuit, comprising: a Q-node controller configured to charge or discharge a Q-node to receive a high-potential voltage input and output a scan signal; an inverter configured to change the voltage level of a Qb-node according to the voltage level of the Q-node; and a Q-node stabilization circuit configured to discharge the Q-node to a low-potential level in response to the voltage of the Qb-node. A sensing circuit configured to sense the threshold voltage of at least one transistor included in the Q-node stabilization circuit; and A compensation circuit is configured to generate a compensation value for compensating the high potential voltage applied to the gate drive circuit based on the result of sensing the threshold voltage.

2. The display device according to claim 1, wherein, The Q-node stabilization circuit includes a transistor controlled by a voltage input to the gate of the Qb node, thereby applying a low potential voltage input to the first electrode of the transistor to the Q-node connected to the second electrode of the transistor.

3. The display device according to claim 2, wherein, The sensing circuit includes: A first switch, configured to connect the first electrode of the transistor to one of an initialization line transmitting an initialization voltage, a low-potential voltage line transmitting the low-potential voltage, and a sensing line acquiring a sensed value, or to electrically float the first electrode; and A second switch is configured to electrically separate the Qb node into two Qb nodes.

4. The display device according to claim 3, wherein, The Qb node is electrically separated into a first Qb node that remains in a floating state and a second Qb node whose voltage level is determined according to the output of the inverter.

5. The display device according to claim 4, wherein, The sensing circuit controls the second switch in a sensing mode for sensing the threshold voltage of the transistor so that the voltage of the Qb node is floating at a high level, and then controls the first switch so that the first electrode of the transistor is electrically floating when the voltage of the Q node connected to the second electrode of the transistor is high.

6. The display device according to claim 5, wherein, When a reference time has elapsed after the first electrode of the transistor has been electrically floated, the sensing circuit connects the first electrode of the transistor to the sensing line.

7. The display device according to claim 5, wherein, The transistor performs a source follower operation based on the voltage of the Q node in the sensing mode.

8. The display device according to claim 7, wherein, After the source follower operation of the transistor based on the voltage of the Q node is completed, the sensing circuit connects the first electrode of the transistor to the sensing line.

9. The display device according to claim 5, wherein, The Q-node controller receives the input of the gate start pulse or the carry signal from the previous stage, and charges the Q-node at the high level.

10. A driving method for a display device, the display device comprising a gate driving circuit, the gate driving circuit comprising: Q-node controller, the Q-node controller being configured to charge or discharge Q-nodes to receive high-potential voltage inputs and output scan signals; An inverter configured to change the voltage level of the Qb node according to the voltage level of the Q node; The method includes the following steps: A Q-node stabilization circuit is configured to discharge the Q-node to a low potential level in response to the voltage of the Qb node. When the voltage of the Qb node connected to the gate of the Q node stabilizing transistor is at a high level, the Qb node is electrically separated into a first Qb node that remains in a floating state and a second Qb node whose voltage level is determined according to the output of the inverter. When the voltage of the Q node connected to the second electrode of the Q node stabilizing transistor switches to a high level, the first electrode of the Q node stabilizing transistor is floated. After a preset time has elapsed, the voltage value of the first electrode of the Q-node stabilizing transistor is sensed by connecting the first electrode of the Q-node stabilizing transistor to a sensing line. The threshold voltage of the Q-node stabilizing transistor is calculated based on the sensed voltage value; and A compensation value is generated based on the threshold voltage to compensate for the high potential voltage.

11. The method according to claim 10, wherein, In the step of floating the first electrode of the Q-node stabilizing transistor when the voltage of the Q-node connected to the second electrode of the Q-node Zener transistor switches to a high level, the source follower operation is performed by the Q-node stabilizing transistor based on the voltage of the Q-node.

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