Display device

Abstract

Embodiments of the present disclosure relate to a display apparatus, and more particularly, to a display apparatus including a display panel in which a plurality of sub-pixels are disposed, a data driver circuit that applies a plurality of data voltages to the plurality of sub-pixels through a plurality of data lines, a driving voltage supply circuit that supplies a driving voltage to the display panel, and a power management circuit that receives a feedback driving voltage from the display panel, receives the driving voltage output from the driving voltage supply circuit, and outputs a gamma reference voltage to the data driver circuit. The power management circuit includes a register that stores data related to a change in the driving voltage. The gamma reference voltage is capable of being varied according to the feedback driving voltage. Accordingly, a gamma reference voltage that is not affected by noise can be generated.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0173567, filed on November 28, 2024, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0002] Embodiments of this disclosure relate to a display device. Background Technology

[0003] With the advancement of the information society, the demand for display devices capable of displaying images has increased in various forms. Recently, various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, have been widely used.

[0004] In conventional display devices, an analog drive voltage is used to adjust the gamma reference voltage. Therefore, noise caused by the analog drive voltage may be reflected in the gamma reference voltage. Due to this noise, unwanted lines unrelated to the image content may appear in portions of the display area. Summary of the Invention

[0005] Embodiments of this disclosure may provide a display device capable of adjusting the drive voltage using a digital drive voltage.

[0006] Embodiments of this disclosure may provide a display device that uses a feedback drive voltage to adjust a gamma reference voltage.

[0007] Embodiments of this disclosure may provide a display device including a lookup table for adjusting a gamma reference voltage.

[0008] Embodiments of this disclosure may provide a display device, comprising: a display panel having a plurality of sub-pixels; a data driver circuit applying a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines; a drive voltage supply circuit supplying a drive voltage to the display panel; and a power management circuit receiving a feedback drive voltage from the display panel, receiving a drive voltage output from the drive voltage supply circuit, and outputting a gamma reference voltage to the data driver circuit. The power management circuit includes a register storing data related to changes in the drive voltage. The gamma reference voltage is capable of changing according to the feedback drive voltage.

[0009] Embodiments of this disclosure may provide a display device, comprising: a display panel having a plurality of sub-pixels; a data driver circuit applying a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines; a drive voltage supply circuit supplying a drive voltage to the display panel; and a power management circuit receiving a plurality of feedback drive voltages from the display panel and receiving the drive voltage output from the drive voltage supply circuit. The power management circuit includes a register storing data that can vary according to the plurality of feedback drive voltages and the drive voltage.

[0010] According to embodiments of the present disclosure, a display device including a power management circuit that adjusts a gamma reference voltage based on a received value of a feedback drive voltage can be provided.

[0011] According to embodiments of the present disclosure, a display device may be provided that includes a register for storing data, the data of which can vary according to a feedback drive voltage and a drive voltage.

[0012] According to embodiments of the present disclosure, a display device may be provided that includes a register for storing data that changes in response to a change in a feedback drive voltage input to a power management circuit.

[0013] According to embodiments of this disclosure, a lightweight display device that does not require a filter for removing noise from analog voltages can be provided. Attached Figure Description

[0014] Figure 1 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a system example diagram of a display device according to an embodiment of the present disclosure.

[0016] Figure 3 This is a circuit diagram illustrating the sub-pixels of a display device according to an embodiment of the present disclosure.

[0017] Figure 4 This is a configuration diagram illustrating an example of using a feedback drive voltage and a drive voltage to adjust a gamma reference voltage in a display device according to an embodiment of the present disclosure.

[0018] Figure 5 This is a diagram illustrating a gamma voltage generation circuit of a display device according to an embodiment of the present disclosure.

[0019] Figure 6 This is a diagram illustrating the layout structure of multiple lines in a display device according to an embodiment of the present disclosure.

[0020] Figure 7 This is a diagram illustrating the power management circuitry of a display device according to an embodiment of the present disclosure.

[0021] Figure 8 This is a diagram illustrating a lookup table for a display device according to an embodiment of the present disclosure.

[0022] Figure 9 This is a diagram illustrating an example of a power management circuit for generating a lookup table according to an embodiment of the present disclosure.

[0023] Figure 10 This is a diagram illustrating an example of a power management circuit that uses a lookup table to output a gamma reference voltage according to an embodiment of the present disclosure.

[0024] Figure 11 This is a diagram illustrating an example of a power management circuit configured to initiate a lookup table modification in response to a change in the feedback drive voltage, according to an embodiment of the present disclosure.

[0025] Figure 12 This is a waveform diagram of the feedback drive voltage and the gamma reference voltage in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0026] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even if these same reference numerals and symbols are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components will be omitted where such detailed descriptions would make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “containing,” “constituting,” “made of,” “composed of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless such terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0027] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0028] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted as follows: not only can the first element be "directly connected or coupled to" the second element, or "directly in contact with or overlapping" a second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlap" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlap" with each other.

[0029] When time-relative terms (such as “after,” “follow,” “next,” “before,” etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operating method, processing method, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “directly” or “immediately” are used together.

[0030] Furthermore, when referring to any size, relative dimensions, etc., it should be assumed that the numerical values ​​or corresponding information of an element or feature (e.g., level, range, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0031] Various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0033] refer to Figure 1 The display device 100 according to an embodiment of the present disclosure may include: a display panel 110, wherein a plurality of gate lines GL are connected to a plurality of data lines DL, and a plurality of sub-pixels SP are arranged in a matrix; a gate driver circuit 120 that drives the plurality of gate lines GL; a data driver circuit 130 that supplies data voltage through the plurality of data lines DL; a controller 140 that controls the gate driver circuit 120 and the data driver circuit 130; and a power management circuit 150.

[0034] The display panel 110 displays images based on scan signals transmitted from the gate driver circuit 120 through multiple gate lines GL and data voltages transmitted from the data driver circuit 130 through multiple data lines DL.

[0035] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates and can operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode. Conversely, in the case of an organic light-emitting display, the display panel 110 can be implemented using a top-emitting type, a bottom-emitting type, or a dual-emitting type.

[0036] The display panel 110 may include a plurality of pixels arranged in a matrix. Each pixel may include sub-pixels SP of different colors, such as white, red, green, and blue sub-pixels. Each sub-pixel SP may be defined by a data line DL and a gate line GL.

[0037] Each sub-pixel SP may include a thin-film transistor (TFT) formed at the intersection of a data line DL and a gate line GL; a light-emitting device, such as an organic light-emitting diode (OLED), that receives the data voltage; and a storage capacitor electrically connected to the light-emitting device to maintain the voltage.

[0038] For example, when the display device 100 has a resolution of 2,160 × 3,840 and includes four types of sub-pixels SP (white W, red R, green G, and blue B), it can provide a total of 15,360 data lines DL, each data line DL connecting to 3,840 columns × 4 sub-pixels. The sub-pixels SP are arranged at the intersection of the 2,160 gate lines GL and the 15,360 data lines DL.

[0039] The gate driver circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to multiple gate lines GL set in the display panel 110 to control the driving timing of the sub-pixels SP.

[0040] In a display device 100 with a resolution of 2,160 × 3,840, when the scan signal is output sequentially from the first to the second,160 gate lines GL, this is referred to as 2,160-phase driving. Alternatively, when the scan signal is output sequentially in units of four gate lines, for example, from the first to the fourth, and then from the fifth to the eighth, this is referred to as 4-phase driving. More generally, when the scan signal is output sequentially in units of N gate lines, this is referred to as N-phase driving.

[0041] The gate driver circuit 120 may include one or more gate driver integrated circuits (GDICs). Depending on the driving method, the gate driver circuit 120 may be located on one or both sides of the display panel 110. Alternatively, the gate driver circuit 120 may be embedded in the bezel area of ​​the display panel 110 and implemented as a gate in-panel (GIP) structure.

[0042] The data driver circuit 130 receives image data DATA from the controller 140 and converts the received image data into an analog data voltage. Then, synchronized with the scan signal applied through the gate line GL, the data voltage is output to the corresponding data line DL, causing each sub-pixel SP connected to the data line DL to emit light at a brightness corresponding to the data voltage.

[0043] Similarly, the data driver circuit 130 may include one or more source-driving integrated circuits (SDICs). Each SDIC may be connected to the bonding pads of the display panel 110 using a tape-on-board (TAB) method or a chip-on-glass (COG) method, or may be directly mounted on the display panel 110.

[0044] In some cases, the SDIC can be integrated into the display panel 110. Alternatively, the SDIC can be implemented using a chip-on-film (COF) method, in which the SDIC is mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0045] The controller 140 supplies various control signals to the gate driver circuit 120 and the data driver circuit 130, and controls their operation. Specifically, the controller 140 controls the gate driver circuit 120 to output a scan signal according to the timing of each frame, while simultaneously transmitting image data DATA received from an external source to the data driver circuit 130.

[0046] The controller 140 receives various timing signals from the external host system 200, including vertical synchronization (Vsync), horizontal synchronization (Hsync), data enable (DE), master clock (MCLK), and image data DATA.

[0047] The host system 200 can be a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, or wearable device.

[0048] Therefore, the controller 140 uses the timing signals received from the host system 200 to generate control signals and supplies the control signals to the gate driver circuit 120 and the data driver circuit 130.

[0049] For example, to control the gate driver circuit 120, the controller 140 outputs various gate control signals, including a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (GOE). The gate start pulse (GSP) controls the timing of the start of operation of one or more gate driver integrated circuits (GDICs) of the gate driver circuit 120. GCLK is the clock signal typically input to the GDIC and controls the shift timing of the scan signal. GOE specifies the timing information for one or more GDICs.

[0050] Similarly, to control the data driver circuit 130, the controller 140 outputs various data control signals, including a source start pulse (SSP), a source sampling clock (SCLK), and a source output enable signal (SOE). The source start pulse (SSP) controls the timing of data sampling by one or more source driver integrated circuits (SDICs) constituting the data driver circuit 130. SCLK is a clock signal that controls the timing of data sampling in the SDIC. SOE controls the output timing of the data driver circuit 130.

[0051] The display device 100 may also include a power management circuit 150 that supplies various voltages or currents to the display panel 110, the gate driver circuit 120, and the data driver circuit 130, or controls the supply of such voltages or currents.

[0052] The power management circuit 150 adjusts the DC input voltage Vin supplied from the host system 200 to generate the power required to drive the display panel 110, the gate driver circuit 120, and the data driver circuit 130.

[0053] Simultaneously, each sub-pixel SP is located at the intersection of the gate line GL and the data line DL, and may include a light-emitting device. For example, in an organic light-emitting display, each sub-pixel SP may include a light-emitting device such as an OLED, and an image is displayed by controlling the current flowing through the light-emitting device based on the data voltage.

[0054] The display device 100 can be implemented as various types of display devices, including liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), or plasma display panels (PDPs).

[0055] Figure 2 This is a system example diagram of a display device 100 according to an embodiment of the present disclosure.

[0056] refer to Figure 2 , Figure 2One scenario is illustrated in which the data driver circuit 130 is implemented using a chip-on-film (COF) method among various packaging methods (e.g., TAB, COG, COF), and the gate driver circuit 120 is implemented as a gate-in-panel (GIP) structure among various packaging methods (e.g., TAB, COG, COF, GIP).

[0057] When the gate driver circuit 120 is implemented in the form of a gate-in-panel (GIP) structure, a plurality of gate driver integrated circuits (GDICs) included in the gate driver circuit 120 can be directly formed in the bezel area of ​​the display panel 110. In this case, the GDICs can receive various signals required to generate scan signals, such as clock signals, gate high signals, and gate low signals, through gate drive-related signal lines arranged in the bezel area.

[0058] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuitry 130 can be mounted on corresponding source films SFs, and one side of each source film SF can be electrically connected to the display panel 110. Furthermore, wiring for electrically connecting the SDICs to the display panel 110 can be arranged on the upper part of each source film SF.

[0059] The display device 100 may include at least one source printed circuit board (SPCB) for establishing circuit-level connections between multiple SDICs and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0060] At least one source printed circuit board (SPCB) can be connected to the side of the source film SF on which the SDIC is mounted. In other words, the source film SF with the SDIC mounted thereon can be electrically connected to the display panel 110 on one side and electrically connected to the SPCB on the other side.

[0061] The control printed circuit board (CPCB) may have a controller 140 and a power management circuit 150 mounted thereon. The controller 140 may control the operation of the data driver circuit 130 and the gate driver circuit 120. The power management circuit 150 may supply drive voltage or current to the display panel 110, the data driver circuit 130 and the gate driver circuit 120, or may control the supplied voltage or current.

[0062] At least one SPCB and CPCB can be electrically connected via at least one connecting member, and the connecting member may include, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). Alternatively, at least one SPCB and CPCB can be integrated into a single printed circuit board.

[0063] In this case, each sub-pixel SP arranged in the display panel 110 of the display device 100 may include a light-emitting device and circuit elements such as a driving transistor for driving the light-emitting device.

[0064] The type and number of circuit elements forming each sub-pixel SP can vary depending on the provided functions and design scheme.

[0065] Figure 3 This is a diagram illustrating an example of the circuitry of a sub-pixel SP of a display device 100 according to an embodiment of the present disclosure.

[0066] refer to Figure 3 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors, and the organic light-emitting diode may be implemented as a light-emitting device ED.

[0067] For example, a sub-pixel SP may include a driving transistor DRT, a switching transistor SCT, a sensing transistor SENT, a storage capacitor CST, and a light-emitting device ED.

[0068] The driving transistor DRT has a first node N1, a second node N2, and a third node N3. When the switching transistor SCT is turned on, the first node N1 of the driving transistor DRT can act as a gate node, and a data voltage VDATA is applied to this gate node from the data driver circuit 130 through the data line DL. The second node N2 of the driving transistor DRT can be electrically connected to the anode electrode of the light-emitting element ED, and can act as a source node or a drain node. The third node N3 of the driving transistor DRT can be electrically connected to the drive voltage line VDDL to which the drive voltage VDD is applied, and can act as a drain node or a source node.

[0069] During the display driving period, the driving voltage VDD required to display the image can be supplied through the driving voltage line VDDL. For example, the sub-pixel driving voltage VDD required to display the image can be 27V.

[0070] A switching transistor SCT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and its gate node is connected to the gate line GL, so that it operates in response to a scan signal SC supplied through the gate line GL. When the switching transistor SCT is turned on, the data voltage VDATA supplied through the data line DL is delivered to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0071] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line VREFL. The gate line GL is connected to the gate node and operates in response to the sensing signal SEN supplied through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage VREF supplied through the reference voltage line VREFL is applied to the second node N2 of the driving transistor DRT.

[0072] In other words, by controlling the switching transistor SCT and the sensing transistor SENT, the voltage at the first node N1 and the second node N2 of the driving transistor DRT is controlled, so that current can be supplied to drive the light-emitting device ED.

[0073] The gate nodes of the switching transistor SCT and the sensing transistor SENT can be connected to the same gate line GL, or they can be connected to different gate lines GL. Here, an example is shown in which the switching transistor SCT and the sensing transistor SENT are connected to different gate lines GL, such that the switching transistor SCT and the sensing transistor SENT can be independently controlled by a scan signal SC and a sensing signal SEN delivered through different gate lines GL.

[0074] On the other hand, when the switching transistor SCT and the sensing transistor SENT are connected to the same gate line GL, they can be simultaneously controlled by the scan signal SC or the sensing signal SEN delivered through the same gate line GL, which can increase the aperture ratio of the sub-pixel SP.

[0075] Furthermore, the transistors arranged in the sub-pixel SP can be formed not only with n-type transistors but also with p-type transistors. Here, an example is shown in which the transistors are formed with n-type transistors.

[0076] The storage capacitor CST is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and maintains the data voltage VDATA during a frame time period.

[0077] Depending on the type of driving transistor DRT, the storage capacitor CST can be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage VSS can be applied to the cathode of the light-emitting element ED.

[0078] Here, the base voltage VSS can be the ground voltage or a voltage higher or lower than the ground voltage. Furthermore, the base voltage VSS can vary depending on the driving state. For example, the base voltage VSS during the display driving time and the base voltage VSS during the sensing driving time can be set differently.

[0079] For illustrative purposes, the above structure of the sub-pixel SP is an example based on a 3-transistor-1-capacitor (3T1C) configuration and may include one or more additional transistors, or in some cases, one or more additional capacitors. Alternatively, each of the multiple sub-pixel SPs may have the same structure, or some sub-pixel SPs may have different structures.

[0080] A display device 100 according to an embodiment of the present disclosure may use the following method: during a characteristic sensing period of a driving transistor DRT, measuring the current flowing in a storage capacitor CST caused by the voltage charging therein, in order to effectively sense characteristic values ​​of the driving transistor DRT, such as threshold voltage or mobility. This method is referred to as current sensing.

[0081] In other words, by measuring the current flowing from the voltage charging the storage capacitor CST during the characteristic value sensing period of the driving transistor DRT, the characteristic value or characteristic value change of the driving transistor DRT within the sub-pixel SP can be determined.

[0082] In this case, the reference voltage line VREFL is used not only to deliver the reference voltage VREF, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT within the sub-pixel SP. Therefore, the reference voltage line VREFL can be referred to as a sensing line.

[0083] Figure 4 This is a block diagram illustrating an example of using a feedback drive voltage VDDFB and a drive voltage VDD to change a gamma reference voltage in a display device 100 according to an embodiment of the present disclosure.

[0084] The display device 100 may include a display panel 110, a power management circuit 150, a gamma voltage generation circuit 170, a data driver circuit 130, and a drive voltage supply circuit 160.

[0085] The display panel 110 can be electrically connected to the power management circuit 150 via the feedback drive voltage line VDDFBL. The display panel 110 can be electrically connected to the drive voltage supply circuit 160 via the drive voltage line VDDL.

[0086] The drive voltage supply circuit 160 can be electrically connected to the power management circuit 150 via the drive voltage line VDDL. According to an embodiment, the drive voltage supply circuit 160 can be implemented within the power management circuit 150.

[0087] The power management circuit 150 may include a lookup table (LUT). The power management circuit 150 can use the lookup table (LUT) to obtain the difference between the drive voltage VDD and the feedback drive voltage VDDFB. The power management circuit 150 can generate a gamma reference voltage (e.g., a first gamma reference voltage VREFT1 and a second gamma reference voltage VREFB2) based on the difference between the drive voltage VDD and the feedback drive voltage VDDFB. Therefore, the power management circuit 150 can generate a gamma reference voltage that reflects the voltage drop across the drive voltage VDD.

[0088] The power management circuit 150 can be connected to the gamma voltage generation circuit 170 via a gamma reference voltage line. The gamma reference voltage line may include a first gamma reference voltage line VREFTL and a second gamma reference voltage line VREFBL. The first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2 can be input to the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL, respectively. The voltage level of the first gamma reference voltage VREFT1 can be higher than the voltage level of the second gamma reference voltage VREFB2.

[0089] The gamma voltage generation circuit 170 can be connected to the data driver circuit 130 via the gamma reference voltage supply line GRL. The gamma reference voltage used to generate the data voltage VDATA can be applied to the gamma reference voltage supply line GRL.

[0090] The data driver circuit 130 can generate a data voltage VDATA using a gamma reference voltage. The data driver circuit 130 can supply the data voltage VDATA to the display panel 110 via the data line DL.

[0091] The display panel 110 can display an image by supplying a data voltage VDATA to the sub-pixels SP.

[0092] The following section describes an example operation of the gamma voltage generation circuit 170 generating a gamma reference voltage.

[0093] Figure 5 This is a diagram illustrating the gamma voltage generation circuit 170 of a display device 100 according to an embodiment of the present disclosure.

[0094] refer to Figure 5 The gamma voltage generation circuit 170 may include a first gamma reference voltage line VREFLT that is input with a first gamma reference voltage VREFT1, a second gamma reference voltage line VREFBL that is input with a second gamma reference voltage VREFB2, and a series of resistors R for dividing the first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2.

[0095] The first gamma reference voltage VREFT1 can be a level 0 gamma voltage applied to the upper end of the resistor string R, and the second gamma reference voltage VREFB2 can be a level 255 gamma voltage applied to the lower end of the resistor string R.

[0096] Therefore, the gamma voltage generation circuit 170 can output gamma voltages representing multiple gray levels (e.g., gray levels 0, 1, 3, 15, 31, 63, 127, 191, and 255) by dividing the first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2 via a resistor series R. For example, the gamma voltage corresponding to gray level 0 can be output as a first voltage V0, the gamma voltage corresponding to gray level 1 can be output as a second voltage V2, the gamma voltage corresponding to gray level 254 can be output as a third voltage V254, and the gamma voltage corresponding to gray level 255 can be output as a fourth voltage V255.

[0097] Figure 6 This is a diagram illustrating the layout structure of multiple lines in a display device 100 according to an embodiment of the present disclosure.

[0098] refer to Figure 6 The control printed circuit board (CPCB) may have a controller 140, a power management circuit 150, and a drive voltage supply circuit 160 mounted thereon. According to an embodiment, the drive voltage supply circuit 160 may be included in the power management circuit 150.

[0099] The source printed circuit board (SPCB) may have a source film SF mounted thereon, a data driver circuit 130 including a source driver integrated circuit SDIC, and a gamma voltage generation circuit 170. The gamma voltage generation circuit 170 may be disposed separately from the data driver circuit 130 on the source printed circuit board SPCB, or may be included in the data driver circuit 130.

[0100] The power management circuit 150 and the drive voltage supply circuit 160 can be electrically connected via the second drive voltage line VDDL2. The power management circuit 150 can be connected to the gamma voltage generation circuit 170 via the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL. The power management circuit 150 can be connected to the display panel 110 via the feedback drive voltage line VDDFBL.

[0101] The driving voltage supply circuit 160 can be connected to the display panel 110 via the first driving voltage line VDDL1. At least a portion of the first driving voltage line VDDL1 can be disposed on the source film SF. The first driving voltage line VDDL1 can be connected to the display panel 110 via the source film SF.

[0102] The feedback drive voltage line VDDFBL can be connected to the sub-pixel SP located at the outermost edge of the display panel 110. The connection point of the sub-pixel SP can be located in the display area DA or the non-display area NDA. At least a portion of the feedback drive voltage line VDDFBL can be located on the source film SF.

[0103] For example, the feedback drive voltage line VDDFBL can consist of multiple lines. The feedback drive voltage line VDDFBL can be connected to the leftmost sub-pixel SP and the rightmost sub-pixel SP in the display panel 110, respectively. The connected feedback drive voltage line VDDFBL can be electrically connected to the power management circuit 150.

[0104] The gamma voltage generation circuit 170 can be connected to the data driver circuit 130 via the gamma reference voltage supply line GRL.

[0105] The data driver circuit 130 can generate a data voltage VDATA based on the gamma reference voltage, and can supply the data voltage VDATA to the display panel 110 through the data line DL.

[0106] exist Figure 2 The description describes the source film SF and the source driver integrated circuit SDIC located on the source printed circuit board (SPCB), and therefore redundant descriptions can be omitted.

[0107] Figure 7 This is a diagram of the power management circuit 150 of a display device 100 according to an embodiment of the present disclosure.

[0108] refer to Figure 7 The power management circuit 150 may include a first analog-to-digital converter ADC1, a second analog-to-digital converter ADC2, a first subtractor circuit SUB1, a readdressing circuit 510, a register 520, a first switch 530, a second switch 540, a selector circuit MUX, a limiter circuit CLAMP, and a second subtractor circuit SUB2.

[0109] The readdressing circuit 510 may include a first comparator circuit 511, a second comparator circuit 513, and an OR circuit 515. The register 520 may include data in the form of a lookup table (LUT).

[0110] The first analog-to-digital converter (ADC1) can be connected to the feedback drive voltage line VDDFBL. The second analog-to-digital converter (ADC2) can be connected to the drive voltage line VDDL2. The first ADC1 and the second ADC2 can be connected to the first subtractor circuit SUB1.

[0111] The first subtractor circuit SUB1 can be connected to the first switch 530. The first analog-to-digital converter ADC1 can be connected to the second switch 540. The first switch 530 and the second switch 540 can be connected to the register 520. The register 520 can be connected to the limiter circuit CLAMP. The limiter circuit CLAMP can be connected to the second subtractor circuit SUB2. The second subtractor circuit SUB2 can be connected to the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL.

[0112] The first analog-to-digital converter (ADC1) can be connected to the readdressing circuit 510. The first ADC1 can be connected to the first comparator circuit 511 and the second comparator circuit 513. The first comparator circuit 511 and the second comparator circuit 513 can be connected to the OR circuit 515. The OR circuit 515 can be connected to the selector circuit MUX. The selector circuit MUX can be connected to the controller 140, or can receive a selection signal from the controller 140.

[0113] The first analog-to-digital converter (ADC1) converts the analog feedback drive voltage VDDFB received from the feedback drive voltage line VDDFBL into digital form. The second analog-to-digital converter (ADC2) converts the analog drive voltage VDD received from the drive voltage line VDDL2 into digital form.

[0114] The first analog-to-digital converter (ADC1) can output the converted digital feedback drive voltage VDDFB to the first subtractor circuit SUB1, the second switch 540, and the re-addressing circuit 510. The second analog-to-digital converter (ADC2) can output the converted digital drive voltage VDD to the first subtractor circuit SUB1.

[0115] By converting the drive voltage VDD and feedback drive voltage VDDFB into digital form, noise present in the analog form of the drive voltage VDD or the analog form of the feedback drive voltage VDDFB may not be reflected in the adjustment of the gamma reference voltage. Since the drive voltage VDD and feedback drive voltage VDDFB are converted into digital form, the filters that are normally provided in the display device 100 to remove noise from the drive voltage VDD or the feedback drive voltage VDDFB can be omitted.

[0116] The first subtractor circuit SUB1 subtracts the value of the feedback drive voltage VDDFB from the value of the drive voltage VDD. By performing this subtraction, the first subtractor circuit SUB1 calculates the difference between the drive voltage VDD and the feedback drive voltage VDDFB. The first subtractor circuit SUB1 outputs the difference between the drive voltage VDD and the feedback drive voltage VDDFB to the first switch 530 and the register 520.

[0117] The first comparator circuit 511 can compare the input feedback drive voltage VDDFB with the maximum feedback drive voltage VDDFB_MAX. The second comparator circuit 513 can compare the input feedback drive voltage VDDFB with the minimum feedback drive voltage VDDFB_MIN.

[0118] When the input feedback drive voltage VDDFB is less than or equal to the maximum feedback drive voltage VDDFB_MAX, the first comparator circuit 511 can output a low signal to the OR circuit 515. When the input feedback drive voltage VDDFB is greater than the maximum feedback drive voltage VDDFB_MAX, the first comparator circuit 511 can output a high signal to the OR circuit 515.

[0119] When the input feedback drive voltage VDDFB is greater than the minimum feedback drive voltage VDDFB_MIN, the second comparator circuit 513 can output a low signal to the OR circuit 515. When the input feedback drive voltage VDDFB is less than or equal to the minimum feedback drive voltage VDDFB_MIN, the second comparator circuit 513 can output a high signal to the OR circuit 515.

[0120] When a high signal is received from the first comparator circuit 511 and / or the second comparator circuit 513, the OR circuit 515 can output a high signal to the selector circuit MUX. When a low signal is received from both the first comparator circuit 511 and the second comparator circuit 513, the OR circuit 515 can output a low signal to the selector circuit MUX.

[0121] Controller 140 can output a first selection signal or a second selection signal to the selector circuit MUX.

[0122] The selector circuit MUX can be configured as a multiplexer or a demultiplexer. The selector circuit MUX can change the state of the first switch 530 and the second switch 540 to an on or off state in response to signals received from the readdressing circuit 510 and / or the controller 140. Figures 9 to 11 The description illustrates the control operations of the first switch 530 and the second switch 540 in the selector circuit MUX.

[0123] When the first switch 530 is turned on, the difference between the drive voltage VDD and the feedback drive voltage VDDFB can be input into register 520. When the second switch 540 is turned on, the value of the feedback drive voltage VDDFB can be input into register 520.

[0124] Register 520 can store the difference between the drive voltage VDD and the feedback drive voltage VDDFB, as well as the value of the feedback drive voltage VDDFB, as data in the form of a lookup table (LUT). Figure 8The description provides data related to the changes in the drive voltage VDD included in the lookup table LUT.

[0125] Register 520 can output a first digital value, determined based on the value of the feedback drive voltage VDDFB, to the limiter circuit CLAMP. The first digital value can be the difference between the drive voltage VDD and the feedback drive voltage VDDFB. When the amplitude of the first digital value exceeds a threshold, the limiter circuit CLAMP can change the input first digital value to a second digital value with a fixed value. When a crack or short circuit occurs in the display panel 110, the difference between the feedback drive voltage VDDFB and the drive voltage VDD may exceed the threshold. If this difference exceeds the threshold and is reflected in the gamma reference voltage, voltage adjustment unrelated to the drive voltage VDD or the feedback drive voltage VDDFB may occur. By changing the amplitude of the first digital value, the limiter circuit CLAMP can prevent the data voltage VDATA from being adjusted regardless of the drive voltage VDD.

[0126] The limiter circuit CLAMP can output either the first digital value or the second digital value to the second subtractor circuit SUB2.

[0127] The second subtractor circuit SUB2 can subtract either a first digital value or a second digital value from a first gamma reference voltage VREFT1 and a second gamma reference voltage VREFB2, which is lower than the first gamma reference voltage VREFT1. As a result of the subtraction, the first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2 can become a third gamma reference voltage VREFT3 and a fourth gamma reference voltage VREFB4, respectively, each with a different value. Therefore, the gamma reference voltage used to generate the data voltage VDATA can be changed.

[0128] The second subtractor circuit SUB2 can output the third gamma reference voltage VREFT3 and the fourth gamma reference voltage VREFB4 to the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL, respectively.

[0129] The lookup table (LUT) in the power management circuit 150 will be described below.

[0130] Figure 8 This is a diagram illustrating the lookup table (LUT) of a display device 100 according to an embodiment of the present disclosure.

[0131] refer to Figure 8 The lookup table (LUT) can include multiple gradation levels (GRAY), multiple feedback drive voltages (VDDFB) corresponding to the multiple gradation levels (GRAY), and the difference between the drive voltage (VDD) and the multiple feedback drive voltages (VDDFB).

[0132] When a lookup table (LUT) is generated in register 520, register 520 can receive multiple feedback drive voltages VDDFB, drive voltage VDD, and multiple differences between feedback drive voltages VDDFB and drive voltage VDD.

[0133] The amount of current flowing through the display panel 110 can be proportional to the grayscale level GRAY. As the amount of current flowing through the display panel 110 increases, the voltage drop of the drive voltage VDD increases. Therefore, the grayscale level GRAY can be proportional to the voltage drop of the drive voltage VDD. Since the feedback drive voltage VDDFB is obtained by subtracting the voltage drop from the drive voltage VDD, the feedback drive voltage VDDFB may be large when the voltage drop of the drive voltage VDD is small. Therefore, the power management circuit 150 can store the feedback drive voltage VDDFB with the maximum value among the multiple input feedback drive voltages VDDFB as the first grayscale level corresponding to the minimum grayscale value (e.g., grayscale level 0).

[0134] Since the feedback drive voltage VDDFB is obtained by subtracting the voltage drop from the drive voltage VDD, the feedback drive voltage VDDFB may be small when the voltage drop is large. The power management circuit 150 can store the feedback drive voltage VDDFB with the minimum value among the multiple input feedback drive voltages VDDFB as a second gray level corresponding to the maximum gray value (e.g., gray level 255).

[0135] The power management circuit 150 can obtain multiple feedback drive voltages VDDFB corresponding to multiple gray levels GRAY between the first and second gray levels through interpolation. The power management circuit 150 can store the obtained multiple feedback drive voltages VDDFB as corresponding to the multiple gray levels GRAY.

[0136] For example, if the feedback drive voltage VDDFB corresponding to gray level 0 is a digital value equal to 4000mV, and the feedback drive voltage VDDFB corresponding to gray level 255 is a digital value equal to 3745mV, then the power management circuit 150 can obtain a voltage with a digital value equivalent to 3999mV as the feedback drive voltage VDDFB corresponding to gray level 254. The power management circuit 150 can store the obtained feedback drive voltage VDDFB with a digital value equivalent to 3999mV as corresponding to gray level 254.

[0137] When the driving voltage VDD has a fixed value, the difference between the driving voltage VDD and the feedback driving voltage VDDFB can be inversely proportional to the value of the feedback driving voltage VDDFB.

[0138] The power management circuit 150 can store a first difference (which is the minimum difference between the input drive voltage VDD and the feedback drive voltage VDDFB) as a corresponding feedback drive voltage VDDFB or a first gray level with a maximum value.

[0139] The power management circuit 150 can store a second difference (which is the maximum difference between the input drive voltage VDD and the feedback drive voltage VDDFB) as a second gray level corresponding to the feedback drive voltage VDDFB with the minimum value.

[0140] The power management circuit 150 can obtain multiple differences corresponding to multiple feedback drive voltages VDDFB by interpolating between a first difference and a second difference. For example, when the first difference corresponding to the maximum feedback drive voltage VDDFB is 0 and the second difference corresponding to the minimum feedback drive voltage VDDFB is 255, the difference corresponding to gray level 254 or the difference corresponding to the feedback drive voltage VDDFB associated with gray level 254 can have a value of 254.

[0141] Register 520 can use data stored in a lookup table (LUT) to output a voltage having the difference between the drive voltage VDD and the feedback drive voltage VDDFB. For example, register 520 can store data in the LUT including grayscale level 255, the feedback drive voltage VDDFB corresponding to grayscale level 255 with a digital value equivalent to 4000mV, and the difference 255 corresponding to the feedback drive voltage VDDFB with a digital value of 4000mV. When a feedback drive voltage VDDFB with a digital value equivalent to 4000mV is input from an external source, register 520 can output the difference corresponding to the value 255.

[0142] However, this is just an example and is not limited to generating a lookup table (LUT) based solely on two sensed values ​​(drive voltage VDD and feedback drive voltage VDDFB).

[0143] For example, the power management circuit 150 can generate (or store or update) the values ​​of the drive voltage VDD and feedback drive voltage VDDFB for all gray levels in a lookup table (LUT) based on the results obtained by acquiring the drive voltage VDD and feedback drive voltage VDDFB under at least three gray-scale conditions.

[0144] The power management circuit 150 can operate in the first mode ( Figure 9 ), second mode ( Figure 10 ), and the third mode ( Figure 11The first mode is used to store the values ​​of the driving voltage VDD and feedback driving voltage VDDFB for each grayscale level in the lookup table LUT. The second mode is used to adjust and output multiple gamma reference voltages VREFT1, VREFB2, VREFT3 and VREFB4 based on the actual values ​​of the driving voltage VDD and feedback driving voltage VDDFB during display driving. The third mode is used to update the lookup table LUT.

[0145] Figure 8 An example of generating or updating a LUT is shown.

[0146] Figure 9 This is a diagram illustrating an example of a power management circuit 150 for generating a lookup table (LUT) according to an embodiment of the present disclosure.

[0147] refer to Figure 9 The power management circuit 150 can operate in a first mode. For example, the first mode can be executed during the initial startup of the display device or before the product is shipped.

[0148] The first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 can each convert the values ​​of the feedback drive voltage VDDFB and the drive voltage VDD provided to them into digital form.

[0149] The first analog-to-digital converter (ADC1) outputs the digitally converted feedback drive voltage VDDFB to the first subtractor circuit SUB1 and the second switch 540. The second analog-to-digital converter (ADC2) outputs the digitally converted drive voltage VDD to the first subtractor circuit SUB1.

[0150] The first subtractor circuit SUB1 can calculate the difference between the drive voltage VDD and the feedback drive voltage VDDFB, and output it to the first switch 530.

[0151] The selector circuit MUX can receive a first selection signal SE1 from the controller 140. The first selection signal SE1 can be a control signal for turning on the first switch 530 and the second switch 540 via the selector circuit MUX. The selector circuit MUX can apply a first control signal SC1 to the first switch 530 and the second switch 540 in response to the first selection signal SE1.

[0152] The first switch 530 and the second switch 540 can be turned on in response to the first control signal SC1. Therefore, the difference between the drive voltage VDD and the feedback drive voltage VDDFB, as well as the value of the feedback drive voltage VDDFB, can be provided to the register 520.

[0153] When the first selection signal SE1 is input to the selector circuit MUX, register 520 can obtain or store data included in the lookup table LUT based on the feedback drive voltage VDDFB of multiple inputs and the difference between the drive voltage VDD and the feedback drive voltage VDDFB. For example, in the first mode, the values ​​of the drive voltage VDD and the feedback drive voltage VDDFB for each grayscale level can be stored. Because in Figure 8 The description explains the operations for obtaining or storing data included in the lookup table LUT, so redundant explanations are omitted.

[0154] Figure 10 This is a diagram illustrating an example of a power management circuit 150 for outputting a gamma reference voltage using a lookup table (LUT) according to an embodiment of the present disclosure.

[0155] refer to Figure 10 The power management circuit 150 can operate in a second mode. For example, the second mode can be executed in real time during the use of the display device, and the output gamma reference voltage can be adjusted based on the sensed feedback drive voltage VDDFB.

[0156] The feedback drive voltage VDDFB can be input to the first analog-to-digital converter ADC1 through the feedback drive voltage line VDDFBL.

[0157] The first analog-to-digital converter ADC1 can convert the value of the feedback drive voltage VDDFB into digital form.

[0158] The first analog-to-digital converter ADC1 can output the digital conversion value of the feedback drive voltage VDDFB to the second switch 540 and the re-addressing circuit 510.

[0159] The value of the feedback drive voltage VDDFB input to the readdressing circuit 510 can be input to the first comparator circuit 511 and the second comparator circuit 513 included in the readdressing circuit 510.

[0160] refer to Figure 10 When the feedback drive voltage VDDFB is lower than the maximum feedback drive voltage VDDFB_MAX, the low signal LS can be output to the OR circuit 515. When the input feedback drive voltage VDDFB is higher than the minimum feedback drive voltage VDDFB_MIN, the second comparator circuit 513 can output the low signal LS to the OR circuit 515. When the OR circuit 515 receives the low signal LS, it can output the low signal LS to the selector circuit MUX.

[0161] The selector circuit MUX can receive a low signal LS from the OR circuit 515. Upon receiving the low signal LS, the selector circuit MUX can continue to receive a second selection signal SE2 from the controller 140. Upon receiving the second selection signal SE2, the selector circuit MUX can output a second control signal SC2 to the first switch 530 and a first control signal SC1 to the second switch 540.

[0162] When the second control signal SC2 is received, the first switch 530 can be in the off state. That is, the second control signal SC2 can be a signal used to turn off the switch. The second switch 540 can be in the on state when the first control signal SC1 is received. When the second switch 540 is on, the register 520 can receive the value of the feedback drive voltage VDDFB. In other words, when the feedback drive voltage VDDFB is between the maximum feedback drive voltage VDDFB_MAX and the minimum feedback drive voltage VDDFB_MIN, the second switch 540 can be on.

[0163] When the first selection signal SE1 is applied to the selector circuit MUX, register 520 can use the input feedback drive voltage VDDFB and the value stored in the lookup table LUT to output a first digital value to the limiter circuit CLAMP, having a digital value corresponding to the difference between the drive voltage VDD and the feedback drive voltage VDDFB. Because in Figure 8 The description explains the operation of register 520 using the difference between the data output drive voltage VDD and the feedback drive voltage VDDFB included in the LUT, so redundant explanations are omitted.

[0164] When the first digital value exceeds the threshold voltage, the limiter circuit CLAMP can change the first digital value, which has a digital value corresponding to the difference between the drive voltage VDD and the feedback drive voltage VDDFB, to a second digital value with a fixed value, and can output the second digital value to the second subtractor circuit SUB2.

[0165] The second subtractor circuit SUB2 can subtract a first digital value or a second digital value from the first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2, respectively, and can correspondingly change the first gamma reference voltage VREFT1 and the second gamma reference voltage VREFB2 to the third gamma reference voltage VREFT3 and the fourth gamma reference voltage VREFB4, respectively.

[0166] The first gamma reference voltage VREFT1, the second gamma reference voltage VREFB2, the third gamma reference voltage VREFT3, and the fourth gamma reference voltage VREFB4 can have digital values.

[0167] The third gamma reference voltage VREFT3 and the fourth gamma reference voltage VREFB4 can be output to the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL, respectively.

[0168] The output third gamma reference voltage VREFT3 and fourth gamma reference voltage VREFB4 can be input to the gamma voltage generation circuit 170 through the first gamma reference voltage line VREFTL and the second gamma reference voltage line VREFBL, respectively.

[0169] Figure 11 This is a diagram illustrating an example of a power management circuit 150 configured to initiate an update of the lookup table LUT when the feedback drive voltage VDDFB changes, according to an embodiment of the present disclosure.

[0170] refer to Figure 11 The power management circuit 150 can operate in a third mode. For example, the third mode can be executed during use of the display device to update the values ​​stored in the lookup table (LUT). The feedback drive voltage VDDFB can be input to the first analog-to-digital converter (ADC1) via the feedback drive voltage line VDDFBL. The drive voltage VDD can be input to the second analog-to-digital converter (ADC2) via the second drive voltage line VDDL2.

[0171] The first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 can each convert the feedback drive voltage VDDFB and the drive voltage VDD into digital form.

[0172] The first analog-to-digital converter (ADC1) can output the digital value of the feedback drive voltage VDDFB to the first subtractor circuit SUB1, the second switch 540, and the re-addressing circuit 510. The second analog-to-digital converter (ADC2) can output the digital value of the drive voltage VDD to the first subtractor circuit SUB1.

[0173] The first subtractor circuit SUB1 can calculate the difference between the drive voltage VDD and the feedback drive voltage VDDFB, and can output the result to the first switch 530.

[0174] The value of the feedback drive voltage VDDFB input to the readdressing circuit 510 can be input to the first comparator circuit 511 and the second comparator circuit 513 included in the readdressing circuit 510.

[0175] refer to Figure 11When the feedback drive voltage VDDFB becomes higher than the maximum feedback drive voltage VDDFB_MAX, the first comparator circuit 511 can output a high signal HS to the OR circuit 515. When the input feedback drive voltage VDDFB becomes lower than the minimum feedback drive voltage VDDFB_MIN, the second comparator circuit 513 can output a high signal HS to the OR circuit 515. When the OR circuit 515 receives a high signal HS from either the first comparator circuit 511 or the second comparator circuit 513, it can output a high signal HS to the selector circuit MUX.

[0176] The selector circuit MUX can receive a high signal HS from the OR circuit 515. Upon receiving the high signal HS, the selector circuit MUX can stop receiving the second selection signal SE2 from the controller 140. Upon receiving the high signal HS, the selector circuit MUX can apply the first control signal SC1 to the first switch 530 and the second switch 540.

[0177] When the first control signal SC1 is received, the first switch 530 and the second switch 540 can be in the on state. When the first switch 530 and the second switch 540 are on, the register 520 can receive the difference between the driving voltage VDD and the feedback driving voltage VDDFB, as well as the value of the feedback driving voltage VDDFB.

[0178] When the selector circuit MUX receives a high signal HS, register 520 can retrieve or store data included in the lookup table LUT based on multiple feedback drive voltages VDDFB input to register 520 and the difference between the drive voltage VDD and the feedback drive voltage VDDFB. Because in Figure 8 The description describes the operations for retrieving or storing data included in the lookup table LUT, so redundant descriptions have been omitted.

[0179] Therefore, when the feedback drive voltage VDDFB deviates from the range between the maximum feedback drive voltage VDDFB_MAX and the minimum feedback drive voltage VDDFB_MIN, the lookup table LUT can be updated. A gamma reference voltage can be generated based on the updated lookup table LUT. The display device 100 can generate a data voltage VDATA based on the generated gamma reference voltage. For example, the value of the feedback drive voltage VDDFB or the drive voltage VDD may deviate from a predetermined range when the display device 100 is powered on or off. When the value of the feedback drive voltage VDDFB or the drive voltage VDD deviates from the predetermined range, the display device 100 can update the lookup table LUT. The display device 100 can generate a gamma reference voltage based on the updated lookup table LUT. The display device 100 can use the data voltage VDATA corresponding to the generated gamma reference voltage to prevent noise generation in the image. Since noise generation is prevented, the appearance of residual horizontal lines in the image can be reduced.

[0180] The improvements of the display device 100 according to various embodiments of the present disclosure will be described below.

[0181] Figure 12 This is a waveform diagram of the feedback drive voltage VDDFB and the gamma reference voltage of the display device 100 according to an embodiment of the present disclosure.

[0182] Noise in the display panel 110 may cause residual horizontal lines in the image. The noise can be proportional to the amplitude of the waveform of the feedback drive voltage VDDFB and the amplitude of the waveform of the gamma reference voltage.

[0183] refer to Figure 12 The first gamma reference voltage waveform 1210 can refer to the waveform of the gamma reference voltage before adjustment using a lookup table (LUT). The second gamma reference voltage waveform 1220 can refer to the waveform of the gamma reference voltage after adjustment using a lookup table (LUT).

[0184] The amplitude of the first gamma reference voltage waveform 1210 is greater than the amplitude of the second gamma reference voltage waveform 1220. Furthermore, the amplitude of the maximum peak value in the first gamma reference voltage waveform 1210 is greater than the amplitude of the maximum peak value in the second gamma reference voltage waveform 1220. Therefore, during the adjustment of the gamma reference voltage using a lookup table (LUT), the frequency of noise phenomena in the display device 100 can be reduced. As the frequency of noise phenomena decreases, the number of residual horizontal lines displayed in the image can also be reduced.

[0185] refer to Figure 12The first feedback drive voltage waveform 1230 refers to the waveform of the feedback drive voltage VDDFB before adjusting the gamma reference voltage using a lookup table (LUT). The second feedback drive voltage waveform 1240 refers to the waveform of the feedback drive voltage VDDFB after adjusting the gamma reference voltage using a lookup table (LUT).

[0186] The amplitude of the first feedback drive voltage waveform 1230 is greater than the amplitude of the second feedback drive voltage waveform 1240. Therefore, during the adjustment of the gamma reference voltage using a lookup table (LUT), the frequency of noise phenomena in the display device 100 can be reduced. As the frequency of noise phenomena decreases, the number of residual horizontal lines in the displayed image can also be reduced.

[0187] The embodiments of the present disclosure described above will now be briefly summarized as follows.

[0188] The display device may include: a display panel having a plurality of sub-pixels; a data driver circuit that applies a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines; a drive voltage supply circuit that supplies drive voltages to the display panel; and a power management circuit that receives feedback drive voltages from the display panel, receives drive voltages output from the drive voltage supply circuit, and outputs a gamma reference voltage to the data driver circuit.

[0189] The power management circuit may include registers that store data related to changes in the drive voltage.

[0190] The gamma reference voltage can vary according to the feedback drive voltage.

[0191] The display device may also include a feedback drive voltage line connected between the display panel and the power management circuit, and a drive voltage line connected between the drive voltage supply circuit and the power management circuit.

[0192] The power management circuit may further include: a first analog-to-digital converter (ADC) connected between the feedback drive voltage line and the register, and converting the feedback drive voltage into digital form; a second ADC connected between the drive voltage line and the register, and converting the drive voltage into digital form; and a first subtractor circuit that calculates the difference between the output of the first ADC and the output of the second ADC, and provides the difference to the register.

[0193] The power management circuit may further include: a first switch connected between the first subtractor circuit and the register; a second switch connected between the first analog-to-digital converter and the register; and a selector circuit for controlling the first switch and the second switch.

[0194] When the first switch is turned on, the difference can be input from the first subtractor circuit to the register.

[0195] When the second switch is turned on, the value of the feedback drive voltage can be input from the first analog-to-digital converter to the register.

[0196] The display device may also include a controller that controls a power management circuit and a drive voltage supply circuit and outputs a first selection signal or a second selection signal to a selector circuit.

[0197] The selector circuit can turn on the first switch and the second switch in response to the first selection signal.

[0198] The selector circuit can turn off the first switch and turn on the second switch in response to the second selection signal.

[0199] The power management circuit may also include a re-addressing circuit.

[0200] The readdressing circuit can control the selector circuit based on the comparison between the feedback drive voltage and a preset voltage range.

[0201] The re-addressing circuit may also include a first comparator circuit and a second comparator circuit.

[0202] The first comparator circuit can compare the value of the feedback drive voltage input from the feedback drive voltage line with the maximum feedback drive voltage value.

[0203] The second comparator circuit can compare the value of the feedback drive voltage input from the feedback drive voltage line with the minimum feedback drive voltage value.

[0204] Readdressing circuits can also include OR circuits.

[0205] When the value of the feedback drive voltage is greater than the value of the maximum feedback drive voltage, the first comparator circuit can apply the first signal to the OR circuit.

[0206] When the value of the feedback drive voltage is less than or equal to the value of the maximum feedback drive voltage, the first comparator circuit can apply the second signal to the OR circuit.

[0207] When the value of the feedback drive voltage is less than or equal to the minimum feedback drive voltage value, the second comparator circuit can apply the first signal to the OR circuit.

[0208] When the value of the feedback drive voltage is greater than the minimum feedback drive voltage value, the second comparator circuit can apply the second signal to the OR circuit.

[0209] When a first signal is applied from the first comparator circuit or the second comparator circuit, the OR circuit can apply the first signal to the selector circuit.

[0210] When a second signal is applied from both the first comparator circuit and the second comparator circuit, the OR circuit can apply the second signal to the selector circuit.

[0211] The selector circuit can turn on the first switch and the second switch in response to the first signal.

[0212] When the first switch and the second switch are turned on, the difference between the driving voltage and the feedback driving voltage, as well as the value of the feedback driving voltage, can be input into the register.

[0213] The value of the feedback drive voltage can be input to the register from the first analog-to-digital converter.

[0214] The register can output the difference between the drive voltage and the feedback drive voltage based on the input value of the feedback drive voltage.

[0215] The power management circuit may include a second subtractor circuit that subtracts the difference from the gamma reference voltage, and a gamma reference voltage line that outputs the gamma reference voltage.

[0216] The second subtractor circuit can output a voltage to the gamma reference voltage line with a value obtained by subtracting the difference from the gamma reference voltage.

[0217] The gamma reference voltage line may include a first gamma reference voltage line that outputs a first gamma reference voltage and a second gamma reference voltage line that outputs a second gamma reference voltage lower than the first gamma reference voltage.

[0218] The second subtractor circuit can change the first gamma reference voltage and the second gamma reference voltage into the third gamma reference voltage and the fourth gamma reference voltage respectively based on the difference.

[0219] The second subtractor circuit can output the third gamma reference voltage to the first gamma reference voltage line.

[0220] The second subtractor circuit can output the fourth gamma reference voltage to the second gamma reference voltage line.

[0221] The power management circuit may also include a limiter circuit connected between the register and the second subtractor circuit and configured to limit the magnitude of the difference.

[0222] A display device may include: a display panel having a plurality of sub-pixels; a data driver circuit that applies a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines; a drive voltage supply circuit that supplies drive voltages to the display panel; and a power management circuit that receives a plurality of feedback drive voltages from the display panel and receives the drive voltages output from the drive voltage supply circuit.

[0223] The power management circuit may include a register that stores data that can vary according to multiple feedback drive voltages and drive voltages.

[0224] Power management circuits can store data in registers in the form of lookup tables.

[0225] The lookup table may include multiple gray levels, multiple feedback drive voltages corresponding to the multiple gray levels, and the difference between the drive voltage and the multiple feedback drive voltages.

[0226] The power management circuit can input the first feedback drive voltage with the maximum value among multiple feedback drive voltages, the second feedback drive voltage with the minimum value among multiple feedback drive voltages, and the drive voltage into a register, and can store the first feedback drive voltage input into the register as the first gray level with the minimum value among multiple gray levels.

[0227] The power management circuit can store the second feedback drive voltage input to the register as the second gray level with the maximum value among multiple gray levels.

[0228] The power management circuit can obtain a first difference corresponding to the first feedback drive voltage by subtracting the first feedback drive voltage from the input drive voltage.

[0229] The power management circuit can obtain a second difference corresponding to the second feedback drive voltage by subtracting the second feedback drive voltage from the input drive voltage.

[0230] The register can store the obtained first difference as corresponding to the first feedback drive voltage, and can store the obtained second difference as corresponding to the second feedback drive voltage.

[0231] The power management circuit can obtain multiple feedback drive voltages corresponding to multiple gray levels between the first gray level and the second gray level based on the first feedback drive voltage and the second feedback drive voltage.

[0232] The power management circuit can store multiple feedback drive voltages obtained in a register as corresponding to multiple gray levels.

[0233] The power management circuit can obtain the differences between multiple feedback drive voltages corresponding to the first feedback drive voltage and the second feedback drive voltage based on the first difference and the second difference.

[0234] The power management circuit can store the obtained difference in a register as a correspondence to multiple feedback drive voltages.

[0235] The above description has been provided to enable any person skilled in the art to make and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings provide examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0236] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to utilize the concepts of the various embodiments to provide even further embodiments.

[0237] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents conferred by those claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: The display panel contains multiple sub-pixels; A data driver circuit configured to apply multiple data voltages to the multiple sub-pixels via multiple data lines; A driving voltage supply circuit, the driving voltage supply circuit being configured to apply a driving voltage to the display panel; as well as A power management circuit is configured to receive a feedback drive voltage from the display panel, to receive the drive voltage output from the drive voltage supply circuit, and to output a gamma reference voltage to the data driver circuit. The power management circuit includes a register configured to store data related to changes in the drive voltage. The gamma reference voltage can vary based on the feedback drive voltage.

2. The display device according to claim 1, further comprising: A feedback drive voltage line is connected between the display panel and the power management circuit. as well as A drive voltage line is connected between the drive voltage supply circuit and the power management circuit. The power management circuit includes: A first analog-to-digital converter is connected between the feedback drive voltage line and the register, and converts the feedback drive voltage into digital form; A second analog-to-digital converter, connected between the drive voltage line and the register, converts the drive voltage into digital form; and A first subtractor circuit is configured to calculate the difference between the output of the first analog-to-digital converter and the output of the second analog-to-digital converter, and provide the difference to the register.

3. The display device according to claim 2, wherein, The power management circuit also includes: A first switch is connected between the first subtractor circuit and the register; A second switch, the second switch being connected between the first analog-to-digital converter and the register; and A selector circuit, configured to control the first switch and the second switch. Specifically, when the first switch is turned on, the difference is sent from the first subtractor circuit to the register, and When the second switch is turned on, the value of the feedback drive voltage is sent from the first analog-to-digital converter to the register.

4. The display device according to claim 3 further includes a controller configured to control the power management circuit and the drive voltage supply circuit, and to output a first selection signal or a second selection signal to the selector circuit. in, The selector circuit responds to the first selection signal by turning on the first switch and the second switch, and The selector circuit responds to the second selection signal by turning off the first switch and turning on the second switch.

5. The display device according to claim 3, in, The power management circuit also includes a re-addressing circuit, and The readdressing circuit is configured to control the selector circuit based on a comparison between the feedback drive voltage and a preset voltage range.

6. The display device according to claim 5, wherein, The readdressing circuit also includes a first comparator circuit and a second comparator circuit. The first comparator circuit is configured to compare the value of the feedback drive voltage input from the feedback drive voltage line with the maximum feedback drive voltage value, and The second comparator circuit is configured to compare the value of the feedback drive voltage input from the feedback drive voltage line with the minimum feedback drive voltage value.

7. The display device according to claim 6, in, The re-addressing circuit also includes an OR circuit. Specifically, when the value of the feedback drive voltage is greater than the maximum feedback drive voltage value, the first comparator circuit applies a first signal to the OR circuit. Specifically, when the value of the feedback drive voltage is less than or equal to the maximum feedback drive voltage value, the first comparator circuit applies a second signal to the OR circuit. Specifically, when the value of the feedback drive voltage is less than or equal to the minimum feedback drive voltage value, the second comparator circuit applies the first signal to the OR circuit. Specifically, when the value of the feedback drive voltage is greater than the minimum feedback drive voltage value, the second comparator circuit applies the second signal to the OR circuit. Wherein, when the first signal is applied from the first comparator circuit or the second comparator circuit, the OR circuit applies the first signal to the selector circuit, and Specifically, when the second signal is applied from both the first comparator circuit and the second comparator circuit, the OR circuit applies the second signal to the selector circuit.

8. The display device according to claim 7, in, The selector circuit is configured to turn on the first switch and the second switch in response to the first signal, and When the first switch and the second switch are turned on, the difference between the driving voltage and the feedback driving voltage, as well as the value of the feedback driving voltage, are input to the register.

9. The display device according to claim 2, in, In operation, the value of the feedback drive voltage is input from the first analog-to-digital converter to the register, and The register outputs the difference between the driving voltage and the feedback driving voltage based on the value of the input feedback driving voltage.

10. The display device according to claim 9, wherein, The power management circuit includes: A second subtractor circuit, configured to subtract the difference from the gamma reference voltage; and A gamma reference voltage line, configured to output the gamma reference voltage, and The second subtractor circuit is configured to output a voltage to the gamma reference voltage line having a value obtained by subtracting the difference from the gamma reference voltage.

11. The display device according to claim 10, in, The gamma reference voltage line includes: a first gamma reference voltage line configured to output a first gamma reference voltage; and a second gamma reference voltage line configured to output a second gamma reference voltage lower than the first gamma reference voltage. The second subtractor circuit is configured to change the first gamma reference voltage and the second gamma reference voltage to a third gamma reference voltage and a fourth gamma reference voltage, respectively, based on the difference. In operation, the third gamma reference voltage is output to the first gamma reference voltage line, and In operation, the fourth gamma reference voltage is output to the second gamma reference voltage line.

12. The display device according to claim 10, in, The power management circuit also includes a limiter circuit connected between the register and the second subtractor circuit and configured to limit the magnitude of the difference.

13. A display device, comprising: The display panel contains multiple sub-pixels; A data driver circuit configured to apply multiple data voltages to the multiple sub-pixels via multiple data lines; A driving voltage supply circuit, configured to supply a driving voltage to the display panel; as well as A power management circuit is configured to receive multiple feedback drive voltages from the display panel and to receive the drive voltage output from the drive voltage supply circuit. The power management circuit includes a register configured to store data that can vary according to the plurality of feedback drive voltages and the drive voltage.

14. The display device according to claim 13, in, The power management circuit is configured to store the data in the register in the form of a lookup table, and The lookup table includes multiple gray levels, multiple feedback drive voltages corresponding to the multiple gray levels, and the difference between the drive voltage and the multiple feedback drive voltages.

15. The display device according to claim 14, wherein, The power management circuit is configured as follows: The first feedback drive voltage with the maximum value among the plurality of feedback drive voltages, the second feedback drive voltage with the minimum value among the plurality of feedback drive voltages, and the drive voltage are input into the register; The first feedback drive voltage input to the register is stored as the first gray level with the minimum value among the plurality of gray levels; The second feedback drive voltage input to the register is stored as the second gray level with the maximum value among the plurality of gray levels; A first difference corresponding to the first feedback drive voltage is obtained by subtracting the first feedback drive voltage from the input drive voltage; as well as A second difference corresponding to the second feedback drive voltage is obtained by subtracting the second feedback drive voltage from the input drive voltage, and The register is configured to store the obtained first difference as corresponding to the first feedback drive voltage and to store the obtained second difference as corresponding to the second feedback drive voltage.

16. The display device according to claim 15, wherein, The power management circuit is also configured to: Based on the first feedback driving voltage and the second feedback driving voltage, multiple feedback driving voltages corresponding to multiple gray levels between the first gray level and the second gray level are obtained. The obtained plurality of feedback drive voltages are stored in the register as corresponding to the plurality of grayscale levels; Based on the first difference and the second difference, the differences of the plurality of feedback drive voltages corresponding to the first feedback drive voltage and the second feedback drive voltage are obtained respectively; and The obtained difference is stored in the register as a corresponding plurality of feedback drive voltages.

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