Pixel driving circuit and display apparatus

Abstract

A pixel driving circuit and a display apparatus, relating to the technical field of display. The pixel driving circuit comprises a driving transistor (DT), a threshold compensation module (10), a data writing module (20), a first light-emitting control module (31) and a first capacitor (C1); a gate electrode of the driving transistor (DT) is connected to a first node (N1), a first electrode thereof is connected to a first power supply voltage terminal (PVDD), and a second electrode thereof is connected to a third node (N3); two electrodes of the first capacitor (C1) are respectively connected to the first node (N1) and a second node (N2); the first light-emitting control module (31) is connected between a third node (N3) and a fourth node (N4); the fourth node (N4) is connected to a light-emitting element (D0); the threshold compensation module (10) is connected between the first node (N1) and the third node (N3); the threshold compensation module (10) comprises an N-type transistor; in a threshold compensation stage, the threshold compensation module (10) is configured to provide to the gate electrode of the driving transistor (DT) a first power supply voltage signal provided by the first power supply voltage terminal (PVDD), so as to perform threshold compensation on the driving transistor (DT); the data writing module (20) is connected between a data signal terminal (Vdata) and a second node (N2), so as to improve the output accuracy of the pixel driving circuit.

Description

A pixel driving circuit and display device

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411855930.5, filed on December 16, 2024, entitled “A Pixel Driving Circuit and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and display device. Background Technology

[0004] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0005] In display products, pixels are typically driven to emit light through pixel driving circuits. Improving the accuracy of the driving signals output by pixel driving circuits has become one of the technical problems that urgently need to be solved at present.

[0006] Application content

[0007] To address the aforementioned technical problems, this disclosure provides a pixel driving circuit and a display device, aiming to improve the accuracy of the output signal of the pixel driving circuit and enhance the display effect.

[0008] In a first aspect, this disclosure provides a pixel driving circuit for electrical connection with a light-emitting element, comprising a driving transistor, a threshold compensation module, a data writing module, a first light-emitting control module, and a first capacitor, wherein the gate of the driving transistor is connected to a first node, the first plate of the first capacitor is connected to the first node, and the second plate of the first capacitor is connected to a second node; the first electrode of the driving transistor is connected to a first power supply voltage terminal, and the second electrode of the driving transistor is connected to a third node.

[0009] The first light-emitting control module is connected between the third node and the fourth node. The fourth node is connected to the light-emitting element. The first light-emitting control module is configured to be turned on during the light-emitting phase and transmit the driving signal to the light-emitting element.

[0010] The threshold compensation module is connected between the first node and the third node. The threshold compensation module includes an N-type transistor. The threshold compensation module is configured to provide the first power supply voltage signal provided by the first power supply voltage terminal to the gate of the driving transistor during the threshold compensation stage, so as to perform threshold compensation on the driving transistor.

[0011] The data writing module is connected between the data signal terminal and the second node. The data writing module is configured to write the data signal provided by the data signal terminal to the second node during the data writing phase.

[0012] Secondly, based on the same technical concept, this disclosure also provides a display device, including the pixel driving circuit provided in the first aspect of this disclosure.

[0013] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0014] In the pixel driving circuit and display device provided in this disclosure, during the threshold compensation stage, the first power supply voltage signal provided by the first power supply voltage terminal is transmitted to the gate of the driving transistor, i.e., the first node, after passing through the driving transistor and the threshold compensation module. This is equivalent to using the first power supply voltage signal from the first power supply voltage signal terminal to perform threshold compensation on the driving transistor. During the data writing stage, the data signal is written to the second node through the data writing module. It is evident that the threshold compensation stage and the data writing stage are two independent stages. The threshold compensation process is not affected by the duration of the data writing stage. Therefore, the problem of insufficient threshold compensation due to a short data writing duration is eliminated. When performing threshold compensation on the driving transistor using the first power supply voltage signal, the duration of the threshold compensation stage can be extended as needed, thereby ensuring sufficient threshold compensation for the driving transistor and avoiding inaccurate output signals of the pixel driving circuit due to insufficient threshold compensation of the driving transistor. This improves the accuracy of the driving signal transmitted from the pixel driving circuit to the light-emitting element, thus enhancing the display effect of the display product. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 shows a schematic diagram of a pixel driving circuit in the related technology;

[0018] Figure 2 shows a timing diagram of one operation of the pixel driving circuit in Figure 1;

[0019] Figure 3 shows a block diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0020] Figure 4 shows a timing diagram of one operation of the pixel driving circuit in Figure 3;

[0021] Figure 5 shows another timing diagram of the pixel driving circuit in Figure 3;

[0022] Figure 6 shows another block diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0023] Figure 7 shows another block diagram of the pixel driving circuit provided in the embodiments of this disclosure;

[0024] Figure 8 shows a schematic diagram of a pixel driving circuit corresponding to Figure 6.

[0025] Figure 9 shows a schematic diagram of a pixel driving circuit corresponding to Figure 7.

[0026] Figure 10 shows a schematic diagram of a pixel driving circuit corresponding to Figure 7.

[0027] Figure 11 shows the timing diagram corresponding to the pixel driving circuit in Figure 10;

[0028] Figure 12 shows a timing diagram of the pixel driving circuit in a holding frame provided in an embodiment of the present disclosure.

[0029] Figure 13 shows a schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure.

[0030] Figure 14 shows the driving timing diagram corresponding to the pixel driving circuit in Figure 13;

[0031] Figure 15 shows a schematic diagram of a pixel driving circuit provided in a disclosed embodiment;

[0032] Figure 16 shows the driving timing diagram corresponding to the pixel driving circuit in Figure 15;

[0033] Figure 17 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0034] Figure 18 shows the driving timing diagram corresponding to the pixel driving circuit in Figure 17;

[0035] Figure 19 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0036] Figure 20 shows the driving timing diagram corresponding to the pixel driving circuit in Figure 19;

[0037] Figure 21 shows another timing diagram of the pixel driving circuit in Figure 17;

[0038] Figure 22 shows another timing diagram of the pixel driving circuit in Figure 19;

[0039] Figure 23 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0040] Figure 24 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0041] Figure 25 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0042] Figure 26 shows the timing diagram corresponding to the pixel driving circuit in Figure 25;

[0043] Figure 27 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0044] Figure 28 shows the timing diagram corresponding to the pixel driving circuit in Figure 27;

[0045] Figure 29 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0046] Figure 30 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0047] Figure 31 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0048] Figure 32 shows another circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0049] Figure 33 shows a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0050] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0051] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0052] Figure 1 shows a schematic diagram of a pixel driving circuit in the related art, and Figure 2 shows a timing diagram of the pixel driving circuit in Figure 1. The pixel driving circuit 100 includes seven transistors M1 to M7 and a capacitor C. The pixel driving circuit includes three operating stages: an initialization stage t01, a data writing stage t02, and a light-emitting stage t03. In the initialization stage t01, transistors M5 and M7 are turned on, resetting the anodes of the first node N1 and the light-emitting element D0, respectively. In the data writing stage t02, transistors M2, M3, and M4 are turned on, writing data signals to the second node N2 and performing threshold compensation on the gates of the driving transistors through the data signals. At this time, the potential of the second node N2 is Vdata, and the potentials of the first node N1 and the third node N3 are Vdata-|Vth|. In the light-emitting stage t03, transistors M1, M3, and M6 are turned on. At this time, the voltage of the second node N2 becomes PVDD, and the voltage of the first node N1 remains at Vdata-|Vth|. At this time, the current transmitted to the light-emitting element D0 is I = K × (PVDD - Vdata + |Vth| - |Vth|). 2 =K×(PVDD-Vdata) 2 As can be seen, during the data writing stage, the data signal is used to perform threshold compensation on the gate of the driving transistor. The threshold compensation time is limited by the duration of the data writing stage. If the duration of the data writing stage is short, there may be insufficient threshold compensation, resulting in a difference between the driving signal output by the pixel driving circuit and the expected signal, which affects the display effect of the display panel.

[0053] To address the aforementioned problems, this disclosure provides a pixel driving circuit that eliminates the need for threshold compensation of the driving transistor's gate using data signals. This removes the impact of data writing duration on threshold compensation, allowing for a more thorough compensation process. Consequently, this improves the accuracy of the driving signal output by the pixel driving circuit, thereby enhancing display performance. The following will further illustrate this disclosure with reference to specific embodiments.

[0054] Figure 3 shows a block diagram of a pixel driving circuit provided in an embodiment of this disclosure. Referring to Figure 3, this embodiment of the disclosure provides a pixel driving circuit for electrical connection with a light-emitting element D0. The pixel driving circuit includes a driving transistor DT, a threshold compensation module 10, a data writing module 20, a first light-emitting control module 31, and a first capacitor C1. The gate of the driving transistor DT is connected to a first node N1, the first plate of the first capacitor C1 is connected to the first node N1, and the second plate of the first capacitor C1 is connected to a second node N2. The first electrode of the driving transistor DT is connected to a first power supply voltage terminal PVDD, and the second electrode of the driving transistor DT is connected to a third node N3. The first light-emitting control module 31 is connected between the third node N3 and a fourth node N4. The fourth node N4 is connected to the first electrode of the light-emitting element D0. The first light-emitting control module 31 is configured to be turned on during the light-emitting phase and transmit a driving signal to the light-emitting element D0. A threshold compensation module 10 is connected between the first node N1 and the third node N3. The threshold compensation module 10 includes an N-type transistor and is configured to provide a first power supply voltage signal from the first power supply voltage terminal PVDD to the gate of the driving transistor DT during the threshold compensation phase, thereby performing threshold compensation on the driving transistor DT. A data writing module 20 is connected between the data signal terminal Vdata and the second node N2. The data writing module 20 is configured to write the data signal provided by the data signal terminal Vdata to the second node N2 during the data writing phase.

[0055] In the pixel driving circuit provided in this embodiment, during the threshold compensation stage, the first power supply voltage signal provided by the first power supply voltage terminal PVDD is transmitted to the gate of the driving transistor DT, i.e., the first node N1, after passing through the driving transistor DT and the threshold compensation module 10. This is equivalent to using the first power supply voltage signal of the first power supply voltage terminal PVDD to perform threshold compensation on the driving transistor DT. During the data writing stage, the data signal is written to the second node N2 through the data writing module 20. It can be seen that the threshold compensation stage and the data writing stage are two independent stages. The threshold compensation process is not affected by the duration of the data writing stage. Therefore, the problem of insufficient threshold compensation due to a short data writing duration is eliminated. When performing threshold compensation on the driving transistor DT using the first power supply voltage signal, the duration of the threshold compensation stage can be extended as needed to ensure sufficient threshold compensation for the driving transistor DT. This avoids the problem of inaccurate output signal of the pixel driving circuit due to insufficient threshold compensation of the driving transistor DT, thereby improving the accuracy of the driving signal transmitted by the pixel driving circuit to the light-emitting element D0 and improving the display effect of the display product.

[0056] Furthermore, considering that the threshold compensation module 10 is directly electrically connected to the gate of the driving transistor DT, when the threshold compensation module 10 includes an N-type transistor, since the N-type transistor has the advantage of smaller leakage current, the leakage current from the threshold compensation module 10 to the gate of the driving transistor DT can be reduced, thereby reducing the influence of leakage current on the potential of the gate of the driving transistor DT and avoiding the problem of inaccurate driving signal output by the pixel driving circuit.

[0057] Figure 4 shows one timing diagram of the pixel driving circuit in Figure 3, and Figure 5 shows another timing diagram of the pixel driving circuit in Figure 3. In an optional embodiment of this disclosure, the start time of the threshold compensation stage is earlier than the start time of the data writing stage. Referring to Figures 3 to 5, the control signal Scan1 is a signal connected to the control terminal of the threshold compensation module 10. The effective level signal in the control signal Scan1 can control the threshold compensation module 10 to conduct, so that the first power supply voltage signal can be transmitted to the first node N1 through the driving transistor DT and the threshold compensation module 10 to realize the threshold compensation of the driving transistor DT. The control signal Scan2 is a signal connected to the control terminal of the data writing module 20. The effective level signal in the control signal Scan2 can control the data writing module 20 to conduct, so that the data signal at the data signal terminal is provided to the second node N2. In the timing diagrams shown in Figures 4 and 5, the moment when the control signal Scan1 transitions to a high level can be considered the start time of the threshold compensation stage, and the moment it transitions to a low level can be considered the end time of the threshold compensation stage; similarly, the moment when the control signal Scan2 transitions to a low level can be considered the start time of the data writing stage, and the moment it transitions to a high level can be considered the end time of the data writing stage. In this embodiment, the start time of the threshold compensation stage is earlier than the start time of the data writing stage. That is, threshold compensation can be performed on the driving transistor DT before data writing. Compared with the related art, which performs threshold compensation simultaneously with data writing, the solution of this disclosure is advantageous in extending the threshold compensation time, thereby achieving sufficient threshold compensation for the driving transistor DT, and thus improving the accuracy of the driving signal output by the pixel driving circuit.

[0058] Referring to Figure 4, in one optional embodiment of this disclosure, the start time of the data writing phase is earlier than the end time of the threshold compensation phase. This embodiment discloses a scheme where the start time of the data writing phase is earlier than the start time of the threshold compensation phase, the duration of the threshold compensation phase is longer than the duration of the data writing phase, and the data writing phase and the threshold compensation phase overlap. This is equivalent to performing data writing while threshold compensation has been performed for a period of time but is not yet complete. This design approach is beneficial for both extending the overall duration of the threshold compensation phase, ensuring the sufficiency of threshold compensation, and reducing the overall duration of the threshold compensation phase and the data writing phase, thereby improving the driving efficiency of the pixel driving circuit.

[0059] It should be noted that the embodiment shown in Figure 4 illustrates a scheme in which the start and end times of the data writing phase are both within the time period of the threshold compensation phase. In some other embodiments of this disclosure, when the start time of the data writing phase is before the end time of the threshold compensation phase, the end time of the data writing phase may coincide with the end time of the threshold compensation phase, or the end time of the data writing phase may be after the end time of the threshold compensation phase. This disclosure does not impose specific limitations on this.

[0060] Please refer to Figure 5. In one optional embodiment of this disclosure, the start time of the data writing stage is later than the end time of the threshold compensation stage. That is, data writing is performed after the threshold compensation process is completed. In this embodiment, the threshold compensation stage and the data writing stage are also two independent stages. The duration of the threshold compensation stage is not affected by the duration of the data writing stage. Therefore, it is also beneficial to ensure the sufficiency of threshold compensation and to improve the accuracy of the output signal of the pixel driving circuit.

[0061] Figures 6 and 7 show another block diagram of the pixel driving circuit provided in the embodiments of this disclosure. Referring to Figures 6 and 7, in an optional embodiment of this disclosure, the pixel driving circuit further includes a first reset module 41. The first reset module 41 is connected between the first reset signal terminal Vref1 and the second node N2. The first reset module 41 is configured to reset the second node N2 in the first reset phase.

[0062] In this embodiment, the first capacitor C1 is connected between the first node N1 and the second node N2. Due to the coupling effect of the first capacitor C1, the potential change of the second node N2 will be coupled to the first node N1. When the first reset module 41 is introduced between the first reset signal terminal and the second node N2, the first reset module 41 can be turned on in the first reset stage. The reset signal of the first reset signal terminal Vref1 is used to reset the second node N2, thereby pulling the potential of the first node N1 low, which can indirectly reset the first node N1. The first reset stage will be described in detail in subsequent embodiments with reference to the refined structure of Figures 6 and 7.

[0063] Figure 8 shows a schematic diagram of a pixel driving circuit corresponding to Figure 6. Referring to Figures 6 and 8, in an optional embodiment of this disclosure, the control terminal of the first reset module 41 and the control terminal of the first light-emitting control module 31 are connected to the same control signal terminal EM. Optionally, the first reset module 41 includes a first reset transistor T1, and the first light-emitting control module 31 includes a first light-emitting control transistor T4. The first reset transistor T1 and the first light-emitting control transistor T4 are transistors of the same type. This embodiment uses P-type transistors as an example, where P-type transistors turn on in response to a low-level control signal and turn off in response to a high-level control signal. However, this disclosure is not limited to this. In some other embodiments of this disclosure, the first reset transistor T1 and the first light-emitting control transistor T4 can also be N-type transistors, where N-type transistors turn on in response to a high-level control signal and turn off in response to a low-level control signal.

[0064] Please continue referring to Figures 6 and 8, and in conjunction with the timing shown in Figure 4, in this embodiment, the control terminals of the first reset module 41 and the first light-emitting control module 31 are connected to the same control signal terminal, such as the light-emitting control signal terminal EM. This eliminates the need to introduce different control signals for the first reset module 41 and the first light-emitting control module 31, simplifying circuit control. Optionally, the pixel driving circuit further includes a second reset module 42, connected between the second reset signal terminal Vref2 and the fourth node N4. The second reset module 42 is configured to reset at least the fourth node N4 during the second reset phase. In this embodiment, optionally, the second reset module 42 is configured to reset the fourth node N4, the third node N3, and the first node N1 during the second reset phase. Optionally, the second reset module 42 includes a second reset transistor T5. This embodiment uses a P-type transistor as an example, but it is not limited thereto. In some other embodiments of this disclosure, the second reset transistor T5 may also be an N-type transistor. To more clearly illustrate the contents of this disclosure, the signal terminals and the signals transmitted by the signal terminals are represented by the same reference numerals. In the first reset phase, the control signal Scan1 is high, controlling the threshold compensation transistor T2 in the threshold compensation module 10 to conduct; the light emission control signal EM is low, controlling the first reset transistor T1 and the first light emission control transistor T4 to conduct; the control signal SPX is low, controlling the second reset transistor T5 in the second reset module 42 to conduct. In the first reset phase, the reset signal from the first reset signal terminal Vref1 is transmitted to the second node N2 to reset the second node N2. Simultaneously, the reset signal from the second reset signal terminal Vref2 is transmitted through the second reset transistor T5 to the fourth node N4, through the first light emission control module 31 to the third node N3, and further through the threshold compensation module 10 to the first node N1, thereby achieving the reset of the fourth node N4, the third node N3, and the first node N1. In this way, the first node N1, the second node N2, the third node N3 and the fourth node N4 are reset simultaneously in one reset phase, which helps to simplify the overall control timing of the pixel driving circuit.

[0065] The following will explain the operation of the circuit structure shown in Figure 8 in conjunction with the timing diagram shown in Figure 4.

[0066] In the first stage t1, the control signal Scan1 is high, the light emission control signal EM and the control signal SPX are low, and the threshold compensation transistor T2, the first reset transistor T1, the first light emission control transistor T4 and the second reset transistor T5 are all turned on. The reset signal of the first reset signal terminal Vref1 resets the second node N2, and the reset signal of the second reset signal terminal Vref2 resets the fourth node N4, the third node N3 and the first node N1 respectively. At this time, the potential of the second node N2 is Vref1 and the potential of the first node N1 is Vref2.

[0067] In the second stage t2, the light emission control signal EM goes high, the first light emission control transistor T4 and the first reset transistor T1 are turned off, the control signal Scan1 remains high, the control signal SPX remains low, the threshold compensation transistor T2 and the second reset transistor T5 remain on, the reset signal at the second reset signal terminal Vref2 continues to reset the fourth node N4, and the first power supply voltage signal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0068] In the third stage t3, the control signal Scan1 remains high and the control signal SPX remains low, continuing to reset the fourth node N4 and perform threshold compensation on the driving transistor DT. Simultaneously, the control signal Scan2 goes low, and the data signal Vdata is transmitted to the second node N2 for data writing. The potential of the second node N2 is Vdata. At this time, the threshold compensation transistor T2 is still conducting, and the potential of the first node N1 is PVDD-|Vth|. This avoids the potential of the second node N2 affecting the potential of the first node N1, ensuring the accuracy of the circuit output in the subsequent light-emitting stage. In the timing diagram shown in Figure 4, after the data writing period, i.e., after the third stage t3 ends, the control signal Scan1 remains high for a period of time, continuously performing threshold compensation on the driving transistor DT. This helps to extend the threshold compensation time and ensure the sufficiency of the threshold compensation. It should be noted that the circuit shown in Figure 8 is illustrated using a P-type transistor as an example of the data writing transistor T3 in the data writing module 20. The transistor is turned on when the control signal Scan2 is a low-level signal. In some other embodiments of this disclosure, the data writing transistor T3 can also be an N-type transistor. The data writing transistor T3 is turned on when the control signal Scan2 is a high-level signal. The level of the control signal Scan2 can be adjusted based on the timing shown in Figure 4. This disclosure will not elaborate further on this.

[0069] In the fourth stage t4, control signal Scan1 goes low, control signals SPX and Scan2 go high, and the light-emitting control signal EM goes low. Threshold compensation transistor T2, first reset transistor T1, and second reset transistor T5 are all turned off, and first light-emitting control transistor T4 turns on. The signal from the first power supply voltage terminal PVDD is transmitted to the driving transistor DT, generating a driving current that is transmitted to the light-emitting element D0, driving D0 to emit light. During the light-emitting stage, the first reset transistor T1 turns on, and the potential of the second node N2 changes from Vdata to Vref1. Due to the coupling effect of the first capacitor C1, the potential of the first node N1 becomes PVDD - |Vth| + Vref1 - Vdata. At this time, the current sent to the light-emitting element D0 is I = K × (PVDD - |Vth| - PVDD + |Vth| - Vref1 + Vdata). 2 =K×(Vdata-Vref1) 2 .

[0070] It should be noted that the first reset stage mentioned in the aforementioned embodiments can be regarded as the stage in which the first reset transistor T1 is turned on, corresponding to the first stage t1 mentioned above. The second reset stage can be regarded as the stage in which the second reset transistor T5 is turned on, corresponding to the period when the control signal SPX is at a low level. The threshold compensation stage mentioned above can be regarded as the stage in which the threshold compensation transistor T2 is turned on, corresponding to the period when the control signal Scan1 is at a high level. Optionally, the start time of the second reset stage coincides with the start time of the first reset stage. Corresponding to the timing shown in Figure 4, the start time of the second reset stage and the start time of the first reset stage are both located at the start time of the first stage t1 mentioned above. This design can realize the simultaneous reset of the first node N1, the second node N2, the third node N3 and the fourth node N4, which is beneficial to simplify the control process of the pixel driving circuit.

[0071] Optionally, referring to Figure 8, the pixel driving circuit further includes a second capacitor C2. The two plates of the second capacitor C2 are respectively connected to the first power supply voltage terminal PVDD and the second node N2. Since the signal at the first power supply voltage terminal PVDD is a fixed potential signal, when the first power supply voltage terminal PVDD and the second node N2 are connected through the second capacitor C2, the coupling effect of the second capacitor C2 can stabilize the potential of the second node N2, preventing the potential of the second node N2 from drifting and affecting the potential of the first node N1. This helps to improve the stability of the potential of the first node N1, and thus helps to improve the stability of the driving signal output by the pixel driving circuit. It should be noted that the second capacitor C2 in subsequent embodiments has the same function, and the similarities will not be described again.

[0072] The above embodiments are illustrated using the example that both the first reset transistor T1 and the first light-emitting control transistor T4 are P-type transistors. In some other embodiments of this disclosure, the first reset transistor T1 may also be an N-type transistor. For example, please refer to Figure 9, which shows a circuit diagram of the pixel driving circuit corresponding to Figure 7. In an optional embodiment of this disclosure, the first reset module 41 includes an N-type transistor, and the control terminal of the first reset module 41 and the control terminal of the threshold compensation module 10 are connected to the same control signal terminal Scan1.

[0073] Specifically, this embodiment shows a scheme in which the first reset transistor T1 is set as an N-type transistor. Considering that the threshold compensation transistor T2 is also an N-type transistor, and both respond to the same signal to turn on or off, this embodiment connects the control terminals of the first reset transistor T1 and the threshold compensation transistor T2 to the same control signal terminal Scan1. In this way, there is no need to introduce other control signal terminals separately for the first reset module 41, which helps to simplify the overall structure of the pixel driving circuit.

[0074] Please continue to refer to Figure 9. In one optional embodiment of this disclosure, the pixel driving circuit further includes a second reset module 42. The second reset module 42 is connected between the second reset signal terminal Vref2 and the fourth node N4. The second reset module 42 is configured to reset at least the fourth node N4 during the second reset phase so that the anode of the light-emitting element D0 can be restored to the initial state before each emission. When the driving signal is received, the light-emitting element D0 can respond to the driving signal and emit light accurately, thereby improving the accuracy of the light emission brightness of the light-emitting element D0.

[0075] The operation of the pixel driving circuit shown in Figure 9 will be explained below with reference to the timing shown in Figure 5.

[0076] In the first stage t1, the control signals Scan1, Scan2 and the light emission control signal EM are all at high level. The first reset transistor T1 and the threshold compensation transistor T2 are turned on, the data writing transistor T3 is turned off, the reset signal of the first reset signal terminal Vref1 is transmitted to the second node N2 to reset the second node N2, and the signal of the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0077] In the second stage t2, corresponding to the second reset stage, the control signal SPX is low, resetting the anode of the fourth node N4, i.e., the light-emitting element D0. The start time of the control signal SPX is after the start time of the control signal Scan1 and before the end time. This embodiment uses a scheme where the effective level signals of the control signal SPX and Scan1 overlap as an example for illustration. In some other embodiments of this disclosure, the effective level signals of the control signal SPX may also be within the effective level signal range of the control signal Scan1, and this disclosure does not specifically limit this.

[0078] In the third stage t3, the control signal Scan1 goes low and the control signal Scan2 goes low. The data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal terminal is transmitted to the second node N2.

[0079] In the fourth stage t3, the control signal Scan1 remains at a low level, while the control signals Scan2 and SPX become high. The first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, and the second reset transistor T5 are all turned off. The light emission control signal EM becomes low, and the first light emission control transistor T4 is turned on. A current path is formed between the first power supply voltage terminal PVDD and the cathode of the light emission element D0, driving the light emission element D0 to emit light.

[0080] The above embodiment uses a P-type transistor as an example to illustrate the data writing module 20. In an optional embodiment of this disclosure, the data writing module 20 includes an N-type transistor. For example, please refer to Figure 10, which shows a circuit diagram of the pixel driving circuit corresponding to Figure 7. The difference between Figure 10 and Figure 9 is that the type of data writing transistor T3 is different. Figure 11 shows a timing diagram corresponding to the pixel driving circuit in Figure 10. The difference between Figure 11 and Figure 5 is that the control signal Scan2 is different. When the data writing transistor T3 is an N-type transistor, in the aforementioned third stage t3, the control signal Scan2 becomes a high-level signal, controlling the data writing transistor T3 to conduct and write the data signal to the second node N2. The working process of other stages can be referred to Figures 9 and 5, and will not be described again in this embodiment. Since N-type transistors have the advantage of low leakage current, when the data writing transistor T3 is set as an N-type transistor, it is beneficial to reduce or avoid the influence of the leakage current of the data writing transistor T3 on the potential of the second node N2. In turn, it is possible to reduce or avoid the influence of the leakage current coupled to the first node N1 on the potential of the first node N1, thereby improving the output accuracy of the pixel driving circuit.

[0081] Figure 12 shows a timing diagram of the pixel driving circuit in a holding frame provided in an embodiment of this disclosure. The timing diagrams corresponding to Figures 4, 5 and 11 are the timing diagrams of the pixel driving circuit in a writing frame. In an optional embodiment of this disclosure, the working process of the pixel driving circuit includes a writing frame and a holding frame. The writing frame includes the aforementioned threshold compensation stage, data writing stage, first reset stage and second reset stage. The holding frame includes a third reset stage tb. Referring to Figures 8, 9, 10 and 12, the second reset module 42 is also configured to reset the fourth node N4 in the third reset stage. The third reset stage tb is located in the cutoff period of the first light emission control module 31.

[0082] Referring to Figures 8, 9, 10, and 12, during the hold frame, the first reset transistor T1, threshold compensation transistor T2, and data write transistor T3 are all off. When the light emission control signal is low, the drive signal is transmitted to the light-emitting element D0. When the light emission control signal is high, the first light emission control module 31 is off. During the period when the light emission control signal is high, the control signal SPX transmits an effective level signal, controlling the second reset transistor T5 to conduct, resetting the anode of the light-emitting element D0, so that the light-emitting element D0 is in its initial state before each light emission. It should be noted that during the hold frame, the effective level signal of the control signal SPX is within the range of the ineffective level signal of the light emission control signal EM, that is, the control signal SPX does not exceed the ineffective level signal range of the light emission control signal EM. For the circuit structure shown in Figure 8, during the hold frame, when the effective level signal of the control signal SPX overlaps with the effective level signal of the light emission control signal, a large current may exist between the first power supply voltage terminal PVDD and the second reset signal terminal Vref2, which may cause the transistors in the corresponding path to be burned. Therefore, keeping the third reset phase within the period corresponding to the invalid level of the light emission control signal in the holding frame helps to avoid the risk of transistor burn-out due to the above reasons.

[0083] Considering the embodiments corresponding to Figures 8 and 4, in the first stage t1 corresponding to the write frame, the effective level signal of the control signal SPX and the effective level signal of the light emission control signal overlap. To reduce the risk of transistor burn-out, the overlap duration of the effective level signals of the control signal SPX and the light emission control signal can be minimized. Optionally, the duration of the first stage t1 is the duration required to scan one row of pixels. The shorter the duration of the first stage t1, the fewer pixels will be reset simultaneously, and the smaller the current from the first power supply voltage terminal PVDD to the second reset signal terminal Vref2 will be, thus reducing the risk of transistor burn-out. In some other embodiments of this disclosure, the current from the first power supply voltage terminal PVDD to the second reset signal terminal Vref2 can also be reduced by widening the line width of the reset signal line connected to the second reset signal terminal Vref2. For example, the line width of the reset signal line connected to the second reset signal terminal Vref2 can be made larger than the line width of the reset signal line connected to the first reset signal terminal Vref1. When the line width of the signal line is increased, the transistor is less likely to be burned out when the same current passes through.

[0084] Figure 13 shows a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure. Figure 14 shows a driving timing diagram corresponding to the pixel driving circuit in Figure 13. Figure 15 shows a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure. Figure 16 shows a driving timing diagram corresponding to the pixel driving circuit in Figure 15. Please refer to Figures 13 and 14, as well as Figures 15 and 16. In an optional embodiment of this disclosure, the pixel driving circuit 00 further includes a third reset module 43. The third reset module 43 is connected between the third reset signal terminal Vref0 and the first node N1. The third reset module 43 is configured to reset the first node N1 during the first node reset phase. The first node reset phase is executed before the threshold compensation phase, and the first node reset phase and the threshold compensation phase do not overlap.

[0085] This embodiment shows the introduction of a third reset module 43 in the pixel driving circuit, which is specifically used to reset the first node N1. Before the threshold compensation stage, the first node N1 is reset by the third reset module 43. During the first node reset stage, no current path is formed between the first power supply voltage terminal PVDD and the second reset signal terminal Vref2. Therefore, the method of introducing the third reset module 43 to reset the first node N1 separately helps to avoid the formation of a large current between the first power supply voltage terminal PVDD and the second reset signal terminal, which could burn out the transistor.

[0086] The operation of the pixel driving circuit in Figure 13 will be explained below with reference to the timing shown in Figure 14. Optionally, the third reset module 43 includes an N-type transistor. Since the third reset transistor T9 is directly electrically connected to the first node N1, when the third reset transistor T9 is an N-type transistor, it is beneficial to reduce the leakage current from the third reset transistor T9 to the first node N1, which is beneficial to improve the stability of the potential of the first node N1. The first reset transistor T1 in the first reset module 41 and the first light-emitting control transistor T4 in the first light-emitting control module 41 are both P-type transistors, and their control terminals are connected to the same control signal terminal EM.

[0087] During the first node reset phase t11, the control signal terminal Scan0 is at a high level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal is transmitted to the first node N1 to reset the first node N1.

[0088] During the fourth node reset phase t12, the control signal SPX is low, the second reset transistor T5 is turned on, and the reset signal at the second reset signal terminal Vref2 is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0. Optionally, the first node reset phase t11 and the fourth node reset phase t12 overlap.

[0089] In the first stage t1, the control signal Scan1 goes high, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, and the signal at the first reset signal terminal Vref1 resets the second node N2. The signal at the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT. During the threshold compensation period, the data stage t13 is executed, the control signal Scan2 goes low, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal terminal is transmitted to the second node N2. That is to say, the data writing process is located during the threshold compensation period.

[0090] In the second stage t2, the control signal Scan1 is at a low level, and the control signals Scan2 and SPX become high level. The first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, and the second reset transistor T5 are all turned off. The light emission control signal EM becomes low level, the first light emission control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light emission element D0, driving the light emission element D0 to emit light.

[0091] The operation of the pixel driving circuit in Figure 15 will be explained below with reference to the timing shown in Figure 16.

[0092] During the first node reset phase t11, the control signal terminal Scan0 is at a high level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1.

[0093] During the fourth node reset phase t12, the control signal SPX is low, the second reset transistor T5 is turned on, and the reset signal from the second reset signal terminal is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0. Optionally, the fourth node reset phase t12 overlaps with the first node reset phase t11.

[0094] In the first stage t1, the control signal Scan1 goes high, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal at the first reset signal terminal resets the second node N2, and the signal at the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0095] In the second stage t2, control signal Scan1 goes low, control signal Scan2 goes low, and data writing transistor T3 in data writing module 20 is turned on, transmitting the signal from the data signal terminal to the second node N2. In this embodiment, the threshold compensation process and the data writing process are separate and do not overlap.

[0096] In the third stage t3, the control signal Scan1 is low, and the control signals Scan2 and SPX become high. The first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, and the second reset transistor T5 are all turned off. The light emission control signal EM becomes low, the first light emission control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light emission element D0, driving the light emission element D0 to emit light.

[0097] Optionally, in the embodiments shown in Figures 13 and 15, the third reset module 43 includes an N-type transistor. Since the third reset transistor T9 is directly electrically connected to the first node N1, when the third reset transistor T9 is an N-type transistor, it is beneficial to reduce the leakage current from the third reset transistor T9 to the first node N1, which is beneficial to improve the stability of the potential of the first node N1.

[0098] Figure 17 shows another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 18 shows a driving timing diagram corresponding to the pixel driving circuit in Figure 17. Figure 19 shows another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 20 shows a driving timing diagram corresponding to the pixel driving circuit in Figure 19. The difference between Figure 17 and Figure 13 is that the signal connected to the control terminal of the third reset module 43 is different, and the type of the third reset transistor T9 is different. The difference between Figure 19 and Figure 15 is that the signal connected to the control terminal of the third reset module 43 is different, and the type of the third reset transistor T9 is different. In the embodiments shown in Figures 17 and 19, the third reset transistor T9 is a P-type transistor. Referring to Figures 17 and 18, and Figures 19 and 20, in one optional embodiment of this disclosure, the pixel driving circuit includes a third reset module 43 and a second reset module 42. The third reset module 43 is connected between the third reset signal terminal Vref0 and the first node N1. The third reset module 43 is configured to reset the first node N1 during the first node reset phase. The first node reset phase is executed before the threshold compensation phase, and the first node reset phase and the threshold compensation phase do not overlap. The second reset module 42 is connected between the second reset signal terminal and the fourth node N4. The control terminal of the third reset module 43 and the control terminal of the second reset module 42 are connected to the same control signal terminal.

[0099] In this embodiment, the third reset transistor T9 and the second reset transistor T5 are both shown. This embodiment illustrates a scheme in which, when the third reset module 43 is introduced into the pixel driving circuit to reset the first node N1, the control terminal of the third reset module 43 and the control terminal of the second reset module 42 that resets the fourth node N4 are connected to the same control terminal SPX. That is, the process of resetting the first node N1 and the process of resetting the anode of the light-emitting element D0 are performed simultaneously. In this way, there is no need to introduce a separate control signal for the third reset module 43, which helps to simplify the overall design of the pixel driving circuit.

[0100] The following will explain the operation of the pixel driving circuit in Figure 17 with reference to Figures 17 and 18.

[0101] During the reset phase t21, the control signal terminal Scan0 is at a low level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1; the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal Vref2 is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0.

[0102] In the first stage t1, the control signal Scan1 goes high, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, and the signal at the first reset signal terminal resets the second node N2. The signal at the first power supply voltage terminal PVDD is transmitted to the first node N1 through the drive transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the drive transistor DT. During the threshold compensation period, the control signal Scan2 goes low, the data writing transistor T3 in the data writing module 20 is turned on, and the signal at the data signal terminal is transmitted to the second node N2.

[0103] In the second stage t2, the control signal Scan1 is at a low level, and the control signals Scan2 and SPX become high level. The first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, and the second reset transistor T5 are all turned off. The light emission control signal EM becomes low level, the first light emission control transistor is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light emission element D0, driving the light emission element D0 to emit light.

[0104] The operation of the pixel driving circuit in Figure 19 will be explained below with reference to Figures 19 and 20.

[0105] During the reset phase t21, the control signal terminal Scan0 is at a low level, the third reset transistor T9 is turned on, and the reset signal of the third reset signal terminal Vref0 is transmitted to the first node N1 to reset the first node N1; the control signal SPX is at a low level, the second reset transistor T5 is turned on, and the reset signal of the second reset signal terminal is transmitted to the fourth node N4 to reset the anode of the light-emitting element D0.

[0106] In the first stage t1, the control signal Scan1 goes high, the first reset transistor T1 and the threshold compensation transistor T2 are turned on, the signal at the first reset signal terminal resets the second node N2, and the signal at the first power supply voltage terminal PVDD is transmitted to the first node N1 through the driving transistor DT and the threshold compensation transistor T2 to perform threshold compensation on the driving transistor DT.

[0107] In the second stage t2, control signal Scan1 goes low and control signal Scan2 goes low. Data writing transistor T3 in data writing module 20 is turned on, and the signal from the data signal terminal is transmitted to the second node N2.

[0108] In the third stage t3, the control signal Scan1 is low, and the control signals Scan2 and SPX become high. The first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, and the second reset transistor T5 are all turned off. The light emission control signal EM becomes low, the first light emission control transistor T4 is turned on, and a current path is formed between the first power supply voltage terminal PVDD and the cathode of the light emission element D0, driving the light emission element D0 to emit light.

[0109] Figure 21 shows another working timing diagram of the pixel driving circuit in Figure 17. The difference from the timing diagram in Figure 17 is that the control signal of the third reset module 43 does not reuse the control signal of the second reset module 42. Figure 22 shows another working timing diagram of the pixel driving circuit in Figure 19. The difference from the timing diagram in Figure 19 is that the control signal of the third reset module 43 does not reuse the control signal of the second reset module 42. Please refer to Figures 21 and 22. In an optional embodiment of this disclosure, the pixel driving circuit is connected to a cascaded shift register. The control terminal of the third reset module 43 in the Nth row of the pixel driving circuit is connected to the output terminal of the Nth stage shift register. The output terminal of the Nth stage shift register is connected to the control terminal of the data writing module 20 in the Nmth row of the pixel driving circuit. Here, N and m are both integers, and 1≤m<N, N≥2.

[0110] This embodiment uses the example of the third reset transistor T9 in the third reset module 43 and the data writing transistor T3 in the data writing module 20 being the same type of transistor, specifically assuming both are P-type transistors. In this embodiment, the control signal terminals of each pixel driving circuit are provided by shift registers. For example, in a set of cascaded shift registers, one bit of the register in the first stage is connected to the control terminal of the data writing transistor in the first row of pixel driving circuits, one bit of the register in the second stage is connected to the control terminal of the data writing transistor in the second row of pixel driving circuits, and so on. The control signal output by the aforementioned shift register is the control signal Scan2 mentioned in this embodiment. The control signal Scan2 includes multiple valid pulse signals. For example, the first row of pixel driving circuits corresponds to the first valid pulse signal, the second row of pixel driving circuits corresponds to the second valid pulse signal, and so on. It should be noted that the specific structure of the shift register can be referred to related technologies, and this disclosure does not specifically limit it. In this embodiment, the control signal received by the third reset transistor T9 is multiplexed with the effective pulse signals of the first few stages of the control signal Scan2 corresponding to the data writing transistor T3. When m=1, the control signal of the third reset transistor T9 in the current row corresponds to the same effective pulse as the control signal of the data writing transistor T3 in the previous row. That is, while writing data to the pixel driving circuit of the previous row, the first node in the pixel driving circuit of the current row is reset using the third reset module 43. In this way, the control terminals of the third reset transistor T9 and the data writing transistor T3 can be connected to the same set of gate driving circuits, which helps to simplify the overall design of display products that include the pixel driving circuit in this embodiment.

[0111] Figure 23 shows another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. The difference from Figure 13 is the addition of a bias module 60. Figure 24 shows another schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. The difference from Figure 15 is the addition of a bias module 60. Referring to Figures 23 and 24, in an optional embodiment of this disclosure, the pixel driving circuit 00 further includes a bias module 60. The bias module 60 is connected between the bias signal terminal and the first terminal of the driving transistor DT, or the bias module 60 is connected between the bias signal terminal and the second terminal of the driving transistor DT. The embodiment shown in Figure 23 is illustrated by the bias module 60 being connected to the third node N3, i.e., the second terminal of the driving transistor DT. The embodiment shown in Figure 24 is illustrated by the bias module 60 being connected to the first terminal of the driving transistor D. The computer is not limited to this. The bias module 60 is configured to adjust the bias state of the driving transistor DT during the bias adjustment phase. The control terminal of the bias module 60 and the control terminal of the third reset module 43 are connected to the same control signal terminal Scan0. The bias adjustment phase coincides with the first node reset phase.

[0112] When both the bias module 60 and the third reset module 43 exist in the pixel driving circuit, optionally, the bias transistor T8 in the bias module 60 and the third reset transistor T9 in the third reset module 43 are transistors of the same type. In this case, the control terminal of the third reset transistor T9 and the control terminal of the bias transistor T8 can be connected to the same control signal terminal Scan0. Similarly, there is no need to introduce a separate control signal terminal for the third reset transistor T9, which helps to simplify the overall structure of the pixel driving circuit. When the control terminal of the third reset transistor T9 and the control terminal of the bias transistor T8 are connected to the same control signal terminal Scan0, the process of resetting the first node N1 and the stage of adjusting the bias state of the driving transistor DT overlap, and both can be performed before the threshold compensation stage. For the specific processes of the threshold compensation stage, data writing stage, and light emission stage, please refer to the embodiments shown in Figure 14 or Figure 16, which will not be described in detail in this embodiment.

[0113] It should be noted that when the pixel driving circuit includes the third reset module 43, the second reset module 42 and the bias module 60, the transistors in the three modules can be set to the same type, and the control terminals of the three modules can be connected to the same control signal terminal, so that the reset process of the first node N1, the reset process of the fourth node N4 and the bias voltage adjustment process overlap, which is also beneficial to simplify the overall control and timing of the pixel driving circuit.

[0114] Figure 25 shows another schematic diagram of the pixel driving circuit provided in this embodiment. Figure 26 shows a timing diagram corresponding to the pixel driving circuit in Figure 25. The difference between Figure 26 and Figure 27 is that the type of data writing transistor T3 is different. Figure 26 uses an N-type transistor as an example for illustration. Figure 27 shows another schematic diagram of the pixel driving circuit provided in this embodiment. Figure 28 shows a timing diagram corresponding to the pixel driving circuit in Figure 27. The difference between Figure 28 and Figure 29 is that the type of data writing transistor T3 is different. Figure 28 uses an N-type transistor as an example for illustration. When the data writing transistor T3 is an N-type transistor, it is turned on when the control signal Scan2 is high. Other working processes are the same as in Figures 23 and 24, and the similarities will not be repeated in this embodiment. When the data writing transistor T3 is an N-type transistor, it is beneficial to reduce the leakage current of the data writing transistor T3 to the second node N2, thereby reducing the influence of the leakage current of the second node N2 on the potential of the first node N1, thus improving the overall output accuracy of the pixel driving circuit. The operation of the pixel driving circuit in Figure 25 can be referred to the embodiment shown in Figure 23, and the operation of the pixel driving circuit in Figure 27 can be referred to the embodiment shown in Figure 24. The similarities will not be repeated here.

[0115] Please continue to refer to Figures 13 and 15. In one optional embodiment of this disclosure, the pixel driving circuit further includes a second light-emitting control module 32 and a first switch control module 50. The second light-emitting control module 32 is connected between the first power supply voltage terminal PVDD and the first terminal of the driving transistor DT, and the first switch control module 50 is connected between the first power supply voltage terminal PVDD and the first terminal of the driving transistor DT. The control terminal of the second light-emitting control module 32 is connected to the same control signal terminal EM as the control terminal of the first light-emitting control module 31, and the control terminal of the first switch control module 50 is connected to the same control signal terminal Scan1 as the control terminal of the threshold compensation module 10. The first switch control module 50 is configured to be turned on during the threshold compensation stage, and the second light-emitting control module 32 is configured to be turned on during the light-emitting stage.

[0116] In this embodiment, the second light-emitting control transistor T6 included in the second light-emitting control module 32 is of the same type as the first light-emitting control transistor T4 included in the first light-emitting control module 31. Their control terminals are connected to the same light-emitting control signal terminal EM. This embodiment uses the example where both the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are P-type transistors. The switch control transistor T7 included in the first switch control module 50 is of a different type than the second light-emitting control transistor T6. This embodiment uses the example where the switch control transistor T7 is of the same type as the threshold compensation transistor T2. In this embodiment, both are N-type transistors, and their control terminals are connected to the control signal Scan1. During the threshold compensation stage, the control signal Scan1 controls the switch control transistor T7 and the threshold compensation transistor T2 to conduct, while the second switch control transistor T6 is turned off. Thus, the first power supply voltage signal PVDD can also be used to perform threshold compensation on the driving transistor DT. During the light-emitting phase, the light-emitting control signal EM controls the first light-emitting control transistor T4 and the second light-emitting control transistor T6 to turn on, while the switch control transistor T7 turns off. This creates a current path between the first power supply voltage terminal PVDD and the cathode of the light-emitting element D0, driving the light-emitting element D0 to emit light. By introducing the second light-emitting control module 32 and the first switch control module 50, time-division multiplexing of the first power supply voltage signal is achieved.

[0117] Furthermore, when the second light-emitting control module 32 and the first switch control module 50 are introduced into the pixel driving circuit, a bias module 60 may also be included. For example, please refer to Figures 23 and 24. The bias module 60 is used to transmit the bias signal to the first or second terminal of the driving transistor DT during the bias adjustment stage. The bias adjustment stage is not connected to the threshold compensation stage and the light-emitting stage. Thus, during the bias adjustment stage, both the second light-emitting control transistor T6 and the switch control transistor T7 are in the off state. A large current path will not be formed between the first power supply voltage terminal PVDD and the bias signal terminal, which helps to avoid the phenomenon of burning the driving transistor DT due to the formation of a large current path.

[0118] Figures 29 and 30 show alternative circuit diagrams of the pixel driving circuit provided in this disclosure, respectively, which are based on the embodiments shown in Figures 8 and 9, with the addition of a bias module 60. That is, even if the pixel driving circuit does not include the third reset module, it can still include the bias module 60. Referring to Figures 29 and 30, in an optional embodiment of this disclosure, the pixel driving circuit further includes the bias module 60. The bias module 60 is connected between the bias signal terminal and the first terminal of the driving transistor DT, or the bias module 60 is connected between the bias signal terminal and the second terminal of the driving transistor DT. The bias module 60 is configured to adjust the bias state of the driving transistor DT during the bias adjustment phase. By introducing the bias module 60 to adjust the bias state of the driving transistor DT, ghosting and first frame brightness can be effectively improved, enhancing the overall display effect.

[0119] Figures 31 and 32 respectively show another circuit diagram of the pixel driving circuit provided in the embodiments of this disclosure. The difference between Figure 31 and Figure 29 is that the control signal connected to the control terminal of the bias module is different, and the difference between Figure 32 and Figure 30 is that the control signal connected to the control terminal of the bias module is different. Referring to Figure 31, in an optional embodiment of this disclosure, the pixel driving circuit further includes a second reset module 42, which is connected between the second reset signal terminal and the fourth node N4. The control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal terminal SPX. That is, the control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal, eliminating the need to introduce a new control signal for the bias module 60, which simplifies the overall design of the pixel driving circuit. In this embodiment, the bias adjustment stage and the process of resetting the fourth node N4 can be performed simultaneously. In an optional embodiment of this disclosure, the working process of the pixel driving circuit includes writing frames and holding frames, and the holding frame includes the bias adjustment stage. It should be noted that when the control terminal of the bias module 60 and the control terminal of the second reset module 42 are connected to the same control signal segment SPX, the reset process of the fourth node N4 and the bias state adjustment process can also be performed in the holding frame, which is also beneficial to improving the display effect. It should also be noted that in some other embodiments of this disclosure, a new control signal can be introduced separately for the bias module 60. In this case, the bias state adjustment can also be performed in both the write frame and the holding frame, which is beneficial to improving the overall display effect.

[0120] Of course, in some other embodiments of this disclosure, please refer to FIG32. The control terminal of the bias module 60 can also be connected to the same control signal terminal Scan2 as the control terminal of the data writing module 20. The bias transistor T8 in the bias module 60 and the data writing transistor T3 in the data writing module 20 are of the same type. In this way, the bias state adjustment process and the data writing process are performed simultaneously. Similarly, there is no need to introduce a new control signal for the bias module 60 separately, which is beneficial to simplifying the overall design of the pixel driving circuit.

[0121] Based on the same technical concept, this disclosure also provides a display device. Figure 33 shows a schematic diagram of a display device provided in an embodiment of this disclosure. Referring to Figure 33, the display device 200 includes the pixel driving circuit 00 in any of the above embodiments. The display device 200 provided in the embodiments of this disclosure can be any electronic device with display function, such as a tablet computer, display cabinet display product, television, or vehicle display device. The display device 200 provided in the embodiments of this disclosure has the beneficial effects of the pixel driving circuit 00 provided in the embodiments of this disclosure. For details, please refer to the specific descriptions of the pixel driving circuit 00 in the above embodiments, which will not be repeated here.

[0122] It is understood that Figure 33 only illustrates the display device with a rectangular structure. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it in this regard.

[0123] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0124] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel driving circuit for electrically connecting with a light emitting element, comprising a driving transistor, a threshold compensation module, a data writing module, a first light emitting control module and a first capacitor, wherein, The gate of the driving transistor is connected to the first node, the first plate of the first capacitor is connected to the first node, and the second plate is connected to the second node; the first terminal of the driving transistor is connected to the first power supply voltage terminal, and the second terminal of the driving transistor is connected to the third node. The first light-emitting control module is connected between the third node and the fourth node, the fourth node is connected to the light-emitting element, and the first light-emitting control module is configured to be turned on during the light-emitting phase and transmit a driving signal to the light-emitting element. The threshold compensation module is connected between the first node and the third node. The threshold compensation module includes an N-type transistor. The threshold compensation module is configured to provide a first power supply voltage signal provided by the first power supply voltage terminal to the gate of the driving transistor during the threshold compensation stage, so as to perform threshold compensation on the driving transistor. The data writing module is connected between the data signal terminal and the second node, and the data writing module is configured to write the data signal provided by the data signal terminal to the second node during the data writing phase.

2. The pixel driving circuit according to claim 1, wherein The threshold compensation phase starts earlier than the data writing phase.

3. The pixel driving circuit of claim 2, wherein, The start time of the data writing phase is earlier than the end time of the threshold compensation phase.

4. The pixel driving circuit of claim 2, wherein, The start time of the data writing phase is later than the end time of the threshold compensation phase.

5. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further includes a first reset module, which is connected between the first reset signal terminal and the second node. The first reset module is configured to reset the second node during a first reset phase.

6. The pixel driving circuit of claim 5, wherein, The control terminal of the first reset module and the control terminal of the first light-emitting control module are connected to the same control signal terminal.

7. The pixel driving circuit of claim 5, wherein, The first reset module includes an N-type transistor, and the control terminal of the first reset module is connected to the same control signal terminal as the control terminal of the threshold compensation module.

8. The pixel driving circuit of claim 5, wherein, The pixel driving circuit further includes a second reset module, which is connected between the second reset signal terminal and the fourth node. The second reset module is configured to reset at least the fourth node during the second reset phase.

9. The pixel driving circuit of claim 8, wherein, The second reset module is configured to reset the fourth node, the third node, and the first node during the second reset phase.

10. The pixel driving circuit of claim 8, wherein, The start time of the second reset phase coincides with the start time of the first reset phase.

11. The pixel driving circuit of claim 8, wherein, The operation of the pixel driving circuit includes a write frame and a hold frame. The write frame includes the threshold compensation stage, the data writing stage, the first reset stage, and the second reset stage. The hold frame includes a third reset stage. The second reset module is also configured to reset the fourth node in the third reset stage. The third reset stage is located during the cutoff period of the first light emission control module.

12. The pixel driving circuit of claim 1, wherein, The data writing module includes an N-type transistor.

13. The pixel driving circuit of claim 1, wherein, It also includes a third reset module, which is connected between the third reset signal terminal and the first node, and is configured to reset the first node during the first node reset phase. The first node reset phase is executed before the threshold compensation phase, and the first node reset phase and the threshold compensation phase do not overlap.

14. The pixel driving circuit of claim 13, wherein, It also includes a second reset module, which is connected between the second reset signal terminal and the fourth node; The control terminal of the third reset module is connected to the same control signal terminal as the control terminal of the second reset module.

15. The pixel driving circuit of claim 13, wherein, It also includes a bias module, which is connected between the bias signal terminal and the first terminal of the driving transistor, or the bias module is connected between the bias signal terminal and the second terminal of the driving transistor; The bias module is configured to adjust the bias state of the driving transistor during the bias adjustment phase. The control terminal of the bias module and the control terminal of the third reset module are connected to the same control signal terminal, and the bias adjustment stage coincides with the first node reset stage.

16. The pixel driving circuit of claim 13, wherein, The pixel driving circuit is connected to a cascaded shift register; the control terminal of the third reset module in the pixel driving circuit of the Nth row is connected to the output terminal of the shift register of the Nth stage, and the output terminal of the shift register of the Nth stage is connected to the control terminal of the data writing module in the pixel driving circuit of the Nmth row, where N and m are both integers, and 1≤m<N, N≥2.

17. The pixel driving circuit of claim 13, wherein, The third reset module includes an N-type transistor.

18. The pixel driving circuit of claim 1, wherein, It also includes a second light-emitting control module and a first switch control module. The second light-emitting control module is connected between the first power supply voltage terminal and the first electrode of the driving transistor, and the first switch control module is connected between the first power supply voltage terminal and the first electrode of the driving transistor. The control terminal of the second light-emitting control module is connected to the same control signal terminal as the control terminal of the first light-emitting control module, and the control terminal of the first switch control module is connected to the same control signal terminal as the control terminal of the threshold compensation module; the first switch control module is configured to be turned on during the threshold compensation phase, and the second light-emitting control module is configured to be turned on during the light-emitting phase.

19. The pixel driving circuit of claim 1, wherein, It also includes a bias module, which is connected between the bias signal terminal and the first terminal of the driving transistor, or the bias module is connected between the bias signal terminal and the second terminal of the driving transistor; The bias module is configured to adjust the bias state of the driving transistor during the bias adjustment phase.

20. The pixel driving circuit of claim 19, wherein, It also includes a second reset module, which is connected between the second reset signal terminal and the fourth node; The control terminal of the bias module is connected to the control terminal of the second reset module via the same control signal terminal; or, the control terminal of the bias module is connected to the control terminal of the data writing module via the same control signal terminal.

21. The pixel driving circuit of claim 19, wherein, The operation of the pixel driving circuit includes writing frames and holding frames, and the holding frame includes the bias adjustment stage.

22. A display device comprising the pixel driving circuit according to any one of claims 1 to 21.

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