Display panel

Abstract

The application discloses a display panel, which comprises a pixel driving circuit, a light emitting element, a first power supply line, a second power supply line, a data line and the light emitting element. The pixel driving circuit comprises a driving transistor, a compensation transistor, a writing transistor, a first storage capacitor and a second storage capacitor. The writing transistor is electrically connected between the second electrode of the driving transistor and the data line, and the second storage capacitor is electrically connected between the first gate electrode and the second electrode of the driving transistor. Thus, accurate driving current can be obtained at different gray scales, accurate control of the gray scale is realized, the orthographic projection of the first storage capacitor on a reference plane and the orthographic projection of the second storage capacitor on the reference plane at least partially overlap, the pixel density of the display panel is improved, and the display effect of the display panel is improved while the color deviation is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] With the development of display technology, organic light-emitting diode (OLED) display panels have been widely used in various display devices such as smartphones, tablets, and televisions. OLED display panels typically include light-emitting elements and pixel driving circuits. By writing data signals and control signals into the pixel driving circuits, the pixel driving circuits can drive the light-emitting elements to emit light according to the data signals and control signals, thereby displaying an image on the display panel.

[0003] Currently, the active layer of the driving transistors in pixel driving circuits typically uses metal-oxide-semiconductor (MOS) materials. However, due to the low mobility of MOS materials, the control precision for grayscale current is not high, leading to color distortion and color shift in the displayed image, thus affecting the display panel's performance. To improve color shift, a complex compensation circuit structure is constructed by introducing more transistors and capacitors into the pixel driving circuit, thereby compensating for the threshold voltage of the driving transistors. However, this complex circuit structure occupies a large layout area, limiting the increase in pixel density and making it difficult to meet the requirements of high-resolution displays.

[0004] Therefore, it is necessary to provide a display panel to improve this deficiency. Summary of the Invention

[0005] This application provides a display panel that can increase pixel density while improving the control accuracy of grayscale current and reducing color shift.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: a pixel driving circuit, a light-emitting element, a first power line, a second power line, a data line, and a light-emitting element, wherein the pixel driving circuit comprises: A driving transistor is connected in series with the light-emitting element between the first power line and the second power line; A compensation transistor is electrically connected between the first electrode and the first gate of the driving transistor; A write transistor is electrically connected between the second electrode of the drive transistor and the data line; and The first storage capacitor is electrically connected between the first gate of the driving transistor and the anode of the light-emitting element; The pixel driving circuit further includes a second storage capacitor, which is electrically connected between the first gate and the second electrode of the driving transistor. The first storage capacitor is disposed on the second storage capacitor. The orthographic projection of the first storage capacitor on the reference plane at least partially overlaps with the orthographic projection of the second storage capacitor on the reference plane. The reference plane is parallel to the light-emitting surface of the display panel.

[0007] Optionally, the first storage capacitor includes a first electrode plate and a second electrode plate disposed on the first electrode plate, and the second storage capacitor includes the first electrode plate and a third electrode plate, with the first electrode plate disposed on the third electrode plate; Wherein, the orthographic projection of the first electrode plate on the reference plane at least partially overlaps with the orthographic projection of the third electrode plate on the reference plane.

[0008] Optionally, the orthographic projection of the second electrode plate onto the reference plane at least partially overlaps with the orthographic projection of the third electrode plate onto the reference plane.

[0009] Optionally, the driving transistor includes a driving active portion, the first gate is disposed on the driving active portion, and the second storage capacitor includes a third plate, with the driving active portion located on the third plate.

[0010] Optionally, the driving transistor includes a second gate, the driving active portion is disposed on the second gate, and the second gate is electrically connected to the second electrode of the driving transistor; The second gate and the third electrode plate are disposed on the same layer and connected as a whole.

[0011] Optionally, the display panel includes a first connecting portion and multiple scan lines, wherein the first connecting portion is disposed on the same layer as the second gate and is connected between the second gate and the third electrode plate; The first connecting portion and the scanning line extend along a first direction, and the third electrode plate extends along a second direction. The first direction is different from the second direction and is perpendicular to the thickness direction of the display panel.

[0012] Optionally, the multiple scan lines include a first scan line and a second scan line, the gate of the compensation transistor is electrically connected to the first scan line, the gate of the write transistor is electrically connected to the second scan line, and the first scan line and the second scan line are arranged at intervals along the second direction; The orthographic projections of the third electrode plate and the first connecting portion onto the reference plane are located between the orthographic projections of the first scan line and the second scan line onto the reference plane.

[0013] Optionally, the distance between the orthogonal projections of the third electrode plate and the first scan line onto the reference plane in the second direction is greater than the distance between the orthogonal projections of the second gate and the first scan line onto the reference plane in the second direction. And / or, the distance between the orthogonal projections of the third electrode plate and the second scan line onto the reference plane in the second direction is less than the distance between the orthogonal projections of the second gate and the second scan line onto the reference plane in the second direction.

[0014] Optionally, the dimension of the third electrode plate in the first direction is smaller than the dimension of the first electrode plate in the first direction; And / or, the dimension of the third electrode in the second direction is smaller than the dimension of the first electrode in the second direction.

[0015] Optionally, the first electrode plate includes: The main body extends along the second direction; and An extension portion extends from one side of the main body portion along the first direction; The orthographic projection of the main body on the reference plane overlaps with the orthographic projection of the third electrode plate on the reference plane, the orthographic projection of the extension on the reference plane overlaps with the orthographic projection of the first connecting part on the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

[0016] Optionally, the first storage capacitor includes a first electrode plate, which is disposed on the same layer as the first gate and connected as an integral structure.

[0017] Optionally, the capacitance of the first storage capacitor is greater than the capacitance of the second storage capacitor.

[0018] Optionally, the ratio of the capacitance of the first storage capacitor to the capacitance of the second storage capacitor is greater than 1 and less than or equal to 5.

[0019] Optionally, the driving transistor is an oxide transistor.

[0020] In the display panel of this application embodiment, by electrically connecting the write transistor between the second electrode of the driving transistor and the data line, and electrically connecting the second storage capacitor between the first gate and the second electrode of the driving transistor, the voltage of the data signal can be differentiated. The same grayscale current requires a larger voltage of the data signal, which can ensure that a precise driving current can be obtained at different grayscale levels, and achieve precise control of grayscale. On this basis, by setting the first storage capacitor on the second storage capacitor, and making the orthographic projection of the first storage capacitor on the reference plane at least partially overlap with the orthographic projection of the second storage capacitor on the reference plane, the space of the first storage capacitor is used to arrange the second storage capacitor, avoiding the second storage capacitor occupying too much space. In this way, while keeping the total capacitance at the first gate of the driving transistor unchanged, the space occupied by the first storage capacitor can be reduced, thereby solving the color shift problem, increasing the pixel density of the display panel, and improving the display effect of the display panel.

[0021] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 A circuit diagram of a pixel driving circuit for a display panel provided in an embodiment of this application; Figure 2 Timing diagram of a display panel provided for embodiments of this application; Figure 3 A schematic diagram of the film layer structure of a display panel provided for an embodiment of this application; Figure 4 A layout of a pixel driving circuit provided for an embodiment of this application; Figure 5 A film layer diagram of the second gate layer in a display panel provided for embodiments of this application; Figure 6 A film layer diagram of the third gate layer in a display panel provided for embodiments of this application; Figure 7 A film layer diagram of the fourth gate layer in a display panel provided for embodiments of this application; Figure 8 A stack-up diagram of the second gate layer, the third gate layer, and the fourth gate layer in a display panel provided for embodiments of this application; Figure 9 A stack-up diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a fourth gate layer in a display panel provided for embodiments of this application; Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0026] Embodiments of this application provide a display panel including a pixel driving circuit, a light-emitting element, a first power line, a second power line, a data line, and a light-emitting element. The pixel driving circuit includes a driving transistor, a compensation transistor, a write transistor, a first storage capacitor, and a second storage capacitor. The driving transistor and the light-emitting element are connected in series between the first power line and the second power line. The compensation transistor is electrically connected between the first electrode and the first gate of the driving transistor. The write transistor is electrically connected between the second electrode of the driving transistor and the data line. The first storage capacitor is electrically connected between the first gate of the driving transistor and the anode of the light-emitting element. The second storage capacitor is electrically connected between the first gate and the second electrode of the driving transistor. The first storage capacitor is disposed on the second storage capacitor. The orthographic projection of the first storage capacitor on the reference plane and the orthographic projection of the second storage capacitor on the reference plane at least partially overlap. The reference plane is parallel to the light-emitting surface of the display panel.

[0027] In the embodiments of this application, by electrically connecting the write transistor between the second electrode of the driving transistor and the data line, and electrically connecting the second storage capacitor between the first gate and the second electrode of the driving transistor, the voltage of the data signal can be differentiated. The same grayscale current requires a larger voltage of the data signal, which can ensure that a precise driving current can be obtained at different grayscale levels, and achieve precise control of grayscale. On this basis, by setting the first storage capacitor on the second storage capacitor, and making the orthographic projection of the first storage capacitor on the reference plane at least partially overlap with the orthographic projection of the second storage capacitor on the reference plane, the space of the first storage capacitor is used to arrange the second storage capacitor, avoiding the second storage capacitor occupying too much space. In this way, while keeping the total capacitance at the first gate of the driving transistor unchanged, the space occupied by the first storage capacitor can be reduced, thereby solving the color shift problem, increasing the pixel density of the display panel, and improving the display effect of the display panel.

[0028] like Figure 1 As shown, Figure 1 The circuit diagram of the pixel driving circuit of the display panel provided in the embodiments of this application includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, a first storage capacitor Cst1, and a second storage capacitor Cst2. The driving transistor T1 is connected in series with the light-emitting element between the first power line VDD and the second power line VSS. The compensation transistor T3 is electrically connected between the first electrode and the first gate of the driving transistor T1. The writing transistor T2 is electrically connected between the second electrode of the driving transistor T1 and the data line Data. The first storage capacitor Cst1 is electrically connected between the first gate of the driving transistor T1 and the anode of the light-emitting element. The second storage capacitor Cst2 is electrically connected between the first gate and the second electrode of the driving transistor.

[0029] In some embodiments, such as Figure 1As shown, the pixel driving circuit includes a driving transistor T1, a write transistor T2, a compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first storage capacitor Cst1, and a second storage capacitor Cst2. The driving transistor T1 includes a first gate and a second gate. The first electrode of the driving transistor T1 is electrically connected to a first node A, the second electrode and the second gate are electrically connected to a second node B, and the first gate is electrically connected to a third node Q. The first electrode of the write transistor T2 is electrically connected to the data line Data, the second electrode is electrically connected to the second node B, and the write gate is electrically connected to the second scan line Scan2. The first electrode of the compensation transistor T3 is electrically connected to the first node A, the second electrode is electrically connected to the third node Q, and the compensation gate is electrically connected to the first scan line Scan1. The first electrode of the reset transistor T4 is electrically connected to the reset signal line Vref, the second electrode is electrically connected to the bottom fourth node C, and the reset gate is electrically connected to the third light-emitting control signal line. EM2(n+1); The first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply line VDD, the second electrode is electrically connected to the first node A, and the first light-emitting control gate is electrically connected to the first light-emitting control signal line EM1; The first electrode of the second light-emitting control transistor T6 is electrically connected to the second node B, the second electrode is electrically connected to the fourth node C, and the second light-emitting control gate is electrically connected to the second light-emitting control signal line EM2; The first plate of the first storage capacitor Cst1 is electrically connected to the third node Q, and the second plate is electrically connected to the second node B; The second storage capacitor Cst is electrically connected between the third node Q and the second node B; The anode of the light-emitting element is electrically connected to the fourth node C, and the cathode of the light-emitting element is electrically connected to the second power supply line VSS.

[0030] In the embodiments of this application, the first electrode of the transistor in the pixel driving circuit can be one of the source and the drain, and the second electrode can be the other of the source and the drain.

[0031] In some embodiments, such as Figure 1 As shown, the driving transistor T1, writing transistor T2, compensation transistor T3, and reset transistor T4 are all N-type thin-film transistors, while the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type thin-film transistors. In practical applications, each transistor can be arbitrarily configured as either an N-type or P-type thin-film transistor according to the driving timing.

[0032] In some embodiments, such as Figure 2 As shown, Figure 2 The timing diagram of the display panel provided for the embodiments of this application shows that a display frame of the display panel includes a reset phase, a data writing phase, and a light emission phase.

[0033] During the reset phase t1, the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is at a low level, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal transmitted by the second light-emitting control signal line EM2 is at a high level, the reset transistor T4 is turned on, and the second light-emitting control transistor T6 is turned off; the first scan control signal transmitted by the first scan line Scan1 is at a high level, and the compensation transistor T3 is turned on; the second scan control signal transmitted by the second scan line Scan2 is at a low level, and the write transistor T2 is turned off. During the reset phase, both the compensation transistor T3 and the first light-emitting control transistor T5 are turned on, and the first power supply signal can be written to the third node Q; the reset transistor T4 is turned on, and the reset signal can be written to the fourth node C to reset the anode of the light-emitting element.

[0034] During the data writing phase t2, the first light-emitting control signal is high, and the first light-emitting control transistor T5 is off; the second light-emitting control signal is high, the reset transistor T4 is on, and the second light-emitting control transistor T6 is off; the first scan control signal is high, and the compensation transistor T3 is on; the second scan control signal is high, and the write transistor T2 is on. During the data writing phase, both the write transistor T2 and the compensation transistor T3 are on, and the data signal is written to the third node Q. The gate voltage of the driving transistor T1 is the sum of the threshold voltage and the data signal voltage, thus compensating for the threshold voltage of the driving transistor T1; the reset transistor T4 remains on, and the reset signal is continuously written to the fourth node C, continuously resetting the anode of the light-emitting element.

[0035] During the light-emitting stage t3, the first light-emitting control signal is low, and the first light-emitting control transistor is turned on; the second light-emitting control signal is low, the reset transistor is turned off, and the second light-emitting control transistor is turned on; the first scan control signal is low, and the compensation transistor T3 is turned off; the second scan control signal is low, and the write transistor is turned off. During the light-emitting stage, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The driving transistor T1 is turned on because the third node Q is at a high potential. The current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting element to emit light.

[0036] In this embodiment, during the data writing stage t2, the potential of the third node Q is written to the sum of the threshold voltage and the voltage of the data signal, and the potentials of the second node B and the fourth node C are written to the voltage of the data signal and the voltage of the reset signal, respectively. During the light-emitting stage t3, the potentials of the second node B and the fourth node C become the first potential Vc. The second node B and the fourth node C are coupled to the third node Q through the first storage capacitor Cst1 and the second storage capacitor Cst2, respectively. The theoretical coupling amount is C_QB / C_Q(Vc-VData)+C_Cst / C_Q(Vc-Vref), where C_Q is the total capacitance of the third node Q, C_Cst is the capacitance of the first storage capacitor Cst1, C_QB is the capacitance of the second storage capacitor Cst2, VData is the potential of the data signal, and Vref is the potential of the reset signal. The potential of the third node Q is VQ=VData+Vth+C_QB / C_Q(Vc-Data)+C_Cst / C_Q(Vc-Vref), and the grayscale current I= k{Data(1-C_QB / C_Q)-Vref(C_QB / C_Q)+Vc[(C_Cst+C_QB) / C_Q-1]}^2. By adding a second storage capacitor Cst2 and electrically connecting it between the first gate and the second electrode of the driving transistor T1, the grayscale current and data signal voltage coefficient can be reduced. The same grayscale current requires a larger data signal voltage, which ensures that a precise driving current can be obtained under different grayscale levels, thereby achieving precise control of grayscale and solving the color shift problem and improving the display effect of the display panel.

[0037] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the film structure of a display panel provided in an embodiment of this application. The display panel includes a substrate 10 and a first barrier layer 11, a light-shielding layer 12, a second barrier layer 13, a buffer layer 14, a first active layer 15, a first gate insulating layer 16, a first gate layer 17, a second gate insulating layer 18, a second gate layer 19, a first interlayer dielectric layer 20, a second active layer 21, a third gate insulating layer 22, a third gate layer 23, a fourth gate insulating layer 24, a fourth gate layer 25, a second interlayer dielectric layer 26, a first source-drain layer 27, a passivation layer 28, a first planarization layer 29, a second source-drain layer 30, a second planarization layer 31, an anode layer 32, a pixel definition layer 33, a support layer 34, a light-emitting layer, a cathode layer, and an encapsulation layer (not shown in the figure) sequentially stacked on the substrate 10.

[0038] In some embodiments, such as Figure 3 and Figure 4 As shown, Figure 4The layout of the pixel driving circuit provided in the embodiments of this application shows that the first storage capacitor Cst1 is disposed on the second storage capacitor Cst2, and the orthographic projection of the first storage capacitor Cst1 on the reference plane at least partially overlaps with the orthographic projection of the second storage capacitor Cst2 on the reference plane. The reference plane is parallel to the light-emitting surface of the display panel.

[0039] It should be noted that since the first storage capacitor Cst1 and the second storage capacitor Cst2 overlap at least partially in the thickness direction of the display panel, the space of the first storage capacitor Cst1 can be used to arrange the second storage capacitor Cst2, avoiding the second storage capacitor Cst2 occupying too much space. With the total capacitance at the third node Q remaining constant, by adding the second storage capacitor Cst2 between the second node B and the third node Q, the area of ​​the first storage capacitor Cst1 can be reduced. Therefore, the space occupied by the first storage capacitor Cst1 can be reduced, thereby increasing the pixel density of the display panel.

[0040] In some embodiments, the orthographic projection of the first storage capacitor Cst1 onto the reference plane partially overlaps with the orthographic projection of the second storage capacitor Cst2 onto the reference plane. In other embodiments, the orthographic projection of the first storage capacitor Cst1 onto the reference plane and the orthographic projection of the second storage capacitor Cst2 onto the reference plane may completely overlap.

[0041] In some embodiments, such as Figure 3 and Figure 4 As shown, the first storage capacitor Cst1 includes a first plate Cst11 and a second plate Cst12 disposed on the first plate Cst11. The orthographic projections of the first plate Cst11 and the second plate Cst12 on the reference plane at least partially overlap to jointly form the first storage capacitor Cst1.

[0042] In some embodiments, the first electrode plate Cst11 and the first gate T1G1 are disposed on the same layer and connected as an integral structure.

[0043] like Figures 5 to 8 As shown, Figure 5 A film layer diagram of the second gate layer in a display panel provided for embodiments of this application. Figure 6 A film layer diagram of the third gate layer in a display panel provided for embodiments of this application. Figure 7 A film layer diagram of the fourth gate layer in a display panel provided for embodiments of this application. Figure 8 The stack-up diagram of the second gate layer, the third gate layer and the fourth gate layer in the display panel provided in the embodiments of this application is shown. The third gate layer 23 includes the first gate T1G1 of the driving transistor T1 and the first electrode Cst11 of the first storage capacitor Cst1. The first gate T1G1 and the first electrode Cst11 are connected as an integral structure.

[0044] The fourth gate layer 25 includes a second electrode Cst12 of the first storage capacitor Cst1. The size of the second electrode Cst12 is larger than that of the first electrode Cst11. This ensures that the orthogonal projection of the second electrode Cst12 on the reference plane completely covers the orthogonal projection of the first electrode Cst11 on the reference plane, thus avoiding changes in the capacitance of the first storage capacitor Cst1 due to process errors.

[0045] In some embodiments, the second storage capacitor Cst2 includes a first electrode Cst11 and a third electrode Cst21. The orthographic projection of the first electrode Cst11 onto the reference plane at least partially overlaps with the orthographic projection of the third electrode Cst21 onto the reference plane, so that together with the third electrode Cst21, they constitute the second storage capacitor Cst2. By utilizing the space of the first electrode Cst11 of the first storage capacitor Cst1 to arrange the second storage capacitor Cst2, the second storage capacitor Cst2 avoids occupying too much space and can reduce the area of ​​the first storage capacitor Cst1. Therefore, the space occupied by the first storage capacitor Cst1 can be reduced, thereby increasing the pixel density of the display panel.

[0046] In some embodiments, the driving transistor T1 includes a driving active portion T1A, a first gate T1G1 is disposed on the driving active portion T1A, and the second storage capacitor Cst2 includes a third plate Cst21, with the driving active portion T1A located on the third plate Cst21.

[0047] like Figure 3 As shown, the second active layer 21 includes a driving active part T1A of driving transistor T1, a compensation active part of compensation transistor T3, and a reset active part of reset transistor T4. The driving active part T1A is located on the third plate Cst21, and the first plate Cst11 is located on the driving active part T1A.

[0048] In some embodiments, the material of the second active layer 21 includes an oxide semiconductor material, i.e., the driving transistor T1, the compensation transistor T3, and the reset transistor T4 are all oxide transistors. Specifically, the oxide semiconductor material may include, but is not limited to, any one of indium tin oxide, indium gallium zinc oxide, and indium zinc oxide.

[0049] In some embodiments, the first active layer 15 includes a write active portion of a write transistor T2, a first light-emitting control active portion of a first light-emitting control transistor T5, and a second light-emitting control active portion of a second light-emitting control transistor T6.

[0050] In some embodiments, the material of the first active layer 15 includes a silicon semiconductor material, which may include, but is not limited to, amorphous silicon and polycrystalline silicon. For example, the write transistor T2, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all low-temperature polycrystalline silicon transistors.

[0051] In some embodiments, the second gate T1G2 and the third electrode plate Cst21 are disposed on the same layer and connected as a single structure.

[0052] like Figures 5 to 8 As shown, the second gate layer 19 includes the second gate T1G2 of the driving transistor T1 and the third plate Cst21 of the second storage capacitor Cst2. The size of the first plate Cst11 is larger than the size of the third plate Cst21. This ensures that the orthographic projection of the first plate Cst11 on the reference plane completely covers the orthographic projection of the third plate Cst21 on the reference plane, thus avoiding changes in the capacitance of the second storage capacitor Cst2 due to process errors.

[0053] In some embodiments, the display panel includes a first connection portion 191 and a plurality of scan lines. The first connection portion 191 is disposed on the same layer as the second gate T1G2 and is connected between the second gate T1G2 and the third electrode plate Cst21. The first connection portion extends along the extension direction of the scan lines, and the third electrode plate extends in a direction perpendicular to the extension direction of the scan lines.

[0054] like Figures 4 to 8 As shown, multiple scan lines include a first scan line Scan1 and a second scan line Scan2. The first scan line Scan1 and the second scan line Scan2 extend laterally from a top-view angle. The first connecting portion 191 extends in the same direction as the first scan line Scan1. The second gate T1G2 has a block structure and extends in a direction perpendicular to the extension direction of the first scan line Scan1 to connect with the first connecting portion 191. The third electrode plate Cst21 extends in a direction perpendicular to the extension direction of the first scan line Scan1 and has an elongated structure. In this way, within a limited space, the overlap area of ​​the third electrode plate Cst21 and the first electrode plate Cst11 can be increased to increase the capacitance of the second storage capacitor Cst2 and decrease the area of ​​the first storage capacitor Cst1, thereby facilitating an increase in the pixel density of the display panel.

[0055] In some embodiments, such as Figure 9 As shown, Figure 9The stack-up diagram of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and fourth gate layer in the display panel provided in the embodiments of this application shows that the first scan line Scan1 and the second scan line Scan2 both extend along the first direction X and are spaced apart along the second direction Y. The first direction X and the second direction Y are different and perpendicular to the thickness direction of the display panel. For example, the first direction X can be the horizontal direction from a top-view perspective, and the second direction Y can be the vertical direction from a top-view perspective. The first direction X and the second direction Y are perpendicular.

[0056] In some embodiments, such as Figure 9 As shown, the orthographic projections of the third electrode plate Cst21 and the first connecting portion 191 on the reference plane are located between the orthographic projections of the first scan line Scan1 and the second scan line Scan2 on the reference plane. By utilizing the space between the first scan line Scan1 and the second scan line Scan2 to place the third electrode plate Cst21 and the first connecting portion 191, the space occupied by the third electrode plate Cst21 and the first connecting portion 191 can be reduced, thus avoiding affecting the pixel density of the display panel.

[0057] In some embodiments, the distance between the orthogonal projections of the third electrode plate Cst21 and the first scan line Scan1 onto the reference plane in the second direction Y is greater than the distance between the orthogonal projections of the second gate T1G2 and the first scan line Scan1 onto the reference plane in the second direction Y.

[0058] like Figure 9 As shown, the distance between the orthogonal projections of the third electrode plate Cst21 and the first scan line Scan1 on the reference plane in the second direction Y is a first distance d1, and the distance between the orthogonal projections of the second gate T1G2 and the first scan line Scan1 on the reference plane in the second direction Y is a second distance d2. The first distance d1 is greater than the second distance d2, meaning that the third electrode plate Cst21 is farther from the first scan line Scan1 than the second gate T1G2 and the first connection portion 191. Thus, without affecting the pixel density, sufficient space can be reserved between the first scan line Scan1 and the third electrode plate Cst21 for placing the compensation active portion of the compensation transistor T3, so that the compensation active portion of the compensation transistor T3 can overlap with the source or drain through vias between film layers.

[0059] In some embodiments, the distance between the orthogonal projection of the third electrode plate Cst21 and the second scan line Scan2 on the reference plane in the second direction Y is less than the distance between the orthogonal projection of the second gate T1G2 and the second scan line Scan2 on the reference plane in the second direction Y.

[0060] like Figure 9As shown, the distance between the orthogonal projections of the third electrode plate Cst21 and the second scan line Scan2 on the reference plane in the second direction Y is the third distance d3. The distance between the orthogonal projections of the second gate T1G2 and the second scan line Scan2 on the reference plane in the second direction Y is the fourth distance d4. The third distance d3 is greater than the fourth distance d4, meaning that the third electrode plate Cst21 is closer to the second scan line Scan2 than the second gate T1G2 and the first connection portion 191. Thus, without affecting the pixel density, sufficient space can be reserved between the second scan line Scan2 and the second gate T1G2 and the first connection portion 191 for placing the active write portion of the write transistor T2, allowing the active write portion of the write transistor T2 to overlap with the source or drain through vias between film layers.

[0061] In some embodiments, the distance between the orthogonal projections of the third electrode plate Cst21 and the first scan line Scan1 on the reference plane in the second direction Y is greater than the distance between the orthogonal projections of the second gate T1G2 and the first scan line Scan1 on the reference plane in the second direction Y, and the distance between the orthogonal projections of the third electrode plate Cst21 and the second scan line Scan2 on the reference plane in the second direction Y is less than the distance between the orthogonal projections of the second gate T1G2 and the second scan line Scan2 on the reference plane in the second direction Y.

[0062] In some embodiments, the distance between the orthogonal projections of the third electrode plate Cst21 and the first scan line Scan1 on the reference plane in the second direction Y is greater than the distance between the orthogonal projections of the second gate T1G2 and the first scan line Scan1 on the reference plane in the second direction Y, and the distance between the orthogonal projections of the third electrode plate Cst21 and the second scan line Scan2 on the reference plane in the second direction Y is greater than or equal to the distance between the orthogonal projections of the second gate T1G2 and the second scan line Scan2 on the reference plane in the second direction Y.

[0063] In some embodiments, the distance between the orthogonal projections of the third electrode plate Cst21 and the first scan line Scan1 on the reference plane in the second direction Y is less than or equal to the distance between the orthogonal projections of the second gate T1G2 and the first scan line Scan1 on the reference plane in the second direction Y, and the distance between the orthogonal projections of the third electrode plate Cst21 and the second scan line Scan2 on the reference plane in the second direction Y is less than the distance between the orthogonal projections of the second gate T1G2 and the second scan line Scan2 on the reference plane in the second direction Y.

[0064] In some embodiments, combined with Figures 5 to 8As shown, the first electrode plate Cst11 is composed of a main body Cst111 and an extension Cst112. The main body Cst111 extends along the second direction Y, and the extension Cst112 extends from one side of the main body Cst111 along the first direction X. The orthographic projection of the main body Cst111 on the reference plane overlaps with the orthographic projection of the third electrode plate Cst21 on the reference plane, and the orthographic projection of the extension Cst112 on the reference plane overlaps with the orthographic projection of the first connecting part 191 on the reference plane. This increases the overlapping area of ​​the first electrode plate Cst11 and the third electrode plate Cst21, thereby increasing the capacitance of the second storage capacitor Cst2 and decreasing the capacitance of the first storage capacitor Cst1, thus reducing the area of ​​the first storage capacitor Cst1. This reduces the space occupied by the first storage capacitor Cst1, which is beneficial for increasing the pixel density of the display panel.

[0065] In some embodiments, the dimension of the third electrode plate Cst21 in the first direction X is smaller than the dimension of the first electrode plate Cst11 in the first direction X.

[0066] Combination Figures 5 to 8 As shown, the third electrode plate Cst21 has a first width w1 in the first direction X, and the first electrode plate Cst11 has a second width w2 in the first direction X, referring to the main body Cst111. The first width w1 is smaller than the second width w2. Thus, even if the manufacturing process fluctuates in the first direction X, it can be ensured that the first electrode plate Cst11 can cover the third electrode plate Cst21, preventing fluctuations in the manufacturing process in the first direction X from affecting the size of the second storage capacitor Cst2.

[0067] In some embodiments, the dimension of the third electrode plate Cst21 in the second direction Y is smaller than the dimension of the first electrode plate Cst11 in the second direction Y.

[0068] Combination Figures 5 to 8 As shown, the dimension of the third electrode plate Cst21 in the second direction Y is a first length L1, and the dimension of the first electrode plate Cst11 in the second direction Y refers to the second length L2 of the main body Cst111 in the second direction Y. The first length L1 is smaller than the second length L2. In this way, even if the manufacturing process fluctuates in the second direction Y, it can be ensured that the first electrode plate Cst11 can cover the third electrode plate Cst21, avoiding the influence of the manufacturing process fluctuation in the second direction Y on the size of the second storage capacitor Cst2.

[0069] In some embodiments, the dimension of the third electrode plate Cst21 in the first direction X is smaller than the dimension of the first electrode plate Cst11 in the first direction X, and the dimension of the third electrode plate Cst21 in the second direction Y is smaller than the dimension of the first electrode plate Cst11 in the second direction Y. This ensures that the orthographic projection of the first electrode plate Cst11 on the reference plane can completely cover the orthographic projection of the third electrode plate Cst21 on the reference plane, so as to avoid the capacitance of the second storage capacitor Cst2 changing due to process fluctuations.

[0070] In some embodiments, the dimension of the third electrode plate Cst21 in the first direction X is smaller than the dimension of the first electrode plate Cst11 in the first direction X, and the dimension of the third electrode plate Cst21 in the second direction Y is greater than or equal to the dimension of the first electrode plate Cst11 in the second direction Y.

[0071] In some embodiments, the dimension of the third electrode plate Cst21 in the first direction X is greater than or equal to the dimension of the first electrode plate Cst11 in the first direction X, and the dimension of the third electrode plate Cst21 in the second direction Y is less than the dimension of the first electrode plate Cst11 in the second direction Y.

[0072] In some embodiments, the orthographic projection of the second electrode plate Cst12 onto the reference plane at least partially overlaps with the orthographic projection of the third electrode plate Cst21 onto the reference plane.

[0073] like Figure 8 As shown, the size of the second electrode plate Cst12 is larger than the size of the third electrode plate Cst21. The orthographic projection of the second electrode plate Cst12 on the reference plane partially overlaps with the orthographic projection of the third electrode plate Cst21 on the reference plane. The orthographic projection of the second electrode plate Cst12 on the reference plane completely covers the orthographic projection of the third electrode plate Cst21 on the reference plane. The space of the second electrode plate Cst12 of the first storage capacitor Cst1 is used to arrange the second storage capacitor Cst2, avoiding the second storage capacitor Cst2 from occupying too much space and reducing the area of ​​the first storage capacitor Cst1. Therefore, the space occupied by the first storage capacitor Cst1 can be reduced, thereby increasing the pixel density of the display panel.

[0074] In some other embodiments, the orthographic projection of the second electrode plate Cst12 on the reference plane partially overlaps with the orthographic projection of the third electrode plate Cst21 on the reference plane. This can also reduce the space occupied by the first storage capacitor Cst1, thereby increasing the pixel density of the display panel.

[0075] In some embodiments, the capacitance of the first storage capacitor Cst1 is greater than the capacitance of the second storage capacitor Cst2. It should be noted that the size of the second storage capacitor Cst2 is proportional to its area; the larger the area, the larger the capacitance of the second storage capacitor Cst2. This embodiment ensures that the second storage capacitor Cst2 is within the coverage area of ​​the first storage capacitor Cst1 by making the second storage capacitor Cst2 smaller than the first storage capacitor Cst1. This utilizes the space of the first storage capacitor Cst1 to arrange the second storage capacitor Cst2, avoiding the second storage capacitor Cst2 occupying too much space. Furthermore, it reduces the area of ​​the first storage capacitor Cst1, thus reducing the space occupied by the first storage capacitor Cst1 and thereby increasing the pixel density of the display panel.

[0076] In some embodiments, the ratio of the capacitance of the first storage capacitor Cst1 to the capacitance of the second storage capacitor Cst2 is greater than 1 and less than or equal to 5. For example, the ratio of the capacitance of the first storage capacitor Cst1 to the capacitance of the second storage capacitor Cst2 can be 1.2, 1.5, 1.8, 2, 2.5, 3, 3.5, 4, 4.5, or 5, etc.

[0077] It should be noted that if the capacitance of the second storage capacitor Cst2 is too large, the voltage of the split data signal will be too small, which will not improve the control accuracy of the grayscale current. Furthermore, if the capacitance of the second storage capacitor Cst2 is too large, it will increase the space occupied by the pixel driving circuit, which is detrimental to improving pixel density. This embodiment, by limiting the ratio of the first storage capacitor to the second storage capacitor to between 1 and 5, can improve the control accuracy of the grayscale current, reduce color shift, and simultaneously increase the pixel density of the display panel.

[0078] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device, such as... Figure 10 As shown, Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be described in detail here.

[0079] The beneficial effects of the embodiments of this application are as follows: A display panel includes a pixel driving circuit, a light-emitting element, a first power line, a second power line, a data line, and a light-emitting element. The pixel driving circuit includes a driving transistor, a compensation transistor, a write transistor, a first storage capacitor, and a second storage capacitor. The driving transistor and the light-emitting element are connected in series between the first power line and the second power line. The compensation transistor is electrically connected between the first electrode and the first gate of the driving transistor. The first storage capacitor is electrically connected between the first gate of the driving transistor and the anode of the light-emitting element. By electrically connecting the write transistor between the second electrode of the driving transistor and the data line, and electrically connecting the second storage capacitor between the first gate and the second electrode of the driving transistor, differential data signals can be achieved. For the same grayscale current, a larger voltage is required for the data signal. This ensures that a precise driving current can be obtained at different grayscale levels, achieving precise control of the grayscale. Based on this, by placing the first storage capacitor on top of the second storage capacitor and ensuring that the orthographic projection of the first storage capacitor on the reference plane at least partially overlaps with the orthographic projection of the second storage capacitor on the reference plane, the space of the first storage capacitor is used to arrange the second storage capacitor, avoiding the second storage capacitor occupying too much space. In this way, while keeping the total capacitance at the first gate of the driving transistor unchanged, the space occupied by the first storage capacitor is reduced. This solves the color shift problem while increasing the pixel density of the display panel and improving the display effect of the display panel.

[0080] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0083] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The system includes a pixel driving circuit, a light-emitting element, a first power line, a second power line, a data line, and a light-emitting element. The pixel driving circuit includes: A driving transistor is connected in series with the light-emitting element between the first power line and the second power line; A compensation transistor is electrically connected between the first electrode and the first gate of the driving transistor; A write transistor is electrically connected between the second electrode of the drive transistor and the data line; and The first storage capacitor is electrically connected between the first gate of the driving transistor and the anode of the light-emitting element; The pixel driving circuit further includes a second storage capacitor, which is electrically connected between the first gate and the second electrode of the driving transistor. The first storage capacitor is disposed on the second storage capacitor. The orthographic projection of the first storage capacitor on the reference plane at least partially overlaps with the orthographic projection of the second storage capacitor on the reference plane. The reference plane is parallel to the light-emitting surface of the display panel.

2. The display panel as described in claim 1, characterized in that, The first storage capacitor includes a first electrode plate and a second electrode plate disposed on the first electrode plate; the second storage capacitor includes the first electrode plate and a third electrode plate, with the first electrode plate disposed on the third electrode plate. Wherein, the orthographic projection of the first electrode plate on the reference plane at least partially overlaps with the orthographic projection of the third electrode plate on the reference plane.

3. The display panel as described in claim 2, characterized in that, The orthographic projection of the second electrode plate onto the reference plane at least partially overlaps with the orthographic projection of the third electrode plate onto the reference plane.

4. The display panel as described in claim 1, characterized in that, The driving transistor includes a driving active portion, the first gate is disposed on the driving active portion, and the second storage capacitor includes a third plate, with the driving active portion located on the third plate.

5. The display panel as described in claim 4, characterized in that, The driving transistor includes a second gate, the driving active portion is disposed on the second gate, and the second gate is electrically connected to the second electrode of the driving transistor; The second gate and the third electrode plate are disposed on the same layer and connected as a whole.

6. The display panel as described in claim 5, characterized in that, The display panel includes a first connecting portion and multiple scan lines. The first connecting portion is disposed on the same layer as the second gate and is connected between the second gate and the third electrode plate. The first connecting portion and the scanning line extend along a first direction, and the third electrode plate extends along a second direction. The first direction is different from the second direction and is perpendicular to the thickness direction of the display panel.

7. The display panel as described in claim 6, characterized in that, Multiple scan lines include a first scan line and a second scan line. The gate of the compensation transistor is electrically connected to the first scan line, and the gate of the write transistor is electrically connected to the second scan line. The first scan line and the second scan line are arranged at intervals along the second direction. The orthographic projections of the third electrode plate and the first connecting portion onto the reference plane are located between the orthographic projections of the first scan line and the second scan line onto the reference plane.

8. The display panel as described in claim 7, characterized in that, The distance between the orthogonal projections of the third electrode plate and the first scan line onto the reference plane in the second direction is greater than the distance between the orthogonal projections of the second gate and the first scan line onto the reference plane in the second direction. And / or, the distance between the orthogonal projections of the third electrode plate and the second scan line onto the reference plane in the second direction is less than the distance between the orthogonal projections of the second gate and the second scan line onto the reference plane in the second direction.

9. The display panel as described in claim 6, characterized in that, The first storage capacitor includes a first electrode plate, and the dimension of the third electrode plate in the first direction is smaller than the dimension of the first electrode plate in the first direction; And / or, the dimension of the third electrode in the second direction is smaller than the dimension of the first electrode in the second direction.

10. The display panel as claimed in claim 6, characterized in that, The first storage capacitor includes a first electrode plate, and the first electrode plate includes: The main body extends along the second direction; and An extension portion extends from one side of the main body portion along the first direction; The orthographic projection of the main body on the reference plane overlaps with the orthographic projection of the third electrode plate on the reference plane, the orthographic projection of the extension on the reference plane overlaps with the orthographic projection of the first connecting part on the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

11. The display panel as claimed in any one of claims 1 to 10, characterized in that, The first storage capacitor includes a first electrode plate, which is disposed on the same layer as the first gate and connected as an integral structure.

12. The display panel as claimed in any one of claims 1 to 10, characterized in that, The capacitance of the first storage capacitor is greater than the capacitance of the second storage capacitor.

13. The display panel as claimed in claim 12, characterized in that, The ratio of the capacitance of the first storage capacitor to the capacitance of the second storage capacitor is greater than 1 and less than or equal to 5.

14. The display panel as claimed in any one of claims 1 to 10, characterized in that, The driving transistor is an oxide transistor.

Images