Method and device for automatically testing switch, terminal equipment and storage medium

Abstract

The application provides a switch automatic testing method and device, terminal equipment and storage medium, which are suitable for the technical field of switch testing. The method comprises the following steps: acquiring each logical topology; the logical topology is a logical network relationship of a network device in a test scene generated based on a preset naming rule; the network device comprises at least one switch to be tested; matching each logical topology with a preset physical topology to determine a mapping relationship between each logical topology and a physical sub-topology; the physical topology comprises at least one physical sub-topology; and based on a test case corresponding to each logical topology, the mapping relationship between each logical topology and the physical sub-topology is used to perform testing. The embodiment of the application realizes automatic matching of the logical topology and the physical topology, automation of operation, and improvement of the accuracy of topology matching and the testing efficiency.

Description

Technical Field

[0001] This application relates to the field of switch testing technology, and in particular to an automatic testing method, apparatus, terminal equipment and storage medium for switches. Background Technology

[0002] With the deepening of the digital economy, the network scale of scenarios such as data centers, campus networks, and SMBs (small and medium-sized enterprises) continues to expand. As core network interconnection devices, switches have become a core supporting element for ensuring the efficient and reliable operation of network architecture, with their performance, stability, and compatibility being crucial. The efficiency and accuracy of the testing process, as a key process for ensuring product quality, directly affect the product development cycle and delivery quality.

[0003] Currently, testers typically obtain the logical topology manually according to a pre-planned device interconnection structure. They also need to manually input the physical topology and manually establish mapping relationships for testing. This manual operation method is not only cumbersome and inefficient, but also prone to topology matching errors that can lead to test process interruptions. Summary of the Invention

[0004] In view of this, embodiments of this application provide an automatic testing method, apparatus, terminal device, and storage medium for switches, in order to solve the problems of cumbersome operation, low efficiency, or easy interruption of the testing process due to topology matching errors caused by manual operation in the prior art.

[0005] The first aspect of this application provides an automatic testing method for a switch, comprising: Obtain each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; the network devices include at least one switch under test. Each logical topology is matched with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; the physical topology includes at least one physical sub-topology. Tests are performed based on the test cases corresponding to each logical topology, using the mapping relationship between each logical topology and the physical sub-topology.

[0006] In one possible implementation, the network device also includes at least one tester, and the logical topology is obtained as follows: Determine the number of switches to be tested in the test scenario; Determine the number of testers to connect to each switch under test; Determine the number of loopbacks for each switch under test; Determine the number of interconnections between each switch under test and other switches under test; The logical topology is determined based on the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks for each switch under test, and the number of computed connections between each switch under test and other switches under test.

[0007] In one possible implementation, the number of computed connections between each switch under test and other switches under test is determined, including: Sort the switches under test to determine their order. For each switch under test, based on the arrangement order, determine the number of connections between the switch under test and other switches under test excluding those arranged before the switch under test. This number is used as the calculated number of connections between the switch under test and other switches under test.

[0008] In one possible implementation, the logical topology is determined based on the number of switches under test (SUT), the number of testers connected to each SUT, the number of loopbacks of each SUT, and the number of computed connections between each SUT and other SUTs, including: The logical topology is determined by sequentially arranging the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks for each switch under test, and the number of computed connections between each switch under test and other switches under test.

[0009] In one possible implementation, each logical topology is matched with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology, including: In the first matching cycle, each logical topology is matched with a preset physical topology to determine the matched logical topology and the mapping relationship between each matched logical topology and physical sub-topology. In the Nth matching cycle, the remaining unmatched logical topologies are matched with the preset physical topologies to determine the matched logical topologies and the mapping relationship between each matched logical topology and physical sub-topology, until the mapping relationship between all logical topologies and physical sub-topologies is determined; N is an integer greater than 1.

[0010] In one possible implementation, tests are performed based on the test cases corresponding to each logical topology, using the mapping relationship between each logical topology and the physical sub-topology, including: For each matching cycle, based on the test cases corresponding to the logical topology of each match, tests are executed in parallel using the mapping relationship between the logical topology and the physical sub-topology of each match.

[0011] In one possible implementation, the network device also includes at least one tester, and the physical topology is obtained as follows: Determine the physical connection information; the physical connection information includes the connection relationship between each switch under test and other switches under test, and the connection relationship between each switch under test and each tester. Determine port connection information; port connection information includes the port information of the two ports corresponding to the connection relationship; The physical topology is determined based on physical connection information and port connection information.

[0012] A second aspect of this application provides an automatic testing apparatus for a switch, comprising: The acquisition module is used to acquire each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; the network devices include at least one switch under test. The matching module is used to match each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; the physical topology includes at least one physical sub-topology; The testing module is used to execute tests based on the test cases corresponding to each logical topology, using the mapping relationship between each logical topology and the physical sub-topology.

[0013] A third aspect of this application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method of the first aspect.

[0014] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method of the first aspect.

[0015] Compared with the prior art, the embodiments of this application have at least the following technical effects: The automatic testing method for switches according to the first aspect of this application can acquire various logical topologies. The logical topologies are logical network relationships of network devices in a test scenario generated based on preset naming rules, and each network device includes at least one switch under test. Then, this application matches each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and its physical sub-topology. That is, the logical topologies generated by this application using preset naming rules can achieve automatic matching between logical and physical topologies. Furthermore, this application can execute tests based on test cases corresponding to each logical topology, using the mapping relationship between each logical topology and its physical sub-topology. Therefore, this application uses automatic matching of logical and physical topologies instead of manually establishing mapping relationships, automating the operation, improving the accuracy of topology matching and testing efficiency, and efficiently and accurately achieving automatic correspondence between logical and actual topologies in scenarios such as the tester and the switch under test, and switches under test and other switches under test.

[0016] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of an automatic testing method for a switch provided in an embodiment of this application; Figure 2 This is a flowchart of the logic topology acquisition provided in the embodiments of this application; Figure 3 This is a flowchart of another automatic testing method for a switch provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the automatic testing device for the switch provided in the embodiments of this application; Figure 5 This is a schematic diagram of the terminal device provided in the embodiments of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] In the description of this application, unless otherwise stated, the " / " used in this specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application merely describes the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c. Here, a, b, and c can be single or multiple.

[0023] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0024] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0026] Research has revealed a surge in testing demands and testing scenarios for switch products. Large-scale, multi-dimensional testing (covering functional testing, performance testing, and compatibility testing) is required in all stages, including functional verification during product development, performance testing before shipment, compatibility verification before network deployment, and fault reproduction and troubleshooting during operation and maintenance, to ensure the reliable operation of products in different scenarios.

[0027] However, manual operation is inefficient. To improve testing efficiency, automated testing has become the core direction for upgrading the testing process. However, existing automated testing solutions still have key technical shortcomings when adapting to multi-device interconnection scenarios: In the interconnection testing scenarios between testers and switches, and between switches, there is a lack of efficient and accurate automated matching mechanism for the correspondence between logical topology (the device interconnection structure pre-planned by testers) and actual topology (the actual connection relationship of devices in the physical environment). Most solutions rely on manual input of physical topology information and manual establishment of mapping relationships, which is not only cumbersome and inefficient, but also prone to interruption of the testing process due to topology matching errors. This solution is only suitable for test cases with the same topology structure and lacks the ability to adapt to dynamic changes in topology, making it difficult to meet the company's multi-scenario and highly complex testing needs.

[0028] With the continuous growth in demand for switch product testing and the urgent need for automated testing, how to efficiently and accurately achieve automatic mapping between the logical topology and actual topology of test instruments and switches, and between switches in different scenarios, has become a key bottleneck restricting the automation upgrade of the testing process and ensuring the quality and efficiency of product testing. Therefore, there is an urgent need to propose a technical solution that can address these issues and provide core technical support for the automated testing of switch products.

[0029] The automatic testing method, apparatus, terminal equipment, and storage medium for switches provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0030] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0031] See Figure 1 As shown, this application provides a flowchart of an automatic testing method for a switch. Figure 1 As shown, the automatic testing method for the switch includes steps S101 to S103.

[0032] S101. Obtain each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; the network devices include at least one switch under test.

[0033] Optionally, the automation script may include at least one logical topology, and the automation script may also include test cases corresponding to each logical topology, the test cases being generated based on the logical topology.

[0034] Optionally, the logical topology includes the interconnection of network devices, port configurations, and test scenario labels.

[0035] It is conceivable that the automatic testing method of this application embodiment can also be applied to other network devices such as optical modules, optical transmission, and optical network devices.

[0036] S102. Match each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; the physical topology includes at least one physical sub-topology.

[0037] The physical topology corresponds to the actual network device connections. This application's embodiments can achieve a precise mapping between logical and physical topologies through preset multi-dimensional matching rules.

[0038] S103. Based on the test cases corresponding to each logical topology, the test is executed using the mapping relationship between each logical topology and the physical sub-topology.

[0039] The automatic testing method for switches in this application embodiment can acquire various logical topologies. These logical topologies are logical network relationships of network devices in a test scenario generated based on preset naming rules, and each network device includes at least one switch under test. Then, this application embodiment matches each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and its physical sub-topology. That is, the logical topology generated by this application embodiment using preset naming rules can achieve automatic matching between logical and physical topologies. Furthermore, this application embodiment can execute tests based on test cases corresponding to each logical topology, using the mapping relationship between each logical topology and its physical sub-topology.

[0040] Therefore, the embodiments of this application adopt an automatic matching method of logical topology and physical topology, instead of manually establishing mapping relationships. This automates the operation, improves the accuracy of topology matching and testing efficiency, and can efficiently and accurately realize the automatic correspondence between logical topology and actual topology in scenarios such as tester and switch under test, and switch under test and switch under test.

[0041] See Figure 2 As shown, this application embodiment provides a flowchart for obtaining a logical topology. The network device further includes at least one tester; as... Figure 2 As shown, the logical topology is obtained in the following way: S201. Determine the number of switches to be tested in the test scenario.

[0042] S202. Determine the number of testers connected to each switch under test.

[0043] S203. Determine the number of loopbacks for each switch under test.

[0044] S204. Determine the number of connections between each switch under test and other switches under test.

[0045] In some embodiments, determining the number of computed connections between each switch under test and other switches under test includes: Sort the switches under test to determine their order. For each switch under test, based on the arrangement order, determine the number of connections between the switch under test and other switches under test excluding those arranged before the switch under test. This number is used as the calculated number of connections between the switch under test and other switches under test.

[0046] S205. Determine the logical topology based on the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the number of calculated connections between each switch under test and other switches under test.

[0047] In some embodiments, the logical topology is determined based on the number of switches under test (SUT), the number of testers connected to each SUT, the number of loopbacks of each SUT, and the number of computed connections between each SUT and other SUTs, including: The logical topology is determined by sequentially arranging the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks for each switch under test, and the number of computed connections between each switch under test and other switches under test.

[0048] Optionally, the number of switches under test is preceded by a logical topology identifier.

[0049] As an example, the first letter of the logical topology is L (logic), representing the logical topology identifier. The second number is the number of switches under test, separated by an underscore. The third number is the number of ports on each switch connected to the tester (N digits). Separated by an underscore, the following numbers are the number of loopbacks for each switch under test and the calculated number of connections between each switch under test and other switches under test. First, the system displays the number of connections of the first switch under test (SUTP) to other SUTPs (N numbers); followed by an underscore, then the number of connections of the second switch under test (SUTP) to other SUTPs (excluding the first SUTP) (N-1 numbers); followed by an underscore, then the number of connections of the third switch under test (SUTP) to other SUTPs (excluding the first and second SUTPs) (N-2 numbers), and so on. Finally, it displays the number of connections of the second-to-last switch under test (SUTP) to the last switch under test (2 numbers); and then the number of connections of the last switch under test (SUTP) to the last switch under test (1 number).

[0050] For example: L_1_1_0: L represents the logical topology identifier, the first 1 represents a single switch under test, the second 1 represents one tester port on the switch under test, and the third 0 represents that the number of loopback connections is 0.

[0051] L_2_10_01_0: L represents the logical topology identifier. The first number 2 represents a topology of 2 switches under test. The second number 1 represents that there is 1 tester on the first switch under test. The third number 0 represents that there are 0 testers on the second switch under test. The fourth number 0 represents that there are 0 loopbacks on the first switch under test. The fifth number 1 represents that there is 1 connection between the two switches under test. The sixth number represents that there are no loopbacks on the second switch under test.

[0052] Optionally, in test scenarios where network devices lack testing equipment, the logical topology can be determined based on the number of switches under test, the number of loopbacks for each switch under test, and the number of computed connections between each switch under test and other switches under test.

[0053] In some embodiments, the network device further includes at least one tester; the physical topology is obtained as follows: Determine the physical connection information; the physical connection information includes the connection relationship between each switch under test and other switches under test, and the connection relationship between each switch under test and each tester. Determine port connection information; port connection information includes the port information of the two ports corresponding to the connection relationship; The physical topology is determined based on physical connection information and port connection information.

[0054] The connection between each switch under test and other switches under test is the connection between the tester and the switch under test, as well as the connection between the switches under test and each other.

[0055] Optionally, the connection relationship between each switch under test (SUT) and other SUTs can be represented by the correspondence between the device identifiers of the SUTs and other SUTs, and the connection relationship between each SUT and each tester can be represented by the correspondence between the device identifiers of the SUTs and the device identifiers of the testers. Port connection information can be the information of the ports corresponding to two corresponding device identifiers.

[0056] Optionally, the physical topology includes device identifiers, the correspondence between device identifiers, port connection information, and hardware attributes.

[0057] Optionally, in test scenarios where network devices lack testing equipment, physical connection information includes the connection relationships between each switch under test and other switches under test.

[0058] Optionally, the physical topology, or actual topology, is represented using a JSON file. In the JSON file, the `switch` keyword represents the switch under test (DUT), and the "id" in `switch` represents the unique device identifier of the DUT. Multiple DUTs can be defined simultaneously. The device brand keyword can represent various parameters of the device, and "id" represents the unique device identifier of the tester. Multiple testers can be defined simultaneously. The `topology` keyword is mainly used to define the connections between the tester and the DUT, as well as between DUTs themselves. `sourcedutid` and `dstdutid` represent the device identifiers of the two connected devices, which can be a combination of DUT-DUT IDs or a combination of tester-DUT IDs. `sourcedutport` and `destdutport` represent the port information for the corresponding ID combination.

[0059] In some embodiments, matching each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology includes: In the first matching cycle, each logical topology is matched with a preset physical topology to determine the matched logical topology and the mapping relationship between each matched logical topology and physical sub-topology. In the Nth matching cycle, the remaining unmatched logical topologies are matched with the preset physical topologies to determine the matched logical topologies and the mapping relationship between each matched logical topology and physical sub-topology, until the mapping relationship between all logical topologies and physical sub-topologies is determined; N is an integer greater than 1.

[0060] In practical applications, testing multiple logical topologies may require multiple uses of physical topologies. After each matching cycle, physical topology matching can be performed before testing. After testing is completed, the remaining unmatched logical topologies are rematched with the preset physical topologies to obtain new matched logical topologies and the mapping relationship between each matched logical topology and physical sub-topology, and testing continues.

[0061] In some embodiments, tests are performed based on the test cases corresponding to each logical topology, using the mapping relationship between each logical topology and the physical sub-topology, including: For each matching cycle, based on the test cases corresponding to the logical topology of each match, tests are executed in parallel using the mapping relationship between the logical topology and the physical sub-topology of each match.

[0062] In practical applications, tests are performed sequentially for each matching cycle, following the order of the matching cycles.

[0063] See Figure 3 As shown, this application embodiment provides a flowchart of another automatic testing method for switches. Figure 1 As shown, the automatic testing method for the switch includes steps S301 to S304.

[0064] S301. Obtain each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; the network devices include at least one switch under test.

[0065] S302. In the first matching cycle, each logical topology is matched with a preset physical topology to determine the matched logical topology and the mapping relationship between each matched logical topology and the physical sub-topology.

[0066] Optionally, each logical topology is matched with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; including: The physical resource status database is called to determine the device occupancy status; the device occupancy status is used to indicate that a device in the physical topology is in an occupied state. Identify idle devices in the physical topology based on device occupancy status; Based on the idle devices in the physical topology, the logical topology to be matched is matched with the physical topology to determine the mapping relationship between the matched logical topology and the physical sub-topology.

[0067] The matching process between the logical topology and the preset physical topology in each matching cycle can be carried out in the manner described above.

[0068] Optionally, before calling the physical resource status library to determine the device occupancy status, the method further includes: marking the device as occupied when it is determined that the device in the physical topology is in an occupied state.

[0069] Optionally, the occupied state can be either currently executing a test or already occupied by a previously matched logical topology within the same matching cycle.

[0070] S303. In the Nth matching cycle, the remaining unmatched logical topologies are matched with the preset physical topologies to determine the matched logical topologies and the mapping relationship between each matched logical topology and physical sub-topology, until the mapping relationship between all logical topologies and physical sub-topologies is determined.

[0071] Optionally, the process of matching the remaining unmatched logical topologies with the preset physical topologies is consistent with the implementation principle of the first matching cycle.

[0072] S304. For each matching cycle, based on the test cases corresponding to the logical topology of each match, the tests are executed in parallel using the mapping relationship between the logical topology and the physical sub-topology of each match.

[0073] The embodiments of this application solve the problem of matching logical topology and physical topology in the process of automated testing, and at the same time, adopt a dynamic environment allocation method to enable test cases to be executed in parallel, thereby improving the efficiency of automated testing.

[0074] The process of determining the mapping relationship between each logical topology and physical sub-topology in this embodiment can be implemented through a matching module. The matching module includes a topology matching module and a dynamic topology allocation module.

[0075] The topology matching module includes: Input layer: Synchronously receives logical topology (i.e., the string naming logical topology, such as L_1_0_0) and physical topology. Physical topology is a topology graph, which can also be in JSON format. If the physical topology is a topology graph, it will also be converted to JSON format during the final matching.

[0076] Processing layer: Invokes the matching rule of "device identifier (correspondence between source ID and destination ID) + port connection information (source port and destination port) + test scenario"; Output layer: Generates a mapping table between logical topology and physical sub-topology (including network device IDs in logical topology, actual device IDs in physical sub-topology, and port mapping relationships), and pushes it synchronously to the dynamic topology allocation module and the testing module.

[0077] Module interaction: Upstream, it connects to the logical topology definition module and the physical topology definition module, while downstream, it provides basic topology relationship data to the dynamic topology allocation module.

[0078] The dynamic topology allocation module is a resource scheduling unit adapted to multiple test case scenarios. Its functions and working logic are as follows: Functional refinement: Based on the mapping table between logical topology and physical sub-topology output by the topology matching module, and combined with the current idle status of physical test resources, dynamic scheduling and topology configuration of test resources are realized for the topology requirements of different test cases, so as to avoid resource conflicts and improve resource utilization.

[0079] Workflow: (1) Triggering conditions: When loading new test cases, or after the topology matching module updates the mapping table between logical topology and physical sub-topology; (2) Processing layer: Read the topology requirements of the test cases (such as "two switches are interconnected, and each switch is connected to a test instrument port"); call the physical resource status database (records the occupancy status of the devices), filter idle resources; generate a topology resource allocation scheme based on the "test case priority + resource load balancing" rule; (3) Output layer: Push the allocated test topology configuration to the test module, and update the resource status database occupancy record at the same time.

[0080] Module interaction: The upstream receives the mapping table between logical topology and physical sub-topology, and the downstream outputs executable test topology resource configuration to the test module.

[0081] The embodiments of this application can dynamically schedule and configure test resources based on the mapping relationship between each logical topology and physical sub-topology, combined with the current idle status of physical test resources, and according to the topology requirements of different test cases, thereby avoiding resource conflicts and improving resource utilization.

[0082] This application's embodiments solve the problem of flexible topology matching in automated testing. Through logical topology naming design, physical topology representation design, and the use of topology matching and dynamic topology allocation modules, it achieves the rational utilization of automated resources and improves the efficiency of automated testing. This application's embodiments can achieve at least the following technical effects: (1) Topology matching accuracy optimization: By using the multi-dimensional matching rules of “device identifier (correspondence between source ID and destination ID) + port connection information (source port and destination port) + test scenario”, the tedious manual operation error is avoided, the topology matching accuracy reaches more than 9%, and the test failure rate caused by topology matching error is reduced by 90%.

[0083] (2) Enhanced multi-scenario testing adaptability: Supports interconnection scenarios of multiple types of devices such as switch under test-switch and tester-switch under test, and can adapt to the testing needs of the company's full range of switch products such as data center, campus network, and SMB, covering functional, performance and compatibility testing in different scenarios.

[0084] (3) Significantly optimized test resource utilization: The dynamic topology allocation module schedules based on the topology requirements of test cases and the idle status of resources, avoiding the idleness or conflict of physical resources, and making the overall utilization rate of test resources such as switches and testers more than 50%, and increasing the number of test cases that can be executed in parallel in a single batch by 2-3 times.

[0085] (4) Improved efficiency of parallel testing of multiple test cases: For the differentiated topology requirements of different test cases, the dynamic topology allocation module can automatically complete the rapid reuse and reconfiguration of resources. The topology preparation time when multiple test cases are executed in parallel is shortened from hours / test cases to seconds / test cases, and the overall cycle of batch testing is compressed by 50% to 60%.

[0086] This application belongs to the field of communication technology and is primarily applied to automated testing of network devices and related scenarios, specifically including: (1) Switch product testing scenarios: covering the factory functional testing, performance testing and compatibility testing of the company's data center switches, campus network switches and SMB switches. As the core module of the topology management of the automated testing system, it realizes the automatic correspondence between logic and actual topology.

[0087] (2) Continuous Integration (CI) Automated Testing Scenarios: Integrated into the CI process of switch development, when code submission triggers automated testing, the topology matching module quickly establishes the correspondence between the logical topology and the physical topology of the CI environment, and the dynamic topology allocation module automatically schedules idle test resources to achieve a fully automated closed loop of the testing process of "code submission - topology configuration - test execution".

[0088] (3) Switch operation and maintenance test scenario: In the fault reproduction and performance verification test during the switch operation and maintenance phase, it is used to quickly establish the correspondence between the logical topology and the actual operation and maintenance environment topology, thereby improving the efficiency and accuracy of operation and maintenance testing.

[0089] See Figure 4 As shown in the diagram, this application embodiment provides an automatic testing device 40 for a switch. The automatic testing device 40 for a switch includes: an acquisition module 401, a matching module 402, and a testing module 403.

[0090] The acquisition module 401 is used to acquire each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; the network devices include at least one switch under test; The matching module 402 is used to match each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; the physical topology includes at least one physical sub-topology; Test module 403 is used to perform tests based on the test cases corresponding to each logical topology, using the mapping relationship between each logical topology and the physical sub-topology.

[0091] Optionally, the automatic testing device for the switch further includes a logical topology definition module, and the network device further includes at least one tester; the logical topology definition module is used to determine the number of switches under test in the test scenario; determine the number of testers connected to each switch under test; determine the number of loopbacks of each switch under test; determine the number of computed connections between each switch under test and other switches under test; and determine the logical topology based on the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the number of computed connections between each switch under test and other switches under test.

[0092] Optionally, the logical topology definition module is used to sort the switches under test and determine the arrangement order of the switches under test; for each switch under test, based on the arrangement order, the number of connections between the switch under test and other switches under test excluding those arranged before the switch under test is determined as the calculated number of connections between the switch under test and other switches under test.

[0093] Optionally, the logical topology definition module is used to sequentially arrange the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the number of computed connections between each switch under test and other switches under test to determine the logical topology.

[0094] Optionally, the matching module 402 is used to match each logical topology with a preset physical topology in the first matching cycle to determine the matched logical topology and the mapping relationship between each matched logical topology and the physical sub-topology; in the Nth matching cycle, the remaining unmatched logical topology is matched with the preset physical topology to determine the matched logical topology and the mapping relationship between each matched logical topology and the physical sub-topology, until the mapping relationship between all logical topologies and physical sub-topologies is determined; N is an integer greater than 1.

[0095] Optionally, the test module 403 is used to perform tests in parallel based on the test cases corresponding to the logical topology of each match for each matching cycle, using the mapping relationship between the logical topology and the physical sub-topology of each match.

[0096] Optionally, the automatic testing device for the switch further includes a physical topology definition module, and the network device further includes at least one tester; the physical topology definition module is used to determine physical connection information; the physical connection information includes the connection relationship between each switch under test and other switches under test, and the connection relationship between each switch under test and each tester; determine port connection information; the port connection information includes the port information of the two ports corresponding to the connection relationship; and determine the physical topology based on the physical connection information and the port connection information.

[0097] In applications, the modules in the automatic testing device 40 of the switch can be software program modules, or they can be implemented by different logic circuits integrated in the processor, or they can be implemented by multiple distributed processors.

[0098] The automatic testing device 40 for the switch in this application embodiment can execute the method provided in this application embodiment. The implementation principle is similar. The actions performed by each module in the automatic testing device 40 for the switch in each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the automatic testing device 40 for the switch, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0099] See Figure 5 As shown, this application provides a schematic diagram of the structure of a terminal device 50. Figure 5 As shown, the terminal device 50 of this application embodiment includes: a memory 52, a processor 51, and a computer program 53 stored in the memory 52 and executable on the processor 51. When the processor 51 executes the computer program, it implements the steps of the methods of the various embodiments of this application.

[0100] Terminal device 50 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. Terminal device 50 may include, but is not limited to, a processor 51 and a memory 52. ​​Those skilled in the art will understand that terminal device 50 may also include more or fewer components, or combinations of certain components, or different components, such as input / output devices, network access devices, etc.

[0101] The processor 51 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0102] In some embodiments, memory 52 may be an internal storage unit, such as a hard disk or RAM. Memory 52 may be a removable / non-removable, volatile / non-volatile computer system storage medium; for example, memory 52 may be a non-volatile memory used for reading and writing non-volatile magnetic media. In other embodiments, memory 52 may be an external storage device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on terminal device 50. Memory 52 is used to store operating systems, applications, bootloaders, data, and other programs, such as program code for computer programs. Memory 52 may also be used to temporarily store data that has been output or will be output.

[0103] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0105] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the above-described method embodiments.

[0106] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0107] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium can also include combinations of the above types of memory.

[0108] This application provides a computer program product that, when run on a processor, enables the processor to execute the steps described in the various method embodiments above.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0111] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0112] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An automatic testing method for a switch, characterized in that, include: Obtain each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules; The network device includes at least one switch under test; Each logical topology is matched with a preset physical topology to determine the mapping relationship between each logical topology and the physical sub-topology; the physical topology includes at least one physical sub-topology; Based on the test cases corresponding to each logical topology, tests are performed using the mapping relationship between each logical topology and the physical sub-topology.

2. The automatic testing method for a switch according to claim 1, characterized in that, The network device also includes at least one tester; the logical topology is obtained in the following manner: Determine the number of switches to be tested in the test scenario; Determine the number of testers connected to each of the switches under test; Determine the number of loopbacks for each of the switches under test; Determine the number of computed connections between each of the switches under test and other switches under test; The logical topology is determined based on the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the number of computed connections between each switch under test and other switches under test.

3. The automatic testing method for a switch according to claim 2, characterized in that, The step of determining the number of calculated connections between each of the switches under test and other switches under test includes: Sort the switches under test to determine their arrangement order; For each of the switches under test, based on the arrangement order, the number of connections between the switch under test and other switches under test excluding those arranged before the switch under test is determined, and this number is used as the calculated number of connections between the switch under test and other switches under test.

4. The automatic testing method for a switch according to claim 2, characterized in that, The determination of the logical topology based on the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the calculated number of connections between each switch under test and other switches under test includes: The logical topology is determined by sequentially arranging the number of switches under test, the number of testers connected to each switch under test, the number of loopbacks of each switch under test, and the number of computed connections between each switch under test and other switches under test.

5. The automatic testing method for a switch according to claim 1, characterized in that, The step of matching each logical topology with a preset physical topology to determine the mapping relationship between each logical topology and physical sub-topology includes: In the first matching cycle, each logical topology is matched with a preset physical topology to determine the matched logical topology and the mapping relationship between each matched logical topology and physical sub-topology. In the Nth matching cycle, the remaining unmatched logical topologies are matched with the preset physical topologies to determine the matched logical topologies and the mapping relationship between each matched logical topology and physical sub-topology, until the mapping relationship between all logical topologies and physical sub-topologies is determined; N is an integer greater than 1.

6. The automatic testing method for a switch according to claim 5, characterized in that, The test cases based on each logical topology, which employ the mapping relationship between each logical topology and the physical sub-topology, are used to execute tests, including: For each matching cycle, based on the test cases corresponding to each matched logical topology, tests are executed in parallel using the mapping relationship between each matched logical topology and physical sub-topology.

7. The automatic testing method for a switch according to any one of claims 1-6, characterized in that, The network device also includes at least one tester; the physical topology is obtained as follows: Determine the physical connection information; the physical connection information includes the connection relationship between each of the switches under test and other switches under test, and the connection relationship between each of the switches under test and each of the test instruments. Determine the port connection information; the port connection information includes the port information of the two ports corresponding to the connection relationship; The physical topology is determined based on the physical connection information and the port connection information.

8. An automatic testing device for a switch, characterized in that, include: The acquisition module is used to acquire each logical topology; the logical topology is the logical network relationship of network devices in the test scenario generated based on preset naming rules. The network device includes at least one switch under test; A matching module is used to match each of the logical topologies with a preset physical topology to determine the mapping relationship between each of the logical topologies and the physical sub-topologies; the physical topology includes at least one physical sub-topology; The testing module is used to perform tests based on the test cases corresponding to each logical topology and using the mapping relationship between each logical topology and physical sub-topology.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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