Tcam-based longest prefix matching storage device, method and chip

Abstract

The application discloses a longest prefix matching storage device, method and chip based on TCAM, and relates to the technical field of data communication. The device comprises a TCAM and an AD SRAM, the TCAM comprises a plurality of memory banks and is virtually divided into a non-tail sub-table and a tail sub-table; the non-tail sub-table stores non-tail sub-sections in the LPM common prefix which are not masked and need to be accurately matched with full memory bank bit width; the tail sub-table stores tail sub-sections in the LPM common prefix with masks; each non-tail sub-section of the same common prefix is stored in an independent entry; and the AD SRAM corresponding to the tail sub-section stores a non-common prefix subset pointer. The application solves the problems of TCAM resource waste and limited LPM rule storage capacity in the prior art, improves the TCAM resource utilization rate and the chip LPM capacity specification through sub-table division and sub-section sharing.

Description

Technical Field

[0001] This application relates to the field of data communication technology, and in particular to a longest prefix matching method based on TCAM, a storage device, and a network switching chip. Background Technology

[0002] Longest Prefix Match (LPM) is an algorithm and concept widely used in computer networks, especially in the field of IP routing. It is typically used to find the routing entry in a routing table that best matches the destination IP address.

[0003] In the current implementation, LPM prefixes are typically stored and retrieved in two stages: a complete LPM rule is divided into a common prefix and non-common prefixes. The common prefix is ​​extracted based on the prefix binary tree and stored in the ternary content-addressable memory (TCAM). Multiple non-common prefixes that share the same common prefix are stored as a subset in the static random-access memory (SRAM).

[0004] During the lookup, the destination IP address of the packet is used as the key to first search the TCAM to find the common prefix and obtain a pointer to the subset of non-common prefixes. Then, the non-common prefixes within the subset are matched to obtain the final result. Since the number of non-common prefixes in a subset is very limited, such as less than 10, the matching can be completed quickly using hardware methods such as Content Addressable Memory (CAM).

[0005] The existing IPv6 Longest Prefix Matching (LPM6) uses a two-stage storage lookup scheme of TCAM and SRAM. Because the length of the LPM common prefix is ​​unpredictable, TCAM needs to reserve storage resources based on the longest prefix length, resulting in a large amount of wasted TCAM storage lines for short prefixes. Although the industry provides two static configuration modes, lpm6_64 and lpm6_128, users cannot accurately predict the prefix length, limiting their usability. Furthermore, each TCAM's storage bank is equipped with a corresponding address data static random access memory (AD SRAM), but when storing the LPM common prefix, only the AD SRAM of the last bank is effectively used, while the AD SRAMs of the remaining banks are idle, further exacerbating the waste of storage resources. Summary of the Invention

[0006] This application discloses a longest prefix matching LPM storage device, an LPM rule writing method, an LPM lookup method, a network switching chip, and a computer-readable storage medium based on a tri-state content addressing memory (TCAM). The aim is to solve the technical problems of TCAM storage resource waste and limited LPM rule storage capacity in the prior art, and to improve TCAM resource utilization and chip LPM capacity specifications.

[0007] The core technical solution of this application is as follows: Based on one aspect of the embodiments of this application, this application provides a longest prefix matching storage device based on TCAM, including TCAM and address data static random access memory (ADSRAM) associated with TCAM. The TCAM includes multiple banks for storing the common prefix of LPM; The TCAM is virtually divided into a nonlast table and a last table. The nonlast table stores nonlast segments in the LPM common prefix that are unmasked and require precise matching of the entire storage block bit width. The last table stores last segments in the LPM common prefix that are masked.

[0008] The AD SRAM associated with the storage bank corresponding to the tail sub-table is used to store pointers to the non-common prefix subsets corresponding to the common prefix.

[0009] Furthermore, each non-tail segment split from the same LPM common prefix is ​​stored in a non-tail sub-table as an independent entry. The byte width of the entries in both the non-tail sub-table and the tail sub-table corresponds to the byte width of one or more memory banks plus AD SRAM. A memory bank and a corresponding associated AD SRAM are allocated and used in pairs. The entry widths of both are consistent, and the number of TCAM memory banks corresponding to the entries is configurable. The granularity of segment division of the common prefix can be adjusted by adjusting the number of memory banks.

[0010] Furthermore, in the TCAM's multiple storage units, in the initial state, at least one storage unit is allocated to the non-tail sub-table, at least one storage unit is allocated to the tail sub-table, and the remaining storage units serve as an idle resource pool; when the storage units occupied by the non-tail sub-table or the tail sub-table are full, storage units are allocated from the idle resource pool for expansion.

[0011] Furthermore, the number of non-tail segments and tail segments split is determined based on the mapping between the length of the LPM common prefix and the bit width of the TCAM memory; the longer the common prefix, the more non-tail segments are split.

[0012] Based on the above-mentioned storage device, this application provides two specific implementation forms: In the first implementation, each non-tail sub-segment and tail sub-segment carries a sub-segment identifier, which is used to mark the sequence number of the sub-segment in its respective common prefix; in the non-tail sub-table, the same non-tail sub-segments of different common prefixes share the same sub-segment table entry, and the AD SRAM corresponding to the shared sub-segment stores a preset special value; the AD SRAM corresponding to the non-shared sub-segment stores the unique rule identifier of the common prefix to which the sub-segment belongs.

[0013] In the second implementation, non-tail segments and tail segments do not carry segment identifiers, and the AD SRAM corresponding to non-tail segments does not store rule identifiers; non-tail segments with the same value in the non-tail sub-table are stored only once for multiple common prefix rules to share.

[0014] Based on one aspect of the embodiments of this application, this application also provides a method for writing the longest prefix matching rule based on the above-mentioned storage device, the core steps of which include: The process involves obtaining the LPM common prefix rules to be issued, dividing the rules into tail segments according to a preset format, or at least one non-tail segment and one tail segment; writing all non-tail segments into the TCAM storage corresponding to the non-tail segment table as table entries; and writing the tail segments into the TCAM storage corresponding to the tail segment table as table entries. Depending on the implementation of the storage device, the writing method has different specific procedures, including rule identifier allocation, segment identifier addition, tail segment uniqueness verification, non-tail segment sharing, and reference count management.

[0015] This application also provides a longest prefix matching lookup method based on the aforementioned storage device. The core steps include: obtaining the destination address of the message to be matched; dividing and splitting it into multiple address segments corresponding to the common prefix segment according to a preset format; matching each address segment corresponding to the non-tail segment with entries in the non-tail sub-table; and matching each address segment corresponding to the tail segment with entries in the tail sub-table. If all address segments match successfully, obtaining the pointer to the non-common prefix subset stored in the AD SRAM corresponding to the tail segment, thus completing the lookup. Depending on the implementation of the storage device, the lookup method has different matching verification logic, including rule identifier verification and shared segment value verification.

[0016] In addition, this application also provides a network switching chip, which includes any of the above-mentioned longest prefix matching storage devices based on TCAM; and a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the above-mentioned longest prefix matching rule writing methods and / or search methods.

[0017] By adopting the technical solution of this application, TCAM space waste can be significantly reduced and chip LPM capacity specifications can be improved in scenarios where most LPM common prefixes are short prefixes. By flexibly configuring the number of storage bodies corresponding to sub-tables, LPM common prefixes of different lengths can be adapted without statically limiting the prefix length. At the same time, through the non-tail segment sharing mechanism, the utilization rate of TCAM resources can be further improved, and more LPM rules can be stored under the same physical resources.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an example diagram illustrating resource waste caused by storing the LPM common prefix in TCAM technology. Figure 2 This is a schematic diagram of the structure for storing the common prefix of LPM after TCAM is virtually divided into non-tail sub-table and tail sub-table in one embodiment of this application; Figure 3 This is a schematic diagram of the storage structure using the first implementation form (the common prefix is ​​divided into four formats, A, B, C, and D, according to its length) in one embodiment of this application; Figure 4 This is an example diagram illustrating the first implementation with segment identifiers and rule identifiers in one embodiment of this application; Figure 5 This is a schematic diagram of the second implementation form (the public prefix is ​​divided into four formats: A', B', C', and D' according to its length) in one embodiment of this application. Detailed Implementation

[0021] The exemplary embodiments will now be described in detail. When the description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification; they are merely exemplary embodiments of apparatuses and methods consistent with some aspects of this specification.

[0022] The two-stage storage scheme for Longest Prefix Matching (LPM) is based on splitting the complete LPM routing rule into two parts: common prefix and non-common prefix. These parts are stored in different devices to achieve efficient lookup. The Tri-State Content Addressing Memory (TCAM) is used to store the common prefix extracted from the prefix binary tree, enabling fast coarse matching. Each common prefix corresponds to a subset of multiple non-common prefixes in Static Random Access Memory (SRAM). After the TCAM matches a common prefix, a fine match is performed in the corresponding SRAM subset to obtain the longest prefix matching result. This scheme can save expensive TCAM storage resources while ensuring lookup efficiency.

[0023] Table 1 shows an example of LPM prefix two-segment storage. Looking at the example in Table 1, each common prefix in TCAM corresponds to a unique subset of non-common prefixes in SRAM. Common prefixes are indicated by "prefix + ... The format is " / length", where " The quotation marks "" represent wildcards, and the length indicates the number of bits in the prefix. Non-common prefixes in SRAM subsets are represented as "specific bit string / length," all of which are fixed-length, fine-grained prefixes. For example, the common prefix RamSubset_1 00 in TCAM... / 2 represents all addresses whose first two bits are "00" and belong to this group, corresponding to 00000 / 5 and 00011 / 5 in the SRAM subset. This means that a precise 5-bit prefix match is required within this group; RamSubset_2 001 / 3 corresponds to the address group whose first 3 bits are "001", with subsets being 00110 / 5 and 00111 / 5; RamSubset_3 01 / 2 corresponds to an address group whose first two bits are "01", containing three 5-bit non-common prefixes; RamSubset_4 1 / 1 corresponds to the address group where the first bit is "1", which contains three 5-bit non-common prefixes. All addresses must first be matched with the common prefixes through TCAM to determine their subset, and then the final matching is completed through SRAM.

[0024] Table 1

[0025] Figure 1 This is a schematic diagram of a traditional LPM prefix two-segment storage. (Example:) Figure 1For example, consider a TCAM with four banks. Each TCAM bank is 5 bytes (5B) wide. The four banks are combined to a width of 20B to accommodate the longest prefix (16B IP address + 2B VPNID) of the Longest Prefix Match for IPv6 (LPM6). The diagram shows four prefixes. Prefix_1 is less than 5B, but it needs to occupy one line in each of the four banks. Prefix_2 is less than 10B. Prefix_2_1 is the first complete 5B, occupying one line in bank0. The remaining part occupies one line in bank1, and banks2 and 3 also each occupy one line. For prefix_3, the first complete 5B prefix_3_1 occupies one line in bank0, the second complete 5B prefix_3_2 occupies one line in bank1, the third complete 5B prefix_3_3 occupies one line in bank2, and the remaining part less than 5B occupies one line in bank3. As shown in the figure, prefix1, prefix2, and prefix_4 all have a full 5B of unused bank space.

[0026] Based on Table 1 and Figure 1 As the example shows, the common prefix of LPM can be very short (sparse prefix binary tree) or very long (dense prefix binary tree), which cannot be predicted in advance. Therefore, in traditional storage methods, TCAM storage resources are reserved based on the longest prefix length. When there are many short prefixes, TCAM space waste becomes significant. Later, the industry proposed two modes: lpm6_64 and lpm6_128. lpm6_64 only reserves 64 bits of width for each prefix, which can reduce resource waste. The limitation is that the issued LPM prefix length cannot exceed 64 bits (one lpm6_128 mode prefix space can hold two lpm6_64 mode prefixes). However, these two modes can only be selected statically, and in many cases, users cannot accurately predict whether there will be LPM6 prefixes with a width exceeding 64 bits.

[0027] like Figure 1For example, each TCAM bank has a corresponding AD SRAM (Address Data SRAM). The AD SRAM is a dedicated SRAM module in TCAM used to store the matching result address and associated data. However, when storing the LPM common prefix, only the AD SRAM of the last bank will store the corresponding data, such as the pointer address pointing to the subset. The AD SRAMs of the previous few banks are idle, which also causes a waste of resources.

[0028] To address the waste of TCAM storage resources caused by the traditional two-segment LPM prefix storage and to improve TCAM resource utilization and chip LPM capacity specifications, this application provides a longest prefix matching storage device based on TCAM and an LPM writing and matching lookup method based on the storage device. The following describes the method in detail with reference to embodiments.

[0029] Example 1: Longest Prefix Matching Storage Device Based on TCAM This embodiment provides a longest prefix matching storage device based on TCAM to solve the technical problems of resource waste and inflexibility in adapting to prefixes of different lengths when storing LPM common prefixes in existing technologies. The specific structure is as follows: The device includes a TCAM and an AD SRAM associated with the TCAM. The TCAM is a ternary content-addressable memory, and the AD SRAM is an address data static random access memory (AD SRAM). The AD SRAM is an SRAM module in the TCAM specifically used to store the matching result address and associated data.

[0030] The TCAM includes multiple banks. This embodiment uses a TCAM containing 4 banks as an example for detailed explanation. Each bank is 5 bytes wide. The 4 banks can be combined to form a 20-byte width, which can accommodate the longest prefix of the Internet Protocol Version 6 (IPv6) LPM (LPM6) (16-byte IP address + 2-byte Virtual Private Network ID (VPNID)). This number of banks is only an example. In actual applications, it can be flexibly adjusted according to hardware resource requirements.

[0031] The TCAM is used to store the common prefix of LPM. Its core improvement is that the TCAM is virtually divided into two sub-tables, namely the nonlast sub-table and the last sub-table.

[0032] like Figure 2 For example, the non-tail sub-table is used to store non-tail segments in the LPM common prefix that have no mask and require full-width exact matching, such as Prefix_2_1, Prefix_3_1, Prefix_3_2, Prefix_3_3, Prefix_4_1, and Prefix_4_2. These segments do not contain mask bits and need to be matched with the corresponding part of the matching keyword with full-width exact matching. The tail sub-table is used to store tail segments in the LPM common prefix that have a mask, such as Prefix_1, Prefix_2, Prefix_3, and Prefix_4. These segments contain mask bits and are directly associated with pointers to non-common prefix subsets.

[0033] Each non-tail segment derived from the same LPM common prefix is ​​stored as an independent entry in the non-tail sub-table, ensuring that each non-tail segment can participate in matching independently. Figure 2 For example, the non-tail segments Prefix_3_1, Prefix_3_2, and Prefix_3_3 of the same LPM common prefix 3 are all stored as independent entries in the non-tail sub-table. The byte width of the entries in the non-tail sub-table and the tail sub-table corresponds to the byte width of one or more memory banks plus AD SRAM, and the memory banks and AD SRAM are allocated and used in pairs, that is, one memory bank corresponds to one AD SRAM module, ensuring the synchronization of entry storage and associated data storage. At the same time, the entry widths of the non-tail sub-table and the tail sub-table are consistent, and the number of TCAM memory banks corresponding to the entries of both is configurable. By adjusting the corresponding number of memory banks, the granularity of the common prefix segment division can be flexibly adjusted. For example, the segment division granularity can be adjusted to 2 memory banks (10B width) or 4 memory banks (20B width) to adapt to the requirements of different lengths of common prefixes.

[0034] The core function of the AD SRAM associated with the storage bank corresponding to the tail sub-table is to store pointers to the non-common prefix subset associated with the common prefix corresponding to the tail sub-segment. These pointers are used to point to the non-common prefix subset stored in Static Random-Access Memory (SRAM) for subsequent lookup processes. The AD SRAM corresponding to the non-tail sub-table stores rule identifiers or preset special values ​​depending on the specific implementation of the device.

[0035] Furthermore, in the TCAM's multiple storage banks, in the initial state, at least one storage bank is allocated to a non-tail sub-table, at least one storage bank is allocated to a tail sub-table, and the remaining storage banks serve as an idle resource pool. Taking four storage banks as an example, in the initial state, storage bank 0 (bank0) can be allocated to a non-tail sub-table, storage bank 3 (bank3) can be allocated to a tail sub-table, and storage banks 1 (bank1) and 2 (bank2) can serve as an idle resource pool. When the storage bank occupied by the non-tail sub-table (storage bank 0) is full, storage banks are allocated sequentially from the idle resource pool (storage banks 1 and 2) to the non-tail sub-table to complete the expansion. Similarly, when the storage bank occupied by the tail sub-table (storage bank 3) is full, storage banks are also allocated from the idle resource pool for expansion, ensuring that the sub-table storage capacity can be flexibly expanded to adapt to the storage needs of more LPM common prefix rules.

[0036] Furthermore, the number of non-tail segments and tail segments split is determined based on the mapping between the length of the LPM common prefix and the bit width of the TCAM memory bank. The longer the common prefix length, the more non-tail segments are split. Taking four memory banks (each 5B, 40 bits) as an example, the mapping relationship between the common prefix length and the number of segments split is as follows: When the common prefix length is in the range [0, 37], only one tail segment is split, and there is no explicit non-tail segment; when the common prefix length is in the range [38, 75], one non-tail segment and one tail segment are split; when the common prefix length is in the range [76, 113], two non-tail segments and one tail segment are split; when the common prefix length is greater than 113, three non-tail segments and one tail segment are split. If the number of storage units corresponding to the sub-table entries is adjusted (e.g., adjusted to 2 storage units, 10B, 80bit), the mapping relationship between the common prefix length and the number of sub-segments will be adjusted accordingly. For example, when the common prefix length is in the range [0,79], only 1 tail sub-segment will be split; when the common prefix length is greater than 79, 1 non-tail sub-segment and 1 tail sub-segment will be split.

[0037] Analysis of the technical effects of this embodiment: In the prior art, regardless of the length of the common prefix, each sub-segment needs to occupy one row in all memory banks, resulting in a large amount of idle memory space corresponding to short prefixes and wasting TCAM resources. However, this embodiment virtually divides the TCAM into a non-tail sub-table and a tail sub-table, storing only the non-tail sub-segments (without masks) of the common prefix in the non-tail sub-table and the tail sub-segments (with masks) in the tail sub-table. Multiple non-tail sub-segments of the same common prefix can occupy the same memory bank without occupying space in all memory banks, effectively reducing TCAM resource waste. At the same time, by setting the idle resource pool and configuring the number of memory banks, flexible expansion of the sub-table capacity and flexible adjustment of the sub-segment division granularity are realized, which can adapt to LPM common prefixes of different lengths. This solves the problem that the static mode in the prior art cannot adapt to prefixes of unknown length, improving the TCAM resource utilization and chip LPM capacity specifications.

[0038] Example 2: Longest prefix matching storage device based on TCAM (first implementation) This embodiment, based on the basic structure of Embodiment 1, provides a first specific implementation form, suitable for scenarios with sufficient hardware resources and high requirements for mismatch protection. Specific improvements are as follows: like Figure 3 For example, in this embodiment, the public prefixes to be issued are categorized and divided according to the following preset public prefix rule formatting rules: When the length of the common prefix is ​​in the range [0,37], only one tail segment is split out, corresponding to Format D. When the length of the common prefix is ​​in the range [38, 75], it is split into one non-tail sub-segment and one tail sub-segment, corresponding to Format C. When the length of the common prefix is ​​in the range [76, 113], it is split into 2 non-tail segments and 1 tail segment, corresponding to Format B. When the length of the common prefix is ​​greater than 113, it is split into 3 non-tail segments and 1 tail segment, corresponding to Format A.

[0039] Each non-tail and tail sub-segment carries a sub-segment identifier, which marks the sub-segment's sequence number within its common prefix, ensuring differentiation between different sub-segments and avoiding mismatches. Taking four memory banks (40 bits each) as an example, the sub-segment identifier uses only 2 bits to distinguish the four sub-segments (the sequence number RoundID ranges from 0 to 3). After combining the sub-segment identifier and the sub-segment value, padding is applied according to the bit width of the TCAM memory bank to ensure matching compatibility.

[0040] In the non-tail sub-table, identical non-tail segments from different common prefixes can share the same sub-segment entry. That is, if multiple common prefixes have the same non-tail segment value, they do not need to be stored repeatedly; only one entry is stored for all related common prefixes to share, thereby further reducing the storage size of non-tail segments and improving TCAM resource utilization. For shared non-tail segments, a preset special value is stored in their corresponding ADSRAM. For non-shared non-tail segments (i.e., non-tail segments belonging only to a certain common prefix), a unique rule identifier for the common prefix to which the segment belongs is stored in its corresponding AD SRAM. This rule identifier is assigned by the software and is used to uniquely identify a common prefix rule, ensuring that the corresponding common prefix can be accurately associated during matching.

[0041] Figure 4 The diagram shows an example of the first type of common prefix storage structure. The diagram contains 4 prefixes, where the non-tail sub-fields prefix_3_1 and prefix_4_1 of prefix 3 and prefix 4 share a non-tail sub-table entry.

[0042] Prefix 1 is format D, with only one tail sub-segment prefix_1, identified as 0 (located at the end). It is stored in the tail sub-table in bank3, and the corresponding position in the associated AD SRAM (AD3) stores a subset pointer (Subset Pointer, SubPtr) for prefix 1. Since the sum of the bits of prefix_1 and the sub-segment identifier is less than 40 bits, bit padding is required before the sub-segment identifier. Similarly, bit padding is also required for prefix 2 and prefix 3, which will not be elaborated further below. Prefix 2 is in format C, consisting of two parts: prefix_2 and prefix_2_1. The non-tail sub-segment prefix_2_1 and sub-segment identifier 0 are stored in the table entry of the non-tail sub-table in bank0. The table entry is associated with the corresponding position of AD SRAM (AD0) to store the rule identifier (R2) of prefix 2. The tail sub-segment prefix_2 and sub-segment identifier 1 are stored in the tail sub-table in bank3. The corresponding position of AD SRAM (AD3) to store the subset pointer (Subset2) of prefix 2.

[0043] Prefix 3 is format A, consisting of four parts: prefix_3, prefix_3_1, prefix_3_2, and prefix_3_3. The non-tail sub-field prefix_3_1 and sub-field identifier 0 are stored in the entry of the non-tail sub-table of bank0. The corresponding AD SRAM (AD0) associated with this entry stores a preset special value 0xFFFF, indicating that this entry is a shared entry. The non-tail sub-field prefix_3_2 and sub-field identifier 1 are stored in the entry of the non-tail sub-table of bank0. The corresponding AD SRAM (AD0) associated with this entry stores the rule identifier R3 of prefix 3, indicating that this entry is a non-shared entry. Similarly, prefix_3_3 and sub-field identifier 2 are stored in the AD SRAM (AD0) associated with the entry of the non-tail sub-table of bank0, storing the rule identifier R3 of prefix 3, indicating that this entry is a non-shared entry. The tail segment prefix_3 and the sub-segment identifier 3 are stored in the tail sub-table in bank3, and the corresponding position in the associated AD SRAM (AD3) stores the pointer to the subset of prefix 3 (Subset3).

[0044] Prefix 4 is format B, consisting of three parts: prefix_4, prefix_4_1, and prefix_4_2. The non-tail sub-field prefix_4_1 and its sub-field identifier 0 share an entry with prefix_3_1 and its sub-field identifier 0 of prefix 3. The corresponding ADSRAM (AD0) stores a preset special value 0xFFFF, indicating that this entry is a shared entry. The non-tail sub-field prefix_4_2 and its sub-field identifier 1 are stored in the entry of the non-tail sub-table in bank0. The corresponding AD SRAM (AD0) stores the rule identifier R4 of prefix 4, indicating that this entry is a non-shared entry. The tail sub-field prefix_4 and its sub-field identifier 2 are stored in the tail sub-table in bank3. The corresponding position in the associated AD SRAM (AD3) stores a subset pointer (Subset4) of prefix 4.

[0045] To achieve shared management of non-tail segments, this embodiment also needs to maintain a reference count for the non-tail segments. The reference count is used to record how many common prefix rules reference the shared segment. There are three specific implementation methods for its storage, which can be flexibly selected according to the chip hardware resources: Method 1: The software maintains a global reference count table, stored in on-chip SRAM. This table is indexed by "non-tail segment values," with each index corresponding to a record containing the reference count of that segment and the associated set of rule identifiers (when shared). When the software performs segment sharing or deletion operations, it synchronously updates the count in this table. The TCAM memory and the associated AD SRAM only store the segment value and associated data (special value 0xFFFF or rule identifier), without needing to store the reference count separately.

[0046] Method 2: Utilize the free space of the AD SRAM attached to the TCAM for storage. Each non-tail segment corresponds to a storage unit in the AD SRAM. In addition to storing the rule identifier or the special value 0xFFFF, some bits (such as 8 bits or 16 bits) can be reserved for storing the reference count. This method does not require additional SRAM resources and is suitable for scenarios with limited hardware resources.

[0047] Method 3: Dedicated reference register. A dedicated reference register is allocated to each non-tail segment. The register address corresponds one-to-one with the storage address of the segment in the TCAM memory. The software reads and updates the reference count by accessing this register. This method has fast read and write speed and is suitable for scenarios with high performance requirements.

[0048] Analysis of the technical effects of this embodiment: Based on embodiment one, this embodiment adds sub-segment identifiers and rule identifiers, and simultaneously implements non-tail sub-segment sharing and reference counting management, forming a triple mismatch protection mechanism of "sub-segment identifier + rule identifier + shared segment verification". This can effectively avoid mismatches of sub-segments with different common prefixes (such as mismatches caused by sub-segments with the same value but different rules belonging to different common prefixes), and the risk of mismatches is extremely low. At the same time, the non-tail sub-segment sharing mechanism further compresses the storage volume and maximizes the utilization of TCAM resources. More LPM common prefix rules can be stored under the same physical resources. The three implementation methods of reference counting can be adapted to different hardware resource scenarios, improving the flexibility and applicability of the device.

[0049] Example 3: Longest prefix matching storage device based on TCAM (second implementation) This embodiment, based on the basic structure of Embodiment 1, provides a second specific implementation form, suitable for scenarios with limited hardware resources and moderate requirements for mismatch protection. Specific improvements are as follows: Figure 5 This is a schematic diagram of the common prefix storage structure using the second implementation method in this embodiment. Unlike Embodiment 2, in this embodiment, the non-tail subfield and the tail subfield do not carry subfield identifiers, simplifying the subfield structure and reducing bit occupancy; at the same time, the AD SRAM corresponding to the non-tail subfield does not store rule identifiers, further saving AD SRAM storage resources.

[0050] In the non-tail sub-table, non-tail sub-fields with the same value are stored only once, so that multiple common prefix rules can share them without duplicate storage. This reduces the storage size of non-tail sub-fields and improves TCAM resource utilization.

[0051] In this embodiment, the segmentation format of the common prefix is ​​adjusted according to the memory bank width. Taking four memory banks (each 40 bits) as an example, the mapping relationship between the length of the common prefix and the number of segment splits is as follows: When the length of the common prefix is ​​in the range [0,39], only one tail segment is split out (format D'). When the length of the common prefix is ​​in the range [40, 79], split it into one non-tail sub-segment and one tail sub-segment (format C'). When the length of the common prefix is ​​in the range [80, 119], it is split into 2 non-tail segments and 1 tail segment (format B'). When the length of the common prefix is ​​greater than 119, it is split into 3 non-tail sub-segments and 1 tail sub-segment (format A').

[0052] Among them, the tail subfield corresponding to format A' needs to be padded with [128,159] bits (32 bits) because the common prefix length corresponding to format A' is >119 bits, and the key bit width corresponding to the tail subfield is 120~127 bits (8 bits in total), which is less than 40 bits. Padding with 32 bits can make the total bit width of the tail subfield 40 bits, which is compatible with the bit width requirements of TCAM storage.

[0053] This embodiment, based on embodiment one, removes the sub-segment identifier and rule identifier, reducing hardware resource consumption and making it suitable for scenarios with limited hardware resources. At the same time, it retains the sharing mechanism for non-tail sub-segments, which can effectively reduce TCAM resource waste and improve storage efficiency. Although the mismatch protection relies solely on "matching shared segments with sub-keywords", the risk of mismatch is slightly higher than in embodiment two. However, the process is simple, requires no identifier management, and the search latency is basically unaffected. It can improve TCAM resource utilization and increase LPM rule storage capacity even with limited hardware resources.

[0054] Example 4: Longest prefix matching rule writing method (corresponding to the device in Example 2) This embodiment provides a method for writing the longest prefix matching rule based on the device described in Embodiment 2. This method distributes the LPM common prefix rule to the non-tail sub-table and tail sub-table of the TCAM, ensuring the uniqueness, sharing, and correctness of the stored segments. The specific steps are as follows: S1. Obtain the LPM common prefix rule to be issued, divide the rule according to the preset common prefix rule format, and split the common prefix rule into a tail segment (corresponding to format D), or at least one non-tail segment and one tail segment (corresponding to format A, B or C).

[0055] Specifically, the preset common prefix rule format is determined based on the bit width of the TCAM storage bank and the sub-table configuration. Taking four storage banks (each 40 bits) as an example, the preset format is divided into four types: Format A (common prefix length > 113 bits), which is split into three non-tail segments and one tail segment; Format B (common prefix length is in the range [76, 113]), which is split into two non-tail segments and one tail segment; Format C (common prefix length is in the range [38, 75]), which is split into one non-tail segment and one tail segment; and Format D (common prefix length is in the range [0, 37]), which is split into only one tail segment.

[0056] Meanwhile, the software assigns a unique rule identifier value to each public prefix rule to be issued. The correspondence between the rule identifier and the public prefix rule is stored in a "rule identifier-public prefix rule" mapping table maintained by the software. This mapping table can be stored in the chip's on-chip memory (such as SRAM) or in an external storage medium for the software to query and update. It is also used to verify the legality of the match during the search process.

[0057] In addition, a segment identifier is added to each non-tail segment and tail segment obtained from the splitting. The segment identifier is used to mark the sequence number of the segment in the common prefix rule (e.g., the identifiers of the 3 non-tail segments are 0, 1, and 2, and the identifier of the tail segment is 3). If the bit width of the tail segment plus the segment identifier is less than the bit width of the TCAM storage, it is padded to the bit width of the TCAM storage. For example, the common prefix 0x1234 5678 0000 0000 0000 0000 0000 0000 / 16 corresponds to format D, with only one tail segment. The actual value sent is 0x1234 5678 00, and the mask is 0xffff ffff 03. The TCAM value and the mask are both filled to 40 bits to ensure matching compatibility.

[0058] S2. Before executing the non-tail segment write, first check if a tail segment with the same value already exists in the tail segment table. If it already exists, adjust the length of the public prefix rule to be issued, re-split the non-tail segment and the tail segment, and then start executing from step S1. If it does not exist, execute the non-tail segment write operation.

[0059] Specifically, duplicate segments are not allowed in the tail sub-table. The core reason is that the tail segment is the "masked tail" of the common prefix, directly associated with the subset pointer. If duplicate tail segments exist, multiple common prefix rules will point to the same subset, causing lookup errors. Therefore, the tail segment must be unique. When the tail segment of the common prefix to be issued (the tail segment divided according to the current format) already exists in the tail sub-table, the boundary between "common prefix and non-common prefix" is redefined by shortening or lengthening the common prefix, and then the non-tail segments and tail segments of the common prefix are re-extracted, ensuring that the newly extracted tail segments do not exist in the tail sub-table. The purpose of adjusting the length of the common prefix is ​​twofold: first, to ensure that each tail segment in the tail sub-table is unique, avoiding subset pointer confusion caused by multiple common prefix rules sharing a single tail segment; second, to ensure that the division of the common prefix conforms to the sub-table storage logic of this application, ensuring that non-tail segments can be shared and tail segments are unique, thereby improving TCAM resource utilization and avoiding mismatches.

[0060] S3. Write all the non-tail segments obtained from the splitting into the TCAM storage body corresponding to the non-tail sub-table in the form of table entries; refer to Figure 4 For example, for each non-tail segment with an added segment identifier, first check if a non-tail segment with the same value already exists in the non-tail segment table; if it already exists, share the stored segment table entry, synchronously update the reference count corresponding to the non-tail segment, and if the segment is being shared for the first time, replace the rule identifier stored in its AD SRAM with a preset special value (such as 0xFFFF); if it does not exist, write the non-tail segment as an independent table entry to an empty position in the non-tail segment table, store the unique rule identifier of the common prefix rule to which the non-tail segment belongs in its corresponding AD SRAM, and set the reference count of the non-tail segment to 1.

[0061] Specifically, the update method for the reference count is determined by its storage method: If method one (software maintaining a global reference count table) is used, the software increments the reference count by 1 upon sharing, and simultaneously changes the rule identifier in the AD SRAM to 0xFFFF upon the first sharing; if method two (AD SRAM free space stores the count), the reserved count bits in the AD SRAM are directly updated; if method three (dedicated count register) is used, the corresponding register value is directly updated. For example, there are 4 common prefix rules, where the non-tail field 1 value of 3 rules is R_1, and the non-tail field 2 value of 2 rules is R_2. Through the sharing mechanism, the 3 repeated R_1 non-tail fields share one field table entry, and the 2 repeated R_2 non-tail fields share one field table entry. The 4 rules only need to store 9 field table entries in the non-tail sub-table instead of 12, significantly saving TCAM space.

[0062] S4. Write the obtained tail segments into the TCAM storage body corresponding to the tail sub-table in the form of table entries, and at the same time store the pointers of the non-common prefix subsets corresponding to the common prefix rule in the AD SRAM corresponding to the tail segments.

[0063] In addition, when the storage space occupied by the non-tail sub-table or the tail sub-table is full, storage space is first allocated from the free resource pool to complete the expansion of the non-tail sub-table or the tail sub-table, and then the corresponding sub-segment write operation is performed to ensure that all sub-segments to be sent can be stored normally.

[0064] The technical effects of this embodiment are as follows: In the prior art, when TCAM stores the common prefix of LPM, short prefixes cause a large amount of storage space waste and cannot flexibly adapt to prefixes of different lengths. At the same time, without a sharing mechanism, duplicate sub-segments will further waste resources. The writing method of this embodiment avoids subset pointer confusion and lookup errors by verifying the uniqueness of the tail sub-segment. By sharing the non-tail sub-segment and managing reference counting, the storage volume of the non-tail sub-segment is maximized and the TCAM resource utilization is improved. By adding sub-segment identifiers and rule identifiers, support is provided for the protection against mismatches in the subsequent lookup process. At the same time, the expansion mechanism of the idle resource pool ensures that more LPM rules can be issued normally, solving the problem of limited storage capacity in the prior art and achieving the technical goals of "reducing resource waste, increasing storage capacity, and ensuring matching correctness".

[0065] Example 5: Longest prefix matching rule writing method (corresponding to the device in Example 3) This embodiment provides a method for writing the longest prefix matching rule based on the device described in Embodiment 3. It is suitable for scenarios with limited hardware resources, and the process is simplified. The specific steps are as follows: S1. Obtain the LPM common prefix rule to be issued, divide the rule according to the preset common prefix rule format, and split the common prefix rule into a tail segment or at least one non-tail segment and a tail segment.

[0066] Specifically, the preset common prefix rule format is determined based on the bit width of the TCAM memory bank. Taking four memory banks (each 40 bits) as an example, there are four preset formats: Format A' (common prefix length > 119 bits), split into three non-tail segments and one tail segment; Format B' (common prefix length in the range [80, 119]), split into two non-tail segments and one tail segment; Format C' (common prefix length in the range [40, 79]), split into one non-tail segment and one tail segment; Format D' (common prefix length in the range [0, 39]), split into only one tail segment. Among them, the tail segment corresponding to Format A' needs to be padded with 32 bits ([128, 159] bits) to make the total bit width of the tail segment 40 bits, adapting to the bit width requirements of the TCAM memory bank.

[0067] Unlike Embodiment 4, in this embodiment, the non-tail sub-segments and tail sub-segments obtained by splitting do not carry sub-segment identifiers, and the AD SRAM corresponding to the non-tail sub-segments does not store rule identifiers, which simplifies the sub-segment structure and storage content and saves hardware resources.

[0068] S2. Before executing the non-tail segment write, first check if a tail segment with the same value already exists in the tail segment table. If it already exists, adjust the length of the public prefix rule to be issued, re-split the non-tail segment and the tail segment, and then start executing from step S1. If it does not exist, execute the non-tail segment write operation.

[0069] The uniqueness verification logic of the tail segment in this step is the same as in Example 4. The core purpose is to avoid subset pointer confusion and search errors caused by multiple common prefix rules sharing a tail segment. The method of adjusting the length of the common prefix is ​​also the same as in Example 4, and will not be repeated here.

[0070] S3. Write all the non-tail segments obtained from the splitting into the TCAM storage body corresponding to the non-tail sub-table in the form of table entries. The specific operation is as follows: For each non-tail segment, first check whether there is a non-tail segment with the same value in the non-tail sub-table. If it exists, skip the write operation of the segment and process the next non-tail segment; if it does not exist, write the non-tail segment into the free position of the non-tail sub-table in the form of an independent table entry.

[0071] S4. Write the obtained tail segments into the TCAM storage body corresponding to the tail sub-table in the form of table entries, and at the same time store the pointers of the non-common prefix subsets corresponding to the common prefix rule in the AD SRAM corresponding to the tail segments.

[0072] The writing method in this embodiment retains the core advantages of tail segment uniqueness verification and non-tail segment sharing, while removing the management of segment identifiers and rule identifiers, greatly simplifying the process and reducing hardware resource consumption, making it suitable for scenarios with limited hardware resources. At the same time, through tail segment uniqueness verification and non-tail segment sharing, it can still effectively reduce TCAM resource waste and increase LPM rule storage capacity. While sacrificing some mismatch protection capabilities and sharing flexibility, it achieves a balance between hardware resource consumption and storage efficiency.

[0073] Example 6: Longest prefix matching search method (corresponding to the device in Example 2) This embodiment provides a longest prefix matching lookup method based on the device described in Embodiment 2, used to match the destination address of a packet with the LPM common prefix, ensuring matching accuracy. The specific steps are as follows: T1. Obtain the destination address of the message to be matched, and divide the destination address into multiple address sub-segments corresponding to the common prefix sub-segments according to the preset common prefix rule format (i.e., sub-segment division rule).

[0074] Specifically, the destination address of the message to be matched can be a simple IP address or an IP address plus a VPN ID (Virtual Private Network Identifier). The splitting rule is consistent with the common prefix splitting rule in Example 4. Taking four memory blocks (each 40 bits) as an example, the destination address is split into four address segments, where: the keywords [0,37]b+2b'0 are combined to form K_1 (segment identifier 0), the keywords [38,75]b+2b'1 are combined to form K_2 (segment identifier 1), the keywords [76,113]b+2b'2 are combined to form K_3 (segment identifier 2), and the keywords [114,127]b+24b'0+2b'3 are combined to form K_4 (segment identifier 3).

[0075] The purpose of adding 24b'0 to K_4 is to pad the bit width of the TCAM storage bank and ensure matching compatibility. In this embodiment, the bit width of each TCAM storage bank is 40 bits. K_4 corresponds to the keyword [114,127]b (14 bits in total) + 2 bits of sub-segment identifier (identifier is 3), with a total bit width of 16 bits, which is far less than 40 bits. Since TCAM matching is performed completely according to the storage bank bit width, if the bit width is not padded, K_4 will not be able to match the sub-segment stored in the tail sub-table (which has been padded to a 40-bit bit width), resulting in matching failure or mismatch. Therefore, adding 24b'0 (16 bits + 24 bits = 40 bits) padded the total bit width of K_4 to 40 bits, which is consistent with the bit width of the TCAM storage bank, ensuring that the matching logic is executed normally; at the same time, 24b'0 is a fixed padding bit, which does not affect the matching of the keyword core bit (14 bits + 2 bits) and will not interfere with the search results.

[0076] In this step, two arrays also need to be initialized: the rule identifier array RuleID[] and the shared segment array SharedSection[]. The rule identifier array RuleID[] is used to record the rule identifier corresponding to the sub-segment identifier stored in the AD SRAM. For example, RuleID[0] stores the rule identifier stored in the AD SRAM for the sub-segment with sub-segment identifier 0. The shared segment array SharedSection[] is used to record "non-tail sub-segment value + sub-segment identifier value" when the rule identifier stored in the AD SRAM of the TCAM is a special value (0xFFFF). For example, SharedSection[1] stores the non-tail sub-segment value stored in the TCAM at bit [38,75]b+2b'1 for the sub-segment with sub-segment identifier 1.

[0077] T2. Match the address segments corresponding to the non-tail segments one by one with the non-tail segment entries stored in the non-tail segment table; match the address segments corresponding to the tail segments with the tail segment entries stored in the tail segment table.

[0078] Specifically, for the address segments (K_1, K_2, K_3) corresponding to the first three non-tail segments, the non-tail sub-table is queried one by one: if the address segment matches successfully, the content in the AD SRAM corresponding to the matching entry is read; if the rule identifier stored in the AD SRAM is a non-preset special value (non-0xFFFF), then the rule identifier is recorded in the rule identifier array RuleID[Round] (Round is the segment identifier, with a value of 0~2); if the AD SRAM stores a preset special value (0xFFFF), then the value of the matched non-tail segment is recorded in the shared segment array SharedSection[Round], and 0xFFFF is recorded in the corresponding position of the rule identifier array, marking the segment as a shared segment.

[0079] For the address segment (K_4) corresponding to the 4th segment, query the tail sub-table: if K_4 matches a tail segment entry in the tail sub-table, continue to step T3; if no match is found, the search fails and the search process ends.

[0080] T3. If all address segments are matched successfully, obtain the pointer to the non-common prefix subset stored in the AD SRAM corresponding to the tail segment, and complete the longest prefix matching search.

[0081] Specifically, the criteria for determining a successful match for all address segments include the following two points: First, all non-special value rule identifiers recorded in the rule identifier array are unique rule identifiers for the same common prefix rule, ensuring that all non-tail segments belong to the same common prefix rule; second, all non-tail segment values ​​recorded in the shared segment array are completely consistent with the address segment values ​​at their corresponding positions, ensuring that the actual value of the shared segment matches the segment corresponding to the keyword, avoiding mismatches of shared segments from different rules. Only when both conditions are met can a common prefix hit be confirmed, thereby obtaining the pointer to the non-common prefix subset in the ADSRAM corresponding to the tail segment. Subsequently, this pointer can be used to query the non-common prefix subset in the SRAM to complete the final LPM matching.

[0082] It should be noted that in this embodiment, the non-tail segments of the same keyword are searched serially. However, since TCAM obtains the result in one clock cycle, the search overhead is only extended from one clock cycle (parallel search of 4 memory banks) in the original scheme to a maximum of 4 clock cycles (serial search of the first 3 non-tail segments, while the tail segments can be searched in parallel, plus the final matching confirmation step). The negative impact on the overall search performance is not significant.

[0083] The search method in this embodiment ensures the correctness of the sub-segment number by adding sub-segment identifiers; it forms a dual protection against mismatches through rule identifier verification and shared segment verification, effectively avoiding mismatches of sub-segments with different common prefix rules and improving matching accuracy; at the same time, the search process is adapted to scenarios where non-tail sub-segments are shared, and can accurately identify the common prefix rules corresponding to shared sub-segments. While improving TCAM resource utilization, it ensures the correctness and efficiency of the search, achieving a balance between "improving resource utilization, ensuring matching accuracy, and controlling search latency".

[0084] Example 7: Longest prefix matching search method (corresponding to the device in Example 3) This embodiment provides a longest prefix matching search method based on the device described in Embodiment 3, which is suitable for scenarios with limited hardware resources. The process is simplified, and the specific steps are as follows: T1. Obtain the destination address of the message to be matched, and divide the destination address into multiple address sub-segments corresponding to the common prefix sub-segments according to the preset common prefix rule format (i.e., sub-segment division rule).

[0085] Specifically, the splitting rule is consistent with the common prefix splitting rule in Embodiment 5. Taking four memory banks (each 40 bits) as an example, the destination address is split into four address sub-segments: keywords [0,39]b are combined into K_1, keywords [40,79]b are combined into K_2, keywords [80,119]b are combined into K_3, and keywords [120,127]b + 32b'0 are combined into K_4. The purpose of adding 32b'0 to K_4 is to pad the 40-bit width of the TCAM memory bank to ensure matching compatibility, which is consistent with the K_4 padding logic in Embodiment 6.

[0086] Unlike Embodiment Six, in this embodiment, the split address segments do not carry segment identifiers; they are simply padded according to the bit width of the TCAM memory, simplifying the address segment processing flow and reducing bit usage. Simultaneously, only the SharedSection[] array is initialized to record successfully matched non-tail segment values, eliminating the need to initialize the rule identifier array and further simplifying the process.

[0087] T2. Match the address segments corresponding to the non-tail segments one by one with the non-tail segment entries stored in the non-tail segment table; match the address segments corresponding to the tail segments with the tail segment entries stored in the tail segment table.

[0088] Specifically, for the address segments (K_1, K_2, K_3) corresponding to the first three non-tail segments, the non-tail sub-table is queried one by one: if the address segment matches successfully, the value of the matched non-tail segment is recorded in the shared segment array SharedSection[Round] (Round is the segment number, with a value of 0~2); if no match is found, the search fails and the search process ends.

[0089] For the address segment (K_4) corresponding to the 4th segment, query the tail sub-table: if K_4 matches a tail segment entry in the tail sub-table, continue to step T3; if no match is found, the search fails and the search process ends.

[0090] T3. If all address segments are matched successfully, obtain the pointer to the non-common prefix subset stored in the AD SRAM corresponding to the tail segment, and complete the longest prefix matching search.

[0091] Specifically, the criteria for determining whether all address segments match successfully are: all non-tail segment values ​​recorded in the shared segment array are completely identical to the address segment values ​​at their corresponding positions, and the address segment corresponding to the tail segment matches the tail segment entry in the tail segment table. Only when both conditions are met simultaneously can a common prefix hit be confirmed, thereby obtaining the pointer to the non-common prefix subset in the ADSRAM corresponding to the tail segment and completing the final LPM matching.

[0092] The lookup latency in this embodiment is basically the same as that in embodiment six, which is a maximum of 4 clock cycles. This is because only the rule identifier verification step has been removed, and the time consumed by this step is negligible, so it has a very small impact on the overall lookup efficiency.

[0093] The search method in this embodiment removes the processing of sub-segment identifiers and rule identifiers, simplifies the process, reduces hardware resource consumption, and is suitable for scenarios with tight hardware resources. At the same time, by verifying the shared segment value and the address sub-segment value, it can effectively avoid mismatches of shared sub-segments and ensure search accuracy. The search latency is basically the same as that in Embodiment Six. Under the premise of sacrificing some mismatch protection capabilities, it achieves a balance between hardware resource consumption and search efficiency and accuracy, and can meet the LPM search requirements in hardware-constrained scenarios.

[0094] Example 8: Network Switching Chip This embodiment provides a network switching chip, which includes any of the longest prefix matching storage devices based on TCAM described in Embodiment 1, Embodiment 2 or Embodiment 3 of this application.

[0095] Specifically, this network switching chip can be applied to network devices such as routers and switches to implement the LPM lookup function in IP routing. The TCAM in the chip is virtually divided into a non-tail sub-table and a tail sub-table according to the technical solution of this application, storing the LPM common prefix; AD SRAM and TCAM storage are allocated in pairs to store rule identifiers, special values, or pointers to subsets of non-common prefixes; depending on the chip's hardware resources, either Embodiment 2 or Embodiment 3 can be selected. When hardware resources are sufficient, Embodiment 2 is chosen to pursue higher storage efficiency and mismatch protection capabilities; when hardware resources are limited, Embodiment 3 is chosen to pursue efficient utilization of hardware resources and process simplicity.

[0096] The network switching chip also integrates the longest prefix matching rule writing method described in embodiments four and five of this application, as well as the longest prefix matching lookup method described in embodiments six and seven, to realize the distribution of LPM common prefix rules and the matching of packet destination addresses, ensuring that the chip's routing and forwarding functions are efficient and accurate.

[0097] The network switching chip of this embodiment, by integrating the storage device and method of this application, effectively improves the utilization rate of TCAM resources, and can store more LPM rules under the same hardware resources, thereby improving the LPM capacity specification of the chip. At the same time, a suitable device implementation form can be selected according to the hardware resource situation, taking into account storage efficiency, lookup efficiency and mismatch protection capability, improving the flexibility and applicability of the chip, and meeting the application needs of different network devices.

[0098] Example 9: Computer-readable storage medium This embodiment provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the longest prefix matching rule writing method described in any one of embodiments four and five of this application, and / or the longest prefix matching search method described in any one of embodiments six and seven.

[0099] Specifically, the computer-readable storage medium can be a read-only memory (ROM), random access memory (RAM), hard disk, optical disk, USB flash drive, or other media capable of storing computer programs; the processor can be a processor in a network switching chip, a microcontroller, a microprocessor, or other devices with data processing capabilities. When the processor executes the computer program, it can send the LPM common prefix rules to the non-tail sub-table and tail sub-table of the TCAM according to the corresponding writing method, and complete the LPM matching of the packet destination address according to the corresponding lookup method, achieving the same technical effect as the aforementioned method embodiments of this application.

[0100] The computer-readable storage medium of this embodiment stores the LPM rule writing method and the lookup method in the form of a computer program, which can be flexibly deployed in different processors and devices, facilitating upgrades and maintenance. At the same time, when the program is executed, it can achieve the core technical effects of this application, namely, reducing TCAM resource waste, increasing LPM rule storage capacity, and ensuring matching accuracy and efficiency, providing a flexible and convenient carrier for the implementation of LPM lookup function.

[0101] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A longest prefix matching (LPM) storage device based on a TCAM, comprising a tri-state content-addressable memory (TCAM) and an address-data static random access memory (AD SRAM) associated with the TCAM, wherein the TCAM comprises multiple memory banks, and the TCAM is used to store the common prefix of the longest prefix matching (LPM), characterized in that: The TCAM is virtually divided into non-tail sub-tables and tail sub-tables; The non-tail sub-table is used to store non-tail segments in the LPM common prefix that have no mask and require precise matching of the entire storage block bit width; in the non-tail sub-table, the same non-tail segments of different common prefixes share the same sub-segment table entry; The tail sub-table is used to store the masked tail sub-segments in the LPM common prefix; Among them, each non-tail segment split from the same LPM common prefix is ​​stored in the non-tail sub-table as an independent entry. The byte width of the entries in the non-tail sub-table and the tail sub-table corresponds to the byte width of one or more memory banks plus AD SRAM. The AD SRAM associated with the storage bank corresponding to the tail sub-table is used to store pointers to the non-common prefix subsets corresponding to the common prefix.

2. The apparatus according to claim 1, characterized in that, In the initial state of the TCAM, at least one storage unit is allocated to the non-tail sub-table, at least one storage unit is allocated to the tail sub-table, and the remaining storage units serve as an idle resource pool. When the storage units occupied by the non-tail sub-table or the tail sub-table are full, storage units are allocated from the idle resource pool for expansion.

3. The apparatus according to claim 1, characterized in that, The number of non-tail segments and tail segments split is determined based on the mapping between the length of the LPM common prefix and the bit width of the TCAM memory; the longer the common prefix, the more non-tail segments are split.

4. The apparatus according to claim 1, characterized in that, Each non-tail sub-segment and tail sub-segment carries a sub-segment identifier, which is used to mark the sequence number of the sub-segment in its common prefix; In the non-tail sub-table, the same non-tail sub-segments with different common prefixes share the same sub-segment table entry, and the AD SRAM corresponding to the shared sub-segment stores a preset special value.

5. The apparatus according to claim 1, characterized in that, The non-tail sub-segment and tail sub-segment do not carry sub-segment identifiers, and the AD SRAM corresponding to the non-tail sub-segment does not store rule identifiers.

6. A method for writing the longest prefix matching rule based on the device of claim 1, characterized in that, Includes the following steps: S1. Obtain the longest prefix matching LPM common prefix rule to be issued, divide the rule according to the preset common prefix rule format, and split the common prefix rule into a tail segment or at least one non-tail segment and a tail segment. S2. Write all the non-tail segments obtained from the splitting into the TCAM storage body corresponding to the non-tail sub-table in the form of table entries; S3. Write the split tail segments into the TCAM storage body corresponding to the tail sub-table in the form of table entries.

7. The method according to claim 6, characterized in that, When the storage space occupied by the non-tail sub-table or the tail sub-table is full, the storage space is first allocated from the free resource pool to complete the expansion of the non-tail sub-table or the tail sub-table, and then the write operation of the corresponding sub-segment is performed. The number of non-tail segments and tail segments split is determined by the mapping between the length of the LPM common prefix rule to be issued and the bit width of the TCAM storage. The longer the length of the common prefix rule, the more non-tail segments are split. The length of the LPM common prefix rule to be issued is related to the bit width mapping of the TCAM storage and the configuration of the number of TCAM storage corresponding to the sub-table entries. The sub-segment division granularity of the common prefix rule can be adjusted by adjusting the number of TCAM storage corresponding to the sub-table entries.

8. The method according to claim 6, characterized in that, The device is the device according to claim 4. In step S1, a unique rule identifier is assigned to the public prefix rule to be issued, and a sub-segment identifier is added to each non-tail sub-segment and tail sub-segment obtained by splitting. The sub-segment identifier is used to mark the sequence number of the sub-segment in the public prefix rule to which it belongs. If the bit width of the tail sub-segment plus the sub-segment identifier is less than the bit width of the TCAM storage, it is padded according to the bit width of the TCAM storage. Before executing step S2, first check whether there is a tail segment with the same value in the tail sub-table. If it exists, adjust the length of the public prefix rule to be issued, re-split the non-tail segment and the tail segment, and then start executing from step S1. Step S2 specifically involves: for each non-tail segment with an added segment identifier, first query whether a non-tail segment with the same value already exists in the non-tail sub-table; if it already exists, then share the stored segment table entry, synchronously update the reference count corresponding to the non-tail segment; if this is the first time the segment is shared, then replace the rule identifier stored in its AD SRAM with a preset special value; if it does not exist, then write the non-tail segment as an independent table entry into the free space of the non-tail sub-table, store the unique rule identifier of the common prefix rule to which the non-tail segment belongs in its corresponding AD SRAM, and set the reference count of the non-tail segment to 1; If no tail segment with the same value is found in the tail segment table, the tail segment write operation in step S3 is performed, and the pointer of the non-common prefix subset corresponding to the common prefix rule is stored in the AD SRAM corresponding to the tail segment.

9. The method according to claim 6, characterized in that, The device is the device described in claim 5, wherein the non-tail segment and tail segment obtained by splitting do not carry segment identifiers, and the AD SRAM corresponding to the non-tail segment does not store rule identifiers. Before executing step S2, first check if there is already a tail segment with the same value in the tail sub-table. If it exists, adjust the length of the public prefix rule to be issued, re-split the non-tail segment and the tail segment, and then start executing from step S1. The specific steps of step S2 are as follows: For each non-tail sub-segment, first check whether a non-tail sub-segment with the same value already exists in the non-tail sub-table. If it already exists, skip the write operation of that sub-segment and process the next non-tail sub-segment. If it does not exist, write the non-tail sub-segment into the free position of the non-tail sub-table as an independent entry. If no tail segment with the same value is found in the tail segment table, the tail segment write operation in step S3 is performed, and the pointer of the non-common prefix subset corresponding to the common prefix rule is stored in the AD SRAM corresponding to the tail segment.

10. A longest prefix matching search method based on the device of claim 1, characterized in that, Includes the following steps: T1. Obtain the destination address of the message to be matched, and divide the destination address into multiple address sub-segments corresponding to the common prefix sub-segments according to the preset common prefix rule format. T2. Match each address segment corresponding to a non-tail segment with the non-tail segment entries stored in the non-tail segment table; match each address segment corresponding to a tail segment with the tail segment entries stored in the tail segment table. T3. If all address segments are matched successfully, obtain the pointer to the non-common prefix subset stored in the AD SRAM corresponding to the tail segment, and complete the longest prefix matching search.

11. The method according to claim 10, characterized in that, The device is the device according to claim 4. In step T1, a corresponding sub-segment identifier is added to the end of each address sub-segment according to the sub-segment division rule. The sub-segment identifier is used to mark the sequence number of the address sub-segment in the destination address. If the address sub-segment plus the sub-segment identifier bit width is less than the TCAM storage bit width, it is padded to the TCAM storage bit width. Step T2 specifically involves: matching each address segment corresponding to a non-tail segment with an entry in the non-tail sub-table; if the address segment matches successfully, reading the content in the AD SRAM corresponding to the matching entry; if the rule identifier stored in the AD SRAM is not a preset special value, recording the rule identifier in the rule identifier array; if the value stored in the AD SRAM is a preset special value, recording the matched non-tail segment value in the shared segment array. In step T3, the conditions for determining that all address segments are successfully matched include: all non-special value rule identifiers recorded in the rule identifier array are unique rule identifiers of the same common prefix rule; all non-tail segment values ​​recorded in the shared segment array are completely consistent with the address segment values ​​at the corresponding positions; and the address segment corresponding to the tail segment is successfully matched with the tail segment entry in the tail segment table.

12. The method according to claim 10, characterized in that, The device is the device according to claim 5. In step T1, the split address sub-segments do not carry sub-segment identifiers and are padded according to the bit width of the TCAM storage. Step T2 specifically involves: matching each address segment corresponding to a non-tail segment with an entry in the non-tail sub-table; if the address segment matches successfully, recording the matched non-tail segment value in the shared sub-array. In step T3, the conditions for determining that all address segments are successfully matched include: all non-tail segment values ​​recorded in the shared segment array are completely consistent with the address segment values ​​at the corresponding positions, and the address segment corresponding to the tail segment is successfully matched with the tail segment entry in the tail segment table.

13. A network switching chip, characterized in that, Includes the longest prefix matching storage device based on TCAM as described in any one of claims 1-5.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the longest prefix matching rule writing method according to any one of claims 6-9, and / or the longest prefix matching search method according to any one of claims 10-12.

Images