Hardware fast reconfiguration terminal and method

Abstract

The application belongs to the technical field of wireless communication, and relates to a hardware fast reconfiguration terminal and method. A VPX architecture is used to configure a plurality of slot positions of the terminal to support flexible plugging of a signal processing module and a radio frequency front end. Standardized interaction of data communication between modules, system control monitoring and health management is realized based on PCIe / SIRO, a local area network and an IIC bus. An embedded operating system is deployed in a main control module. A core framework of a domain manager and a device manager and basic equipment and service components corresponding to hardware capabilities / resources are included. The hardware platform is logically abstracted to release deep binding of software and hardware. In addition, terminal functions are disassembled into independent waveform components with standard interfaces. Standardized communication between the components is realized through a soft bus and a hardware abstraction layer interface. Waveform application is dynamically deployed by relying on external waveform deployment management software to complete function switching. In this way, the architecture limitation of strong coupling of existing communication equipment software and hardware is broken, and the technical problem that hardware resources cannot be dynamically reconfigured is solved.

Description

Technical Field

[0001] This application belongs to the field of wireless communication technology, and more specifically, relates to a terminal and method for rapid hardware reconfiguration. Background Technology

[0002] In the field of wireless communication, such as emergency communication, field operation communication, and dedicated data transmission, communication equipment needs to frequently cope with unpredictable environmental changes and diverse task requirements, such as communication waveform upgrades, the emergence of new types of interference, and differentiated requirements such as data acquisition, signal monitoring, and multi-band communication. This requires communication equipment to have the characteristics of dynamically switching functional modules and combining hardware resources to achieve capability upgrades.

[0003] Existing professional wireless communication equipment generally adopts a demand-driven customized development model, focusing on the ultimate balance between single-unit performance and cost. This results in a strong coupling between the equipment's software configuration and hardware structure. Specifically, the selection of hardware modules, connection methods, and the execution logic of software programs are deeply bound together. Changes in the model or parameter adjustments of a single hardware module can cause the entire equipment system to malfunction. Based on this architecture, equipment upgrades must follow a complete process of withdrawal, transportation, R&D modifications, compatibility testing, and redeployment. This requires not only professional technicians to complete hardware replacement and software burning in a dedicated site, but also multiple rounds of full-system compatibility testing to avoid interference with the original functions. Therefore, its deployment flexibility is poor. The software is stored in the chip using a fixed burning method and cannot be dynamically loaded according to on-site needs. The addition or removal of hardware modules depends on the pre-designed specifications before delivery, making rapid on-site reconstruction impossible. Summary of the Invention

[0004] This invention provides a terminal device and method for rapid hardware reconfiguration, aiming to solve the technical problem that current strongly coupled communication equipment cannot achieve dynamic reconfiguration of hardware resources.

[0005] A terminal device with rapid hardware reconfiguration includes a main control module, a signal processing module, an RF front-end, a chassis, and an antenna; The terminal adopts a VPX architecture. The chassis is provided with multiple slots to support the insertion of multiple signal processing modules and radio frequency front-ends. The main control module, signal processing modules and radio frequency front-ends communicate with each other via PCIe or SIRO. System control and status monitoring are achieved through a local area network, and health management is achieved through an IIC bus. The main control module is equipped with an embedded operating system, a core framework, and basic devices and service components. The core framework includes a domain manager and a device manager. The basic devices and service components constitute a logical abstraction of the hardware platform, and each basic device and service component corresponds to a part of the capabilities or resources of the hardware platform. The terminal is functionally divided into multiple waveform applications. Each waveform application contains multiple waveform components in the form of independent processes. Each waveform component is deployed and runs separately and provides a standard interface. The waveform components communicate with each other through the standard interface and the soft bus. The waveform components of heterogeneous platforms communicate with each other after the message format is uniformly encapsulated through the hardware abstraction layer interface. The waveform applications and functions of the terminal are controlled by external waveform deployment management software. Function switching is achieved by deploying different waveform applications, and the terminal's working status can be adjusted by accessing the attributes attached to the waveform components or by modifying the hardware and software parameters.

[0006] This invention utilizes a VPX architecture to configure multiple slots for the terminal unit, supporting flexible plug-and-play of signal processing modules and RF front-ends. It implements standardized interactions for inter-module data communication, system control and monitoring, and health management based on PCIe / SIRO, LAN, and IIC bus, respectively. Simultaneously, an embedded operating system is deployed in the main control module, including the core framework of a domain manager and device manager, as well as the corresponding hardware capabilities / resources and service components. The hardware platform is logically abstracted to decouple deep software and hardware integration. Furthermore, the terminal unit's functions are decomposed into independent waveform components with standard interfaces. Standardized communication between components is achieved through a software bus and hardware abstraction layer interface, and external waveform deployment management software is relied upon. Dynamically deploying waveform applications enables function switching and allows for the adjustment of hardware and software parameters by accessing waveform component properties. This breaks the limitations of the existing tightly coupled hardware and software architecture of communication equipment and solves the technical problem of the inability to dynamically reconfigure hardware resources. It not only enables rapid on-site reconfiguration of communication equipment hardware resources and flexible function switching without the need for complex withdrawal, modification, testing, and redeployment processes, but also significantly improves the flexibility of equipment deployment and its adaptability to environmental changes and diverse task requirements. Furthermore, because waveform components are deployed and run independently with standardized interfaces, the impact of hardware module changes and parameter adjustments on system operation is reduced, ensuring system stability and reducing the manpower and time costs of upgrades and maintenance.

[0007] Preferably, the main control module includes a general-purpose processor, which is an ARM processor, an x86 processor, or an ARM core of a SOC chip; the embedded operating system is a Linux operating system, a VxWorks operating system, or a ReWorks operating system.

[0008] Preferably, the signal processing module includes a field-programmable gate array (FPGA) chip and an analog-to-digital (ADC) / digital-to-analog (DAC) chip; The radio frequency front end includes a radio frequency switch, a power amplifier chip, and a filter chip; The terminal is equipped with multiple sets of RF front-ends and antennas adapted to different operating frequency bands. Each set of RF front-ends and antennas can be replaced through the slots in the chassis. Different sets of RF front-ends and antennas are assigned to adapt to shortwave, VHF, L-band, S-band and C-band. By replacing different sets of RF front-ends and antennas, the terminal can operate in the corresponding frequency band.

[0009] Preferably, the core framework also implements distributed invocation of waveform components through CORBA middleware, and the waveform components are managed by the core framework through installation, creation, startup, shutdown, release and uninstallation operations.

[0010] A method for rapid hardware reconfiguration, employing a terminal device for rapid hardware reconfiguration as described in this invention, includes the following steps: Step 1: Based on the target functional requirements, perform hardware reconfiguration on the terminal device. Specifically, the hardware reconfiguration operation can be any one of hardware module replacement, hardware module addition, or terminal device cascading. Step 2: The terminal's health management service monitors hardware status changes in real time. When a hardware refactoring operation is detected, the hardware change information is sent to the device manager of the core framework. Step 3: Based on the hardware change information, the Device Manager triggers the core framework to deploy basic devices and service components adapted to the new hardware through the logical abstraction capabilities of basic devices and service components, thus completing the logical encapsulation of hardware capabilities; Step 4: After receiving the hardware ready notification sent by the core framework, the external waveform deployment management software deploys the corresponding waveform application according to the target functional requirements. Each waveform component of the waveform application is registered to the core framework through a standard interface, and the components establish communication connections through a soft bus or hardware abstraction layer interface. Step 5: By reading and writing the attached attributes of the waveform component, adjust the hardware and software parameters of the terminal to make the terminal run in the target working state and complete the rapid reconstruction.

[0011] Preferably, the hardware module replacement in step 1 is as follows: the object of the hardware module replacement is the radio frequency front end, which is replaced by removing the original radio frequency front end from the terminal chassis slot and installing a new radio frequency front end adapted to the target frequency band. The parameters of the radio frequency switch, power amplifier chip and filter chip of the new radio frequency front end are matched with the target frequency band.

[0012] Preferably, the addition of hardware modules in step 1 is as follows: the added hardware modules are a signal processing module and an RF front-end. An unoccupied slot in the terminal chassis is selected, and the newly added signal processing module and the RF front-end adapted to the new frequency band are inserted in sequence. The FPGA chip of the newly added signal processing module and the AD / DA chip of the newly added RF front-end are pre-complied with hardware.

[0013] Preferably, in step 1, the terminal cascading is performed by connecting the local area network interfaces of the two terminal devices via Ethernet, and setting one of them as the master terminal device and the other as the slave terminal device through waveform deployment management software. The IP addresses of the master terminal device and the slave terminal device are in the same local area network segment to achieve communication.

[0014] Preferably, the deployment of basic equipment and service components in step 3 includes the following steps: After the device manager reads the model identifier of the new hardware, it calls the appropriate basic devices and service components from the preset component library. If it is a replacement of the RF front end, it deploys the RF logic device and FPGA logic device of the corresponding frequency band. If it is a module addition, it adds and registers the corresponding model of AD / DA logic device and FPGA logic device.

[0015] Preferably, the waveform application deployment in step 4 includes the following steps: The waveform deployment management software selects the corresponding waveform application from the waveform library according to the target function, and deploys the multiple waveform components contained in the waveform application to the main control module and the signal processing module in a preset order. After deployment, each waveform component registers with the domain manager of the core framework through a standard interface.

[0016] The beneficial effects of this invention include: This invention utilizes a VPX architecture to configure multiple slots for the terminal unit, supporting flexible plug-and-play of signal processing modules and RF front-ends. It implements standardized interactions for inter-module data communication, system control and monitoring, and health management based on PCIe / SIRO, LAN, and IIC bus, respectively. Simultaneously, an embedded operating system is deployed in the main control module, including the core framework of a domain manager and device manager, as well as the corresponding hardware capabilities / resources and service components. The hardware platform is logically abstracted to decouple deep software and hardware integration. Furthermore, the terminal unit's functions are decomposed into independent waveform components with standard interfaces. Standardized communication between components is achieved through a software bus and hardware abstraction layer interface, and external waveform deployment management software is relied upon. Dynamically deploying waveform applications enables function switching and allows for the adjustment of hardware and software parameters by accessing waveform component properties. This breaks the limitations of the existing tightly coupled hardware and software architecture of communication equipment and solves the technical problem of the inability to dynamically reconfigure hardware resources. It not only enables rapid on-site reconfiguration of communication equipment hardware resources and flexible function switching without the need for complex withdrawal, modification, testing, and redeployment processes, but also significantly improves the flexibility of equipment deployment and its adaptability to environmental changes and diverse task requirements. Furthermore, because waveform components are deployed and run independently with standardized interfaces, the impact of hardware module changes and parameter adjustments on system operation is reduced, ensuring system stability and reducing the manpower and time costs of upgrades and maintenance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the terminal unit composition provided for an embodiment of the present invention.

[0019] Figure 2 The system architecture shown is intended for embodiments of the present invention.

[0020] Figure 3 A schematic diagram illustrating hardware module replacement provided for an embodiment of the present invention.

[0021] Figure 4 A schematic diagram is added to the hardware module provided in the embodiments of the present invention.

[0022] Figure 5 This is a schematic diagram of terminal cascading provided for an embodiment of the present invention. Detailed Implementation

[0023] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0024] Example 1 See Figure 1 As shown, this invention discloses a terminal device for rapid hardware reconfiguration. The terminal device is a general-purpose wideband software-defined radio terminal device (hereinafter referred to as "terminal device"). It adopts a software communication architecture to achieve hardware-software decoupling. Through modular hardware design and software abstraction layer encapsulation, upper-layer applications are shielded from differences in the underlying hardware. Hardware adjustments do not require modification of the software logic, thus supporting rapid reconfiguration, as detailed below: The terminal hardware adopts the VPX architecture, and the terminal includes the following modules: Main control module: The core component uses a general-purpose processor. In this embodiment, the ARM core of the SOC chip (such as FMQL100TAI900, which has a built-in quad-core ARM Cortex-A9 and a main frequency of 1.0GHz) is preferred to balance computing power and low power consumption requirements. It can also be replaced with an X86 processor (such as Intel Core i5-1035G1) depending on the computing power requirements. The module has a built-in 16GB EMMC storage chip and 4GB DDR4 memory. The embedded operating system is deployed in the storage chip. The Linux 4.14 kernel is selected (open source and stable, supporting multi-process management and component deployment). It can also be replaced with the VxWorks or ReWorks operating system (adapted to strong real-time scenarios).

[0025] Signal processing module: It adopts an integrated FPGA and AD / DA architecture. The FPGA is selected from the RFSOC series (model JFM9RFVU3P5G, containing 150K logic units, supporting high-speed parallel signal processing), which is responsible for implementing digital signal processing functions such as filtering and modulation / demodulation. The AD / DA chip is selected from ADI AD9625 (sampling rate 1GSPS, resolution 12-bit, adapted to 3MHz-8GHz wideband signal acquisition and conversion). The module is connected to the chassis slot through VPX gold fingers. The gold finger pin definitions are completely standardized to ensure that modules from different batches are interchangeable.

[0026] RF Front-End and Antenna: The RF front-end adopts a modular design. Each module integrates an RF switch (SKY13359, supporting 3MHz-8GHz band switching), a power amplifier chip (NXP AH1138, 2W output power), and a custom LC filter chip. The module casing is marked with the compatible frequency bands (e.g., shortwave: 3-30MHz; VHF: 30-300MHz; L-band: 1-2GHz, etc.). The antenna is designed as a multi-band adjustable model (AT-890, adaptable to 3MHz-8GHz), which connects to the RF front-end via an SMA interface. This terminal is equipped with 5 sets of RF front-ends and antennas of different frequency bands, and each set can be quickly replaced through the chassis slots. Through standardized mechanical interfaces and electrical parameters, modules of different frequency bands can be directly replaced without modifying other hardware.

[0027] Chassis: The chassis has 8 VPX standard slots, 4 of which are dedicated to signal processing modules and 4 to RF front-end modules (the slots are distinguished by color to avoid incorrect insertion); the chassis has a built-in intelligent cooling system (including 4 temperature-controlled fans that automatically accelerate when the temperature is ≥50℃) and dual power supply modules (12V / 5V output, supporting redundant power supply), and the back panel integrates PCIe, LAN and IIC bus interfaces to realize signal interconnection between modules.

[0028] As a further implementation of this embodiment, to avoid interference between data transmission and control signals, the terminal is designed with three independent bus interfaces, which respectively undertake data communication, system control, and health management functions, as follows: Data communication interface: The main module uses a PCIe 3.0 interface to transmit high-speed RF data and processed digital information with the signal processing module and the RF front end; the signal processing modules use a SIRO interface to ensure the timing consistency of multi-module collaborative processing. Both PCIe and SIRO are high-speed serial interfaces, which are more resistant to interference than parallel interfaces and are suitable for high-speed transmission of wide-band signals.

[0029] Control and monitoring interface: The main control module uses a 1000M Ethernet (LAN) interface. The main control module sends control commands (such as frequency band switching and power adjustment) to each module via TCP / IP protocol, and at the same time receives the operating status data of each module (such as operating temperature and power supply voltage). Health management interface: The IIC bus is used, and each module has a built-in health management chip. The status data is uploaded to the main control module in real time through this bus.

[0030] See Figure 2 As shown, in this embodiment, the software adopts a layered architecture and component-based deployment design. That is, a unified operating environment is built on the main control module, and hardware capabilities are abstracted into standardized components, so that waveforms are completely decoupled from hardware, as detailed below: Hardware Abstraction Layer: Deploy CORBA middleware (using E-Spectra e) The ORB version supports distributed remote calls and basic equipment and service components (including FPGA logic devices, RF logic devices, GPP logic devices, and MHAL logic devices). It abstracts hardware physical capabilities into standardized interfaces. For example, the filtering function of the FPGA is abstracted into the Filter_Process(data) attribute interface, and the power adjustment function of the RF front end is abstracted into the Set_Power(value) attribute interface. When the upper-layer application calls the interface, it does not need to pay attention to the FPGA model or power amplifier chip parameters. The hardware differences are shielded by the abstraction layer, so that after the hardware is replaced, only the corresponding components of the abstraction layer need to be updated, without modifying the upper-layer application.

[0031] Core Framework Layer: Contains four independent process components, all of which start and run with system operation. These include: Domain Manager: Responsible for component resource management, such as allocating resources, registering, and deregistering waveform application components; Device Manager: Responsible for hardware module registration and status monitoring, automatically updating the resource list when hardware is refactored; Log Service: Records component operation logs in the domain (including timestamps, operation types, and results), stored at / var / log / run_1025.log, facilitating troubleshooting; Health Management Service: Receives hardware status data from the IIC bus, and when parameters exceed thresholds (e.g., temperature ≥ 85℃), sends alarm information to the waveform deployment management software via the LAN interface.

[0032] Waveform application layer: Composed of multiple independent waveform applications (such as Link4A communication, Link11 communication, and satellite communication applications). Each waveform application is divided into multiple independent process-based waveform components (such as signal acquisition components, signal processing components, and data transmission components). All waveform components provide standard CORBA interfaces. For example, the signal acquisition component provides the Data_Collect(freq, gain) interface. Componentization ensures that a single functional failure does not affect the overall application. Independent process deployment supports individual start and stop of components.

[0033] In this embodiment, the core framework layer implements full lifecycle management of waveform components through standardized interfaces. The specific process is as follows: Installation: Download and update the waveform deployment files (including component executables and domain description configuration files) to the / root / xykj / platform / directory through the core framework file system service interface, and start the domain manager and device manager; Creation: Create an application factory and register it to the domain through the domain installation interface installApplication operation; create an application instance and allocate hardware resources through the application manager application factory interface create operation; register component information to the domain; and connect the application component port. Startup: The Start() interface of the component is called through the controllable interface of the application manager; Operation: Components communicate with other components through CORBA middleware and the Hardware Abstraction Layer (MHAL) interface; Stop / Release / Uninstall: Executed via the Stop(), Release(), and Uninstall() interfaces to release occupied resources.

[0034] In this embodiment, a standardized process is used to ensure that components can be dynamically deployed, avoiding the inflexible deployment problem caused by traditional firmware burning.

[0035] Secondly, in this embodiment, the waveform deployment management software is an external control tool (running on Windows or Linux systems and supporting graphical operation). It communicates with the terminal through a LAN interface. Its core functions include: waveform application selection, component deployment progress display, parameter configuration, and status monitoring. Centralized management through external tools reduces the difficulty of on-site operation.

[0036] Example 2 A method for rapid hardware reconfiguration, based on the terminal implementation described in the embodiment, see [link to embodiment]. Figure 3 , Figure 4 and Figure 5 The diagram shows three main forms: hardware module replacement, hardware module addition, and terminal cascading, each corresponding to different scenario requirements, as detailed below: The specific steps for replacing the hardware module are as follows: Step 1: The user performs a power-off operation on the RF front-end through the waveform deployment software, then unplugs the old RF front-end module, inserts the new UHF RF front-end module into the corresponding slot, and then turns on the power switch. Step 2: After the new module is powered on, the health management chip sends the device identifier RF-UHF-001 to the health management service via the IIC bus; the health management service forwards the identifier to the device manager, and the device manager queries the preset device-component mapping table (stored in / etc / device_map.xml) to confirm that the identifier corresponds to the deployment of the UHF logic device and the FPGA logic device V2.1 component. Step 3: The Device Manager sends a resource request to the Domain Manager, which allocates 20% of the FPGA logic units and 512MB of memory to the new component; the Hardware Abstraction Layer automatically unloads the original shortwave RF logic device component, loads the new component and performs initialization (such as calibrating filter chip parameters), and returns a successful adaptation message to the Device Manager after completion. Step 4: The waveform deployment management software receives the hardware ready notification and pops up a prompt window; the user selects the UHF Link4A communication waveform application in the window and clicks the deploy button; the software automatically parses the application configuration file ( / opt / apps / Link4A / config.xml), requests resources from the domain manager through the CORBA middleware, and loads the three components of signal acquisition, processing, and transmission into the main control module and the signal processing module in sequence. After the components are deployed, they are automatically registered with the device manager. Step 5: In the parameter configuration interface of the waveform deployment management software, the user sets the transmit / receive frequency to 255MHz, the power gain to 10dB, and the bandwidth to 25kHz, and clicks the Apply button; the software updates the parameters through the waveform component properties by calling the Set_Freq() and Set_Power() interfaces, and the parameters take effect in real time, and the reconstruction is completed.

[0037] The specific steps for adding the hardware module are as follows: Step 1: The user performs a system standby operation through the waveform deployment management software (ensuring that the original module data is saved); confirms that the corresponding chassis slot (signal processing module and RF front-end) is in an idle state (indicated by the LED indicator next to the slot: green indicates idle, red indicates occupied); inserts the new signal processing module (FPGA model is consistent with the original, JFM9RFVU3P5G, to ensure compatibility), inserts the new UHF RF front-end, and connects the matching antenna to the new RF front-end through the SMA interface; presses the power switch of the new module, and the indicator light turns green to indicate that the power supply is normal; Step 2: After the new module is powered on, it sends a registration request (including module model, hardware parameters, and serial number) to the device manager via the LAN interface; after verifying the validity of the serial number (the default whitelist is stored in / etc / device_whitelist.txt), the device manager adds the new module information to the resource list (e.g., slot 3: FPGA JFM9RFVU3P5G, 100% available logic units) and synchronizes it to the domain manager; Step 3: The domain manager allocates independent resources (50% FPGA logic units, 1GB memory) to the new module to avoid conflicts with existing modules; the hardware abstraction layer automatically deploys the new AD / DA logic devices and UHF / UHF RF logic device components, which operate independently of existing shortwave-related components without interference; the health management service simultaneously begins monitoring the status of the new module. Step 4: In the waveform deployment management software, the user selects two waveform applications: shortwave Link11 communication and ultra-shortwave Link4A communication, and selects the collaborative work option (to ensure that the timing of the two applications is synchronized). The software automatically deploys the Link11 component to the existing module and the Link4A component to the newly added module, establishing a data interaction channel through the soft bus (transmission rate 1Mbps, latency ≤5ms). The operating frequency band of Link11 is configured as 225MHz and that of Link4A as 255MHz to avoid frequency band interference. Step 5: The user clicks the parameter reading button on the status monitoring interface. The software displays the working parameters (frequency band, power, bandwidth) and module status (temperature, voltage) of the two waveform applications. After confirming that there are no abnormalities, the reconstruction is completed.

[0038] The specific steps for terminal cascading are as follows: Step 1: Connect the LAN ports of the two end devices using a Cat5e Ethernet cable (the LAN label is marked on the back of the end device); enter the cascading settings interface in the waveform deployment management software of the master node end device, enter the IP address of the slave node end device (e.g., 192.168.1.102, the slave node IP can be found using the ifconfig command), and click the connect button; the two end devices will automatically be assigned IP addresses in the same network segment via DHCP (master node 192.168.1.101, slave node 192.168.1.102). After successful connection, the software will display that the cascading link is normal; Step 2: After receiving a connection request, the slave node verifies the master node's identity through the health management service (preset key XYKJ2024; connection is rejected if the key does not match). After successful verification, the slave node's domain manager is automatically destroyed (releasing resource control), and its hardware resource information (such as FPGA model and RF front-end frequency band) is uploaded to the master node's device manager via the LAN interface. The master node's domain manager integrates the slave node's resources into its own resource list, forming a virtual unified terminal, and the slave node's status changes to slave node ready. Step 3: The user deploys a protocol message conversion component (deployment path / opt / components / Proto_Trans) and a cross-network data interaction component in the master node software. The protocol message conversion component is deployed to the master node's main control module and is responsible for converting between Link4A and Link11 protocols (conversion rules are stored in / opt / components / Proto_Trans / rule.xml). The cross-network data interaction component is deployed to the signal processing modules of two end machines respectively, and data forwarding is achieved through Ethernet (10MB forwarding buffer to avoid packet loss). The data forwarding rate is configured to 1Mbps to ensure real-time performance. Step 4: The master node connects to the Link4A network, receives data, converts it to Link11 format through a protocol conversion component, and forwards it to the slave node; the slave node sends data to the Link11 network, and at the same time converts the Link11 network data in reverse and sends it back to the master node; the software data monitoring interface displays the bidirectional data transmission rate and bit error rate (≤0.01% is normal), and the reconstruction is completed after verification.

[0039] In summary, this invention solves the problem of difficult reconfiguration of existing communication equipment through VPX modular hardware architecture, software-hardware decoupling design, and three flexible reconfiguration methods. It has significant advantages such as short cycle time, low cost, high flexibility, and strong scalability, and can be widely used in emergency communication, field operations, multi-band communication and other scenarios.

[0040] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A terminal device for rapid hardware reconfiguration, characterized in that, Includes main control module, signal processing module, RF front end, chassis and antenna; The terminal adopts a VPX architecture. The chassis is provided with multiple slots to support the insertion of multiple signal processing modules and radio frequency front-ends. The main control module, signal processing modules and radio frequency front-ends communicate with each other via PCIe or SIRO. System control and status monitoring are achieved through a local area network, and health management is achieved through an IIC bus. The main control module is equipped with an embedded operating system, a core framework, and basic devices and service components. The core framework includes a domain manager and a device manager. The basic devices and service components constitute a logical abstraction of the hardware platform, and each basic device and service component corresponds to a part of the capabilities or resources of the hardware platform. The terminal is functionally divided into multiple waveform applications. Each waveform application contains multiple waveform components in the form of independent processes. Each waveform component is deployed and runs separately and provides a standard interface. The waveform components communicate with each other through the standard interface and the soft bus. The waveform components of heterogeneous platforms communicate with each other after the message format is uniformly encapsulated through the hardware abstraction layer interface. The waveform applications and functions of the terminal are controlled by external waveform deployment management software. Function switching is achieved by deploying different waveform applications, and the terminal's working status can be adjusted by accessing the attributes attached to the waveform components or by modifying the hardware and software parameters.

2. The terminal device for rapid hardware reconfiguration according to claim 1, characterized in that, The main control module includes a general-purpose processor, which is an ARM processor, an x86 processor, or an ARM core of a SOC chip; the embedded operating system is a Linux operating system, a VxWorks operating system, or a ReWorks operating system.

3. The terminal device for rapid hardware reconfiguration according to claim 1, characterized in that, The signal processing module includes a field-programmable gate array (FPGA) chip and an analog-to-digital (ADC) / digital-to-analog (DAC) chip. The radio frequency front end includes a radio frequency switch, a power amplifier chip, and a filter chip; The terminal is equipped with multiple sets of RF front-ends and antennas adapted to different operating frequency bands. Each set of RF front-ends and antennas can be replaced through the slots in the chassis. Different sets of RF front-ends and antennas are adapted to shortwave, VHF, L-band, S-band and C-band respectively. By replacing different sets of RF front-ends and antennas, the terminal can operate in the corresponding frequency band.

4. The terminal device for rapid hardware reconfiguration according to claim 1, characterized in that, The core framework also implements distributed invocation of waveform components through CORBA middleware. The core framework performs management operations on the waveform components, including installation, creation, startup, shutdown, release, and uninstallation.

5. A method for rapid hardware reconfiguration, characterized in that, The terminal device employing any one of claims 1 to 4 for rapid hardware reconfiguration includes the following steps: Step 1: Based on the target functional requirements, perform hardware reconfiguration on the terminal device. Specifically, the hardware reconfiguration operation can be any one of hardware module replacement, hardware module addition, or terminal device cascading. Step 2: The terminal's health management service monitors hardware status changes in real time. When a hardware refactoring operation is detected, the hardware change information is sent to the device manager of the core framework. Step 3: Based on the hardware change information, the Device Manager triggers the core framework to deploy basic devices and service components adapted to the new hardware through the logical abstraction capabilities of basic devices and service components, thus completing the logical encapsulation of hardware capabilities; Step 4: After receiving the hardware ready notification sent by the core framework, the external waveform deployment management software deploys the corresponding waveform application according to the target functional requirements. Each waveform component of the waveform application is registered to the core framework through a standard interface, and the components establish communication connections through a soft bus or hardware abstraction layer interface. Step 5: By reading and writing the attached attributes of the waveform component, adjust the hardware and software parameters of the terminal to make the terminal run in the target working state and complete the rapid reconstruction.

6. The method for rapid hardware reconfiguration according to claim 5, characterized in that, The hardware module replacement in step 1 is as follows: the object of the hardware module replacement is the radio frequency front end. The replacement is completed by removing the original radio frequency front end from the terminal chassis slot and installing a new radio frequency front end adapted to the target frequency band. The parameters of the radio frequency switch, power amplifier chip and filter chip of the new radio frequency front end are matched with the target frequency band.

7. The method for rapid hardware reconfiguration according to claim 5, characterized in that, The addition of hardware modules in step 1 is as follows: the added hardware modules are a signal processing module and an RF front-end. Select an unoccupied slot in the terminal chassis, and insert the newly added signal processing module and the RF front-end adapted to the new frequency band in sequence. The FPGA chip of the newly added signal processing module and the AD / DA chip of the newly added RF front-end are pre-complied with hardware.

8. The method for rapid hardware reconfiguration according to claim 5, characterized in that, In step 1, the terminal cascading is performed as follows: the local area network interfaces of the two terminal devices are connected via Ethernet, and one of them is set as the master terminal and the other as the slave terminal through waveform deployment management software. The IP addresses of the master terminal and the slave terminal are in the same local area network segment to achieve communication.

9. The method for rapid hardware reconfiguration according to claim 5, characterized in that, The deployment of basic equipment and service components in step 3 includes the following steps: After the device manager reads the model identifier of the new hardware, it calls the appropriate basic devices and service components from the preset component library. If it is a replacement of the RF front end, it deploys the RF logic device and FPGA logic device of the corresponding frequency band. If it is a module addition, it adds and registers the corresponding model of AD / DA logic device and FPGA logic device.

10. A method for rapid hardware reconfiguration according to claim 5, characterized in that, Step 4, the waveform application deployment, includes the following steps: The waveform deployment management software selects the corresponding waveform application from the waveform library according to the target function, and deploys the multiple waveform components contained in the waveform application to the main control module and the signal processing module in a preset order. After deployment, each waveform component registers with the domain manager of the core framework through a standard interface.

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