FPGA-based power grid dedicated communication protocol transmission method, system and device

Abstract

The application relates to a power grid special communication protocol transmission method, system and device based on FPGA. The method mainly comprises the following steps: packaging data to be transmitted into frame structure data; performing forward error correction coding on the frame structure data at a sending end to form extended frame structure data; transmitting the extended frame structure data to a receiving end through a communication link; performing forward error correction decoding on the received frame structure data at the receiving end to obtain decoded frame structure data; performing frame disassembling processing on the decoded frame structure data to extract valid data; and checking the valid data, and completing data receiving when the checking is passed. The application can solve the protocol jamming problem caused by asymmetric bandwidth, and improve the reliability and efficiency of data transmission of a power optical fiber communication system.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, system and apparatus for transmitting a power grid-specific communication protocol based on FPGA. Background Technology

[0002] With the increasing demand for power grid communication, traditional embedded data transmission protocols can no longer meet the requirements for high performance and high reliability. Field Programmable Gate Arrays (FPGAs) are widely used in embedded data processing and transmission fields due to their high efficiency and flexibility.

[0003] Existing power grid communication technologies, especially power fiber optic communication, often suffer from bandwidth asymmetry, which leads to protocol blocking due to bandwidth differences. This further results in poor reliability and low efficiency in power grid data transmission.

[0004] In view of this, how to overcome the shortcomings of existing technologies and how to solve the bandwidth asymmetry problem in power grid communication technology have become important technical challenges that the industry urgently needs to address. Summary of the Invention

[0005] Addressing the shortcomings or improvement needs of existing technologies: Existing power grid communication technologies, especially power fiber optic communication, often suffer from bandwidth asymmetry, leading to protocol blocking issues due to bandwidth differences. This further contributes to poor reliability and low efficiency in power grid data transmission. This invention provides an FPGA-based method, system, and apparatus for transmitting dedicated power grid communication protocols, aiming to solve the bandwidth asymmetry problem and improve the reliability and efficiency of power grid data transmission.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a power grid-specific communication protocol transmission method based on FPGA, comprising:

[0008] Pack the data to be transmitted into frame structure data;

[0009] At the transmitting end, forward error correction coding is performed on the frame structure data to form the expanded frame structure data;

[0010] The extended frame structure data is transmitted to the receiving end via a communication link;

[0011] At the receiving end, forward error correction decoding is performed on the received frame structure data to obtain the decoded frame structure data; the decoded frame structure data is then split into frames to extract the valid data; the valid data is then verified, and if the verification passes, the data reception is complete.

[0012] In some embodiments, packaging the data to be transmitted into frame structure data specifically includes: packaging the data to be transmitted into frame structure data containing a frame header, management information, and data payload, wherein:

[0013] The frame header is used to identify the beginning of a frame;

[0014] The management information includes pointer information used to mark the specific position of each data packet in the message and an LEN field that records the effective data length;

[0015] The data payload includes the actual valid data transmitted.

[0016] In some embodiments, performing forward error correction coding on the frame structure data at the transmitting end to form extended frame structure data specifically includes:

[0017] Using RS encoding, a second-byte check data stream is generated based on the first-byte input data stream in the frame structure data, to form a third-byte output data stream, wherein the third-byte count is equal to the sum of the first-byte count and the second-byte count.

[0018] In some embodiments, the extended frame structure data further includes a padding field for storing a verification data stream generated during forward error correction coding.

[0019] Secondly, the present invention also provides an FPGA-based power grid dedicated communication protocol transmission system, which applies the FPGA-based power grid dedicated communication protocol transmission method described in the first aspect. The system includes a TX_module module, an RS_encode module, an RS_decode module, and an RX_module module, wherein:

[0020] The TX_module module is used to package the data to be transmitted into frame structure data;

[0021] The RS_encode module is used to perform forward error correction encoding on the frame structure data to form the extended frame structure data.

[0022] The RS_decode module is used to perform forward error correction decoding on the received frame structure data to obtain the decoded frame structure data.

[0023] The RX_module module is used to split the decoded frame structure data into frames to extract valid data; and to verify the valid data. If the verification is successful, the data reception is completed.

[0024] In some embodiments, a client_rx module is also included, which is used to receive and process data streams, count the number of data packets and their lengths, and store the received data and lengths in a FIFO so that the TX_module module can read data from the client_rx module and output the corresponding frame structure data.

[0025] In some embodiments, a PRBS module is also included, which is used to generate a number of random bits as the basis for data transmission.

[0026] In some embodiments, a top-level file module, top, is also included, which is used to call and manage all other modules.

[0027] Thirdly, the present invention also provides a power grid-specific communication protocol transmission device based on FPGA, the device comprising:

[0028] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the FPGA-based power grid dedicated communication protocol transmission method described in the first aspect.

[0029] Fourthly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions, which are executed by one or more processors to perform the FPGA-based power grid dedicated communication protocol transmission method described in the first aspect.

[0030] Compared with the prior art, the present invention provides a method, system and device for transmitting power grid-specific communication protocols based on FPGA. Its beneficial effects are: to perform data framing, error correction and transmission on the transmitting end signal, and to perform data deframing, verification and reception on the receiving end, aiming to solve the protocol congestion problem caused by bandwidth asymmetry, so as to improve the reliability and efficiency of data transmission in power fiber optic communication systems.

[0031] The embodiments of the present invention are applicable to a variety of communication environments and application scenarios, especially to the interoperability of power grid dedicated communication equipment. They are characterized by low cost and high compatibility, and have broad application prospects and market potential. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0033] Figure 1 A flowchart of a power grid-specific communication protocol transmission method based on FPGA provided in Embodiment 1 of the present invention;

[0034] Figure 2 This is a schematic diagram of a power grid-specific communication protocol transmission system based on FPGA provided in Embodiment 2 of the present invention;

[0035] Figure 3 This is a schematic diagram of a power grid-specific communication protocol transmission device based on FPGA, provided in Embodiment 4 of the present invention. Detailed Implementation

[0036] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention. It should be noted that, unless otherwise specified, the various features in the embodiments of the present invention can be combined with each other, all within the protection scope of this application. Furthermore, although functional modules may be divided in the device schematic diagram, and a logical order may be shown in the flowchart, in some cases, the steps shown or described may be executed differently from the module division in the device or the order in the flowchart.

[0037] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

[0038] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0039] This invention aims to solve the protocol congestion problem caused by bandwidth differences in power fiber optic communication. By designing a transmission protocol with a transmitting bandwidth of 2kbps and a receiving bandwidth of 625Mbps, this invention achieves reliable data transmission and reception. The protocol performs data framing, error correction, transmission, and frame deframing verification at the transmitting end, aiming to solve the protocol congestion problem caused by bandwidth asymmetry and improve the reliability and efficiency of data transmission in power fiber optic communication systems.

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. The invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Example 1:

[0042] like Figure 1 As shown in the figure, this embodiment of the invention provides a power grid-specific communication protocol transmission method based on FPGA, which includes the following steps.

[0043] Step 101: Pack the data to be transmitted into frame structure data. In some embodiments, packing the data to be transmitted into frame structure data specifically includes: packing the data to be transmitted into frame structure data containing a frame header, management information, and a data payload, wherein: the frame header is used to identify the start of the frame; the management (MGT) information includes pointer information used to mark the specific position of each data packet in the message and a LEN field recording the effective data length; the data payload includes the actual effective data to be transmitted. This step involves data framing at the sending end, packing the data to be transmitted into a frame structure containing a frame header, management information, and a data payload.

[0044] It should be noted that the LEN field mentioned above can be a field output by the LEN function. The LEN function is a computer programming term commonly used in Excel software. Its function is to return the number of characters in a text string, and its syntax is Len(text).

[0045] Step 102: Perform forward error correction encoding on the frame structure data at the transmitting end to form extended frame structure data. In some embodiments, performing forward error correction (FEC) encoding on the frame structure data at the transmitting end to form extended frame structure data specifically includes: using RS encoding, generating a second-byte-sized check data stream based on the first-byte-sized input data stream in the frame structure data to form a third-byte-sized output data stream, wherein the third-byte-sized number is equal to the sum of the first-byte-sized number and the second-byte-sized number. In some embodiments, the extended frame structure data further includes a padding field, which is used to store the check data stream generated during forward error correction encoding. In this step, forward error correction encoding is performed on the framed data at the transmitting end using RS encoding technology, and extended frame data is formed by generating a check data stream to enhance the anti-interference capability of data transmission.

[0046] It should be noted that FEC is an encoding scheme used in Ethernet. This scheme employs the Reed-Solomon (RS) encoding algorithm, which is designed to improve the reliability of data transmission.

[0047] For example, in one embodiment, RS(255, 239) encoding is used during the forward error correction encoding process. That is, based on the original 239-byte input data stream, a 16-byte check data stream is generated to form a 255-byte output data stream. The maximum error correction capability in this method is 8 bytes.

[0048] Step 103: Transmit the extended frame structure data to the receiving end via the communication link. In this step, the communication link supports the transmission of low-rate signals between the sending and receiving ends.

[0049] Step 104: At the receiving end, forward error correction decoding is performed on the received frame structure data to obtain the decoded frame structure data; the decoded frame structure data is then split into frames to extract valid data; the valid data is verified, and if the verification passes, data reception is complete. In this step, forward error correction decoding is performed on the received frame data at the receiving end to correct possible transmission errors and recover the original valid data; the decoded frame data is then split into frames at the receiving end to extract valid data, and reception verification is performed to verify the integrity and accuracy of the data.

[0050] The method described in this embodiment is applicable to power fiber optic communication systems with a transmitting end bandwidth of 2kbps and a receiving end bandwidth of 625Mbps. It solves the protocol blocking problem caused by bandwidth differences and realizes reliable transmission of low-speed signals.

[0051] In one embodiment, the method further includes the step of automatically sending frame data at a predetermined period at the sending end, and the step of continuously processing and verifying the received frame data at the receiving end, so as to ensure continuous data transmission and reliability.

[0052] In summary, this invention provides a power grid-specific communication protocol transmission method based on FPGA. The method performs data framing, error correction, and transmission at the transmitting end, and data deframing, verification, and reception at the receiving end. It aims to solve the protocol congestion problem caused by bandwidth asymmetry, thereby improving the reliability and efficiency of data transmission in power fiber optic communication systems.

[0053] The embodiments of the present invention are applicable to a variety of communication environments and application scenarios, especially to the interoperability of power grid dedicated communication equipment. They are characterized by low cost and high compatibility, and have broad application prospects and market potential.

[0054] Example 2:

[0055] Based on the foregoing embodiments, this invention provides an FPGA-based power grid dedicated communication protocol transmission system, applying the FPGA-based power grid dedicated communication protocol transmission method described in the previous embodiments, with reference to... Figure 2 As shown, the system includes a TX_module module, an RS_encode module, an RS_decode module, and an RX_module module, wherein: the TX_module module is used to package the data to be transmitted into frame structure data; the RS_encode module is used to perform forward error correction encoding on the frame structure data to form extended frame structure data; the RS_decode module is used to perform forward error correction decoding on the received frame structure data to obtain decoded frame structure data; the RX_module module is used to perform frame splitting processing on the decoded frame structure data to extract valid data; and to verify the valid data, if the verification passes, the data reception is completed.

[0056] In some embodiments, a client_rx module is also included, which is used to receive and process data streams, count the number of data packets and their lengths, and store the received data and lengths in the FPGA so that the TX_module module can read data from the client_rx module and output the corresponding frame structure data.

[0057] In some embodiments, a PRBS module is also included, which is used to generate a number of random bits as the basis for data transmission. A pseudo-random binary sequence (PRBS) is a pseudo-random sequence containing only 0s and 1s. If a sequence is both predetermined and repeatedly produced and replicated, and also possesses certain random characteristics (i.e., statistical characteristics) of a random sequence, then we call such a sequence a pseudo-random sequence.

[0058] In some embodiments, a top-level file module, top, is also included, which is used to call and manage all other modules.

[0059] The purpose of this invention is to effectively handle the significant bandwidth difference between an uplink bandwidth of 2kbps and a downlink bandwidth of 625Mbps, ensuring reliable data transmission in complex network environments.

[0060] Overall, in one embodiment, the system comprises: a top-level file module (top), a PRBS module, a client_rx module, a TX_module module, an RS_encode module, an RS_decode module, and an RX_module module. The specific workflows of each of these modules are as follows:

[0061] First, the top-level `top` module is responsible for calling and managing all sub-modules. The main function of the `PRBS` module is to generate 64-bit random numbers, which will serve as the basis for subsequent data transmission. The `client_rx` module is used to receive and process data streams, count the number of data packets and their length, and store the received data and length in the FPGA for use by subsequent processing modules.

[0062] Based on this, the TX_module reads data from the client_rx module and outputs the corresponding messages. The function of the TX_module is to integrate the generated random number with the frame header, MGT information, and valid data padding. The MGT information records the data length of each frame, ensuring that the output data format conforms to the standard. The parameters of the valid data module are set to 234 bytes. Since the experimentally simulated transmission signal bandwidth is only 2kbps, considering the protocol transmission rate, the length of the data portion should not be too large. The subsequent error correction process uses the FEC(255,239) error correction scheme.

[0063] Subsequently, 234 valid data points are input into the RS_encode core for forward error correction encoding. After processing, the encoded data is expanded to 255 data points.

[0064] Finally, after receiving the frame data that has been corrected by the RS_encode module, the RX_module module performs frame splitting and verification, and finally outputs a valid signal to ensure that each frame of 234 bytes of data is transmitted correctly and completely.

[0065] In the above process, the TX_module and RS_encode modules complete signal framing and error correction coding at the transmitting end. After transmission through optical fiber and sampling by an analog-to-digital converter (ADC), the data enters the receiving end. The data, after FEC error correction and expansion, is sent to the RS_decode module, where it is decoded and error corrected to extract valid data and ensure that the received data structure is correctly recovered.

[0066] Through the above process, the entire process of data framing, error correction, transmission, and frame deframing verification upon reception is successfully completed. This cyclical process ensures continuous data transmission within the network, improving the reliability and accuracy of communication.

[0067] In one embodiment, FPGA is used to implement functional modules such as data framing, forward error correction coding, forward error correction decoding, frame splitting, and reception verification. By flexibly configuring these modules, the system can adapt to scenarios with extremely large bandwidth differences and ensure the smooth operation of the communication protocol.

[0068] In one embodiment, the system can be further divided into a transmitting module, a receiving module, and a communication link connecting the transmitting module and the receiving module. The transmitting module is used to implement data framing and forward error correction coding functions; the receiving module is used to implement forward error correction decoding, frame deframing, and reception verification functions; the communication link supports the transmission of low-rate signals between the transmitting and receiving ends.

[0069] In one embodiment, the system further includes a wiring diagram and a resource table to illustrate the structure and connections of the system.

[0070] In one embodiment, an FPGA board is used to simulate a 2K low-rate signal during the experiment; the transmission and reception of the low-rate signal are simulated by controlling the clock. The experiment verifies the stability and reliability of the system, as well as the entire process of framing, error correction, transmission, and frame deframing verification.

[0071] The main features of this system include:

[0072] Designed using a dedicated power grid communication protocol: This embodiment adopts a low-speed signal transmission protocol based on FPGA, which can solve the protocol blocking problem caused by bandwidth differences in power fiber optic communication, and provide a reliable sending and receiving communication mechanism to support stable signal transmission in environments with extremely large bandwidth differences.

[0073] Targeted design: Specifically designed for power grid communication, addressing the significant bandwidth difference between transmit bandwidth as low as 2kbps and receive bandwidth as high as 625Mbps.

[0074] Data transmission reliability: Through the entire process of framing, error correction, transmission, and frame deframing verification of reception, reliable data transmission in complex network environments is ensured.

[0075] Forward error correction coding: The RS_encode module is used to implement forward error correction coding, which enhances the anti-interference ability of data transmission and improves data integrity.

[0076] Efficient data processing: The TX_module integrates random numbers, frame headers, MGT information, and valid data to form a complete data frame.

[0077] Cyclic redundancy check (CRC): CRC verification is performed by the RX_module to ensure data integrity and accuracy, thereby improving the accuracy of data transmission.

[0078] Flexibility and scalability: The programmability of FPGAs enables protocols to easily handle various complex network protocols, improving network compatibility and scalability.

[0079] Optimize bandwidth asymmetry: To address the imbalance in bandwidth configuration, an optimization scheme is proposed to enhance uplink bandwidth capabilities and improve network performance.

[0080] In summary, this invention provides an FPGA-based power grid-specific communication protocol transmission system that performs data framing, error correction, and transmission at the transmitting end, and data deframing, verification, and reception at the receiving end. This aims to solve the protocol congestion problem caused by bandwidth asymmetry, thereby improving the reliability and efficiency of data transmission in power fiber optic communication systems.

[0081] The embodiments of the present invention are applicable to a variety of communication environments and application scenarios, especially to the interoperability of power grid dedicated communication equipment. They are characterized by low cost and high compatibility, and have broad application prospects and market potential.

[0082] Example 3:

[0083] Based on the FPGA-based power grid dedicated communication protocol transmission method and system provided in the above embodiments, Embodiment 3 of the present invention provides a specific example for illustration.

[0084] Examples of the above solutions are as follows:

[0085] In this embodiment, the aim is to implement a power grid-specific communication handshake protocol capable of handling significant bandwidth differences using an FPGA. First, two FPGA boards are used as the signal transmitter and receiver, respectively. These boards will be used to simulate a real power grid communication environment, where the transmitter generates a low-rate 2K signal, while the receiver uses a rate of 625Mbps.

[0086] At the software level, an FPGA project was created using the Vivado design suite, and a top-level file, `top`, was written to coordinate the operations of various submodules. Vivado is an integrated design environment developed by Xilinx, primarily used for FPGA design and development. First, the scheme designed a PRBS module, which generates 64-bit random numbers that will serve as the basis for subsequent data transmission. Next, the scheme implemented the TX_module module, which integrates the random numbers generated by the PRBS module with a 4-byte frame header, 5 bytes of MGT information, and 234 bytes of valid data padding into a complete data frame, ensuring that the output data format conforms to the standard.

[0087] The frame structure output by the TX_module module and the frame structure output by the RS_encode module in this embodiment are shown in the table below.

[0088]

[0089]

[0090] To improve data transmission reliability, the experiment adopted a (255, 239) error correction scheme. In this scheme, 234 bytes of valid data and 5 bytes of management data, totaling 239 bytes, are input into the RS_encode module for forward error correction encoding. After padding with 16 bytes of error correction encoding, 255 bytes of data are output. Subsequently, these 255 bytes of data are sent to the RS_decode module for decoding and error correction, extracting the valid 234 bytes of data.

[0091] Finally, the RX_module receives the frame data and performs verification. If verification fails, no valid signal is output; if the frame data passes verification, a valid frame signal is output and valid data is transmitted. To verify the system's stability and reliability, a 2K low-rate signal is simulated by controlling the clock, sent from the transmitting board to the link, sampled by the ADC, and received by the receiving end. Experimental results show that the entire signal transmission process is completed smoothly. The low-rate signal is successfully framed at the transmitting end, and after link transmission and ADC sampling, the signal is successfully deframed at the receiving end and accurately received after verification.

[0092] This invention successfully demonstrates the effectiveness of an FPGA-based power grid-specific communication protocol transmission method. This method not only improves the reliability and efficiency of power grid data transmission, but also achieves reliable data transmission through the high efficiency and flexibility of FPGAs, making it particularly suitable for power grid communication environments with asymmetrical bandwidth.

[0093] Example 4:

[0094] Based on the FPGA-based power grid dedicated communication protocol transmission method provided in Embodiment 1 above, the present invention also provides an FPGA-based power grid dedicated communication protocol transmission device that can be used to implement the above method and system, such as... Figure 3 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. This embodiment of the FPGA-based power grid dedicated communication protocol transmission device includes one or more processors 21 and a memory 22. Wherein, Figure 3 Take a processor 21 as an example.

[0095] Processor 21 and memory 22 can be connected via a bus or other means. Figure 3 Taking the example of a connection between China and Israel via a bus.

[0096] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the FPGA-based power grid dedicated communication protocol transmission method in Embodiment 1. The processor 21 executes various functional applications and data processing of the FPGA-based power grid dedicated communication protocol transmission device by running the non-volatile software programs, instructions, and modules stored in the memory 22, thereby implementing the FPGA-based power grid dedicated communication protocol transmission method of Embodiment 1.

[0097] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0098] The program instructions / modules are stored in memory 22. When executed by one or more processors 21, they perform the FPGA-based power grid dedicated communication protocol transmission method described in Embodiment 1 above, for example, performing the above-described... Figure 1 The steps shown.

[0099] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the methods provided in the embodiments of this application.

[0100] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software and a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power grid-specific communication protocol transmission method based on FPGA, characterized in that, include: Pack the data to be transmitted into frame structure data; At the transmitting end, forward error correction coding is performed on the frame structure data to form the expanded frame structure data; The extended frame structure data is transmitted to the receiving end via a communication link; At the receiving end, forward error correction decoding is performed on the received frame structure data to obtain the decoded frame structure data; The decoded frame structure data is split into frames to extract valid data; the valid data is then verified, and if the verification passes, the data reception is complete.

2. The FPGA-based power grid dedicated communication protocol transmission method according to claim 1, characterized in that, The process of packaging the data to be transmitted into frame structure data specifically includes: packaging the data to be transmitted into frame structure data containing a frame header, management information, and data payload, wherein: The frame header is used to identify the beginning of a frame; The management information includes pointer information used to mark the specific position of each data packet in the message and an LEN field that records the effective data length; The data payload includes the actual valid data transmitted.

3. The FPGA-based power grid dedicated communication protocol transmission method according to claim 1, characterized in that, The step of performing forward error correction coding on the frame structure data at the transmitting end to form the expanded frame structure data specifically includes: Using RS encoding, a second-byte check data stream is generated based on the first-byte input data stream in the frame structure data, to form a third-byte output data stream, wherein the third-byte count is equal to the sum of the first-byte count and the second-byte count.

4. The FPGA-based power grid dedicated communication protocol transmission method according to claim 3, characterized in that, The extended frame structure data also includes a padding field, which is used to store the verification data stream generated during forward error correction coding.

5. An FPGA-based power grid dedicated communication protocol transmission system, employing the FPGA-based power grid dedicated communication protocol transmission method as described in any one of claims 1-4, characterized in that, The system includes the TX_module, RS_encode module, RS_decode module, and RX_module, wherein: The TX_module module is used to package the data to be transmitted into frame structure data; The RS_encode module is used to perform forward error correction encoding on the frame structure data to form the extended frame structure data. The RS_decode module is used to perform forward error correction decoding on the received frame structure data to obtain the decoded frame structure data. The RX_module module is used to split the decoded frame structure data into frames to extract valid data; and to verify the valid data. If the verification is successful, the data reception is completed.

6. The FPGA-based power grid dedicated communication protocol transmission system according to claim 5, characterized in that, It also includes a client_rx module, which is used to receive and process data streams, count the number of data packets and their lengths, and store the received data and lengths in a FIFO so that the TX_module module can read data from the client_rx module and output the corresponding frame structure data.

7. The FPGA-based power grid dedicated communication protocol transmission system according to claim 5, characterized in that, It also includes a PRBS module, which is used to generate a number of random bits as the basis for data transmission.

8. The FPGA-based power grid dedicated communication protocol transmission system according to claim 5, characterized in that, It also includes the top-level file module, which is used to call and manage all other modules.

9. A power grid-specific communication protocol transmission device based on FPGA, characterized in that, The apparatus includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the FPGA-based power grid dedicated communication protocol transmission method according to any one of claims 1-4.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which are executed by one or more processors to perform the FPGA-based power grid-specific communication protocol transmission method as described in any one of claims 1-4.

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