Neuron-like transistor device and method of controlling the same

Abstract

The application provides a neuron-like transistor device, which comprises a substrate, a buried oxygen layer and a channel layer which are sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source electrode and a drain electrode which are respectively located on both sides of the channel layer. The gate electrode is used for applying a front gate voltage as an input signal, the drain electrode is used for applying a constant input current, the voltage of the drain electrode is used as an output signal, and the input signal is changed in a step-by-step manner from small to large. The neuron nonlinear activation of a single device is realized, and it is possible to build a complete and programmable artificial neuron by using a single or few transistors. The neuron-like transistor device has a simple structure, and a manufacturing process which is suitable for a CMOS manufacturing process. The measurement method of the neuron-like transistor device is simple, and an electrode does not need to be additionally introduced, so that the simulation of the neuron characteristics can be realized without additional device design, the integration density of the transistors in a chip is improved, and the neuron-like transistor device is suitable for the integration of a large-scale circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a neuron-like transistor device and its control method. Background Technology

[0002] In recent years, with the rapid increase in the demand for high-efficiency and low-power computing in artificial intelligence, the traditional von Neumann architecture faces challenges in handling neuromorphic computing tasks due to data transmission bottlenecks. Neuromorphic computing, by simulating the information processing mechanisms of neurons and synapses in the biological brain, provides a revolutionary path to achieving next-generation high-efficiency intelligent computing.

[0003] However, most neurons used in current neuromorphic models are based on CMOS technology, utilizing discrete components such as multiple transistors, operational amplifiers, and capacitors to construct complex differential equation circuits (such as the Hodgkin-Huxley or leaky integral-fire model). While this approach is functionally accurate, it results in large circuit areas, high power consumption, and difficulty in large-scale integration. Furthermore, the core parameters of neurons (such as thresholds) are usually fixed, making dynamic reconstruction difficult. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a neuron-like transistor device and its control method, which realizes nonlinear activation of neurons in a single device, has a simple device structure, and is compatible with CMOS fabrication process.

[0005] This application provides a neuron-like transistor device, including:

[0006] A substrate, a buried oxide layer and a channel layer sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer; and a source electrode and a drain electrode located on opposite sides of the channel layer, respectively.

[0007] The gate is used to apply a front gate voltage as an input signal, the drain is used to apply a constant input current, and the voltage of the drain is used as an output signal; the input signal changes in a stepwise manner from small to large.

[0008] In some possible implementations, the substrate is used to apply a back-gate voltage, which serves as a neuronal excitability control signal.

[0009] In some possible implementations, when the substrate includes multiple gates, the substrate is connected to the back gate voltage via a common contact.

[0010] In some possible implementations, the back gate voltage ranges from -20V to 0V.

[0011] In some possible implementations, the input current ranges from 0 to 1 pA.

[0012] In some possible implementations, the front gate voltage ranges from -0.2V to 1.2V.

[0013] In some possible implementations, the total duration of the application of the front gate voltage ranges from 1 ms to 100 s.

[0014] In some possible implementations, the thickness of the buried oxide layer ranges from 20 to 25 nm, and / or the thickness of the channel layer is less than or equal to 12 nm, and / or the doping concentration of the channel layer ranges from 1 × 10⁻⁶. 5 ~1×10 6 cm - ³.

[0015] This application also provides a control method for a neuron-like transistor device, the method comprising:

[0016] For the aforementioned neuron-like transistor device, a front gate voltage is applied to the gate as an input signal, a constant input current is applied to the drain, and the voltage of the drain is detected as an output signal. The input signal changes in a stepwise manner from small to large.

[0017] In some possible implementations, the method further includes:

[0018] A back-gate voltage is applied to the substrate, which serves as a neuronal excitability control signal.

[0019] This application provides a neuron-like transistor device and its control method. The neuron-like transistor device includes a substrate, a buried oxide layer and a channel layer stacked sequentially on the substrate, a gate oxide layer and a gate on the channel layer, and source and drain electrodes located on opposite sides of the channel layer. The gate is used to apply a front gate voltage as an input signal, the drain is used to apply a constant input current, and the drain voltage serves as the output signal. The input signal varies stepwise from small to large. This enables nonlinear activation of neurons in a single device, making it possible to construct fully functional, programmable artificial neurons with a single or minimal number of transistors, providing a unique device foundation for building high-efficiency, highly integrated neuromorphic computing chips. This neuron-like transistor device has a simple structure, its manufacturing process is compatible with CMOS fabrication processes, and its measurement method is simple, requiring no additional electrodes. Therefore, it does not require additional device design to simulate neuron characteristics, which is beneficial for increasing the integration density of transistors in the chip and is suitable for large-scale circuit integration. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This illustration shows a schematic diagram of the electrical behavior of an FDSOI transistor as a neuron according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a measurement method provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the structure of a neuron-like transistor device provided in an embodiment of this application;

[0024] Figure 4 A schematic diagram illustrating the variation of output voltage with input voltage, provided for an embodiment of this application;

[0025] Figure 5 A circuit layout of a neuron-like transistor device provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram illustrating the output characteristics at different scanning speeds, provided as an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0028] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0029] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0030] Most neurons used in current neuromorphic studies are based on CMOS technology, utilizing discrete components such as multiple transistors, operational amplifiers, and capacitors to construct complex differential equation circuits (such as the Hodgkin-Huxley or leaky integral-fire model). While this approach offers precise functionality, it results in large circuit areas, high power consumption, and difficulty in large-scale integration. Furthermore, the core parameters of neurons (such as thresholds) are typically fixed, making dynamic reconstruction challenging.

[0031] In recent years, fully depleted silicon-on-insulator (FDSOI) technology has attracted attention in the field of neuromorphic computing due to its excellent back-gate control capabilities. However, designing bulk contacts requires the introduction of an additional electrode during the design process, necessitates modifications to standard processes, is not fully compatible with CMOS processes, and the additional electrode reduces the integration density of the circuit.

[0032] Specifically, by utilizing the inherent electrical characteristics of the FDSOI transistor, an electrode is led out at the body (channel) terminal to measure the body potential. (or denoted as) ) and gate bias The relationship between neurons is used to simulate their behavior. (Reference) Figure 1 The diagram shown illustrates the electrical behavior of an FDSOI transistor as a neuron according to an embodiment of this application, where the horizontal axis represents... The vertical axis is The units are all volts (V), and each curve indicates a different back gate voltage. Body potential measured under ) With gate bias The relationship.

[0033] refer to Figure 2 The diagram shown is a schematic representation of a measurement method provided in an embodiment of this application. This testing method is used to obtain... Figure 1 The electrical behavior of the device is shown in the figure. The left side of the figure is the structure of the FDSOI MOSFET, and the right side is the electrode layout of the device. The device includes a substrate (Si substrate) 100, a buried plane (GP) 110, a buried oxide (BOX) 120, a channel layer (e.g., P-type doped) 130, a gate oxide layer 140 and a gate 150 stacked sequentially on the substrate 100. The gate 150 is covered by a protective layer 210. Different devices are isolated by a shallow trench isolation (STI) 200 structure. The source 160 and drain 170 are heavily doped (e.g., N-type doped) and led out through a first resistive layer (RSD) 180 and a second resistive layer 190, respectively.

[0034] This test method requires a five-terminal device, including a gate ( ), source pole ( ), drain ( ), back grille ( ) and the body region where the channel is located ( This means that body electrodes need to be specially designed and brought out during layout design, which is incompatible with traditional CMOS processes because it requires modifying standard processes to additionally implement body contacts, increasing manufacturing difficulty. Furthermore, the additional body contacts may introduce other parasitic effects. In large-scale integrated circuit design, each neural unit requires additional electrodes to connect to the body, which occupies wiring space and reduces integration density.

[0035] Currently, there are also digital signal controlled neuron circuits that realize neuronal impulse response modes. However, this approach requires dozens or hundreds of standard CMOS transistors to build impulse generation and control units, which limits the integration density and efficiency in large-scale neuromorphic arrays.

[0036] Based on the above technical problems, this application provides a neuron-like transistor device and its control method. The neuron-like transistor device includes a substrate, a buried oxide layer and a channel layer stacked sequentially on the substrate, a gate oxide layer and a gate on the channel layer, and a source and a drain located on opposite sides of the channel layer. The gate is used to apply a front gate voltage as an input signal, the drain is used to apply a constant input current, and the drain voltage serves as the output signal. The input signal changes stepwise from small to large. This achieves nonlinear activation of neurons in a single device, making it possible to construct fully functional, programmable artificial neurons with a single or very few transistors, providing a unique device foundation for building high-efficiency, highly integrated neuromorphic computing chips. This neuron-like transistor device has a simple structure, its manufacturing process is compatible with CMOS fabrication processes, and its measurement method is simple, requiring no additional electrodes. Therefore, no additional device design is needed to simulate neuron characteristics, which is beneficial for increasing the integration density of transistors in the chip and is suitable for large-scale circuit integration.

[0037] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0038] refer to Figure 3The diagram shown is a schematic diagram of a neuron-like transistor device provided in an embodiment of this application. The neuron-like transistor device includes a substrate 100, a buried oxide (BOX) layer 120 and a channel layer 130 stacked sequentially on the substrate 100, a gate oxide layer 140 and a gate electrode 150 (G) on the channel layer 130, and a source electrode (S) 160 and a drain electrode (D) 170 located on both sides of the channel layer 130.

[0039] The substrate 100 can be a semiconductor substrate, providing support for the film layers thereon. For example, it can be a silicon substrate or a germanium substrate. The buried oxide layer 120 is an insulating layer used to isolate the channel layer from the substrate, preventing carrier leakage from the channel layer during device operation. The buried oxide layer can be, for example, silicon oxide or germanium oxide. The channel layer can be made of silicon (Si) or germanium. A buried ground plane with a high doping concentration is also disposed between the buried oxide layer and the substrate, allowing connection to the back gate voltage.

[0040] The channel layer 130 has a low or no doping concentration to ensure complete depletion. For example, it can be p-type doped or n-type doped; the following explanation will use a p-type doped channel as an example. The doping concentration range of the channel layer 130 is 1 × 10⁻⁶. 5 ~1×10 6 cm - ³. The thickness of the buried oxide layer 120 ranges from 20 to 25 nm, and the thickness of the channel layer 130 is less than or equal to 12 nm. It should be noted that the doping range and thickness range in this application include the endpoints, and the same applies to other ranges thereafter.

[0041] In addition, the device includes a buried plane (GP) 110 between the substrate 100 and the buried oxide layer 120, a gate layer 150 covered by a protective layer 210, and shallow trench isolation (STI) 200 structures to isolate different devices. The source 160 and drain 170 are heavily doped (e.g., N-type doped) and led out through a first resistive layer (RSD) 180 and a second resistive layer 190, respectively. The buried plane 110 can be heavily doped, so the substrate 100 can be led out through the buried plane to connect to the back gate voltage.

[0042] Different process nodes may have different device sizes. For example, at the 28nm process node, the channel layer thickness ranges from 7 to 12nm and the gate length is 28nm; at the 22nm process node, the channel layer thickness ranges from 6 to 8nm and the gate length is 22nm; and at the 14nm process node, the channel layer thickness ranges from 5 to 7nm and the gate length is 14nm.

[0043] The gate is used to apply the front gate voltage. As the input signal, the drain is used to apply a constant input current, and the drain voltage (Drain voltage) The drain voltage is used as the output signal. In other words, the gate (also called the front gate) is used as the signal input terminal, and a constant input current is applied to the drain. The drain voltage is measured as the neuron's output, with the input signal changing in a stepwise manner from small to large. In this mode, the drain voltage exhibits abrupt changes with the front gate voltage.

[0044] The front gate voltage ranges from -0.2V to 1.2V. The total application duration of the front gate voltage ranges from 1ms to 100s, for example, from 6ms to 60s, allowing the application duration of each front gate voltage to vary with the total duration, thus achieving voltage sweeps (V-sweep) at different speeds. This voltage sweep can be implemented by setting the B1500A SMU. The input current ranges from 0 to 1pA.

[0045] refer to Figure 4 The diagram shown illustrates the variation of output voltage with input voltage according to an embodiment of this application, where the horizontal axis represents the front gate voltage. The vertical axis represents the drain voltage. As shown in the figure, during long sweeping, the front gate voltage pushes holes towards the volume. When the input signal is weak, the number of holes pushed towards the volume is small, and the output drain voltage is very small, equivalent to a neuron in a silent state. Once the input signal exceeds a critical point, the number of holes pushed towards the volume increases further, and the output signal spikes sharply, equivalent to a neuron generating an action potential, forming a significant pulse response. Subsequently, after the device is fully turned on, under the effect of the device's supercoupling, holes leave the volume region through the source. At this time, the hole concentration drops by an order of magnitude, and the output signal drops rapidly. The drop in peak value simulates the behavior of rapid reset.

[0046] refer to Figure 5 The diagram shown is a circuit layout of a neuron-like transistor device according to an embodiment of this application. This structure utilizes the floating body effect of FDSOI MOSFETs, using the drain voltage as the output signal. It eliminates the need to measure the body potential or bring out a body electrode, making it compatible with traditional CMOS processes. It avoids modifying standard processes to implement additional body contacts, thus not increasing manufacturing complexity. Furthermore, it avoids introducing additional body contacts and other parasitic effects. In large-scale integrated circuit design, it eliminates the need for additional electrodes to connect the body, saving wiring space and reducing integration density.

[0047] This application's embodiments achieve nonlinear activation of neurons using a single device, reaching the nonlinear activation characteristics of neurons that can only be achieved with complex CMOS circuits. This makes it possible to construct fully functional, programmable artificial neurons using a single or minimal number of transistors, providing a unique device foundation for building high-efficiency, highly integrated neuromorphic computing chips. These neuronal transistor devices have a simple structure, their manufacturing process is compatible with CMOS fabrication processes, and their measurement methods are simple, requiring no additional electrodes. Therefore, no additional device design is needed to simulate neuronal characteristics, which is beneficial for increasing the transistor integration density in the chip. This makes them suitable for large-scale circuit integration, can meet various application scenarios, has high market demand, and offers significant economic benefits.

[0048] In this embodiment, the substrate can also be used to apply a back gate voltage. The back-gate voltage serves as a control signal for neuronal excitability. It regulates neuronal excitability; a higher back-gate voltage indicates higher neuronal excitability and a larger maximum output signal. Conversely, a lower back-gate voltage indicates lower neuronal excitability and a smaller maximum output signal. The back-gate voltage can range from -20V to 0V.

[0049] Specifically, if the substrate includes multiple gates, each corresponding to a neuron, the substrate can be connected to a back-gate voltage through a common contact. In other words, a unified back-gate voltage can be applied to the substrate, allowing control of the excitability of neurons in various devices on the substrate, without needing to set up separate back-gate voltage input contacts for each neuron.

[0050] In other words, Figure 4 The transition point of the output signal, used as the neuron threshold, can be determined by the back gate voltage. Continuous adjustment means that different output signal peaks can be achieved by adjusting different back gate voltages, which are reflected as different jump points. This corresponds to different types of neurons, such as easily excited or relatively calm neurons.

[0051] In this embodiment, the total duration of the front gate voltage application can be determined according to actual conditions. The drain voltage exhibits different characteristics with different sweep times, corresponding to the "integration-leakage-firing" characteristics of the neuron. (Reference) Figure 6 The diagram shown illustrates the output characteristics at different scan speeds according to an embodiment of this application, where the horizontal axis represents the front gate voltage. The vertical axis represents the drain voltage. When the scan time is long and the scan speed is very slow, The slow increase in potential gives the body region ample time to accumulate holes, causing its potential to rise slowly. Therefore, only a relatively low potential is needed. This can trigger conduction, simulating the time integration and leakage of the neuron's membrane potential. A slow scan corresponds to a series of dense, continuous low-frequency input pulses, which accumulate on the cell membrane until a threshold is reached. A fast scan, on the other hand, corresponds to a momentary, isolated stimulus; the charge disappears before it can accumulate, thus failing to trigger conduction. However, regardless of whether it's a fast or slow scan, there is a recovery time after conduction is triggered, so the region corresponding to the peak value followed by a drop reflects the neuron's refractory period / reset behavior (neuronal fatigue).

[0052] This application provides a neuron-like transistor device, including a substrate, a buried oxide layer and a channel layer stacked sequentially on the substrate, a gate oxide layer and a gate on the channel layer, and a source and a drain located on opposite sides of the channel layer. The gate is used to apply a front gate voltage as an input signal, the drain is used to apply a constant input current, and the drain voltage serves as the output signal. The input signal varies stepwise from small to large. This device enables nonlinear activation of neurons in a single device, making it possible to construct fully functional, programmable artificial neurons with a single or minimal number of transistors. This provides a unique device foundation for building high-efficiency, highly integrated neuromorphic computing chips. This neuron-like transistor device has a simple structure, its manufacturing process is compatible with CMOS fabrication processes, and its measurement method is simple, requiring no additional electrodes. Therefore, it eliminates the need for additional device design to simulate neuron characteristics, facilitating increased transistor integration density in chips and making it suitable for large-scale circuit integration.

[0053] Based on the neuron-like transistor device provided in the above embodiments, this application also provides a control method for the neuron-like transistor device. In this method, for the neuron-like transistor device, a front gate voltage is applied to the gate as an input signal, a constant input current is applied to the drain, and the voltage of the drain is detected as an output signal. The input signal changes stepwise from small to large.

[0054] As one possible implementation, a back-gate voltage can also be applied to the substrate, which serves as a neuronal excitability control signal.

[0055] In one possible implementation, when the substrate includes multiple gates, the substrate is connected to the back gate voltage via a common contact.

[0056] Furthermore, the back gate voltage ranges from -20V to 0V. The input current ranges from 0 to 1pA. The front gate voltage ranges from -0.2V to 1.2V. The total application duration of the front gate voltage ranges from 1ms to 100s. The thickness of the buried oxide layer ranges from 20 to 25nm, and / or the thickness of the channel layer is less than or equal to 12nm, and / or the doping concentration of the channel layer ranges from 1×10⁻⁶. 5 ~1×10 6 cm - ³.

[0057] This technology enables nonlinear activation of neurons using a single device, making it possible to construct fully functional, programmable artificial neurons with a single or minimal number of transistors. This provides a unique device foundation for building high-efficiency, highly integrated neuromorphic computing chips. These neuronal transistor devices have a simple structure, are compatible with CMOS fabrication processes, and are easy to measure without requiring additional electrodes. Therefore, they do not require additional device design to simulate neuronal characteristics, facilitating increased transistor density within the chip and making them suitable for large-scale circuit integration.

[0058] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, the control method embodiments are basically similar to the device embodiments, so the description is relatively simple; relevant parts can be referred to the description of the device embodiments. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0059] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. An FDSOI-type neuron transistor device, characterized in that, include: A substrate, a buried oxide layer and a channel layer sequentially stacked on the substrate, and a gate oxide layer and a gate on the channel layer; And the source and drain electrodes located on both sides of the channel layer, respectively; The gate is used to apply a front gate voltage as an input signal, the drain is used to apply a constant input current, and the voltage of the drain is used as an output signal; the input signal changes in a stepwise manner from small to large.

2. The device according to claim 1, characterized in that, The substrate is used to apply a back-gate voltage, which serves as a neuronal excitability control signal.

3. The device according to claim 2, characterized in that, When the substrate includes multiple gates, the substrate is connected to the back gate voltage through a common contact.

4. The device according to claim 2, characterized in that, The range of the back gate voltage is -20V to 0V.

5. The device according to claim 1, characterized in that, The range of the input current is 0~1pA.

6. The device according to claim 1, characterized in that, The front gate voltage ranges from -0.2V to 1.2V.

7. The device according to claim 6, characterized in that, The total duration of the applied front gate voltage ranges from 1ms to 100s.

8. The device according to claim 1, characterized in that, The thickness of the buried oxide layer ranges from 20 to 25 nm, and / or the thickness of the channel layer is less than or equal to 12 nm, and / or the doping concentration of the channel layer ranges from 1 × 10⁻⁶. 5 ~1×10 6 cm⁻³.

9. A control method for an FDSOI-type neuron transistor device, characterized in that, The method includes: For the FDSOI type neuron transistor device according to any one of claims 1-8, a front gate voltage is applied to the gate as an input signal, a constant input current is applied to the drain, and the voltage of the drain is detected as an output signal, wherein the input signal changes in a stepwise manner from small to large.

10. The method according to claim 9, characterized in that, The method further includes: A back-gate voltage is applied to the substrate, which serves as a neuronal excitability control signal.

Images