Semiconductor module and semiconductor module system
By designing a parallel framework and buffer capacitor layout in the semiconductor module, the problem of surge voltage in high-frequency driven semiconductor devices is solved, achieving voltage reduction when switching elements are turned off and improved system safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2025-11-17
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies have failed to effectively reduce surge voltage when switching elements are turned off in high-frequency drive semiconductor devices.
By designing multiple semiconductor chipsets within a semiconductor module, and utilizing the parallel configuration of the framework and the layout of buffer capacitors, parasitic inductance is reduced, thereby reducing surge voltage.
It effectively reduces the surge voltage when the switching element is turned off, and improves the voltage withstand capability of the semiconductor module and the system safety.
Smart Images
Figure CN122121669A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to semiconductor modules, and more particularly to semiconductor modules with reduced surge voltage. Background Technology
[0002] In the case of high-frequency driven semiconductor devices, it is essential to reduce switching losses. To reduce switching losses, the switching speed needs to be increased.
[0003] For example, in patent document 1 Figure 1 In C, a structure is disclosed in which, in order to reduce the switching loss when the switching element is turned on, the path components through which the reverse recovery current and the gate current flow are configured in such a way as to generate mutually induced current, and the switching speed when turned on is increased.
[0004] Existing technical documents
[0005] Patent documents
[0006] Patent Document 1: International Publication No. 2023 / 037809 Summary of the Invention
[0007] The technical problem that the invention aims to solve
[0008] In Patent Document 1, although the switching losses when the switching element is turned on can be reduced, the reduction of the surge voltage when the switching element is turned off is not considered.
[0009] The present invention is proposed to solve the above-mentioned problems, and its purpose is to provide a semiconductor module that reduces the surge voltage when the switching element is turned off.
[0010] Technical means for solving technical problems
[0011] This disclosure relates to a semiconductor module comprising multiple semiconductor chip groups, each semiconductor chip group having a first semiconductor chip and a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are connected in series between a first power line providing a first voltage and a second power line providing a second voltage lower than the first voltage, and perform complementary switching operations. Each of the semiconductor chip groups has: a first frame connected to a lower surface electrode of the first semiconductor chip, having a first terminal as a portion protruding outward from the semiconductor module; a second frame connected to an upper surface electrode of the second semiconductor chip, having a second terminal as a portion protruding outward from the semiconductor module; and a third frame connected to an upper surface electrode of the first semiconductor chip. The surface electrode is connected to the lower surface electrode of the second semiconductor chip and has a third terminal as a portion protruding from the semiconductor module to the outside; a fourth terminal, which is connected to the gate electrode of the first semiconductor chip and protrudes from the semiconductor module to the outside; and a fifth terminal, which is connected to the gate electrode of the second semiconductor chip and protrudes from the semiconductor module to the outside. The semiconductor module has a first relative portion of the second frame and the third frame configured to be parallel with respect to the direction of current flow, and in the plurality of adjacent semiconductor chip groups, at least one of the first frame of one semiconductor chip group and the second frame of the other semiconductor chip group configured to be parallel with respect to the direction of current flow.
[0012] Invention Effects
[0013] According to the semiconductor module disclosed herein, since it has at least one of the first relative portion and the second relative portion, it is possible to reduce the surge voltage when the first semiconductor chip and the second semiconductor chip, which are switching elements, are turned off. Attached Figure Description
[0014] Figure 1 This is a top view showing the structure of the semiconductor module in Embodiment 1.
[0015] Figure 2 This is a top view that visually represents the first relative portion of the semiconductor module in Embodiment 1.
[0016] Figure 3 This is a top view that visually represents the extension of the frame in the semiconductor module of Embodiment 1.
[0017] Figure 4 This is a top view that visually represents the second relative portion of the semiconductor module in Embodiment 1.
[0018] Figure 5 This is a top view showing an example of the configuration of the buffer capacitors in the semiconductor module of Embodiment 1.
[0019] Figure 6 This is a top view showing an example of the configuration of the buffer capacitors in the semiconductor module of Embodiment 1.
[0020] Figure 7 This is a diagram illustrating an example of an external circuit with buffer capacitors mounted on each phase.
[0021] Figure 8 This is a diagram illustrating an example of an external circuit when using a buffer capacitor in a 3-phase configuration.
[0022] Figure 9 This is a diagram illustrating an example of an external circuit when a semiconductor module is used as the semiconductor module corresponding to 1.
[0023] Figure 10 This is a schematic diagram illustrating an example of connecting two semiconductor modules in parallel.
[0024] Figure 11 This is a top view showing the structure of the semiconductor module in a variation of Embodiment 1.
[0025] Figure 12 This is a block diagram illustrating the structure of the semiconductor module system according to Embodiment 2 of this disclosure. Detailed Implementation
[0026] <Implementation Method 1>
[0027] Figure 1 This is a top view showing the structure of the semiconductor module 100 according to Embodiment 1 of this disclosure. For convenience, a portion of the resin encapsulation PG is omitted, and the internal structure is shown.
[0028] like Figure 1 As shown, the semiconductor module 100 has multiple semiconductor chips SC1 and multiple semiconductor chips SC2 mounted on multiple frames disposed on insulating material BS.
[0029] exist Figure 1 The example illustrates a circuit that can be used as a three-phase full-bridge inverter, with the U-phase, V-phase, and W-phase inverters all having the same structure.
[0030] For example, a U-phase inverter consists of semiconductor chips SC1 (first semiconductor chip) and SC2 (second semiconductor chip) connected in series between a power line (first power line) connected to the positive terminal of a DC power source (not shown) and providing a positive voltage (first voltage) and a power line (second power line) connected to the negative terminal and providing a negative and positive voltage (second voltage).
[0031] Semiconductor chip SC1 is mounted on frame 2 (first frame) which forms the circuit pattern, and semiconductor chip SC2 is mounted on frame 9 (third frame). The upper surface electrodes of semiconductor chips SC1 and SC2 are emitter electrode 6 and emitter electrode 3, respectively, and the lower surface electrode is collector electrode.
[0032] One end of frame 2 protrudes outward from the resin-encapsulated PG as the upper arm collector terminal 1 (terminal 1), and one end of frame 9 protrudes outward from the resin-encapsulated PG as the upper arm emitter terminal / lower arm collector terminal 8 (terminal 3), thus becoming the output terminal of the U-phase inverter. The upper arm collector terminal 1 and the upper arm emitter terminal / lower arm collector terminal 8 protrude from opposite sides of the resin-encapsulated PG.
[0033] The emitter electrode 6 of semiconductor chip SC1 is electrically connected to frame 9 (the third frame) via wire WR, and the emitter electrode 3 of semiconductor chip SC2 is electrically connected to frame 5 (the second frame) via wire WR.
[0034] Frame 5 has a portion parallel to frame 2, and one end of frame 5 protrudes outward from the resin-encapsulated PG as the lower arm emitter terminal 4 (second terminal). The lower arm emitter terminal 4 protrudes from the same side of the resin-encapsulated PG as the upper arm collector terminal 1.
[0035] Frame 5 has a portion parallel to frame 2 and a portion parallel to frame 9. In the portion parallel to frame 9, it is electrically connected to the emitter electrode 3 of semiconductor chip SC2 via wire WR.
[0036] The semiconductor chip SC1 has a gate electrode GT on its upper surface, and the gate electrode GT is electrically connected to the control terminal 10 (terminal 4) via a wire WR.
[0037] The semiconductor chip SC2 has a gate electrode GT on its upper surface, and the gate electrode GT is electrically connected to the control terminal 11 (terminal 5) via the wire WR.
[0038] One end of control terminals 10 and 11 protrudes from the side of the resin-encapsulated PG, which is the same as the upper arm emitter terminal / lower arm collector terminal 8. Furthermore, in the above description, it is assumed that semiconductor chips SC1 and SC2 are disposed on a reverse-conducting IGBT (RC-IGBT) on a semiconductor substrate common to both the insulated-gate bipolar transistor (IGBT) and the freewheeling diode (FWD). However, semiconductor chips SC1 and SC2 are not limited to RC-IGBTs; they can also be IGBTs and MOSFETs (MOS field-effect transistors). Additionally, the semiconductor substrate is not limited to a silicon substrate; a carbon silicide (SiC) substrate can also be used.
[0039] The structure of the U-phase inverter described above is the same in the V-phase and W-phase inverters. The same symbols are used for the same structures, and repeated descriptions are omitted. The following section... Figure 1 The characteristic features of the semiconductor module 100 shown will be described.
[0040] <Feature Part 1>
[0041] The upper arm collector terminal 1 (terminal 1) and the lower arm emitter terminal 4 (terminal 2) of the multiple semiconductor chip groups constituting each phase of the inverter are alternately arranged and protrude from one side of the semiconductor module 100, and the upper arm emitter terminal / lower arm collector terminal 8 (terminal 3), control terminal 10 (terminal 4) and control terminal 11 (terminal 5) are alternately arranged and protrude from the opposite side of the semiconductor module 100.
[0042] like Figure 1 As shown, in each semiconductor chip group of semiconductor module 100, frame 5 (second frame) and frame 9 (third frame) have opposite portions arranged in a parallel manner relative to the direction of current flow.
[0043] exist Figure 2 This part is shown visually. Figure 2 Is with Figure 1 The same semiconductor module 100 is shown, but only reference symbols for relevant parts are shown, and a simplified representation is adopted. Figure 2 In the diagram, frames 5 and 9, as indicated by the frame line FL, are arranged in parallel with respect to the direction of current flow (the first relative portion). Here, the currents indicated by the arrows, i.e., the current flowing from the upper arm collector terminal 1 to the lower arm emitter terminal 4, flow in opposite directions, canceling out the magnetic flux generated by the current flow and thus reducing parasitic inductance. Consequently, surge voltage generated by parasitic inductance can be reduced.
[0044] <Feature Part 2>
[0045] exist Figure 2 In the area indicated by frame line FL, the relative portions of frames 5 and 9 are intentionally extended on frame 9 in a manner that maximizes their length. Figure 3 This part is shown visually.
[0046] exist Figure 3 In the diagram, frame 9, indicated by the border FL, is the extension EX, which extends parallel to frame 5 from the mounting portion of semiconductor chip SC2 within frame 9. Compared to the case without the extension EX, the effect of canceling out magnetic flux is improved, and the effect of reducing parasitic inductance is also improved.
[0047] <Feature Part 3>
[0048] like Figure 1 As shown, in adjacent semiconductor chip sets, the frame 2 (first frame) of one semiconductor chip set and the frame 5 (second frame) of the adjacent semiconductor chip set have opposite portions arranged in a parallel manner relative to each other's current flow direction.
[0049] exist Figure 4 This part is shown visually. Figure 4 Is with Figure 1 The same semiconductor module 100 is used, but only reference symbols for relevant parts are shown, and a simplification is applied. Figure 4 In the diagram, frames 2 and 5, located in the region indicated by frame line FL, are opposite portions (the second opposite portion) arranged in parallel with respect to the direction of current flow. Here, the currents indicated by arrows, i.e., the currents flowing in opposite directions, cancel each other out the magnetic flux generated by the current flow, thus reducing parasitic inductance. Therefore, surge voltage generated by parasitic inductance can be reduced.
[0050] <Feature Section 4>
[0051] If used Figure 2 and Figure 4 As explained, in the relative portions where the frames are arranged in parallel with respect to the direction of current flow, the spacing between the opposing frames is set to be as narrow as possible.
[0052] exist Figure 2 In the diagram, the spacing between the opposing frames is schematically shown by arrow AR. That is, the portions indicated by arrow AR between frames 5 and 9 of a semiconductor chipset, between frame 9 and frame 2, and between frame 2 of one semiconductor chipset and frame 5 of the adjacent semiconductor chipset are set to the shortest distance, so as to make them an insulation distance that can ensure the degree of withstand voltage required by the voltage rating of the semiconductor module 100.
[0053] For example, if the withstand voltage of the semiconductor module 100 is 600–1200V, the minimum distance is set to approximately 1–5 mm. By narrowing the gap between the opposing frames as much as possible, the effect of mutually canceling the magnetic flux generated by the flow of current can be further improved.
[0054] <Feature Section 5>
[0055] like Figure 1 As shown, no other terminals are disposed between the upper arm collector terminal 1 (first terminal) and the lower arm emitter terminal 4 (second terminal) of the semiconductor chipset; instead, they are arranged adjacent to each other. By adopting this structure, a buffer capacitor can be disposed between frame 2 (first frame) and frame 5 (second frame), or between the upper arm collector terminal 1 and the lower arm emitter terminal 4. By disposing of the buffer capacitor, parasitic inductance can be further reduced, and surge voltage can be further reduced.
[0056] Figure 5 This illustrates an example of a buffer capacitor SC disposed between frames 2 and 5 within a resin-encapsulated PG. The spacing between frames 2 and 5 is set to be as narrow as possible, but is set to be an insulating distance sufficient to ensure the withstand voltage required by the rated voltage of the semiconductor module 100.
[0057] Figure 6 This illustrates an example of a buffer capacitor SC disposed between the upper arm collector terminal 1 and the lower arm emitter terminal 4. The spacing between the upper arm collector terminal 1 and the lower arm emitter terminal 4 is set to be as narrow as possible, but is set to be an insulation distance that can ensure the degree of withstand voltage required by the rated voltage of the semiconductor module 100.
[0058] In either example, the surge buffer capacitor SC can be positioned as close as possible to the semiconductor chip.
[0059] <Feature Section 6>
[0060] like Figure 1 As shown, the upper arm collector terminal 1 and the lower arm emitter terminal 4 protrude outward from one side of the resin package PG for each phase, thus ensuring the terminal width and internal wiring width, and reducing the wiring inductance inside the semiconductor module 100.
[0061] Additionally, if using Figure 5 and Figure 6 As explained, a buffer capacitor can be installed on each phase, and the capacitance of each buffer capacitor can be reduced. If the capacitance of the buffer capacitor can be reduced, the size of the buffer capacitor can be reduced.
[0062] Figure 7This is a diagram illustrating an example of the external circuitry when buffer capacitors are mounted on each phase. (See diagram for example.) Figure 7 As shown, a buffer capacitor SC is connected between the upper arm collector terminal 1 and the lower arm emitter terminal 4 of each phase. The upper arm collector terminal 1 of each phase is connected to the positive terminal of the DC power supply PW, and the lower arm emitter terminal 4 of each phase is connected to the negative terminal of the DC power supply PW. The upper arm emitter terminal / lower arm collector terminal 8, which serves as the output terminal of each phase, is connected to the wiring of each phase of the motor MT, which serves as the load. The control terminals 10 and 11 of each phase are connected to the DC drive circuit of the semiconductor chip.
[0063] Alternatively, a single buffer capacitor can be used in all three phases, instead of providing a buffer capacitor for each phase. Figure 8 This is a diagram illustrating an example of the external circuitry used when a buffer capacitor is employed in a three-phase system. (Example:) Figure 8 As shown, a buffer capacitor SC is connected in parallel with the DC power supply PW. Other structures are similar. Figure 7 The same applies. Therefore, the number of buffer capacitors can be reduced, simplifying the external circuitry.
[0064] Alternatively, a semiconductor module 100 can be used as the semiconductor module corresponding to 1. Figure 9 This is a diagram illustrating an example of an external circuit when a semiconductor module 100 is used as the semiconductor module corresponding to 1. For example... Figure 9 As shown, the three upper arm emitter terminals / lower arm collector terminals 8 are commonly connected to the wiring of any phase of the motor MT, which serves as the load. All control terminals 10 and 11 are commonly connected to the DC drive circuit of the semiconductor chip. Other structures are similar. Figure 8 The same. By using multiple semiconductor chipsets within semiconductor module 100 as semiconductor chips corresponding to 1, the amount of power that can be used can be increased.
[0065] In addition, by making the upper arm collector terminal 1 and the lower arm emitter terminal 4 protrude outward in each phase, the parallel connection of multiple semiconductor modules 100 becomes easy.
[0066] Figure 10 This is a schematic diagram illustrating an example of connecting two semiconductor modules 100 in parallel. For example... Figure 10 As shown, external wiring OW is used to electrically connect the upper arm collector terminals 1 of each phase of the two semiconductor modules 100 to each other, the lower arm emitter terminals 4 to each other, and the upper arm emitter terminals / lower arm collector terminals 8 to each other, thereby enabling the two semiconductor modules 100 to be connected in parallel and reducing wiring inductance.
[0067] <Variation Example 1>
[0068] exist Figure 1 In the semiconductor module 100 shown, if using Figure 2 As explained, in the relative portions where frames 5 and 9 are arranged parallel to each other with respect to the direction of current flow, the directions of current flow are opposite to each other. The emitter electrode 6 of semiconductor chip SC1 is electrically connected to frame 9 (the third frame) via wire WR, but by changing the position of wire WR connected to frame 9, the current path of frame 9 can be extended. Similarly, by changing the position of wire WR that electrically connects the emitter electrode 3 of semiconductor chip SC2 to frame 5, the current path of frame 5 can be extended.
[0069] Figure 11 This is a top view showing the structure of the semiconductor device 100A according to a variation of Embodiment 1. Furthermore, in Figure 11 In China, regarding the use Figure 1 The semiconductor device 100 described herein is labeled with the same reference numerals, and repeated descriptions are omitted.
[0070] like Figure 11 As shown, the wire WR that electrically connects the emitter electrode 6 of semiconductor chip SC1 to frame 9 is connected to the end of the extension portion disposed on frame 9 that is furthest from the upper arm emitter terminal / lower arm collector terminal 8 (third terminal). Similarly, the wire WR that electrically connects the emitter electrode 3 of semiconductor chip SC2 to frame 5 is connected to the end of the lower arm emitter terminal 4 (second terminal) of frame 5. Thus, as Figure 11 As indicated by the arrows, the current path at the opposite portions of frames 5 and 9 can be extended, further reducing parasitic inductance. Therefore, the surge voltage generated by parasitic inductance can be reduced.
[0071] <Variation Example 2>
[0072] exist Figure 1 In the semiconductor module 100 shown, the upper arm collector terminal 1 (first terminal), the lower arm emitter terminal 4 (second terminal), and the upper arm emitter terminal / lower arm collector terminal 8 (third terminal) represent a structure that protrudes horizontally from the side of the resin package PG. However, it is also possible to protrude in a direction other than the horizontal direction from the interior of the resin package PG by bending the frame shape to a right angle. For example, it can also protrude from one side of the upper or lower surface of the resin package PG. This is also the case with control terminal 10 (fourth terminal) and control terminal 11 (fifth terminal). By changing the protrusion direction of the terminals, the versatility of the use of the semiconductor module 100 can be increased.
[0073] <Implementation Method 2>
[0074] This embodiment relates to a semiconductor module system obtained by applying the semiconductor module described in Embodiment 1 to a power factor improvement circuit. Figure 12 This is a block diagram showing the structure of the semiconductor module system in Embodiment 2.
[0075] Figure 12 The semiconductor module system shown consists of a three-phase AC power supply 1000, a power factor improvement circuit 2000, and a DC / DC converter 3000. The power factor improvement circuit 2000 is a circuit that makes the power factor of the AC power supply 1000 close to 1, and is called a PFC (power factor correction) circuit.
[0076] By using the semiconductor module 100 described in Embodiment 1 as the three-phase full-bridge converter of the power factor improvement circuit 2000, the internal inductance can be reduced. Furthermore, by using a separate semiconductor module 100 as the three-phase full-bridge converter, the routing around the power factor improvement circuit 2000 can be optimized, further reducing the overall system inductance. This reduces surge voltage and improves overall system safety.
[0077] Furthermore, within the scope of this disclosure, the various embodiments can be freely combined, or the various embodiments can be appropriately modified or omitted.
[0078] The above description of this disclosure is summarized as an appendix.
[0079] (Note 1) A semiconductor module,
[0080] The semiconductor module includes multiple semiconductor chip sets, each having a first semiconductor chip and a second semiconductor chip. The first and second semiconductor chips are connected in series between a first power line providing a first voltage and a second power line providing a second voltage lower than the first voltage, and perform complementary switching operations.
[0081] Each of the semiconductor chipsets has:
[0082] A first frame, which is connected to the lower surface electrode of the first semiconductor chip, has a first terminal as a portion protruding outward from the semiconductor module;
[0083] The second frame is connected to the upper surface electrode of the second semiconductor chip and has a second terminal as a portion protruding from the semiconductor module to the outside.
[0084] The third frame is connected to the upper surface electrode of the first semiconductor chip and the lower surface electrode of the second semiconductor chip, and has a third terminal as a portion protruding from the semiconductor module to the outside.
[0085] A fourth terminal, which is connected to the gate electrode of the first semiconductor chip, protrudes from the semiconductor module to the outside; and
[0086] The fifth terminal, which is connected to the gate electrode of the second semiconductor chip, protrudes from the semiconductor module to the outside.
[0087] The semiconductor module has first opposing portions of the second frame and the third frame configured parallel to the direction of current flow, and
[0088] In the plurality of adjacent semiconductor chip sets, at least one of the first frame of one semiconductor chip set and the second frame of the other semiconductor chip set is configured to be parallel to the direction of current flow in a second relative portion.
[0089] (Note 2) The semiconductor module as described in Note 1,
[0090] The third frame has an extension portion.
[0091] In the first opposing portion, the extension extends from the portion carrying the second semiconductor chip in a manner parallel to the second frame.
[0092] (Note 3) The semiconductor module as described in Note 2,
[0093] Regarding the spacing between the second frame and the third frame in the first relative portion,
[0094] It is set to be the shortest distance that can ensure the withstand voltage required for the rated voltage of the semiconductor module.
[0095] (Note 4) The semiconductor module as described in Note 1,
[0096] Among the multiple groups,
[0097] The first terminal and the second terminal are alternately arranged on the first side of the semiconductor module.
[0098] The third terminal, the fourth terminal, and the fifth terminal are alternately arranged on the second side of the semiconductor module opposite to the first side to form the semiconductor module.
[0099] (Note 5) The semiconductor module as described in Note 1,
[0100] The first terminal and the second terminal within the semiconductor chipset are arranged adjacent to each other.
[0101] (Note 6) The semiconductor module as described in any of Notes 1 to 5,
[0102] In each of the semiconductor chipsets
[0103] The first terminal and the second terminal protrude from the semiconductor module toward the outside, respectively.
[0104] (Note 7) The semiconductor module as described in any of Notes 1 to 5,
[0105] The upper surface electrode of the first semiconductor chip is electrically connected in the third frame to the end furthest from the third terminal.
[0106] The upper surface electrode of the second semiconductor chip is electrically connected in the second frame to the end furthest from the second terminal.
[0107] (Appendix 8) A semiconductor module system, comprising:
[0108] AC power supply;
[0109] A power factor correction circuit, connected to the AC power supply, and equipped with a semiconductor module as described in any one of Appendices 1 to 5; and
[0110] A DC / DC converter is connected to the power factor improvement circuit.
Claims
1. A semiconductor module, The semiconductor module includes multiple semiconductor chip sets, each having a first semiconductor chip and a second semiconductor chip. The first and second semiconductor chips are connected in series between a first power line providing a first voltage and a second power line providing a second voltage lower than the first voltage, and perform complementary switching operations. The semiconductor module is characterized in that… Each of the semiconductor chipsets has: A first frame, which is connected to the lower surface electrode of the first semiconductor chip, has a first terminal as a portion protruding outward from the semiconductor module; The second frame is connected to the upper surface electrode of the second semiconductor chip and has a second terminal as a portion protruding from the semiconductor module to the outside. The third frame is connected to the upper surface electrode of the first semiconductor chip and the lower surface electrode of the second semiconductor chip, and has a third terminal as a portion protruding from the semiconductor module to the outside. The fourth terminal is connected to the gate electrode of the first semiconductor chip and protrudes from the semiconductor module to the outside. as well as The fifth terminal, which is connected to the gate electrode of the second semiconductor chip, protrudes from the semiconductor module to the outside. The semiconductor module has a first opposing portion of the second frame and the third frame configured parallel to the direction of current flow, and In the plurality of adjacent semiconductor chip sets, at least one of the first frame of one semiconductor chip set and the second frame of the other semiconductor chip set is configured to be parallel to the direction of current flow in a second relative portion.
2. The semiconductor module as described in claim 1, characterized in that, The third frame has an extension portion. In the first opposing portion, the extension extends from the portion carrying the second semiconductor chip in a manner parallel to the second frame.
3. The semiconductor module as described in claim 2, characterized in that, Regarding the spacing between the second frame and the third frame in the first relative portion, It is set to be the shortest distance that can ensure the withstand voltage required for the rated voltage of the semiconductor module.
4. The semiconductor module as described in claim 1, characterized in that, Among the multiple groups, The first terminal and the second terminal are alternately arranged on the first side of the semiconductor module. The third terminal, the fourth terminal, and the fifth terminal are alternately arranged on the second side of the semiconductor module opposite to the first side to form the semiconductor module.
5. The semiconductor module as described in claim 1, characterized in that, The first terminal and the second terminal within the semiconductor chipset are arranged adjacent to each other.
6. The semiconductor module according to any one of claims 1 to 5, characterized in that, In each of the semiconductor chipsets The first terminal and the second terminal protrude from the semiconductor module toward the outside, respectively.
7. The semiconductor module according to any one of claims 1 to 5, characterized in that, The upper surface electrode of the first semiconductor chip is electrically connected in the third frame to the end furthest from the third terminal. The upper surface electrode of the second semiconductor chip is electrically connected in the second frame to the end furthest from the second terminal.
8. A semiconductor module system, characterized in that, include: AC power supply; A power factor correction circuit, connected to the AC power supply, and equipped with a semiconductor module as described in any one of claims 1 to 5; and A DC / DC converter is connected to the power factor improvement circuit.