A dual BFS hardware accelerator for sparse matrix RCM reordering

Abstract

This invention discloses a dual BFS hardware accelerator for sparse matrix RCM reordering, belonging to the field of sparse matrix computation and hardware acceleration technology. The accelerator includes: a top-level control module, a BFS engine module employing a dual BFS positioning architecture, a degree table module, a neighbor sorter module with a degree-first comparison network, a single-cycle access marker bit vector, and a hardware stack manager module. The BFS engine module achieves automatic pseudo-peripheral node positioning through a three-stage pipeline: the first stage starts BFS from the node with the lowest degree and finds the first farthest node through a hierarchy tracing circuit; the second stage starts BFS again from that node to determine the globally optimal starting point; and the third stage executes degree-first RCM traversal. An extended FIFO queue is used to transmit hierarchy information, and an external memory is interacted with through a decoupled interface. The hardware stack manager achieves single-cycle reverse output. This invention achieves a processing latency of less than 1.2ms on a 1000-node graph, reducing the average matrix bandwidth by 73.85%, and improving upon existing software by 31.85%.

Description

Technical Field

[0001] This invention relates to the field of sparse matrix computation and hardware acceleration technology, specifically to a reverse Cuthill-McKee (RCM) sparse matrix reordering hardware accelerator based on a dual breadth-first search (BFS) architecture and its circuit implementation method. Background Technology

[0002] A sparse matrix is ​​a matrix in which the vast majority of its elements are zero. It is widely used in scientific computing, engineering simulation, and graph computation. In applications such as finite element analysis, solving linear equations, and network analysis, the bandwidth and profile of a sparse matrix directly affect the storage requirements and computational efficiency of algorithms. The Cuthill-McKee algorithm (CM) and the reverse Cuthill-McKee algorithm (RCM) are classic matrix reordering methods. By rearranging the row and column order of the matrix, non-zero elements are concentrated as close to the main diagonal as possible, thereby reducing bandwidth and profile.

[0003] In existing technologies, the most common software implementation directly selects the node with the smallest degree as the starting point and processes neighbors in degree or node number order during BFS. This method is simple to implement but the reordering quality is unstable and lacks a systematic consideration of the global topology of the graph.

[0004] George and Liu proposed locating the endpoints of the graph diameter using iterative BFS: BFS is performed from any node to calculate the tree depth; the node with the minimum degree at the farthest level is selected, and BFS is performed again from that node to obtain the new depth. If the depth increases, the iteration continues until convergence. This method improves the quality of the starting point, but suffers from unpredictable iteration counts. In complex graph structures, the number of iterations can reach 10 or more, with the worst-case total complexity degenerating to O(n(n+e)). This uncertainty is unacceptable in hardware systems requiring fixed latency guarantees: the pipeline depth, buffer size, and timing constraints of the hardware circuit all require a fixed number of processing cycles, creating a fundamental contradiction between dynamic iteration logic and static hardware resource configuration. Furthermore, repeated BFS iterations significantly increase memory accesses, leading to substantial waste of power consumption and memory bandwidth resources in hardware implementation.

[0005] The academic community has also proposed reordering techniques based on graph partitioning (such as multi-level recursive decomposition), spectral analysis (based on Laplacian matrix eigenvectors), or metaheuristic algorithms (genetic algorithms, simulated annealing). These methods can achieve better bandwidth or contours on specific types of matrices, but they generally suffer from high computational complexity (time complexity O(n²) or even O(n³)), difficulty in parameter tuning, and algorithm instability, making them difficult to apply as a general preprocessing step in large-scale real-time computing scenarios.

[0006] Current RCM algorithms are primarily implemented in CPU software, with typical examples including SciPy's `sparse.csgraph.reverse_cuthill_mckee` function and MATLAB's `symrcm` function. These implementations employ serial BFS traversal, which limits performance when processing large-scale matrices with millions of nodes. GPU parallelization attempts to address irregular access patterns in graph traversal are inefficient, resulting in limited speedup. Currently, there is a lack of dedicated hardware acceleration circuits designed specifically for the data flow characteristics and access patterns of the RCM algorithm.

[0007] However, existing technologies still have the following problems:

[0008] Starting node selection strategies struggle to balance quality and hardware implementability. Simple minimum-degree selection strategies can be implemented with fixed circuitry, but their quality is unstable. The George-Liu iterative algorithm offers superior quality, but its uncontrollable iteration count makes it impossible to design deterministic delay hardware pipelines, pre-allocate FIFO depth, fix state machine cycle counts, or perform static timing analysis. This algorithmic uncertainty fundamentally conflicts with the deterministic resource allocation required by hardware circuitry. Current technology lacks a positioning strategy that can obtain high-quality pseudo-peripheral nodes within a fixed number of BFS iterations while remaining suitable for hardware pipeline implementation.

[0009] BFS traversal's neighbor processing lacks hardware-optimized sorting circuits. Existing software implementations employ inconsistent strategies for processing neighbor nodes: some sort by number (no sorting circuit required), while others coarsely sort by degree (using software for fast sorting), failing to systematically utilize the topological characteristic that "low-degree nodes are located on the periphery of the graph." In hardware implementations, there is a lack of feasible circuit architecture solutions for designing efficient degree-first sorting circuits, organizing degree lookup and sorting logic into a low-latency pipeline, and balancing the number of sorting channels with hardware resource overhead. Experiments show that strict degree-first sorting can further reduce bandwidth by 10%-25%, but existing technologies do not provide a suitable sorting module design for hardware-parallel comparison networks.

[0010] The lack of a dedicated hardware acceleration architecture makes it difficult to map operations such as dynamic queue management, hierarchical propagation, and access state tracking of the RCM algorithm to static hardware resources; the adjacency data that frequently accesses external memory lacks efficient request-response interfaces and caching strategies; and there is a lack of feasible solutions for organizing degree lookup, neighbor sorting, and queue management into an efficient pipeline. The general-purpose GPU architecture cannot be deeply optimized for the specific data flow of RCM and has high power consumption.

[0011] The storage format and data structure are not optimized enough. Most software implementations use the CSR format by default, which is inefficient when building adjacency lists. Symmetric matrices need to be manually completed and lack automation. Information such as the level and access flags of BFS are stored in separate arrays, which increases memory overhead. Reverse output requires additional address control logic design in hardware implementation. Summary of the Invention

[0012] The purpose of this invention is to provide a dual BFS hardware accelerator for sparse matrix RCM reordering, which overcomes the problems of uncertainty in the starting node positioning circuit, lack of degree priority sorting hardware unit, and lack of dedicated acceleration circuit in the prior art, and realizes hardware-based matrix reordering processing with deterministic delay.

[0013] This invention discloses a dual BFS hardware accelerator for sparse matrix RCM reordering, the dual BFS hardware accelerator for sparse matrix RCM reordering comprising:

[0014] The top-level control module executes the process through a state machine management algorithm, sequentially completing degree table initialization, three BFS start-up controls, data flow routing, and result output.

[0015] The BFS engine module uses a pipelined state machine with a dual BFS positioning architecture to execute BFS traversal. It achieves hierarchical information transmission by storing a combination of hierarchical and node index data through a FIFO queue with expanded data width, and tracks the maximum level and corresponding node in real time to complete the two-stage positioning from the minimum degree node to the first far-end node and then to the pseudo-peripheral node.

[0016] The degree table module calculates and stores node degrees through memory. During the initialization phase, it calculates the degree based on the difference of column pointers in CSC format. During the query phase, it responds to node index requests and returns the corresponding degree.

[0017] The neighbor sorter module uses a degree-first comparison network to sort neighbor nodes in ascending order of degree. The input data includes a combination of degree and node index, and the output is a sequence of node indices sorted by degree.

[0018] The access marker bit vector uses a bitmap structure to record the node access status, with each node corresponding to one bit, enabling single-cycle status query and update.

[0019] The stack manager module stores the BFS traversal sequence sequentially in memory, and reverses the order of the output by reading the address in reverse order.

[0020] Furthermore, the dual BFS hardware accelerator for sparse matrix RCM reordering includes the following working stages:

[0021] Preprocessing stage: The top-level control module determines whether it is in CSC format through the format detection circuit. If not, it converts the input sparse matrix into compressed sparse column CSC format.

[0022] The symmetry detection circuit detects whether the upper triangular part and the lower triangular part are equal after transposition. If they are not equal, the missing part is filled in by the matrix addition operation unit and the diagonal compensation operation unit.

[0023] The adjacency list construction circuit traverses all non-zero elements of the CSC format matrix and establishes bidirectional adjacency relationships.

[0024] First localization phase: The degree table module calculates the degree of all nodes and selects the node with the smallest degree. The BFS engine module starts from the node with the smallest degree as the first starting node and performs the first breadth-first search. The level tracking register records the level information and determines the first farthest node in the level of the first starting node.

[0025] Second positioning phase: The BFS engine module takes the first remote node as the second starting node, and executes the second BFS from the second starting node. The level tracking register determines the second remote node that is farthest from the second starting node as the pseudo-peripheral node.

[0026] Traversal and sorting phase: The BFS engine module uses the pseudo-outer node as the final starting node to perform the third BFS traversal. During the traversal, the neighbor sorter module sorts all unvisited neighbor nodes of the current node in ascending order according to their degree and adds them to the queue in turn to generate the Cuthill-McKee sort.

[0027] Reverse output stage: The stack manager module reverses the Cuthill-McKee sorting results to obtain the reverse Cuthill-McKee permutation vector;

[0028] Matrix rearrangement stage: The matrix rearrangement circuit synchronously reorders the rows and columns of the original sparse matrix according to the arrangement vector, and outputs a bandwidth-optimized sparse matrix.

[0029] Furthermore, the symmetry detection circuit achieves matrix symmetry detection through a comparator array;

[0030] The matrix addition unit uses a pipelined adder to perform matrix addition operations, while the diagonal compensation unit locates diagonal elements and performs compensation through address mapping logic.

[0031] The adjacency list construction circuit includes a CSC format parser and a bidirectional link controller. The parser traverses all non-zero elements to extract row and column indices, and the link controller establishes bidirectional adjacency relationships in the adjacency list memory based on the index pairs.

[0032] Furthermore, the BFS traversal of the BFS engine module is implemented by the BFS engine module using a hierarchical search circuit:

[0033] The FIFO queue controller stores a combination of node index and hierarchy number;

[0034] The initialization circuit starts from the starting node, marks it as visited in the access flag bit vector, sets the hierarchy register to 0, and adds the data to the queue.

[0035] Traverse the control state machine. When the queue is not empty, take out the first element of the queue. Get all the neighbors of the node through the external memory interface. For unvisited neighbors, mark them as visited by the access flag bit vector. The hierarchical adder sets its level to the current node's level plus 1 and adds it to the queue.

[0036] The level tracing circuit maintains the maximum level value and its corresponding node index during the traversal. The comparator detects when the level of the retrieved node is greater than the current maximum level and updates the maximum level register and the corresponding node register. After the traversal is completed, the node in the register is the farthest node.

[0037] Furthermore, the neighbor sorter module retrieves the current node from the queue, obtains all neighbor nodes of that node, and filters out visited nodes based on the access flag bit vector to form a candidate set;

[0038] For each node in the candidate set, a query request is sent to the degree table module. The degree table module returns the corresponding degree value. The candidate set is then sorted in parallel according to the degree value from smallest to largest.

[0039] In the sorted order, neighboring nodes are marked as visited in the access flag bit vector and added to the queue through the FIFO queue controller to ensure that low-degree nodes are visited first.

[0040] Furthermore, the BFS engine module expands the data width of the FIFO queue to twice the IDX_LEN bit width, and each queue element encapsulates a combination of hierarchical information and node index data; the BFS engine module sets a queue depth counter, and maintains the number of elements in the queue in real time according to enqueue and dequeue operations. The enqueue operation increments the counter, and the dequeue operation decrements the counter. At the same time, the counter remains unchanged during enqueue and dequeue, and the queue is determined to be empty based on the counter value.

[0041] Furthermore, the BFS engine module and the external memory adopt a request-response decoupled interaction mode: the BFS engine sends an adjacency node request and the corresponding column index; the external memory returns all row indices of that column in subsequent consecutive cycles; the BFS engine records the number of adjacency nodes received through a counting mechanism and determines the completion of data transmission based on the state change of the response valid signal.

[0042] Furthermore, the neighbor sorter module employs a comparison network to achieve parallel sorting, and the pipeline depth of the comparison network is calculated and determined based on the number of comparison channels. The input data structure includes a combination of node degree and node index, and unused input channels are filled with extreme values ​​to ensure sorting correctness. During output, node indices are output in degree order and the filled data is filtered, outputting only valid adjacent nodes.

[0043] Furthermore, the degree table module uses random access memory to store node degree information; during the initialization phase, it receives column pointer data of the sparse matrix, calculates the difference between adjacent column pointers to obtain the degree of each node, and stores it in ascending address order; during the query phase, it receives the node index and query request signal, and after a memory read delay, returns the degree value of the corresponding node and outputs a valid signal.

[0044] Furthermore, the stack manager module controls sequential writing and reverse reading through a state machine: during the writing phase, it receives the node index output by the BFS engine and stores it in memory in ascending order of address; the stack manager module selectively processes the traversal results of specific BFS phases according to the control signals of the top-level control module.

[0045] The beneficial effects achieved by this invention are:

[0046] 1. Traditional minimum degree start point selection circuits have a fixed execution cycle but unstable quality; the George-Liu iterative algorithm requires a dynamic number of iterations (more than 10 in the worst case), and its uncertainty makes it impossible to design a fixed pipeline depth, pre-allocate a FIFO buffer, or perform static timing analysis, making it fundamentally unsuitable for hardware circuit implementation.

[0047] This invention employs a dual BFS (Browse-First-Side) localization circuit architecture, solidifying the search for pseudo-peripheral nodes into three BFS circuit operations: the first locates the first farthest node from the minimum degree node, the second locates the pseudo-peripheral node from the first farthest node, and the third performs the final traversal. The hardware pipeline depth is determined, memory resources are fixed, and the number of processing cycles is predictable. Experiments show that the hardware system, at a 100MHz clock frequency, maintains a latency of less than 1.2ms when processing a 1000-node graph, achieving a deterministic latency guarantee.

[0048] In terms of reordering quality, the average bandwidth reduction rate reached 73.85% across 13 test matrices, an improvement of 31.85 percentage points compared to the SciPy standard implementation (50.11%); the average matrix contour reduction rate was 67.89%, an improvement of 38.67 percentage points compared to SciPy (43.52%). The bandwidth reduction rate reached 93.95% on the mesh3em5 matrix (SciPy: 88.26%), and 93.83% on the plat1919 matrix (SciPy: 87.59%).

[0049] 2. Existing software implementations lack consistent neighbor node processing strategies and dedicated hardware sorting circuits. This invention designs a neighbor sorter module based on a comparison network, organizing the degree query circuit and the parallel comparison network into a pipeline, strictly implementing degree-first sorting in each node processing stage of the third BFS.

[0050] The comparison network sorter employs a fixed-depth pipeline design, achieving single-cycle sorting output through multi-channel parallel comparisons. The degree lookup circuit and degree table module interact efficiently via a dedicated interface. The access filter circuit determines the node access status in a single cycle based on a bitmap structure. This hardware sorting circuit ensures that low-degree nodes (located on the periphery of the graph) are accessed first, allowing the traversal path to advance inward along the graph edge, and adjacent nodes are reordered with closer numbers.

[0051] On the bcsstm10 matrix, the bandwidth decreased from 37 to 22 (a reduction of 40.54%, compared to 8.11% in SciPy); the profile decreased from 38129 to 6430 (a reduction of 83.14%, compared to 45.25% in SciPy), demonstrating the effectiveness of the dedicated sorting circuit.

[0052] 3. Existing CPU software implementations are limited in performance on a matrix of millions of nodes, and GPUs offer limited acceleration due to irregular access patterns in graph traversal.

[0053] The hardware accelerator system proposed in this invention adopts a pipelined state machine architecture, efficiently mapping dynamic queue management, hierarchical transfer, and access state tracking to static hardware resources. The extended-width FIFO queue circuit encapsulates both node index and hierarchical information within a single queue element, eliminating the overhead of independent hierarchical storage. A queue depth counter maintains the number of elements in real time, enabling single-cycle queue empty state judgment. The single-cycle access marker bit vector circuit uses a bitmap structure to achieve O(1) complexity node access state query and update. The hardware stack manager circuit automatically completes RCM reverse output through address reverse reading, eliminating the need for additional reversal operations. The request-response decoupled memory interface circuit enables batch transmission of adjacent nodes, reducing handshake overhead and maximizing bandwidth utilization.

[0054] The hardware system delivers predictable deterministic performance with a 1000-node graph processing latency of less than 1.2ms at a 100MHz clock frequency.

[0055] 4. Most RCM implementations use CSR format by default, requiring additional format conversion when constructing the adjacency list; symmetric matrices require manual completion; and reverse output requires additional array copying in software implementation.

[0056] This invention uniformly adopts the CSC format, directly calculating node degree using column pointer differences without traversing non-zero elements; it automatically detects and completes the upper triangular portion of symmetric matrices; in hardware implementation, it automatically completes reverse output using the stack manager's reverse read characteristic, eliminating the need for additional reversal operations. The CSC format is more universal in many numerical computation libraries (such as SuiteSparse), facilitating integration with subsequent solvers.

[0057] 5. The hardware system adopts a modular design, with each functional module (BFS engine, degree table, neighbor sorter, access marker, stack manager) having a clear responsibility and standardized interfaces; it can adapt to matrices of different sizes through parameter configuration (matrix dimension, maximum number of nodes, RAM depth, number of comparator channels); it supports balancing sorting performance and resource consumption by adjusting the number of comparison network channels; modules can be independently simulated and verified, facilitating debugging and optimization; and it is easy to integrate into larger sparse matrix processing systems or scientific computing acceleration platforms.

[0058] In summary, this invention, through the collaborative innovation of dedicated circuit modules such as a fixed triple BFS dual positioning circuit, a degree-first comparison network sorter, an extended-width queue, a single-cycle bitmap access marker, and hardware stack reverse output, achieves significant optimization of sparse matrix bandwidth and profile while ensuring deterministic latency. This provides an efficient hardware-based preprocessing solution for fields such as finite element analysis, linear equation solving, and graph computation. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the hardware accelerator system architecture of the present invention;

[0060] Figure 2 This is the state machine transition diagram of the BFS engine module of this invention;

[0061] Figure 3 This is a timing diagram of the single-node processing hardware of the BFS engine of this invention;

[0062] Figure 4 This is a flowchart of the priority sorting circuit of the present invention;

[0063] Figure 5 This is a schematic diagram comparing the matrix before and after reordering according to the present invention;

[0064] Figure 6 This is a statistical chart showing the overall performance of the present invention across 13 test matrices. Detailed Implementation

[0065] The present invention will be further described below with reference to specific embodiments, and the advantages and features of the present invention will become clearer as a result. However, these embodiments are merely exemplary and do not constitute any limitation on the scope of the present invention. Those skilled in the art should understand that modifications or substitutions can be made to the details and form of the technical solutions of the present invention without departing from the spirit and scope of the present invention, but all such modifications and substitutions fall within the protection scope of the present invention.

[0066] Example 1: Hardware Acceleration System Architecture

[0067] like Figure 1 As shown, this embodiment provides a dual BFS hardware accelerator for sparse matrix RCM reordering. The hardware system adopts a modular pipeline architecture, including: a top-level control module, a BFS engine module, a degree calculator circuit, a degree table module, a neighbor sorter module, an access flag bit vector and a stack manager module, as well as an external memory interface and an output interface.

[0068] The data flow employs a valid-ready handshake protocol, while the control flow uses single-cycle pulse signals. The state machine of the top-level control module manages the three-stage BFS execution process. The BFS engine module retrieves adjacency data from external memory via request signals and receives row indices returned by response signals. The degree table module stores node degrees and responds to queries. The neighbor sorter module sorts nodes by degree and outputs an ordered sequence. The access flag bit vector provides a single-cycle access status query. The stack manager module stores the BFS traversal sequence and outputs it in reverse order.

[0069] Top-level control module design:

[0070] The top-level control module adopts a finite state machine management algorithm. The state definitions include: IDLE (idle), INIT_DEGREE (degree table initialization), FIND_MIN_DEGREE (minimum degree search), BFS_FIRST (first BFS), BFS_SECOND (second BFS), BFS_RCM (RCM traversal), STACK_OUTPUT (stack output), and DONE (complete).

[0071] The state transition logic is as follows: When the top-level control module receives the start signal, the state machine transitions from the IDLE state to the INIT_DEGREE state to begin initializing the degree table; after receiving all column pointer data, the state machine transitions from the INIT_DEGREE state to the FIND_MIN_DEGREE state to find the minimum degree node; after finding the minimum degree node and sending its index to the BFS engine, the state machine transitions from the FIND_MIN_DEGREE state to the BFS_FIRST state to execute the first BFS traversal; after the BFS engine completes the first traversal and returns the first remote node, the state machine transitions to the BFS_FIRST state. The state machine transitions from the BFS_FIRST state to the BFS_SECOND state to execute the second BFS traversal; after the BFS engine completes the second traversal and returns the pseudo-outer nodes, the state machine transitions from the BFS_SECOND state to the BFS_RCM state to execute the third BFS traversal to generate the RCM sequence; after the third BFS traversal is completed, the state machine transitions from the BFS_RCM state to the STACK_OUTPUT state to start the stack manager for reverse output; after the stack manager has completed the output of all nodes, the state machine transitions from the STACK_OUTPUT state to the DONE state to indicate that the algorithm has been completed.

[0072] The state machine circuit enables precise control of the algorithm flow, avoiding data races and resource conflicts. The control signal `is_rcm_phase` enables selective recording by the stack manager, storing only the result of the third BFS step, thus saving storage resources. Deterministic state transitions guarantee fixed delays, providing predictability for real-time systems.

[0073] BFS Engine Module Design:

[0074] The BFS engine module adopts a pipelined state machine architecture, combined with Figure 2 The state transition diagram shown and Figure 3 The timing waveform diagram shown includes the following states: Idle state (IDLE), Node initialization state (INIT_NODE), Neighbor node request state (FETCH_ADJ), Neighbor node receive state (RECV_ADJ), Order waiting state (WAIT_SORT), Enqueue state (ENQUEUE), and Complete state (DONE).

[0075] The BFS engine module expands the data width of the FIFO queue to twice the IDX_LEN bit width, with each queue element encapsulating a combination of hierarchy information and node index. This design eliminates the need for independent hierarchy storage circuits; nodes and hierarchy information are atomically bound, avoiding synchronization issues.

[0076] A local counter, fifo_count, is introduced to manage queue depth: it increments when enqueuing and decrements when dequeuing, while remaining unchanged during both processes. The queue empty state detection circuit is implemented using a zero comparator; when the counter value is zero, it outputs a queue empty signal, providing zero-delay queue status determination.

[0077] State transition logic: such as Figure 2 As shown, when the BFS engine module receives the start signal bfs_start_valid, the state machine transitions from the IDLE state to the INIT_NODE state to initialize the starting node; after the starting node completes the enqueue operation, the state machine transitions from the INIT_NODE state to the FETCH_ADJ state to prepare to request neighboring node data; after sending the neighboring node request signal row_idx_req to the external memory, the state machine transitions from the FETCH_ADJ state to the RECV_ADJ state to start receiving neighboring node data; after receiving all the neighboring nodes of the current node (detecting row...), the state machine continues to receive neighboring node data. After the falling edge of the _idx_valid signal, the state machine transitions from the RECV_ADJ state to the WAIT_SORT state to wait for the neighbor sorter to complete the degree sorting. When the neighbor sorter returns the sorted_valid signal, the state machine transitions from the WAIT_SORT state to the ENQUEUE state to enqueue the sorted neighbor nodes in sequence. After completing the enqueueing operation of all neighbor nodes in the ENQUEUE state, if the queue is not empty, the state machine transitions back to the FETCH_ADJ state to continue processing the next node. If the queue is empty, the state machine transitions to the DONE state to indicate that the BFS traversal is complete.

[0078] Hardware execution timing: such as Figure 3 The diagram shows the complete cycle waveform of the BFS engine processing node 5. When the state machine is in the FETCH_ADJ state, the row_idx_req signal goes high to request adjacent data for node 5; when the state machine transitions to the RECV_ADJ state, the row_idx_valid signal is valid for 3 consecutive cycles, and the circuit receives neighbor nodes 2, 7, and 9 from the outside; after the nodes are received (falling edge of row_idx_valid), the state machine transitions to the WAIT_SORT state; the neighbor sorter outputs the sorted_valid signal, providing the degree-sorted node sequence 2, 9, 7; when the state machine is in the ENQUEUE state, the access flag query circuit detects that node 2 has been visited, the fifo_wr_en signal is valid for only 2 cycles, and the FIFO control circuit enqueues the sorted nodes 9 and 7 in sequence.

[0079] The working principle of the farthest node tracking circuit is as follows: during dequeueing, the level comparator compares the value of the current level with that of the maximum level register. If the current level is greater than the maximum level, the update circuit simultaneously refreshes both the maximum level register and the farthest node register. Due to the level traversal characteristics of BFS, only the first node of each level needs to be recorded to determine the farthest node.

[0080] External memory interface design:

[0081] The BFS engine employs a request-response decoupled interaction model: it sends a single-cycle pulse request signal and column index; the external memory returns all row indices of the column in subsequent consecutive cycles, providing a valid signal each cycle; the BFS engine determines the completion of transmission by listening for the falling edge of the valid signal through an edge detection circuit.

[0082] Single-request streaming response reduces handshake overhead; data length is implicitly expressed through the continuation and termination of the valid signal; zero idle period, continuous transmission of response data maximizes bandwidth utilization.

[0083] Degree meter module design:

[0084] The number table module uses dual-port RAM to store node degrees. The address space is RAM_DEEP, which can be set to 1024 in one embodiment, and the data width is IDX_LEN, which can be set to 32 bits in another embodiment. Port A is used for write operations, and port B is used for read operations.

[0085] The initialization phase circuit operates as follows: It receives a CSC-formatted column pointer `col_ptr`, calculates the degree value `degree_len` using a subtractor (equal to the current column pointer `col_ptr` minus the previous cycle's column pointer `col_ptr_r`), writes the result to the SPRAM memory address `wr_addr`, and increments the write address. Simultaneously, it updates the minimum degree; if `degree_len` is less than `min_degree`, it updates the `min_degree` and `min_degree_idx` registers using a comparator circuit.

[0086] The circuit operates as follows during the query phase: it receives the node index degree_rd and the query request degree_rd_valid, reads them from RAM memory port B, and after a delay of 1 clock cycle, outputs the degree value degree_o and the valid signal degree_o_valid.

[0087] Local caching avoids repeated external memory accesses, reducing access latency and power consumption.

[0088] Neighbor sorter module design:

[0089] like Figure 4As shown, the neighbor sorter module uses a Bitonic sorting network to achieve parallel sorting. The Bitonic sorting network is a comparison network structure suitable for hardware implementation. Its core principle is to construct a Bitonic sequence (a sequence that is first monotonically increasing then monotonically decreasing, or first monotonically decreasing then monotonically increasing) from the input sequence through multiple levels of comparators and exchangers, and then transform it into a completely ordered sequence through a Bitonic merging network. Unlike traditional serial sorting algorithms, the Bitonic sorting network has a fixed comparator topology and a defined pipeline depth. All comparison operations can be executed in parallel in hardware, and the sorting latency depends only on the number of network levels and is independent of the initial order of the input data, making it particularly suitable for hardware implementation.

[0090] The data structure uses a packed structure to encapsulate sorting items (sort_item). Each sorting item contains degree information and a node index, with the degree information located in the high-order bits and the node index in the low-order bits. The comparator circuit compares the overall values, automatically sorting in ascending order of degree. The number of comparison channels is set to MAX_NODES, which can be set to 32 in one embodiment. This parameter must be a power of 2 to preserve system scalability. Unused channels are padded with the maximum value (all 1 bits) to ensure that padded data placed later does not affect the sorting of valid data. The pipeline depth of the comparison network is determined by the number of input channels; when the number of channels is 32, the pipeline depth is 15 clock cycles.

[0091] Example of a sorting circuit: such as Figure 4 The diagram illustrates the processing flow of an 8-channel sorting network. The current node has 8 unvisited neighbors. The input register group receives the degree sequence [3,7,2,5,4,1,6,8]. The first-level comparison unit contains 4 comparators that compare (3,7), (2,5), (4,1), and (6,8) in parallel and swap them to form a partially ordered sequence. The second-level comparison unit continues to compare and swap using different connection patterns. The third-level comparison unit completes the final sorting, and the output register group outputs the degree sequence [1,2,3,4,5,6,7,8], with the corresponding node indices rearranged in ascending degree order to [6,3,1,5,4,7,2,8]. The output control circuit adds the sorting results sequentially to the BFS queue, ensuring that low-degree nodes (located on the periphery of the graph) are traversed first.

[0092] The state machine control flow includes four states: IDLE, COLLECT, SORT, and OUTPUT. The state transition logic is as follows: When a valid input signal is received, the state machine transitions from the IDLE state to the COLLECT state. After completing neighbor node collection and degree lookup in the COLLECT state, it transitions to the SORT state. In the SORT state, it waits for 15 clock cycles to complete the sorting process before transitioning to the OUTPUT state. In the OUTPUT state, valid nodes are output sequentially, and fill values ​​are filtered.

[0093] The Bitonic network achieves a fixed 15-cycle sorting latency, which is faster than serial sorting (hundreds of cycles). It should be noted that other sorting algorithms can be used for this sorting operation without affecting the correctness of the program's functionality.

[0094] Access marker bit vector design:

[0095] The access marker bit vector uses a visited bit vector structure, containing DIM_M bits, implemented using a flip-flop array, with each node corresponding to one bit. The operation interface includes: a polling circuit achieves zero-latency reading through combinational logic; an update circuit completes the marker operation in a single cycle through set logic; and an initialization circuit resets all bits in a single cycle through a global clear signal. Single-cycle clearing makes state switching between consecutive BFS cycles highly efficient, requiring only one clock cycle for initialization.

[0096] The working principle of the enqueue check logic is as follows: In the ENQUEUE state, for each neighbor node, the query result of the access mark bit vector is controlled by the AND gate circuit to enqueue operation. If the node has not been accessed, it is marked as accessed by the set circuit and added to the queue.

[0097] Stack Manager Module Design:

[0098] The stack manager module is implemented using dual-port RAM with a capacity equal to the product of DIM_M and IDX_LEN. In one embodiment, this can be set to 2048 bits, which equals 8 kilobytes. The state machine includes three states: IDLE (idle), WRITE (write sequentially), and READ (read in reverse order). The address control circuit implements zero-overhead sequence reversal with a total delay of 2n clock cycles.

[0099] The write phase circuit operates as follows: it receives the node index and a valid signal. When the is_rcm_phase control signal is high, the write address generator increments from 0 and performs a write operation to store the node index into RAM.

[0100] The read-out stage circuit operates as follows: the read address generator starts decrementing from the address DIM_M minus 1, performs a read operation to read the node index from RAM, and outputs a valid signal permu_o_valid to indicate that the output data is valid.

[0101] Example 2: Hardware Execution Flow

[0102] This embodiment illustrates the complete circuit operation process of a hardware accelerator performing sparse matrix reordering.

[0103] Preprocessing stage circuit operation:

[0104] The input matrix is ​​checked for CSC format by a format detection circuit; if not, the format conversion unit performs the conversion. The CSC format parser extracts the data array, indices array, and indptr array.

[0105] Symmetry detection is implemented using a comparator array. If asymmetry is detected, the matrix addition unit performs addition of the matrix and its transpose. The diagonal compensation unit subtracts diagonal elements through address mapping logic to avoid duplication. The adjacency list is constructed by the traversal controller scanning all non-zero elements, extracting row and column index pairs, and establishing a bidirectional relationship in the adjacency list memory when the row index is not equal to the column index.

[0106] The circuit executes the first positioning stage:

[0107] The initialization circuit of the degree table module calculates the difference between column pointers using a subtractor to obtain the degree value, and the minimum degree lookup circuit uses a cascaded comparator to output the minimum degree node index min_degree_idx.

[0108] The BFS engine module initiates the first BFS traversal from the node with the minimum degree. The initialization circuit clears the access flag bit vector, sets the level register to 0, and adds the starting node to the FIFO queue. During the traversal, the dequeue circuit retrieves data pairs containing the level and node, and the level comparator updates the `max_level` and `farthest_node` registers. The external memory interface obtains adjacency data, the access filter removes visited nodes by querying the bit vector, and the adder calculates the neighbor level before enqueuing it. At the end of the traversal, the `farthest_node` register latches the index of the first farthest node.

[0109] Hardware execution in the second positioning phase:

[0110] The BFS engine module restarts with the first farthest node. The initialization circuit re-zeros the access flag bit vector and executes the same sequence of hardware operations as the first time. This "backward probing" mechanism searches from one end of the graph to the other, and the value latched in the farthest_node register is the pseudo-peripheral node. The dual BFS strategy strictly limits the number of iterations to 2, and the hardware complexity is controlled in O(2^(n+e)) clock cycles.

[0111] Hardware execution during the traversal and sorting phase:

[0112] The is_rcm_phase signal of the top-level control module is set, activating the stack manager write enable gate and the neighbor sorter. The BFS engine starts the third traversal with pseudo-outer nodes.

[0113] The degree-first sorting mechanism is the key circuit operation in this stage. After the BFS state machine receives all the neighbors, the access filter filters out unvisited nodes, and the degree query circuit requests degree values ​​from the degree table module. The input control circuit of the neighbor sorter loads data pairs containing degree and node index into the register array. The comparator pipeline of the Bitonic sorting network performs parallel sorting for 15 clock cycles, and the output circuit outputs the node indices in ascending order of degree.

[0114] The enqueue control circuit processes neighbors in sorted order: the access flag setting circuit marks a visited node, the FIFO write circuit adds the node to the queue, and the stack manager synchronously records the information to memory. This ensures that low-degree nodes are visited first, allowing the traversal path to advance from the outer edge of the graph inwards.

[0115] Hardware operations during the reverse output phase:

[0116] The stack manager's state machine transitions from the WRITE state to the READ state. The read address generator decrements from DIM_M by 1, and the memory read port outputs a node index each cycle, which generates the permu_o and permu_o_valid signals via pipelined registers. Address reversal control automatically reverses the order, converting the CM sorting to an RCM sorting vector without requiring additional reversal operations.

[0117] Hardware operations during matrix rearrangement:

[0118] The permutation vector `perm` is passed to the matrix reordering unit. The reordering unit constructs the inverse permutation mapping relationship using a lookup table or RAM. During row reordering, the traversal controller replaces the original row indices with new indices through the mapping circuit. During column reordering, the column data is reorganized according to the permutation vector order. The reordering control state machine coordinates the pipeline operation, with a total processing time of O(n+e) clock cycles.

[0119] Example 3: System Comprehensive Performance Verification

[0120] This embodiment verifies overall performance through 13 standard test matrices, combined with... Figure 6 The comprehensive performance statistics shown are explained below.

[0121] The test matrices selected 13 sparse matrices from the SuiteSparse Matrix Collection, covering different sizes, number of nodes from 48 to 1919, different sparsity from 0.31% to 17.36%, and different application areas, including power systems, structural mechanics, and finite element meshes.

[0122] Bandwidth optimization performance verification:

[0123] The bandwidth optimization performance of 13 test matrices was evaluated. The statistical results show that the average bandwidth reduction rate of the method of the present invention reaches 73.85%, while the average bandwidth reduction rate achieved by the existing technology SciPy is 50.11%. The present invention improves the performance by 31.85 percentage points compared with the existing technology.

[0124] The specific data for a typical test case is as follows:

[0125] 1. Mesh3em5 matrix: The original bandwidth is 281. After reordering using the method of this invention, the bandwidth is reduced to 17, with a bandwidth reduction rate of 93.95%. After reordering using the SciPy method, the bandwidth is 33, with a bandwidth reduction rate of 88.26%. The bandwidth improvement rate of this invention compared to the SciPy method is 48.48%.

[0126] 2. Plat1919 matrix: The original bandwidth is 1297. After reordering using the method of this invention, the bandwidth is reduced to 80, with a bandwidth reduction rate of 93.83%. After reordering using the SciPy method, the bandwidth is 161, with a bandwidth reduction rate of 87.59%. The bandwidth improvement rate of this invention compared to the SciPy method is 50.31%.

[0127] Its non-zero element arrangement is as follows Figure 5 As shown, the left side represents the original matrix, the middle side represents the matrix processed using the method of this invention, and the right side represents the matrix processed using the SciPy library. The comparison clearly demonstrates that the method of this invention outperforms the SciPy library implementation in terms of matrix bandwidth optimization.

[0128] 3.494_bus matrix: The original bandwidth was 428. After reordering using the method of this invention, the bandwidth was reduced to 62, with a bandwidth reduction rate of 85.51%. After reordering using the SciPy method, the bandwidth was 79, with a bandwidth reduction rate of 81.54%. The bandwidth improvement rate of this invention compared to the SciPy method was 21.52%.

[0129] The above data shows that the method of the present invention has significant advantages over the prior art in bandwidth optimization, especially in the optimization of high bandwidth matrices.

[0130] Contour optimization performance verification:

[0131] like Figure 6 As shown, the contour optimization performance was evaluated on the same 13 test matrices. The statistical results show that the average contour reduction rate of the method of the present invention reaches 67.89%, while the average contour reduction rate achieved by the prior art SciPy is 43.52%. The present invention improves upon the prior art by 38.67 percentage points.

[0132] The specific data for a typical test case is as follows:

[0133] 1. plat1919 matrix: The original contour is 1240723. After reordering using the method of this invention, the contour is reduced to 99959, with a contour reduction rate of 91.94%. After reordering using the SciPy method, the contour is 193742, with a contour reduction rate of 84.38%. The contour improvement rate of this invention compared to the SciPy method is 48.41%.

[0134] 2. ex33 matrix: The original contour is 127617. After reordering using the method of this invention, the contour is reduced to 16771, with a contour reduction rate of 86.86%. After reordering using the SciPy method, the contour is 71796, with a contour reduction rate of 43.74%. The contour improvement rate of this invention compared to the SciPy method is 76.64%.

[0135] 3. bcsstm10 matrix: The original contour was 38129. After reordering using the method of this invention, the contour was reduced to 6430, with a contour reduction rate of 83.14%. After reordering using the SciPy method, the contour was 20876, with a contour reduction rate of 45.25%. The contour improvement rate of this invention compared to the SciPy method was 69.20%.

[0136] The above data shows that the method of the present invention has a more significant advantage over the existing technology in contour optimization, with an improvement rate of over 70% in some test cases. This is of great significance for reducing the number of filler elements in the solver of linear equations and improving the solution efficiency.

[0137] Hardware system performance:

[0138] In one embodiment, the performance parameters of the hardware system are as follows:

[0139] The clock frequency is set to 100MHz, and the critical path is located in the Bitonic sorting network.

[0140] In terms of latency, the latency for processing a 1000-node graph is approximately 1.2ms, which is roughly composed of approximately 10 microseconds for degree table initialization, approximately 350 microseconds for each of the three BFS operations, and approximately 10 microseconds for stack output.

[0141] In terms of scalability, by adjusting the parameters RAM_DEEP and DIM_M, the system can support matrix sorting of very large dimensions.

[0142] In terms of handling exceptions, isolated nodes are automatically placed at the end of the sequence; for graph structures with multiple connected components, the algorithm circuit automatically selects the minimum degree node of the remaining components to continue BFS traversal until all nodes are visited.

[0143] The above embodiments describe in detail the circuit architecture, module implementation, and performance verification of the hardware accelerator of the present invention. Through the collaborative work of dedicated hardware modules such as a fixed triple BFS dual-location circuit, a degree-first comparison network sorter, an extended-width FIFO queue circuit, a single-cycle bitmap access marker circuit, and a hardware stack reverse output circuit, the present invention achieves significant optimization of sparse matrix bandwidth and profile while ensuring deterministic latency. It is particularly suitable for preprocessing requirements in fields such as finite element analysis, linear equation solving, and graph computation, as well as real-time embedded systems and hardware acceleration scenarios requiring deterministic performance guarantees.

[0144] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the scope of protection of the present invention; all technical solutions formed by equivalent transformations or equivalent substitutions fall within the scope of protection of the present invention; the parts of the present invention not described in detail are well-known technologies to those skilled in the art.

Claims

1. A dual BFS hardware accelerator for sparse matrix RCM reordering, characterized in that, The dual BFS hardware accelerator for the sparse matrix RCM reordering includes: The top-level control module executes the process through a state machine management algorithm, sequentially completing degree table initialization, three BFS start-up controls, data flow routing, and result output. The BFS engine module uses a pipelined state machine with a dual BFS positioning architecture to execute BFS traversal. It achieves hierarchical information transmission by storing a combination of hierarchical and node index data through a FIFO queue with expanded data width, and tracks the maximum level and corresponding node in real time to complete the two-stage positioning from the minimum degree node to the first far-end node and then to the pseudo-peripheral node. The degree table module calculates and stores node degrees through memory. During the initialization phase, it calculates the degree based on the difference of column pointers in CSC format. During the query phase, it responds to node index requests and returns the corresponding degree. The neighbor sorter module uses a degree-first comparison network to sort neighbor nodes in ascending order of degree. The input data includes a combination of degree and node index, and the output is a sequence of node indices sorted by degree. The access marker bit vector uses a bitmap structure to record the node access status, with each node corresponding to one bit, enabling single-cycle status query and update. The stack manager module stores the BFS traversal sequence sequentially in memory, and reverses the order of the output by reading the address in reverse order.

2. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The dual BFS hardware accelerator for sparse matrix RCM reordering includes the following working stages: Preprocessing stage: The top-level control module determines whether it is in CSC format through the format detection circuit. If not, it converts the input sparse matrix into compressed sparse column CSC format. The symmetry detection circuit detects whether the upper triangular part and the lower triangular part are equal after transposition. If they are not equal, the missing part is filled in by the matrix addition operation unit and the diagonal compensation operation unit. The adjacency list construction circuit traverses all non-zero elements of the CSC format matrix and establishes bidirectional adjacency relationships. First localization phase: The degree table module calculates the degree of all nodes and selects the node with the smallest degree. The BFS engine module starts from the node with the smallest degree as the first starting node and performs the first breadth-first search. The level tracking register records the level information and determines the first farthest node in the level of the first starting node. Second positioning phase: The BFS engine module takes the first remote node as the second starting node, and executes the second BFS from the second starting node. The level tracking register determines the second remote node that is farthest from the second starting node as the pseudo-peripheral node. Traversal and sorting phase: The BFS engine module uses the pseudo-outer node as the final starting node to perform the third BFS traversal. During the traversal, the neighbor sorter module sorts all unvisited neighbor nodes of the current node in ascending order according to their degree and adds them to the queue in turn to generate the Cuthill-McKee sort. Reverse output stage: The stack manager module reverses the Cuthill-McKee sorting results to obtain the reverse Cuthill-McKee permutation vector; Matrix rearrangement stage: The matrix rearrangement circuit synchronously reorders the rows and columns of the original sparse matrix according to the arrangement vector, and outputs a bandwidth-optimized sparse matrix.

3. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 2, characterized in that, The symmetry detection circuit achieves matrix symmetry detection through a comparator array; The matrix addition unit uses a pipelined adder to perform matrix addition operations, while the diagonal compensation unit locates diagonal elements and performs compensation through address mapping logic. The adjacency list construction circuit includes a CSC format parser and a bidirectional link controller. The parser traverses all non-zero elements to extract row and column indices, and the link controller establishes bidirectional adjacency relationships in the adjacency list memory based on the index pairs.

4. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 2, characterized in that, The BFS traversal of the BFS engine module is implemented by a hierarchical search circuit: The FIFO queue controller stores a combination of node index and hierarchy number; The initialization circuit starts from the starting node, marks it as visited in the access flag bit vector, sets the hierarchy register to 0, and adds the data to the queue. Traverse the control state machine. When the queue is not empty, take out the first element of the queue. Get all the neighbors of the node through the external memory interface. For unvisited neighbors, mark them as visited by the access flag bit vector. The hierarchical adder sets its level to the current node's level plus 1 and adds it to the queue. The level tracing circuit maintains the maximum level value and its corresponding node index during the traversal. The comparator detects when the level of the retrieved node is greater than the current maximum level and updates the maximum level register and the corresponding node register. After the traversal is completed, the node in the register is the farthest node.

5. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 2, characterized in that, The neighbor sorter module retrieves the current node from the queue and obtains all neighbor nodes of that node. It then filters out visited nodes based on the access flag bit vector to form a candidate set. For each node in the candidate set, a query request is sent to the degree table module. The degree table module returns the corresponding degree value. The candidate set is then sorted in parallel according to the degree value from smallest to largest. In the sorted order, neighboring nodes are marked as visited in the access flag bit vector and added to the queue through the FIFO queue controller to ensure that low-degree nodes are visited first.

6. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The BFS engine module expands the data width of the FIFO queue to twice the IDX_LEN bit width; the BFS engine module sets a queue depth counter, and maintains the number of elements in the queue in real time according to enqueue and dequeue operations. Enqueue operation increments the counter, dequeue operation decrements the counter, and the counter remains unchanged during enqueue and dequeue. The queue is empty based on the counter value.

7. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The BFS engine module and the external memory adopt a request-response decoupled interaction mode: the BFS engine sends an adjacency node request and the corresponding column index; the external memory returns all row indices of the column in subsequent consecutive cycles; the BFS engine records the number of adjacency nodes received through a counting mechanism and determines the completion of data transmission based on the state change of the response valid signal.

8. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The neighbor sorter module uses a comparison network to achieve parallel sorting. The pipeline depth of the comparison network is calculated and determined based on the number of comparison channels. The input data structure includes a combination of node degree and node index. Unused input channels are filled with extreme values ​​to ensure the correctness of the sorting. During output, the node indexes are output in degree order and the filled data is filtered to output only valid adjacent nodes.

9. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The degree table module uses random access memory to store node degree information; during the initialization phase, it receives column pointer data of the sparse matrix, calculates the difference between adjacent column pointers to obtain the degree of each node, and stores it in ascending address order. During the query phase, the node index and query request signal are received. After a delay in reading from the memory, the degree value of the corresponding node is returned and a valid signal is output.

10. The dual BFS hardware accelerator for sparse matrix RCM reordering according to claim 1, characterized in that, The stack manager module controls sequential writing and reverse reading through a state machine: during the writing phase, it receives the node index output by the BFS engine and stores it into the memory in ascending order of address. The stack manager module selectively processes the traversal results of specific BFS stages based on the control signals from the top-level control module.

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