Asynchronous communication management method and apparatus, electronic device, and storage medium

Abstract

This application provides an asynchronous communication management method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: modifying the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on instructions sent by the asynchronous communication unit; and modifying the status bits in the memory barrier data block of the asynchronous communication unit when the instruction count and data volume count meet preset conditions. The method and apparatus provided by this application not only manage the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchanged between producers and consumers, but also abstract the complex count update and status judgment logic from specific test cases, forming a general asynchronous communication management mechanism that can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

Description

Technical Field

[0001] This application relates to the field of chip design and manufacturing technology, and in particular to an asynchronous communication management method, apparatus, electronic device and storage medium. Background Technology

[0002] With the widespread application of General Purpose Graphics Processing Units (GPGPUs) in high-performance computing fields such as artificial intelligence and scientific computing, asynchronous communication between their complex parallel processing units has become increasingly important. The producer-consumer model is a classic pattern for implementing such asynchronous communication, where the producer is responsible for generating data and the consumer is responsible for processing it. To ensure data consistency and correctness during read and write processes and to avoid data conflicts caused by race conditions, memory barriers (mbars) are used in GPGPU architectures for asynchronous communication.

[0003] In related technologies, the processing logic of memory barriers is tightly coupled with test cases, resulting in poor reusability; moreover, it only supports targeted testing of memory barriers and cannot effectively perform random verification.

[0004] Therefore, how to provide an asynchronous communication management method that can be randomly verified has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] This application provides an asynchronous communication management method, apparatus, electronic device, and storage medium to ensure the consistency and correctness of data exchanged between producers and consumers, and to support random verification.

[0006] This application provides an asynchronous communication management method, including: Based on the instructions sent by the asynchronous communication unit, the instruction count value and / or data count value in the memory barrier data block of the asynchronous communication unit are modified; If the instruction count value and the data count value meet the preset conditions, the status bit in the memory barrier data block of the asynchronous communication unit is modified; The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

[0007] In some embodiments, the method further includes: When the asynchronous communication unit completes the transmission of the specified instruction, in response to the calibration request, the instruction count value and the data volume count value are modified so that the instruction count value and the data volume count value meet the preset conditions.

[0008] In some embodiments, modifying the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on the instructions sent by the asynchronous communication unit includes: When the asynchronous communication unit sends any instruction, the instruction count value is decremented by one, and the data volume count value is modified. The modification value of the data volume count is consistent with the data operation volume of any instruction.

[0009] In some embodiments, the initialization operation of the memory barrier data block of the asynchronous communication unit includes: Configure the initial value of the instruction count in the memory barrier data block; Configure the initial value of the data volume count value in the memory barrier data block; Configure the initial values ​​of the status bits in the memory barrier data block.

[0010] In some embodiments, the method further includes: If the status bit in the producer's memory barrier data block is modified, the consumer is instructed to wait successfully.

[0011] In some embodiments, the method further includes: In the local computing unit, the impact of the producer's data operations on the memory barrier data block in the remote computing unit is recorded, using the consumer's memory barrier data block as a reference. The memory barrier data block in the remote computing unit is calibrated based on the residual value of the consumer's memory barrier data block in the local computing unit; If the consumer waits successfully in the remote computing unit, the local computing unit and the remote computing unit are synchronized.

[0012] In some embodiments, the method further includes: In the verification environment, the memory barrier data block of the asynchronous communication unit in the design under test is randomly initialized; the asynchronous communication unit is loaded with specified instructions; the verification environment includes a design verification module and a reference model module of the design under test. By comparing the memory barrier data block in the design verification module with the memory barrier data block in the reference model module, the memory barrier verification result of the design under test is determined.

[0013] This application provides an asynchronous communication management device, comprising: The counter value modification module is used to modify the instruction counter value and / or data volume counter value in the memory barrier data block of the asynchronous communication unit based on the instructions sent by the asynchronous communication unit; The status bit modification module is used to modify the status bit in the memory barrier data block of the asynchronous communication unit when the instruction count value and the data count value meet preset conditions. The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

[0014] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the asynchronous communication management method when executing the computer program.

[0015] This application provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the asynchronous communication management method described above.

[0016] The asynchronous communication management method, apparatus, electronic device, and storage medium provided in this application not only enable automatic and accurate tracking and management of the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchanged between producers and consumers; but also abstract the complex count value update and state judgment logic from specific test cases to form a general asynchronous communication management mechanism, which can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is one of the flowcharts of the asynchronous communication management method provided in this application.

[0020] Figure 2 This is an organizational chart of the memory barrier controller provided in this application.

[0021] Figure 3 This is a test schematic diagram of the memory barrier controller provided in this application.

[0022] Figure 4This is a schematic diagram of the synchronization of the computing units provided in this application.

[0023] Figure 5 This is the second flowchart of the asynchronous communication management method provided in this application.

[0024] Figure 6 This is a schematic diagram of the asynchronous communication management device provided in this application.

[0025] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps, units, or modules is not necessarily limited to those explicitly listed, but may include other steps, units, or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0028] In order to address the shortcomings of related technologies, Figure 1 This is one of the flowcharts illustrating the asynchronous communication management method provided in this application, such as... Figure 1 As shown, the method includes steps 110 and 120.

[0029] Step 110: Based on the instructions sent by the asynchronous communication unit, modify the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit. The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

[0030] Specifically, the asynchronous communication management method provided in this application is executed by an asynchronous communication management device. This device can be implemented in software, such as an asynchronous communication management program; or it can be a device that executes the asynchronous communication management method, such as a mobile terminal, tablet computer, desktop computer, or server.

[0031] In this embodiment, asynchronous communication units primarily refer to logical entities that play specific roles in the producer-consumer model. Specifically, they include producers and consumers. A producer is an entity that writes data to a shared memory space, while a consumer is an entity that reads data from that shared memory space. In a verification environment, these asynchronous communication units can be manifested as agents or clients in a testbench.

[0032] The memory barrier slot (mbar slot) is a core data structure defined in this application embodiment for implementing synchronization management. Each memory barrier slot is bound to a specific asynchronous communication unit (i.e., a producer or a consumer) and is simultaneously associated with a shared memory space shared by the producer and consumer.

[0033] The method provided in this application embodiment can be specifically implemented by a memory barrier controller (mbarcontroller) set in the chip.

[0034] Figure 2 This is an organizational chart of the memory barrier controller provided in this application, such as... Figure 2 As shown, multiple memory barrier data blocks can be organized into groups. Each group (e.g., group 0 to n) contains at least one producer's memory barrier data block (mbar slot for producer) and at least one consumer's memory barrier data block (mbar slot for consumer), which together act on the same shared memory space 0 to n.

[0035] Each memory barrier data block can be a memory object identified by an address, which internally stores multiple attribute parameters used for synchronization management. The memory barrier controller can support and manage at least one set.

[0036] Key attribute parameters in a memory barrier data block include the instruction count (pending_cnt) and the data count (tx_cnt). The instruction count records how many pending instructions are involved in the current synchronization process. The data count records the total amount of data transferred (e.g., bytes) during the synchronization process. The initial values ​​of these two counts can be set before use as a baseline for starting synchronization.

[0037] Figure 3 This is a test schematic diagram of the memory barrier controller provided in this application, as shown below. Figure 3 As shown, the memory barrier controller can be integrated into a test platform. Producer or consumer instructions come from different interfaces of the design under test. In the test platform, each interface corresponds to its own agent, which corresponds to the client in the diagram, and the instructions are presented as a sequence of instructions from each agent.

[0038] The memory barrier controller is bound to the instruction sequence of each agent. Therefore, an instruction sent from a certain instruction sequence to the design under test is bound to the memory barrier data block of a specific producer or consumer. After an instruction is issued, the memory barrier controller automatically maintains the memory barrier data block corresponding to that instruction.

[0039] The method provided in this application flexibly supports various producer-consumer patterns, such as one-to-one, one-to-many, many-to-one, and many-to-many. For example, producer clients_0 to_n are configured to connect to n+1 interfaces, each bound to a group, and configured as producers. Correspondingly, consumer clients_0 to_n are configured to connect to n+1 interfaces, each bound to the aforementioned group, and configured as consumers, thus forming a many-to-many producer-consumer group.

[0040] In one specific embodiment, when an asynchronous communication unit (e.g., a producer) sends a command to the Design Under Test (DUT), the count value in the memory barrier data block bound to that asynchronous communication unit is automatically updated. For example, when the producer sends a write command, the management method can decrement the corresponding command count value and simultaneously subtract the amount of data transmitted by the write command from the corresponding data volume count value. Similarly, when a consumer sends a read command, the count value in its bound memory barrier data block will also change accordingly.

[0041] It is worth noting that modification operations can be AND / OR, meaning that an instruction may only affect the instruction count, or only the data count, or both. This depends on the type of instruction. The method in this application embodiment can flexibly support these different instruction behaviors, thereby accurately tracking the synchronization state.

[0042] Step 120: If the instruction count and data count meet the preset conditions, modify the status bits in the memory barrier data block of the asynchronous communication unit.

[0043] Specifically, the preset condition is a logical condition used to determine whether the synchronization phase is complete. In a specific implementation, this preset condition is that both the instruction count and the data count are 0. This indicates that all instructions involved in synchronization have been issued, and all related data has been processed. Of course, in other possible implementations, this preset condition could also be to determine whether only one of the count values ​​has reached a certain threshold (e.g., 0), depending on the specific synchronization requirements.

[0044] Key attribute parameters in a memory barrier data block also include a parity bit. The parity bit is a flag in the memory barrier data block used to indicate its release status or synchronization phase. This parity bit typically has only two values ​​(e.g., 0 and 1) to distinguish consecutive synchronization cycles, preventing a subsequent wait operation from incorrectly matching a previous release signal.

[0045] In one specific embodiment, the memory barrier controller continuously monitors the instruction count and data count values ​​in the memory barrier data block. Once both values ​​have decreased to 0 (i.e., a preset condition is met), it indicates that the asynchronous communication unit (e.g., the producer) has completed all operations in its current phase. At this point, the memory barrier controller automatically modifies its corresponding status bit, for example, toggling the status bit from 0 to 1. This change in status bit is a crucial synchronization signal. The consumer checks the value of this status bit to determine whether its waiting operation was successful.

[0046] The asynchronous communication management method provided in this application not only realizes automatic and accurate tracking and management of the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchange between producers and consumers; it also realizes the abstraction of complex count value update and state judgment logic from specific test cases, forming a general asynchronous communication management mechanism that can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

[0047] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0048] In some embodiments, the method further includes: When the asynchronous communication unit completes the transmission of the specified instruction, in response to the calibration request, the instruction count value and the data volume count value are modified so that the instruction count value and the data volume count value meet the preset conditions.

[0049] Specifically, when performing random verification of a memory barrier, because the sequence of sent instructions is random, the instruction count and data count in the corresponding memory barrier data block may not naturally return to zero after the producer (or consumer) completes its series of random operations. For example, a random test scenario may include 5 operations to increment the count and 4 operations to decrement the count, ultimately resulting in a non-zero residual value. As long as the count does not meet the preset condition (e.g., not 0), the status bit will not flip, and the memory barrier will not be released. This will cause the other party in the communication (e.g., a waiting consumer) to enter an infinite wait, thus suspending the entire test scenario and interrupting the verification process. To address the above shortcomings, embodiments of this application provide a calibration method.

[0050] The specified instruction here does not refer to a specific, fixed instruction, but rather to a set or sequence of instructions planned within a test case. This set of instructions can be randomly generated or specifically constructed, and its purpose is to test the behavior of the design under test under a specific load or combination of operations. Therefore, completing the transmission of the specified instruction signifies that the asynchronous communication unit has completed its task within a test phase.

[0051] A calibration request is an explicit request initiated proactively by an external source (typically the control logic of a test case). For example, a user can generate a calibration request by calling a calibration method provided by the memory barrier controller. This request acts as a signal to modify the instruction count and data count values. The count values ​​are modified to meet preset conditions. In a specific embodiment, the calibration request triggers several instructions sent from an interface to the design under test and the memory barrier controller. These instructions are only related to clearing the instruction count (pending_cnt) and data count (tx_cnt). As long as these values ​​are non-zero, the corresponding instructions are sent to clear the residual values ​​to zero.

[0052] When the memory barrier controller receives a calibration request, it performs a mandatory modification operation on the specified memory barrier data block. Specifically, it directly sets the instruction count and data count to values ​​that meet preset conditions. In one specific embodiment, this means forcibly clearing these two counts to zero (i.e., setting them to 0). This operation ignores the actual residual values ​​of the counts after the random instruction sequence has been executed, ensuring that regardless of how random the previous operations are, the memory will eventually reach a released state.

[0053] Once the producer has finished writing data, it can release its own memory barrier through calibration, notifying the consumer that it can begin the current round of data reading. The same logic applies to the consumer. Once the consumer has finished reading data, it can also release its own memory barrier through calibration, notifying the producer that it can begin the next round of data production.

[0054] The asynchronous communication management method provided in this application effectively transforms the management of memory barriers from a directional verification mode that relies on deterministic instruction sequences to a random verification mode that can support complex and efficient ones by forcibly modifying calibration requests. This ensures that random test scenarios can proceed smoothly without being suspended due to residual count values, thereby greatly improving the efficiency of verification.

[0055] In some embodiments, modifying the instruction count and / or data count in the memory barrier data block of the asynchronous communication unit based on instructions sent by the asynchronous communication unit includes: When any instruction is sent by the asynchronous communication unit, the instruction count is decremented by one, and the data count is modified. The modification value of the data volume count is consistent with the data operation volume of any instruction.

[0056] Specifically, this embodiment of the application closely links the memory barrier synchronization mechanism with each specific instruction action. Before starting a synchronization cycle, the initiator (e.g., the producer) pre-configures the total number of instructions and the total amount of data participating in that cycle. These two values ​​serve as the initial values ​​for the instruction count and the data count, respectively. Subsequently, whenever the asynchronous communication unit sends an instruction related to the memory barrier, the memory barrier controller deducts the impact of that instruction on the instruction count and the data count from these two counts in real time.

[0057] "Any instruction" refers to all instructions configured to participate in memory barrier synchronization. In a general-purpose graphics processor (GPU) verification environment, instructions typically have multiple attributes, which may include a memory barrier attribute to identify whether the instruction needs to be synchronized with a memory barrier data block. The processing logic of the embodiments in this application applies to all instructions with such an identifier.

[0058] Each instruction participating in synchronization, regardless of its specific function (writing data, reading data, or other control operations), is considered an independent synchronization event. Therefore, whenever such an instruction is sent, the total number of pending instructions decreases by one. For example, if the initial value of the instruction count is N, then after sending N related instructions, the count will naturally decrease to 0.

[0059] Data operand size refers to the amount of data transferred in a single instruction. For a write instruction, it refers to the amount of data written (e.g., how many bytes were written); for a read instruction, it refers to the amount of data read. For some control instructions that do not involve data transfer, the data operand size can be 0.

[0060] The modification value of the data volume count is consistent with the amount of data operated on by an instruction, meaning that the modification of the data volume count is precise and related to the instruction content. If the initial value of the data volume count (representing the total amount of data) is M, and the currently sent write instruction writes D bytes of data, then the data volume count will be updated to MD. In this way, the data volume count accurately tracks the total amount of data remaining to be processed.

[0061] The asynchronous communication management method provided in this application achieves refined and automated management of the synchronization process by precisely binding the update of the counter value to the behavior of each instruction; it ensures that the state of the memory barrier block accurately reflects the execution progress and data flow of the underlying instructions. This precise tracking mechanism is the foundation for achieving reliable synchronization and avoids synchronization errors caused by improper counter value management.

[0062] In some embodiments, the initialization operation of the memory barrier data block of the asynchronous communication unit includes: Configure the initial value of the instruction count in the memory barrier data block; Configure the initial value of the data volume count value in the memory barrier data block; Configure the initial values ​​of the status bits in the memory barrier data block.

[0063] Specifically, the initial value of the configuration instruction count is used to set how many instructions are expected to participate in synchronization within a synchronization cycle. This initial value is usually determined by the test scenario.

[0064] Configure the initial value of the data volume counter, which sets the expected total amount of data to be processed within a synchronization cycle. Similar to the instruction counter, this value is set based on the requirements of the test scenario.

[0065] The initial value of the configuration status bit is used to set the initial state of the memory barrier at the start of synchronization. The status bit is usually a binary flag (e.g., 0 or 1) used to distinguish between consecutive synchronization cycles.

[0066] The asynchronous communication management method provided in this application provides a clear and reliable starting benchmark for the entire asynchronous communication synchronization process by pre-configuring three key attribute parameters of the memory barrier data block.

[0067] In some embodiments, the method further includes: If the status bits in the producer's memory barrier data block are modified, the consumer is instructed to wait for success.

[0068] Specifically, in the producer-consumer model, the consumer must wait for the producer to complete data production before it can safely read the data. This application embodiment uses the status bits of a memory barrier to transmit signals. The consumer's wait operation essentially involves continuously polling or monitoring the status bits in the memory barrier data block corresponding to the producer until the status bit changes to the desired value.

[0069] When the producer's instruction count and data count meet preset conditions, the memory barrier controller modifies the parity bit in its memory barrier data block. For example, flipping the parity bit from its initial value of 0 to 1 indicates that the producer has completed the current stage of data production and the data in the shared memory space is ready.

[0070] A successful wait means the consumer's wait operation has ended, and it can continue with subsequent processes (usually reading data). The consumer executes a wait operation targeting the memory barrier data block corresponding to the producer. The wait operation typically includes one parameter: the desired status bit value.

[0071] In one specific embodiment, if the initial value of the producer's state bit is 0, then when the consumer performs a waiting operation in the first round of synchronization, its expected state bit value is 1.

[0072] The consumer's wait operation continuously checks the status bit of the producer's memory barrier data block. As long as the value remains 0, the wait operation will continue to block or poll, and the consumer will remain in a waiting state.

[0073] Once the producer completes its operation, its status bit is changed to 1. The consumer's waiting operation detects this change (the current value matches the expected value) and immediately returns a success status. This returned success status indicates that the consumer's wait has been successful. At this point, the consumer knows it can safely read data from the shared memory space.

[0074] The asynchronous communication management method provided in this application ensures that consumers will not access data before it is ready, thereby fundamentally guaranteeing data consistency and operational correctness.

[0075] In some embodiments, the method further includes: In the local computing unit, the impact of the producer's data operations on the memory barrier data block in the remote computing unit is recorded, using the consumer's memory barrier data block as a reference. The memory barrier data blocks in the remote computing unit are calibrated based on the residual values ​​of the consumer's memory barrier data blocks in the local computing unit. If the consumer waits for success in the remote computing unit, the local computing unit and the remote computing unit are synchronized.

[0076] Specifically, a computational task may need to be executed across different Compute Units (CUs). For example, a producer located in a local CU may need to update a memory barrier located in a remote CU in order to synchronize with a consumer on the remote CU. The producer initiating the operation is located in the local CU, while the target consumer it needs to synchronize with is located in the remote CU.

[0077] Figure 4 This is a schematic diagram of the synchronization of the computing units provided in this application, such as... Figure 4 As shown, when a producer in the local computing unit needs to operate on a remote memory barrier, it is difficult to directly and accurately verify and track its state through random operations. Therefore, in this embodiment, the consumer memory barrier data block of the local computing unit is used as a reference object to synchronously record all operations of the local producer on the remote memory barrier. When the random operation sequence of the local producer is completed, the final residual value on this consumer memory barrier data block accurately reflects the amount that the remote memory barrier should be calibrated.

[0078] Specifically, within the local computing unit, there exists a memory barrier controller. When a local producer sends a command to update the memory barrier controller of a remote computing unit, this command is not only sent to the remote computing unit (through the update path of the local computing unit), but its effect on the count value is also synchronously recorded on a consumer memory barrier data block managed by the local memory barrier controller. This consumer memory barrier data block accumulates or subtracts the expected impact of all operations from the local producer on the count value in the remote memory barrier data block.

[0079] Record the impact of data operations, meaning that whenever the local producer sends an instruction, the corresponding count value in the local consumer memory barrier data block will also be modified in the same way.

[0080] When a local producer completes its series of random instruction operations on a remote memory barrier, the count value of the remote memory barrier may not be zero due to randomness. Simultaneously, the count value in the consumer memory barrier data block, which serves as a local reference, also accumulates from the same operations, and its final value (i.e., the residual value) is theoretically the same as the actual residual value of the remote memory barrier.

[0081] At this point, the memory barrier data block in the remote computing unit can be calibrated based on the residual value of the consumer's memory barrier data block in the local computing unit. For example, the count value in the memory barrier data block in the remote computing unit can be cleared based on the residual value.

[0082] Once the memory barrier of the remote computing unit is successfully calibrated and released, the consumer located on the remote computing unit can wait for success and begin its subsequent operations. After completing its task, the consumer on the remote computing unit may send a synchronization instruction back to the local computing unit, or update another memory barrier that the local computing unit is waiting for. This interaction completes a full synchronization cycle between the two computing units.

[0083] The asynchronous communication management method provided in this application successfully extends the capability of random verification from within a single computing unit to between multiple computing units by introducing a local reference object and a remote calibration mechanism based on residual values. This greatly improves the verification coverage and reliability for complex scenarios where multiple computing units work together.

[0084] In some embodiments, the method further includes: In the verification environment, the memory barrier data block of the asynchronous communication unit in the design under test is randomly initialized; the asynchronous communication unit is loaded with specified instructions; the verification environment includes the design verification module and the reference model module of the design under test. By comparing the memory barrier data blocks in the design verification module and the memory barrier data blocks in the reference model module, the memory barrier verification results of the design under test are determined.

[0085] Specifically, the verification environment is a software platform (testbench) used to test hardware designs. Generally, it includes a stimulus generator, drivers, monitors, as well as design verification modules and reference model modules.

[0086] The design under test (DUT) refers to the hardware circuit design being verified, typically a circuit described by Register Transfer Level (RTL) code. In this application, the DUT may be a general-purpose graphics processor or other processor design that includes hardware implementation logic for memory barriers.

[0087] The design verification module is responsible for interacting with the design under test (DUT) and collecting actual status information from it. For example, it reads the actual values ​​of the physical memory barrier register (i.e., memory barrier data block) inside the DUT after instruction execution via bus transactions or a dedicated debug interface, including the count values ​​of various key attribute parameters (including instruction count, data count, and status bits).

[0088] The reference model module can be a pure software component that functionally simulates the behavior of memory barriers in the design under test (DUT). It receives the exact same instruction stimuli as the DUT and updates its internally maintained memory barrier data block according to the methods described in the above embodiments (including initialization, counter modification, status bit modification, calibration, etc.). This software-maintained data block represents the expected result used for comparison with the hardware.

[0089] In one specific implementation, the return value of the memory barrier (wait mbar) instruction can be waited for. If the return value is 1, it indicates that the memory barrier verification result of the design under test is consistent with expectations.

[0090] In another specific embodiment, the key attribute parameters (including instruction count, data volume count, and status bits) in the memory barrier data block in the design verification module and the memory barrier data block in the reference model module can be directly read and compared by the test memory barrier (test mbar) instruction. If the comparison is consistent, it means that the memory barrier verification result of the design under test is consistent with the expectation.

[0091] The asynchronous communication management method provided in this application constructs a complete, closed-loop automated verification process. Since the method can be executed by a dedicated memory barrier controller, and the count values ​​of each key attribute parameter can be obtained for comparison, the correctness check of the memory barrier function becomes objective, automated, and supports random verification.

[0092] Figure 5 This is the second flowchart of the asynchronous communication management method provided in this application, as shown below. Figure 5 As shown, taking the example of producers and consumers located in the same computing unit, the asynchronous communication management method of the memory barrier controller is explained.

[0093] First, both producers and consumers need to randomly initialize their respective memory barrier data blocks.

[0094] For the producer, write operation instructions can be loaded for the design under test from several interfaces. After the specified instructions are sent, the user can simply call the calibration method supported by the memory barrier controller to calibrate the producer's memory barrier data block. In this way, the consumer can wait for the producer's memory barrier data block to be successfully calibrated; otherwise, it needs to wait indefinitely for the producer's memory barrier data block to be released.

[0095] After the producer's memory barrier data block is successfully waited for, the status bit attribute of the producer's memory barrier data block will automatically flip. In the next round, the consumer needs to use the flipped status bit to wait for the producer's memory barrier data block. This is also automatically maintained by the memory barrier controller, which greatly simplifies the writing of test cases for users. Note that the return value of the waiting memory barrier data block is returned from within the design under test, and the memory barrier controller's release of the memory barrier data block serves as a reference.

[0096] The consumer then sends several random read commands to read data from the specified memory space. At the same time as sending the read commands, the consumer updates its bound memory barrier data block.

[0097] Finally, the user calls the consumer's calibration method to release the consumer's memory barrier data block, causing the producer to wait for the consumer's memory barrier data block to succeed. This allows the producer to continue generating data for the consumer to read.

[0098] This process is repeated several times until the entire process is complete.

[0099] The apparatus provided in the embodiments of this application is described below. The apparatus described below can be referred to in correspondence with the method described above.

[0100] Figure 6 This is a schematic diagram of the asynchronous communication management device provided in this application, as shown below. Figure 6 As shown, the device includes: The counter value modification module 610 is used to modify the instruction counter value and / or data quantity counter value in the memory barrier data block of the asynchronous communication unit based on the instructions sent by the asynchronous communication unit; The status bit modification module 620 is used to modify the status bits in the memory barrier data block of the asynchronous communication unit when the instruction count value and the data count value meet preset conditions. The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

[0101] The asynchronous communication management device provided in this application not only realizes automatic and accurate tracking and management of the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchange between producers and consumers; it also realizes the abstraction of complex count value update and state judgment logic from specific test cases to form a general asynchronous communication management mechanism, which can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

[0102] Figure 7This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 7 As shown, the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communications bus 740, wherein the processor, communications interface, and memory communicate with each other via the communications bus. The processor can invoke logical commands stored in the memory to execute the methods described in the above embodiments, for example: Based on the instructions sent by the asynchronous communication unit, the instruction count and / or data count in the memory barrier data block of the asynchronous communication unit are modified; when the instruction count and data count meet preset conditions, the status bits in the memory barrier data block of the asynchronous communication unit are modified; wherein, the asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

[0103] Furthermore, when the logical commands in the aforementioned memory can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] The processor in the electronic device provided in this application embodiment can call logical instructions in the memory to implement the above method. Its specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effect, which will not be repeated here.

[0105] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the methods provided in the above embodiments.

[0106] The specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effects, so it will not be repeated here.

[0107] This application provides a computer program product, including a computer program that, when executed by a processor, implements the method described above.

[0108] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An asynchronous communication management method, characterized in that, include: Based on the instructions sent by the asynchronous communication unit, the instruction count value and / or data count value in the memory barrier data block of the asynchronous communication unit are modified; If the instruction count value and the data count value meet the preset conditions, the status bit in the memory barrier data block of the asynchronous communication unit is modified; The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

2. The asynchronous communication management method according to claim 1, characterized in that, The method further includes: When the asynchronous communication unit completes the transmission of the specified instruction, in response to the calibration request, the instruction count value and the data volume count value are modified so that the instruction count value and the data volume count value meet the preset conditions.

3. The asynchronous communication management method according to claim 1, characterized in that, The modification of the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on the instructions sent by the asynchronous communication unit includes: When the asynchronous communication unit sends any instruction, the instruction count value is decremented by one, and the data volume count value is modified. The modification value of the data volume count is consistent with the data operation volume of any instruction.

4. The asynchronous communication management method according to claim 1, characterized in that, The initialization operation of the memory barrier data block of the asynchronous communication unit includes: Configure the initial value of the instruction count in the memory barrier data block; Configure the initial value of the data volume count value in the memory barrier data block; Configure the initial values ​​of the status bits in the memory barrier data block.

5. The asynchronous communication management method according to claim 1, characterized in that, The method further includes: If the status bit in the producer's memory barrier data block is modified, the consumer is instructed to wait successfully.

6. The asynchronous communication management method according to claim 1, characterized in that, The method further includes: In the local computing unit, the impact of the producer's data operations on the memory barrier data block in the remote computing unit is recorded, using the consumer's memory barrier data block as a reference. The memory barrier data block in the remote computing unit is calibrated based on the residual value of the consumer's memory barrier data block in the local computing unit; If the consumer waits successfully in the remote computing unit, the local computing unit and the remote computing unit are synchronized.

7. The asynchronous communication management method according to claim 1, characterized in that, The method further includes: In the verification environment, the memory barrier data block of the asynchronous communication unit in the design under test is randomly initialized; the asynchronous communication unit is loaded with specified instructions; the verification environment includes a design verification module and a reference model module of the design under test. By comparing the memory barrier data block in the design verification module with the memory barrier data block in the reference model module, the memory barrier verification result of the design under test is determined.

8. An asynchronous communication management device, characterized in that, include: The counter value modification module is used to modify the instruction counter value and / or data volume counter value in the memory barrier data block of the asynchronous communication unit based on the instructions sent by the asynchronous communication unit; The status bit modification module is used to modify the status bit in the memory barrier data block of the asynchronous communication unit when the instruction count value and the data count value meet preset conditions. The asynchronous communication unit includes a producer and a consumer; the memory barrier data block is bound to the shared memory space corresponding to the asynchronous communication unit.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the asynchronous communication management method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the asynchronous communication management method according to any one of claims 1 to 7.

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