A processor speed reduction tracking debugging method, device, equipment and storage medium

Abstract

This invention discloses a processor speed-down tracing and debugging method, apparatus, device, and storage medium, relating to the field of computer technology and applied to a dual-core processor system. The method includes: caching the processor core's tracing data into a first-in-first-out (FIFO) queue using a data processing component in the system; monitoring the current cached data volume in the FIFO queue using a threshold detection component in the system; if the current cached data volume of a certain queue is not less than a threshold, then sending a speed-down prompt signal to the kernel control component and the corresponding data processing component in the system through the threshold detection component to slow down the corresponding processor core; until the current cached data volume of that queue is less than the threshold, then reverting to the step of caching the tracing data using the data processing component; and transmitting the tracing data in the FIFO queue to a debugger for analysis through an interface controller in the system. This invention improves the precision and debugging capabilities in kernel tracing and debugging.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for processor speed-down tracking and debugging. Background Technology

[0002] As computer systems become increasingly complex, traditional interactive debugging (such as breakpoint debugging) can no longer meet the needs for efficient and comprehensive debugging.

[0003] In existing solutions, dedicated hardware debugging modules are usually integrated inside the CPU (Central Processing Unit), such as Intel's Processor Trace (PT) technology or CoreSight technology in ARM Cortex-M series processors. However, these often put a lot of pressure on data storage, especially in multi-core processor tracing and debugging scenarios, where the large amount of tracing data can also limit the transmission speed.

[0004] It is evident that solving the bottleneck problem of transmission speed caused by the large amount of data traced by multi-core processors, and improving the precision of kernel tracing and debugging, are problems that need to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a processor slowdown tracing and debugging method, apparatus, device, and storage medium, which can solve the bottleneck problem of transmission speed caused by the large amount of multi-core tracing data, and improve the precision of kernel tracing and debugging, thereby enhancing kernel tracing and debugging capabilities. The specific solution is as follows:

[0006] In a first aspect, the present invention provides a processor deceleration tracking and debugging method, applied to a dual-core processor system, comprising:

[0007] After initializing the dual-core processor system, the tracking data of the corresponding processor core is collected by each data processing component in the dual-core processor system, and the tracking data is cached in the local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component;

[0008] The threshold detection component in the dual-core processor system, using the current configuration information, performs threshold monitoring on the current cached data volume of each first-in-first-out queue to determine the current threshold monitoring result; the current configuration information includes the current cache threshold.

[0009] If the current threshold monitoring result indicates that the current cached data amount corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold, then the threshold detection component will send a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system respectively.

[0010] Through the kernel control component and the second data processing component, and by utilizing the received speed-down prompt signal, a preset speed-down mechanism is triggered on the processor core corresponding to the first data processing component.

[0011] Until the current threshold monitoring result indicates that the current cached data amount corresponding to the first data processing component is less than the current cache threshold, the process jumps back to the step of collecting the corresponding processor core trace data through each data processing component in the dual-core processor system.

[0012] The interface controller in the dual-core processor system transmits the cached trace data in the first-in-first-out queue to the debugger for analysis to obtain the analysis results.

[0013] Optionally, the tracking data of the corresponding processor core is collected by each data processing component in the dual-core processor system, and the tracking data is cached in a local first-in-first-out queue, including:

[0014] The first data processing component in the dual-core processor system collects trace data from the first processor core.

[0015] The collected tracking data is cached in the tracking data cache area of ​​the first data processing component's local first-in-first-out queue through the first data processing component;

[0016] The collected tracking data is encoded by the first data processing component and based on the first preset data compression algorithm to determine the first encoded data;

[0017] The first data processing component caches the first encoded data in the encoded data cache area of ​​the first data processing component's local first-in-first-out queue.

[0018] The second data processing component in the dual-core processor system collects tracking data from the second processor core.

[0019] The collected tracking data is cached in the tracking data cache area of ​​the local first-in-first-out queue of the second data processing component through the second data processing component;

[0020] The collected tracking data is encoded using a second data processing component and based on a second preset data compression algorithm to determine the second encoded data.

[0021] The second data processing component caches the second encoded data in the encoded data cache area of ​​the local first-in-first-out queue of the second data processing component.

[0022] Optionally, a threshold detection component in a dual-core processor system, using current configuration information, is used to monitor the current cached data volume of each first-in-first-out queue to determine the current threshold monitoring result, including:

[0023] The threshold detection component in the dual-core processor system, using the threshold monitoring cycle, determines whether the current cached data volume of each first-in-first-out queue is not less than the current cache threshold, thus determining the current threshold monitoring result; the current cache threshold includes several levels of cache thresholds.

[0024] Optionally, processor slowdown tracing and debugging methods also include:

[0025] After initializing the dual-core processor system, a speed-down alarm strategy is determined using a threshold detection component and initial configuration information, including the initial cache threshold.

[0026] The data storage rates of the first and second data processing components are recorded using a threshold detection component.

[0027] The updated cache threshold is obtained by using the threshold detection component and the data storage rate and the initial cache threshold, and then the updated cache threshold is used as the current cache threshold.

[0028] Optionally, through the kernel control component and the second data processing component, and using the received speed-down warning signal, a preset speed-down mechanism is triggered on the processor core corresponding to the first data processing component, including:

[0029] The kernel control component, and by using a preset speed-down mechanism and the received speed-down prompt signal, reduces the operating speed of the processor core corresponding to the first data processing component.

[0030] The second data processing component, using a preset speed-down mechanism and the received speed-down prompt signal, takes over the encoded data buffer area in the first-in-first-out queue of the first data processing component;

[0031] The second data processing component exports the first encoded data from the encoded data buffer.

[0032] Optionally, the first encoded data in the encoded data buffer is exported via the second data processing component, including:

[0033] The second data processing component stores the first encoded data in the encoded data buffer into the random access memory of the dual-core processor system.

[0034] The first encoded data in the random access memory is transmitted to the debugger through the interface manager in the dual-core processor system.

[0035] The debugger decodes and analyzes the first encoded data received to determine the data analysis results.

[0036] Optionally, until the current threshold monitoring result indicates that the current cached data amount corresponding to the first data processing component is less than the current cache threshold, the process jumps back to the step of collecting the corresponding processor core trace data through each data processing component in the dual-core processor system, including:

[0037] Through the monitoring and management interface in the first data processing component, the data increase rate, data transmission rate, expected data increase rate after frequency reduction, and corresponding first-in-first-out queue buffer space remaining of the first data processing component are obtained. The risk assessment of the first-in-first-out queue being full is carried out to determine the current threshold assessment result.

[0038] The current threshold evaluation results are sent to the threshold detection component through the monitoring and management interface;

[0039] The threshold is updated using the threshold detection component and the received threshold evaluation results to obtain the updated current threshold information.

[0040] The threshold detection component is used to determine whether the current cached data volume of the first-in-first-out queue in the first data processing component is not less than the current cache threshold, thereby determining the current threshold monitoring result.

[0041] If the current threshold monitoring result indicates that it is less than a certain value, then the first data processing component will take over the local coded data buffer in the first-in-first-out queue.

[0042] The kernel control component restores the operating speed of the processor core corresponding to the first data processing component.

[0043] Secondly, the present invention provides a processor speed-down tracking and debugging device, applied to a dual-core processor system, comprising:

[0044] The tracking data caching module is used to collect tracking data of the corresponding processor cores through the data processing components in the dual-core processor system after initialization, and cache the tracking data in a local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component.

[0045] The cache level monitoring module is used to monitor the current cache data level of each first-in-first-out queue using the threshold detection component in the dual-core processor system and the current configuration information, so as to determine the current threshold monitoring result; the current configuration information includes the current cache threshold.

[0046] The speed reduction prompt module is used to send a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system through the threshold detection component if the current threshold monitoring result shows that the current cached data volume corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold.

[0047] The speed-down mechanism triggering module is used to trigger a preset speed-down mechanism on the processor core corresponding to the first data processing component through the kernel control component and the second data processing component, and by using the received speed-down prompt signal.

[0048] The step jump module is used to jump back to the step of collecting the tracking data of the corresponding processor core through each data processing component in the dual-core processor system when the current threshold monitoring result shows that the current cache data volume corresponding to the first data processing component is less than the current cache threshold.

[0049] The transmission analysis module is used to transmit the cached trace data in the first-in-first-out queue to the debugger for analysis through the interface controller in the dual-core processor system to obtain the analysis results.

[0050] Thirdly, the present invention provides an electronic device, comprising:

[0051] Memory, used to store computer programs;

[0052] A processor is used to execute computer programs to implement the steps of the aforementioned processor slowdown tracing and debugging method.

[0053] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned processor slowdown tracking and debugging method.

[0054] As can be seen, in this invention, applied to a dual-core processor system, after initializing the dual-core processor system, each data processing component in the dual-core processor system collects the corresponding processor core's tracking data and caches the tracking data in a local first-in-first-out (FIFO) queue. Each data processing component includes a first data processing component and a second data processing component. A threshold detection component in the dual-core processor system, using current configuration information, performs threshold monitoring on the current cached data volume of each FIFO queue to determine the current threshold monitoring result. The current configuration information includes the current cache threshold. If the current threshold monitoring result indicates that the current cached data volume corresponding to the FIFO queue in the first data processing component is not less than the current cache threshold... The threshold detection component sends a speed-down warning signal to the kernel control component and the second data processing component in the dual-core processor system. The kernel control component and the second data processing component, using the received speed-down warning signal, trigger a preset speed-down mechanism on the processor core corresponding to the first data processing component. This continues until the current threshold monitoring result indicates that the current cached data amount corresponding to the first data processing component is less than the current cache threshold. Then, the process jumps back to the step where each data processing component in the dual-core processor system collects the trace data from the corresponding processor core. Finally, the interface controller in the dual-core processor system transmits the cached trace data from the first-in-first-out queue to the debugger for analysis to obtain the analysis results.

[0055] As can be seen from the above technical solution, in this invention, for a dual-core processor system, firstly, after initializing the dual-core processor system, the data processing components in the system collect the tracking data of the corresponding processor cores and cache it in a local first-in-first-out (FIFO) queue. Then, the threshold detection component in the system uses the current cache threshold to monitor the current cached data volume of each FIFO queue to determine the current threshold monitoring result. Next, if the current threshold monitoring result indicates that the current cached data volume corresponding to the first data processing component is not less than the threshold, the threshold detection component sends a speed-down warning signal to the kernel control component and the second data processing component. Then, the kernel control component and the second data processing component use the received speed-down warning signal to trigger a preset speed-down mechanism for the processor core corresponding to the first data processing component. This continues until the current threshold monitoring result indicates that the current cached data volume corresponding to the first data processing component is less than the current cache threshold, at which point the process jumps back to the step of collecting the tracking data of the corresponding processor cores through the data processing components in the system. Finally, the interface controller in the system transmits the cached tracking data in the FIFO queue to the debugger for analysis. This effectively solves the bottleneck problem of transmission speed caused by the large amount of multi-core trace data. While ensuring the integrity and validity of the trace data, it improves the precision of kernel trace debugging, enhances kernel trace debugging capabilities, and increases bus utilization. Attached Figure Description

[0056] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A flowchart of a specific processor deceleration tracking and debugging method provided by the present invention;

[0058] Figure 2 A flowchart of a specific processor deceleration tracking and debugging method provided by the present invention;

[0059] Figure 3 A dual-core processor system framework diagram provided by the present invention;

[0060] Figure 4 A schematic diagram of the structure of a data processing component provided by the present invention;

[0061] Figure 5 A schematic diagram of a processor deceleration tracking and debugging device provided by the present invention;

[0062] Figure 6 This invention provides a structural diagram of an electronic device. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0064] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0065] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] As computer systems become increasingly complex, traditional interactive debugging (such as breakpoint debugging) is no longer sufficient to meet the demands for efficient and comprehensive debugging. Existing solutions typically integrate dedicated hardware debugging modules within the CPU, such as Intel's Processor Trace (PT) technology or CoreSight technology in ARM Cortex-M series processors. However, these solutions often face significant data storage challenges, especially in multi-core processor tracing and debugging scenarios, where the large volume of tracing data can limit transmission speed.

[0067] To address this issue, the present invention provides a processor speed-down tracing and debugging scheme that effectively solves the bottleneck problem caused by the large amount of multi-core tracing data. While ensuring the integrity and validity of the tracing data, it improves the precision of kernel tracing and debugging, enhances kernel tracing and debugging capabilities, and increases bus utilization.

[0068] See Figure 1 As shown, this embodiment of the invention discloses a processor speed-down tracking and debugging method, applied to a dual-core processor system, including:

[0069] Step S11: After initializing the dual-core processor system, the tracking data of the corresponding processor core is collected by each data processing component in the dual-core processor system, and the tracking data is cached in the local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component.

[0070] In this embodiment, combined with Figure 2 As shown, firstly, the system needs to be initialized to... Figure 3 Taking the dual-core processor system shown as an example, this dual-core processor system includes two CPU cores, Core0 (core 0, also known as the first processor core) and Core1 (core 1, also known as the second processor core), data processing components (including the first and second data processing components), threshold detection components, kernel control components, dual-port RAM (Random Access Memory), an interface controller, and a debugger. The functions of each component are as follows:

[0071] (1) Core0 and Core1: CPU cores, used to execute and process instructions and data.

[0072] (2) Data Processing Component: The data processing component is used to collect and compress tracking data. Specifically, the data is encoded into compressed data packets according to the compression algorithm and stored in a FIFO (First In First Out) hardware buffer, awaiting storage in a dual-port random access memory. This component mainly consists of four parts: a data buffer FIFO, a data encoder, a configuration register, and a monitoring and management interface. Their functions are described below:

[0073] 1) Trace data buffer FIFO: used to buffer the data obtained during tracing.

[0074] 2) Encoded Data Buffer FIFO: Used to buffer encoded data. This FIFO can be controlled by other data processing components to output data. When its own core frequency is reduced, another core can control the FIFO to continue outputting data through the data processing component.

[0075] 3) Data encoder: Used to encode the tracking data and package it into standard data packets for transmission.

[0076] 4) Configuration register: Used to configure information such as cache threshold, data encoding format, and checksum.

[0077] 5) Monitoring and Management Interface: Since this solution uses a rate reduction mechanism, the data does not stop immediately after the mechanism is activated, but the data increment decreases. Therefore, the threshold is not based on the FIFO being full, but is evaluated based on factors such as the new data rate, the transmission data rate, the expected rate of new data added due to the rate reduction, and the FIFO margin. The monitoring and management interface will calculate this threshold information and report it to the threshold detection component in real time.

[0078] (3) Threshold detection component: Used to detect the load of the FIFO buffer. If the threshold is reached, a signal will be sent to the kernel control component to remind that the data is full. Multiple threshold levels can be configured (e.g., 75% / 90% / 95%, each level can be configured with a corresponding speed reduction mechanism, which includes but is not limited to the data export rate).

[0079] (4) Kernel control component: used to control the kernel operation and control the kernel to run at a lower frequency according to the threshold prompt signal.

[0080] (5) Dual-port RAM: used to store compressed data blocks and transmit them to external interfaces.

[0081] (6) Interface controller: controls the transmission of RAM data to the external bus.

[0082] (7) Debugger: Responsible for decoding and analyzing compressed data blocks, converting the data back into normal recorded data for extraction and analysis by upper-level software.

[0083] Furthermore, in this embodiment, after system initialization, the tracking function operates normally, namely: the first data processing component in the dual-core processor system collects tracking data from the first processor core; the first data processing component caches the collected tracking data in a tracking data cache area in its local first-in-first-out queue; the first data processing component encodes the collected tracking data based on a first preset data compression algorithm to determine first encoded data; the first data processing component caches the first encoded data in an encoded data cache area in its local first-in-first-out queue; the second data processing component in the dual-core processor system collects tracking data from the second processor core; the second data processing component caches the collected tracking data in a tracking data cache area in its local first-in-first-out queue; the second data processing component encodes the collected tracking data based on a second preset data compression algorithm to determine second encoded data; the second data processing component caches the second encoded data in an encoded data cache area in its local first-in-first-out queue.

[0084] Understandably, after system link initialization, the system is generally in a normal state. Therefore, the Trace function is used, and the two data processing components in the system normally acquire trace data from their respective CPU cores, encode and compress the data into data packets, and store them in a local FIFO hardware buffer for transmission. Each data processing component has its own first-in-first-out queue. Furthermore, the FIFO hardware buffer includes a trace data buffer and an encoded data buffer; the former corresponds to the Trace data buffer FIFO function of the data processing component, and the latter corresponds to the encoded data buffer FIFO function. In addition, the first and second preset data compression algorithms can be configured or adjusted based on actual needs.

[0085] Step S12: Using the threshold detection component in the dual-core processor system and the current configuration information, perform threshold monitoring on the current cached data volume of each first-in-first-out queue to determine the current threshold monitoring result; the current configuration information includes the current cache threshold.

[0086] In this embodiment, combined with Figure 2 As shown, during normal operation of the tracking function, the threshold detection component periodically checks the current cached data volume of the first-in-first-out (FIFO) queue in the data processing component. The current cached data volume refers to the amount of tracking data currently cached in the FIFO queue hardware buffer. Specifically, the threshold detection component in the dual-core processor system, using the threshold monitoring cycle, determines whether the current cached data volume of each FIFO queue is not less than the current cache threshold to determine the current threshold monitoring result. The current cache threshold includes several levels of cache thresholds.

[0087] Understandably, after system link initialization, the threshold detection component imports the strategy based on the initial configuration information, including the initial value of the cache threshold and the initial threshold detection cycle. After the initialization of the threshold detection component is completed, each component in the system begins to work normally. During operation, the threshold detection component records the data storage rate of the data processing component, which is used to update the cache threshold. That is, regarding the current cache threshold in the threshold detection component, in this embodiment: after initializing the dual-core processor system, the threshold detection component, using the initial configuration information, determines the speed-down alarm strategy; the initial configuration information includes the initial cache threshold; the threshold detection component records the data storage rates of the first and second data processing components; the threshold detection component, using the data storage rate and the initial cache threshold, obtains the updated cache threshold, and uses the updated cache threshold as the current cache threshold.

[0088] Step S13: If the current threshold monitoring result indicates that the current cached data volume corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold, then the threshold detection component sends a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system, respectively.

[0089] In this embodiment, combined with Figure 2 As shown, if the current cached data volume in the FIFO queue of the data processing component does not reach the threshold, the current state is maintained, the dual cores operate normally, and the data processing component continues to collect and cache the tracking data of the dual cores. Conversely, if the current cached data volume in the FIFO queue of any core, such as core 0, reaches the threshold, it indicates that core 0 needs to be slowed down. In this case, the threshold detection component, using the current slowdown alarm strategy, sends a slowdown warning signal to the kernel control component and the second data processing component in the dual-core processor system to prompt the activation of the slowdown mechanism corresponding to core 0.

[0090] Understandably, if the current cached data volume of the first-in-first-out queue corresponding to core 1 is detected to reach the threshold, it indicates that core 1 needs to be slowed down. At this time, the threshold detection component, and using the current speed-down alarm strategy, send speed-down prompt signals to the kernel control component and the first data processing component in the dual-core processor system respectively, to prompt the activation of the speed-down mechanism corresponding to core 1.

[0091] Step S14: Through the kernel control component and the second data processing component, and using the received speed-down prompt signal, trigger the preset speed-down mechanism for the processor core corresponding to the first data processing component.

[0092] In this embodiment, combined with Figure 2 As shown, taking core 0 as an example, the kernel control component reduces its frequency, and the second data processing component takes over the encoded data buffer FIFO of the first data processing component to export data. Specifically: the kernel control component, using a preset speed-down mechanism and a received speed-down prompt signal, reduces the operating speed of the processor core corresponding to the first data processing component; the second data processing component, using the preset speed-down mechanism and the received speed-down prompt signal, takes over the encoded data buffer in the first data processing component's FIFO queue; and the second data processing component exports the first encoded data from the encoded data buffer. It can be understood that in this embodiment, after receiving the speed-down prompt signal, the kernel control component reduces the operating speed of core 0 by lowering the frequency to reduce the rate of tracking data generation. The frequency reduction implementation methods include, but are not limited to, common methods such as clock frequency reduction.

[0093] Furthermore, regarding the data export process of the second data processing component, in this embodiment, the second data processing component stores the first encoded data in the encoded data buffer into the random access memory (RAM) of the dual-core processor system; the interface manager of the dual-core processor system transmits the first encoded data in the RAM to the debugger; the debugger decodes and analyzes the received first encoded data to determine the data analysis results. In other words, after receiving the speed-down warning signal, the second data processing component takes over the encoded data buffer FIFO of the first data processing component. At this time, the encoded data buffer FIFO data is exported at full frequency, while the trace data of core 0 is stored in the Trace data buffer FIFO at a lower frequency. This means that the amount of cached data in the encoded data buffer of the first data processing component decreases, and the amount of new data in the trace data buffer decreases, thus reducing the amount of new data in the encoded data buffer. Therefore, the current cached data amount in the first data processing component's first-in-first-out queue will continue to decrease.

[0094] In this way, by implementing a detection and scheduling mechanism to schedule large amounts of tracking information, the integrity and effectiveness of the tracking information are guaranteed, the bus utilization is improved, the problem of transmission bottleneck caused by large amounts of multi-core trace data is solved, the precision of kernel tracing and debugging is improved, and the kernel tracing and debugging capabilities are enhanced.

[0095] Step S15: When the current threshold monitoring result indicates that the current cached data amount corresponding to the first data processing component is less than the current cache threshold, the process jumps back to the step of collecting the corresponding processor core tracking data through each data processing component in the dual-core processor system.

[0096] In this embodiment, combined with Figure 2As shown, when the amount of cached data in the FIFO queue drops below a threshold, the first data processing component takes over its own encoded data cache FIFO, the kernel control component restores the core 0 frequency, and the dual-core system resumes normal operation. Specifically, through the monitoring and management interface in the first data processing component, the data increase rate, data transfer rate, expected data increase rate after frequency reduction, and the corresponding FIFO queue cache space remaining are obtained to perform a FIFO queue full risk assessment to determine the current threshold assessment result. The current threshold assessment result is sent to the threshold detection component through the monitoring and management interface. The threshold is updated through the threshold detection component and the received threshold assessment result to obtain the updated current threshold information. The threshold detection component, using the threshold monitoring cycle, determines whether the current cached data amount in the FIFO queue of the first data processing component is not less than the current cache threshold to determine the current threshold monitoring result. If the current threshold monitoring result indicates that it is less than the threshold, the first data processing component takes over the encoded data cache area in its local FIFO queue. The kernel control component restores the operating speed of the processor core corresponding to the first data processing component.

[0097] It is important to understand that, as the rate of new data and the remaining capacity of the first-in-first-out queue decrease during the activation of the rate reduction mechanism, the cache threshold also changes. Therefore, during this process, when determining whether the current cached data volume corresponding to the first-in-first-out queue of the first data processing component has reached the current cache threshold, the current cache threshold used may be the threshold updated in real time.

[0098] Step S16: The cached trace data in the first-in-first-out queue is transmitted to the debugger for analysis through the interface controller in the dual-core processor system to obtain the analysis results.

[0099] In this embodiment, combined with Figure 3 As shown, similar to the aforementioned data export, when needed, the cached encoded data corresponding to the first-in-first-out queue in each data processing component is stored in a dual-port random access memory. Then, the interface controller transmits the encoded data in the dual-port random access memory to the debugger. After that, the debugger decodes and analyzes the received encoded data to convert it back into normal recorded data for extraction and analysis by the upper-layer software.

[0100] Furthermore, it should be understood that, in addition to solving the problem of two-core processor systems, the implementation logic of the solution proposed in this embodiment can also solve the problem of multi-core processor systems such as three-core and four-core. The core of the solution lies in monitoring the amount of cached data in the queue through the threshold detection component, and when necessary, for a target processor core whose first-in-first-out queue is about to be full, the kernel control component and several other processor cores whose first-in-first-out queues are not about to be full, the speed-down mechanism for the target processor core is enabled.

[0101] Therefore, in this embodiment of the invention, for a dual-core processor system, firstly, after initializing the dual-core processor system, each data processing component in the system collects the tracking data of the corresponding processor core and caches it in a local first-in-first-out (FIFO) queue. Then, a threshold detection component in the system, using the current cache threshold, monitors the current cached data volume of each FIFO queue to determine the current threshold monitoring result. If the current threshold monitoring result indicates that the current cached data volume corresponding to the first data processing component is not less than the threshold, a speed-down warning signal is sent to the kernel control component and the second data processing component through the threshold detection component. Then, the kernel control component and the second data processing component, using the received speed-down warning signal, trigger a preset speed-down mechanism for the processor core corresponding to the first data processing component. This continues until the current threshold monitoring result indicates that the current cached data volume corresponding to the first data processing component is less than the current cache threshold, at which point the process jumps back to the step of collecting the tracking data of the corresponding processor core through each data processing component in the system. Finally, the interface controller in the system transmits the cached tracking data in the FIFO queue to the debugger for analysis. This effectively solves the bottleneck problem of transmission speed caused by the large amount of multi-core trace data. While ensuring the integrity and validity of the trace data, it improves the precision of kernel trace debugging, enhances kernel trace debugging capabilities, and increases bus utilization.

[0102] As a preferred embodiment, for scenarios with large amounts of tracking data, intelligent cache management and data preprocessing components can be added to the processor system. These components involve a multi-level cache architecture and an adaptive cache management algorithm. The multi-level cache architecture can include: Level 1 cache: a small-capacity FIFO queue for each core; Level 2 cache: a shared medium-capacity circular buffer; and Level 3 cache: a shared large-capacity compressed buffer. The adaptive cache management algorithm can include: LRU (Least Recently Used)-based retention of hot data, hierarchical storage of data based on importance, and dynamic data eviction policies. In this way, intelligent cache management avoids data loss due to FIFO overflow, thus preventing disruption to debugging integrity.

[0103] See Figure 5 As shown, this embodiment of the invention also discloses a processor speed-down tracking and debugging device, applied to a dual-core processor system, comprising:

[0104] The tracking data caching module 11 is used to collect the tracking data of the corresponding processor core through each data processing component in the dual-core processor system after initialization of the dual-core processor system, and cache the tracking data in a local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component.

[0105] The cache monitoring module 12 is used to monitor the current cache data volume of each first-in-first-out queue using the threshold detection component in the dual-core processor system and the current configuration information, so as to determine the current threshold monitoring result; the current configuration information includes the current cache threshold.

[0106] The speed reduction prompt module 13 is used to send a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system respectively through the threshold detection component if the current threshold monitoring result shows that the current cached data volume corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold.

[0107] The speed reduction mechanism triggering module 14 is used to trigger a preset speed reduction mechanism for the processor core corresponding to the first data processing component through the kernel control component and the second data processing component, and by using the received speed reduction prompt signal.

[0108] The step jump module 15 is used to jump back to the step of collecting the tracking data of the corresponding processor core through each data processing component in the dual-core processor system when the current threshold monitoring result shows that the current cache data volume corresponding to the first data processing component is less than the current cache threshold.

[0109] The transmission analysis module 16 is used to transmit the cached trace data in the first-in-first-out queue to the debugger for analysis through the interface controller in the dual-core processor system to obtain the analysis results.

[0110] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0111] Furthermore, embodiments of the present invention also disclose an electronic device, Figure 6This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the processor speed-down tracking and debugging method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0112] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0113] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0114] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the processor slowdown tracking and debugging method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0115] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned processor slowdown tracking and debugging method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0116] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned processor slowdown tracking and debugging method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0117] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0118] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0119] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0120] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0121] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A processor speed-down tracking and debugging method, characterized in that, Applied to dual-core processor systems, including: After initializing the dual-core processor system, the tracking data of the corresponding processor core is collected by each data processing component in the dual-core processor system, and the tracking data is cached in a local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component; The threshold detection component in the dual-core processor system, using the current configuration information, performs threshold monitoring on the current cached data volume of each of the first-in-first-out queues to determine the current threshold monitoring result; the current configuration information includes the current cache threshold. If the current threshold monitoring result indicates that the current cached data volume corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold, then the threshold detection component sends a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system, respectively. Through the kernel control component and the second data processing component, and using the received speed-down prompt signal, a preset speed-down mechanism is triggered on the processor core corresponding to the first data processing component; Until the current threshold monitoring result indicates that the current cached data volume corresponding to the first data processing component is less than the current cache threshold, the process jumps back to the step of collecting the tracking data of the corresponding processor core through each data processing component in the dual-core processor system. The interface controller in the dual-core processor system transmits the cached trace data in the first-in-first-out queue to the debugger for analysis to obtain the analysis results.

2. The processor speed-down tracking and debugging method according to claim 1, characterized in that, The step of collecting tracking data from the corresponding processor cores through each data processing component in the dual-core processor system and caching the tracking data in a local first-in-first-out queue includes: The first data processing component in the dual-core processor system collects tracking data from the first processor core. The collected tracking data is cached in the tracking data cache area of ​​the first data processing component's local first-in-first-out queue through the first data processing component; The first data processing component encodes the collected tracking data based on the first preset data compression algorithm to determine the first encoded data. The first data processing component caches the first encoded data in the encoded data cache area of ​​the first data processing component's local first-in-first-out queue. The tracking data of the second processor core is collected by the second data processing component in the dual-core processor system; The collected tracking data is cached in the tracking data cache area of ​​the first-in-first-out queue on the local side of the second data processing component by the second data processing component. The collected tracking data is encoded using the second data processing component and based on a second preset data compression algorithm to determine the second encoded data. The second data processing component caches the second encoded data in the encoded data cache area of ​​the first-in-first-out queue on the local side of the second data processing component.

3. The processor speed-down tracking and debugging method according to claim 1, characterized in that, The step of using the threshold detection component in the dual-core processor system and utilizing the current configuration information to perform threshold monitoring on the current cached data volume of each of the first-in-first-out queues to determine the current threshold monitoring result includes: The threshold detection component in the dual-core processor system, using a threshold monitoring cycle, determines whether the current cached data volume of each first-in-first-out queue is not less than the current cache threshold, thereby determining the current threshold monitoring result; the current cache threshold includes several levels of cache thresholds.

4. The processor deceleration tracking debugging method according to any one of claims 1 to 3, characterized in that, Also includes: After initializing the dual-core processor system, a speed-down alarm strategy is determined using the threshold detection component and the initial configuration information. The initial configuration information includes an initial cache threshold; The threshold detection component records the data storage rates of the first data processing component and the second data processing component. The updated cache threshold is obtained by using the threshold detection component and the data storage rate and the initial cache threshold, and the updated cache threshold is used as the current cache threshold.

5. The processor speed-down tracking and debugging method according to claim 2, characterized in that, The step of triggering a preset speed-down mechanism on the processor core corresponding to the first data processing component through the kernel control component and the second data processing component, and using the received speed-down prompt signal, includes: The kernel control component, using a preset speed-down mechanism and the received speed-down prompt signal, reduces the operating speed of the processor core corresponding to the first data processing component. The second data processing component, using the preset speed reduction mechanism and the received speed reduction prompt signal, takes over the encoded data buffer area in the first-in-first-out queue of the first data processing component; The first encoded data in the encoded data buffer is exported using the second data processing component.

6. The processor speed-down tracking and debugging method according to claim 5, characterized in that, The step of exporting the first encoded data from the encoded data buffer using the second data processing component includes: The second data processing component stores the first encoded data in the encoded data buffer into the random access memory of the dual-core processor system. The first encoded data in the random access memory is transmitted to the debugger through the interface manager in the dual-core processor system; The debugger is used to decode and analyze the received first encoded data to determine the data analysis results.

7. The processor speed-down tracking and debugging method according to claim 5, characterized in that, The step of re-jumping to the step of collecting tracking data from the corresponding processor cores through each data processing component in the dual-core processor system when the current threshold monitoring result indicates that the current cached data amount corresponding to the first data processing component is less than the current cache threshold includes: Through the monitoring and management interface in the first data processing component, the data increase rate, data transmission rate, expected data increase rate after frequency reduction and the corresponding first-in-first-out queue buffer space remaining of the first data processing component are obtained, and the risk assessment of the first-in-first-out queue being full is carried out to determine the current threshold assessment result. The current threshold evaluation result is sent to the threshold detection component through the monitoring and management interface. The threshold is updated using the threshold detection component and the received threshold evaluation result to obtain the updated current threshold information. The threshold detection component, using the threshold monitoring cycle, determines whether the current cached data volume of the first-in-first-out queue in the first data processing component is not less than the current cache threshold, thereby determining the current threshold monitoring result. If the current threshold monitoring result indicates that it is less than a certain value, then the first data processing component will take over the local coded data buffer in the first-in-first-out queue. The kernel control component restores the operating speed of the processor core corresponding to the first data processing component.

8. A processor deceleration tracking and debugging device, characterized in that, Applied to dual-core processor systems, including: The tracking data caching module is used to collect tracking data of the corresponding processor cores through each data processing component in the dual-core processor system after initialization, and cache the tracking data in a local first-in-first-out queue; wherein, each data processing component includes a first data processing component and a second data processing component. The cache volume monitoring module is used to perform threshold monitoring on the current cache data volume of each of the first-in-first-out queues using the threshold detection component in the dual-core processor system and the current configuration information, so as to determine the current threshold monitoring result; the current configuration information includes the current cache threshold. The speed reduction prompt module is used to send a speed reduction prompt signal to the kernel control component and the second data processing component in the dual-core processor system respectively through the threshold detection component if the current threshold monitoring result shows that the current cached data volume corresponding to the first-in-first-out queue in the first data processing component is not less than the current cache threshold. The speed-down mechanism triggering module is used to trigger a preset speed-down mechanism on the processor core corresponding to the first data processing component through the kernel control component and the second data processing component, and by using the received speed-down prompt signal. The step jump module is used to jump back to the step of collecting the tracking data of the corresponding processor core through each data processing component in the dual-core processor system when the current threshold monitoring result shows that the current cache data volume corresponding to the first data processing component is less than the current cache threshold. The transmission analysis module is used to transmit the cached trace data in the first-in-first-out queue to the debugger for analysis through the interface controller in the dual-core processor system to obtain the analysis results.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the processor slowdown tracking debugging method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the processor slowdown tracking and debugging method as described in any one of claims 1 to 7.

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