An in-band interrupt system, method, electronic device, and storage medium

Abstract

This invention relates to the field of computer technology and discloses an in-band interrupt system, method, electronic device, and storage medium. By having the host end enter an interrupt waiting mode after completing a task in high-speed read / write mode, the slave end takes over the data read / write channel and sends an in-band interrupt command to the host end. Upon receiving an in-band interrupt command from any slave end, the host end does not need to exit the current high-speed read / write mode but directly responds to the in-band interrupt command. Based on the target slave end represented by the in-band interrupt command, the host end retrieves the data to be read from the target slave end in high-speed read / write mode. By inserting an interrupt waiting mode after the task is completed in high-speed read / write mode, the host end can directly respond to the in-band interrupt command sent by the slave end in high-speed read / write mode, avoiding the communication complexity caused by "exit-processing-re-entering" and improving communication efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to an in-band interrupt system, method, electronic device, and storage medium. Background Technology

[0002] Under the Improved Inter-Integrated Circuit (I3C) protocol, when an emergency event occurs in the slave device, it can send an in-band interrupt request to the master controller via the bus. The interrupt mechanism of the I3C protocol only exists in SDR mode, meaning that in-band interrupt requests sent by the slave device can only be responded to in SDR mode.

[0003] In related technologies, if a slave device initiates an in-band interrupt request and requests to read data at a higher data rate (High Data Rate - Double Data Rate, or HDR-DDR) mode, the master controller needs to first exit from HDR-DDR mode to Single Data Rate (SDR mode) mode to respond to the slave device's in-band interrupt request, and then enter HDR-DDR mode to read data. This "exit-process-re-enter" process increases the complexity of communication and reduces communication efficiency. Summary of the Invention

[0004] This application provides an in-band interrupt system, method, electronic device, and storage medium to at least solve the problem in the related art of being unable to respond to in-band requests from slave devices in HDR-DDR mode.

[0005] This application provides an in-band interrupt system, including: a master unit and multiple slave units, wherein the master unit and the slave units are connected through a data read / write channel;

[0006] The host is used to enter interrupt wait mode after the task in high-speed read / write mode is completed; The slave device is used to take over the data read / write channel when the master device is in interrupt waiting mode, so as to send in-band interrupt commands to the master device through the data read / write channel; the slave device stores the data to be read. The host is also used to enter high-speed read / write mode in response to receiving an in-band interrupt command from any slave, and to retrieve the data to be read from the target slave according to the target slave represented by the in-band interrupt command.

[0007] This application also provides an in-band interrupt method, applied to the host side of any of the above-mentioned in-band interrupt systems, the method comprising: Upon completion of a task in high-speed read / write mode, the system enters interrupt wait mode. In interrupt waiting mode, the slave device acquires the in-band interrupt command sent by the slave device. In interrupt waiting mode, the slave device takes over the data read / write channel to send the in-band interrupt command to the master device through the data read / write channel. The slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel. Based on the target slave device represented by the in-band interrupt command, retrieve the data to be read from the target slave device.

[0008] This application also provides an in-band interrupt device, applied to the host side of any of the above-mentioned in-band interrupt systems, the device comprising: The interrupt wait module is used to enter interrupt wait mode when a task in high-speed read / write mode is completed; The first acquisition module is used to acquire in-band interrupt commands sent by the slave device in interrupt waiting mode. The slave device takes over the data read / write channel when the master device is in interrupt waiting mode, so as to send in-band interrupt commands to the master device through the data read / write channel. The slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel. The second acquisition module is used to acquire the data to be read from the target slave device according to the target slave device represented by the in-band interrupt command.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described in-band interrupt methods when executing the computer program.

[0010] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described in-band interrupt methods.

[0011] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described in-band interrupt methods.

[0012] By incorporating this application, when the host device completes a task in high-speed read / write mode, it enters an interrupt waiting mode. In this mode, the slave device takes over the data read / write channel and sends an in-band interrupt command to the host device. Upon receiving an in-band interrupt command from any slave device, the host device does not need to exit the current high-speed read / write mode but directly responds to the in-band interrupt command. Based on the target slave device represented by the in-band interrupt command, the host device retrieves the data to be read from the target slave device in high-speed read / write mode. By inserting an interrupt waiting mode after the task is completed in high-speed read / write mode, the host device can directly respond to the in-band interrupt command sent by the slave device in high-speed read / write mode, avoiding the communication complexity caused by "exit-processing-re-entry" and improving communication efficiency. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the interaction flow of an in-band interrupt system provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the structure of an exemplary in-band interrupt command provided in an embodiment of this application; Figure 3 A timing diagram illustrating an exemplary interrupt waiting mode provided for embodiments of this application; Figure 4 A schematic diagram illustrating the timing connection between an exemplary interrupt waiting mode and an in-band interrupt command, provided for embodiments of this application; Figure 5 A schematic flowchart of an exemplary in-band interrupt protocol in SDR mode provided for embodiments of this application; Figure 6 A schematic flowchart of an exemplary in-band interrupt protocol in HDR-DDR mode provided for embodiments of this application; Figure 7 A flowchart illustrating an exemplary in-band interrupt method in HDR-DDR mode provided in this application embodiment; Figure 8 A flowchart illustrating an in-band interrupt method provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an in-band interrupt device provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] The I3C protocol is a next-generation bus protocol that addresses the limitations of traditional I2C and SPI protocols in mobile devices, sensors, and embedded systems, improving performance, reducing power consumption, and enhancing scalability. I3C supports higher transmission rates, 12.5 Mbps in default SDR mode and up to 25 Mbps or even higher in HDR mode, far exceeding the maximum of 3.4 Mbps for the I2C protocol. It also supports dynamic address allocation, multi-master control, hot-joining, and in-band interrupt (IBI) mechanisms, simplifying device management and allowing slave devices to initiate communication, reducing the overhead of master polling. I3C's in-band interrupt mechanism does not require an additional interrupt line; interrupt requests are transmitted via the bus, significantly reducing system complexity. Requests are initiated by the slave device, avoiding frequent master polling. However, in the I3C protocol, the IBI interrupt mechanism only exists in the default SDR mode. If the master controller is in HDR-DDR mode at this time, it will not respond to the slave's in-band interrupt request; it can only be processed after exiting SDR mode. In related technologies, if a slave device initiates an in-band interrupt request and requests data to be read in a higher-speed HDR-DDR mode, the master controller needs to first exit from HDR-DDR mode to SDR mode, respond to the slave device's in-band interrupt request, and then enter HDR-DDR mode to read data. The "exit-process-re-enter" process increases the complexity of communication and reduces the efficiency of communication.

[0018] To address the aforementioned technical problems, this application provides an in-band interrupt system, method, electronic device, and storage medium. In this in-band interrupt system, upon completion of a task in high-speed read / write mode, the host enters an interrupt waiting mode. In this mode, the slave takes over the data read / write channel and sends an in-band interrupt command to the host. Upon receiving an in-band interrupt command from any slave, the host does not need to exit the current high-speed read / write mode but directly responds to the in-band interrupt command. Based on the target slave represented by the in-band interrupt command, the host retrieves the data to be read from the target slave in high-speed read / write mode. By inserting an interrupt waiting mode after the task is completed in high-speed read / write mode, the host can directly respond to the in-band interrupt command sent by the slave in high-speed read / write mode, avoiding the communication complexity caused by "exit-processing-re-entering" and improving communication efficiency.

[0019] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] This application provides an in-band interrupt system for responding to in-band interrupt commands sent by the slave device in HDR-DDR mode. This avoids exiting to SDR mode to respond and then re-entering HDR-DDR mode, reducing communication complexity and improving communication efficiency.

[0021] like Figure 1 The diagram shown is an interactive flow diagram of an in-band interrupt system provided in an embodiment of this application. The system includes a host terminal and multiple slave terminals, which are connected to each other through a data read / write channel. The host side is used to enter the interrupt waiting mode when the task in the high-speed read / write mode is completed; The slave device is used to take over the data read / write channel when the master device is in interrupt waiting mode, so as to send in-band interrupt commands to the master device through the data read / write channel; the slave device stores the data to be read. The host is also used to enter high-speed read / write mode in response to receiving an in-band interrupt command from any slave, and to retrieve the data to be read from the target slave according to the target slave represented by the in-band interrupt command.

[0022] Specifically, the host can be a master controller. In the I3C protocol, the high-speed read / write mode is HDR-DDR mode. After the host completes the read / write in HDR-DDR mode, it enters the interrupt wait mode, i.e., HDR Interrupt Pattern, which provides a specific opportunity for the slave to send an in-band interrupt. During this specific time, the slave takes over the data read / write channel, i.e., the serial data line (SDA). The host provides the serial clock line (SCL). The slave sends an in-band interrupt command to the host through the data read / write channel. The host responds to the in-band interrupt command, enters the high-speed read / write mode, and, according to the target slave represented by the in-band interrupt command, directly and quickly reads the data to be read from the target slave in the current HDR-DDR mode.

[0023] Correspondingly, by inserting an interrupt waiting mode after the task is completed in high-speed read / write mode, the host can directly respond to the in-band interrupt command sent by the slave in high-speed read / write mode. This avoids the host having to exit to SDR mode to respond to the command after receiving the in-band interrupt command from the slave before entering high-speed read / write mode to acquire the data to be read, thus reducing the complexity of communication and improving the efficiency of communication.

[0024] For example, such as Figure 2The diagram shown is an exemplary structural diagram of an in-band interrupt command provided in an embodiment of this application. The in-band interrupt command sent by the slave device is usually an in-band interrupt message. The in-band interrupt information (In-Band InterruptInformation, abbreviated as IBI Info) is created according to the message format in HDR-DDR mode, including interrupt command information (HDR-DDR Interrupt CMD), interrupt data information (HDR-DDR Interrupt Data), and interrupt verification information (HDR-DDR CRC). HDR-DDR Interrupt CMD starts with 2'b01, followed by 16 bits of data, including RnW, which is usually fixed to 1 to indicate read. The 7-bit command opcode (CMD Code) is ignored in the in-band interrupt. The 7-bit Address is the address of the target slave device, and Parity is the priority label of the slave device. HDR-DDR Interrupt Data begins with 2'b10, followed by a 16-bit Mandatory Data Byte (MDB) indicating the interrupt cause. This includes data to be read, indicating that access to the data stored on the slave device is permitted, and non-data to be read information, such as error messages and alarm messages. If the master controller rejects the slave device's in-band interrupt command, the master will respond with 2'b11 after HDR-DDR Interrupt CMD, requiring the slave device to retransmit at a later time. HDR-DDR CRC is calculated at the end of the message and processed according to the HDR-DDR mode standard.

[0025] For example, such as Figure 3 The diagram shown illustrates the timing of an exemplary interrupt wait mode provided in this application embodiment. In interrupt wait mode, both the data read / write channel and the SCL clock are controlled by the host. Upon entering interrupt wait mode, SDA starts at a high level, and SCL starts at a low level. The SDA signal switches six times: low, high, low, high, low, high, unlike the restart signal which only switches the same first four times, and also unlike the high-speed read / write exit mode. The signal ends with a falling edge. After receiving the SDA signal, the slave device sends an in-band interrupt command to the host. The SCL clock remains low throughout the SDA switching process, with the final valid edge being a rising edge, completing the entire pulse and providing the clock for subsequent in-band interrupts sent by the slave device.

[0026] Correspondingly, in high-speed read / write mode, the master device indicates to the slave device that it is currently in interrupt waiting mode through a special SDA signal. When the slave device detects this signal, it can send an in-band interrupt command to the master device through the data read / write channel, thereby enabling the master device to respond to the slave device's in-band interrupt command in high-speed read / write mode.

[0027] For example, such as Figure 4 The diagram illustrates the timing connection between an exemplary interrupt wait mode and an in-band interrupt command provided in this application embodiment. The master continuously provides SCL clock support after entering interrupt wait mode. After recognizing the interrupt wait mode signal sent by the master, the slave determines that the master has entered interrupt wait mode, takes over the SDA line, and sends an in-band interrupt command to the master. The in-band interrupt information of the in-band interrupt command is in HDR-DDR mode format. The slave first sends preamble bits (PRE) in HDR-DDR mode, including PRE1 and PRE0. Data is read on the rising edge of the SCL clock; therefore, PRE1 corresponds to the first double data rate clock edge (First DDR Edge), and PRE0 corresponds to the second double data rate clock edge (Second DDR Edge). PRE1 and PRE0 are fixed at 2'b01. Then, the specific content of the HDR-DDR Interrupt CMD and IBI Info is sent.

[0028] Based on the above embodiments, as an implementable approach, in one embodiment, the host end is specifically configured to: upon receiving an in-band interrupt command from any slave end, parse the in-band interrupt command for in-band interrupt information; if the in-band interrupt information indicates that the data to be read stored on the slave end is accessible, trigger a restart command to enter high-speed read / write mode by responding to the restart command; determine the target slave end based on the address information represented by the in-band interrupt information; generate a corresponding data access command based on the target slave end; take over the data read / write channel, and in response to the data access command, obtain the data to be read from the target slave end; if the data access command is successfully responded to, re-enter the interrupt waiting mode.

[0029] Specifically, after the current read or write task in HDR-DDR mode is completed, the master controller directly enters the in-band interrupt mode, receives the in-band interrupt command sent by the slave device, parses the received in-band interrupt command to obtain the in-band interrupt information in the in-band interrupt command. When the interrupt reason represented by the in-band interrupt information is Pending ReadNotification, it indicates that the data to be read stored in the slave device is accessible. Then the master triggers a restart command, i.e., HDRRestart Pattern. By responding to the restart command, the master enters the high-speed read / write mode. Based on the address information carried by the in-band interrupt information, the master determines the target slave device, which is the slave device corresponding to the responded in-band interrupt command. The master generates the corresponding data access command based on the target slave device, including HDR-DDR CMD, HDR-DDR Data, and HDR-DDR CRC. The master takes over the data read / write channel, responds to the data access command, and obtains the data to be read from the target slave device. If the data access command is successfully responded to, the master re-enters the interrupt wait mode.

[0030] Correspondingly, compared to exiting high-speed read / write mode and then responding to in-band interrupt commands, the restart command enables the host to generate corresponding data access commands based on in-band interrupt commands while still in high-speed read / write mode, and directly execute the corresponding data access operations in high-speed read / write mode, thereby improving communication efficiency.

[0031] Specifically, in one embodiment, the host is further configured to enter a high-speed read / write exit mode when the in-band interrupt information indicates that the data to be read stored on the slave is not allowed to be accessed.

[0032] Specifically, if the interrupt cause represented in the in-band interrupt information is a non-data to be read information, such as error information or alarm information, it indicates that the data to be read stored on the slave is not allowed to be accessed. In this case, the host enters the high-speed read / write exit mode, i.e., HDR Exit Pattern, which causes the data to exit the HDR-DDR mode and enter the SDR mode.

[0033] Specifically, in one embodiment, the host is also configured to re-enter high-speed read / write mode to respond to data access commands again if the data access command response fails.

[0034] Specifically, if the data access command fails to respond, the host detects that the read / write task corresponding to the current data access command has not been completed. In this case, the host triggers a restart command, i.e., HDR Restart Pattern. By responding to the restart command, the host enters high-speed read / write mode, responds to the data access command again, and executes the corresponding read / write task again.

[0035] Correspondingly, by restarting the command, even if the data access command fails, it can be responded to again in high-speed read / write mode, avoiding frequent and time-consuming mode switching caused by minor errors.

[0036] Based on the above embodiments, as an implementable approach, in one embodiment, the host end is specifically configured to: when receiving multiple in-band interrupt commands sent by multiple slave ends, select a target in-band interrupt command from among the multiple in-band interrupt commands according to the priority tag represented by the in-band interrupt information of each in-band interrupt command; and determine the target slave according to the address information represented by the in-band interrupt information of the target in-band interrupt command.

[0037] Specifically, when processing interrupts sent by multiple slave devices in HDR-DDR mode, an address arbitration method is adopted. The priority label in the in-band interrupt information determines the priority selection of the target in-band interrupt command, and the interrupt is executed on the target slave device corresponding to the target in-band interrupt command. The slave devices that are not selected wait and send the in-band interrupt command again.

[0038] Correspondingly, by setting different priority labels for different in-band interrupt commands, bus conflicts and signal chaos caused by multiple slave devices sending in-band interrupt commands are avoided, allowing in-band interrupt commands to be processed in an orderly manner. At the same time, the priority labels enable important in-band interrupt commands to be responded to more quickly.

[0039] Specifically, in one embodiment, the host is further configured to enter a high-speed read / write exit mode if it does not receive an in-band interrupt command from any slave within a preset waiting time threshold in the interrupt waiting mode.

[0040] Specifically, when the host is in interrupt waiting mode, if no in-band interrupt command is received from any slave device within the preset waiting time, that is, if the host's waiting time exceeds the preset waiting time threshold, and no in-band interrupt is generated, the host enters the high-speed read / write exit mode, i.e., HDR Exit Pattern, so that the data exits the HDR-DDR mode and enters the SDR mode.

[0041] Correspondingly, by setting a preset waiting time threshold, the host is prevented from waiting indefinitely, thus avoiding resource blockage.

[0042] For example, such as Figure 5The diagram shows a flowchart of an in-band interrupt protocol in exemplary SDR mode provided in this application embodiment. S or Sr is the communication start signal. The host first sends a broadcast address (7'h7E) on the bus and receives an acknowledgment (ACK). Then, it sends the Enter HDR-DDR CCC command to enter high-speed read / write mode. T is the verification information. Then, it executes the data access command, including sending HDR-DDR CMD to specify the operation type and target, transmitting the actual data through HDR-DDR Data, and finally verifying the data through HDR-DDR CRC to determine whether the current task is completed. If it is not completed, a restart signal is triggered, and the data access command is executed again. If the task is completed, if an in-band interrupt command is received from the slave, it enters the high-speed read / write exit mode, exits the HDR-DDR mode, and enters the SDR mode to respond to the in-band interrupt command sent by the slave.

[0043] For example, such as Figure 6 The diagram illustrates an exemplary in-band interrupt protocol in HDR-DDR mode provided in this application embodiment. S or Sr represents the communication start signal. The host first sends a broadcast address on the bus and receives an ACK, then sends the Enter HDR-DDR CCC command to enter high-speed read / write mode. T represents verification information. Next, it executes a data access command, including sending HDR-DDR CMD to specify the operation type and target, transmitting actual data via HDR-DDR Data, and finally verifying the data using HDR-DDR CRC to determine if the current task is complete. If not, a restart signal is triggered, and the data access command is executed again. If the task is complete, it enters an interrupt waiting mode. If an in-band interrupt command is received from the slave, including HDR-DDR Interrupt CMD, HDR-DDR Interrupt Data, and HDR-DDR Interrupt... CRC is used to parse in-band interrupt commands and obtain in-band interrupt information. When the interrupt cause in the in-band interrupt information is data to be read, a restart command is triggered, entering high-speed read / write mode. A corresponding data access command is generated and executed. The success of the task is checked; if it fails, a restart command is triggered again to respond to the data access command and execute the corresponding task. If successful, it enters interrupt waiting mode, waiting for in-band interrupt commands from other slave devices. If no in-band interrupt command is received from a slave device during interrupt waiting mode, it enters high-speed read / write exit mode, exiting HDR-DDR mode and entering SDR mode. If the interrupt cause in the in-band interrupt information is not data to be read, it also enters high-speed read / write exit mode.

[0044] For example, such as Figure 7The diagram illustrates an exemplary in-band interrupt method in HDR-DDR mode provided in this application embodiment. The host enters HDR-DDR mode and performs the current read / write task. It periodically checks whether the current read / write task is completed. If the task is completed, it enters interrupt waiting mode and determines whether the slave device has an in-band interrupt command. If it does, the slave device takes over the data read / write channel and sends an in-band interrupt command to the host. After receiving the in-band interrupt command from the slave device, the host parses the in-band interrupt command to obtain in-band interrupt information. It determines whether the interrupt reason in the in-band interrupt information is data to be read. If it indicates that the data to be read stored on the slave device is accessible, a restart command is triggered to enter high-speed read / write mode by responding to the restart command. Based on the address information represented by the in-band interrupt information, the target slave device is determined. Based on the target slave device, a corresponding data access command is generated. The host takes over the data read / write channel and, in response to the data access command, obtains the data to be read from the target slave device. If the data access command response fails, a restart command is triggered to enter high-speed read / write mode and respond to the data access command again. If the interrupt cause in the in-band interrupt information is not data to be read, then enter the high-speed read / write exit mode, exit the HDR-DDR mode, and enter the SDR mode. If the host does not receive an in-band interrupt command from the slave in the interrupt waiting mode, then enter the high-speed read / write exit mode, exit the HDR-DDR mode, and enter the SDR mode.

[0045] Specifically, in one embodiment, a counter is added to increment the counter by 1 after a restart command is triggered when a data access command response failure is detected. The counter represents the number of times the same data access command is executed. If the number of times the same data access command is executed exceeds a preset restart threshold, it is determined that the command cannot be executed and enters a high-speed read / write exit mode. By setting a counter to count the number of times the same data access command is executed, the waste of resources caused by repeated execution when encountering unrepairable faults is avoided.

[0046] The in-band interrupt system provided in this application includes a master unit and multiple slave units, which are connected via a data read / write channel. The master unit is used to enter an interrupt waiting mode after the task in the high-speed read / write mode is completed. The slave units are used to take over the data read / write channel when the master unit is in the interrupt waiting mode, so as to send an in-band interrupt command to the master unit through the data read / write channel. The slave units store the data to be read. The master unit is also used to enter the high-speed read / write mode in response to the in-band interrupt command when it receives an in-band interrupt command from any slave unit, and to obtain the data to be read from the target slave unit according to the target slave unit represented by the in-band interrupt command. The method provided by the above scheme allows the host to enter an interrupt waiting mode after completing a task in high-speed read / write mode. In this mode, the slave takes over the data read / write channel and sends an in-band interrupt command to the host. Upon receiving an in-band interrupt command from any slave, the host does not need to exit the current high-speed read / write mode but directly responds to the in-band interrupt command. Based on the target slave represented by the in-band interrupt command, the host retrieves the data to be read from the target slave in high-speed read / write mode. By inserting an interrupt waiting mode after the task is completed in high-speed read / write mode, the host can directly respond to the in-band interrupt command sent by the slave in high-speed read / write mode, avoiding the communication complexity caused by "exit-processing-re-entry" and improving communication efficiency.

[0047] Furthermore, by inserting an interrupt wait mode after the task is completed in high-speed read / write mode, the master can directly respond to in-band interrupt commands sent by the slave in high-speed read / write mode. This avoids the need for the master to exit to SDR mode to respond to the command and then re-enter high-speed read / write mode to acquire the data after receiving the in-band interrupt command from the slave, reducing communication complexity and improving communication efficiency. In high-speed read / write mode, the master uses a special SDA signal to indicate to the slave that it is in interrupt wait mode. When the slave detects this signal, it can send an in-band interrupt command to the master through the data read / write channel, enabling the master to respond to the slave's in-band interrupt command in high-speed read / write mode. Compared to exiting high-speed read / write mode and then responding to in-band interrupt commands, the restart command allows the master to generate the corresponding data access command based on the in-band interrupt command while still in high-speed read / write mode and directly execute the corresponding data access operation in high-speed read / write mode, improving communication efficiency. The restart command also ensures that even if a data access command fails, it can be responded to again in high-speed read / write mode, avoiding frequent and time-consuming mode switching caused by minor errors. By setting different priority tags for different in-band interrupt commands, bus conflicts and signal chaos caused by multiple slave devices sending in-band interrupt commands are avoided, allowing in-band interrupt commands to be processed in an orderly manner. Furthermore, priority tags ensure that important in-band interrupt commands are responded to more quickly. Setting a preset wait time threshold prevents the master from waiting indefinitely, thus avoiding resource congestion.

[0048] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0049] This application provides an in-band interrupt method applied to the in-band interrupt system provided in the above embodiments. The execution subject of this application embodiment is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, and other electronic devices that can perform heterogeneous computing.

[0050] like Figure 8 The diagram shown is a flowchart illustrating an in-band interrupt method provided in an embodiment of this application. The method includes: Step 801: If the task in high-speed read / write mode is completed, enter interrupt wait mode; Step 802: In interrupt waiting mode, acquire the in-band interrupt command sent by the slave device; wherein, when the slave device is in interrupt waiting mode at the master device, it takes over the data read / write channel to send the in-band interrupt command to the master device through the data read / write channel; wherein, the slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel. Step 803: Obtain the data to be read from the target slave device according to the target slave device represented by the in-band interrupt command.

[0051] For a description of the features in the embodiment corresponding to the in-band interrupt method, please refer to the relevant description of the embodiment corresponding to the in-band interrupt system, which will not be repeated here.

[0052] The embodiments of this application also provide an in-band interrupt device applied to the in-band interrupt method provided in the above embodiments.

[0053] like Figure 9 The diagram shown is a structural schematic of an in-band interrupt device provided in an embodiment of this application. The in-band interrupt device 90 includes: an interrupt waiting module 901, a first acquisition module 902, and a second acquisition module 903.

[0054] The system includes an interrupt waiting module, which enters an interrupt waiting mode upon completion of a task in high-speed read / write mode; a first acquisition module, which acquires an in-band interrupt command sent by the slave device while in interrupt waiting mode; wherein the slave device takes over the data read / write channel from the master device while in interrupt waiting mode, and sends an in-band interrupt command to the master device through the data read / write channel; wherein the slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel; and a second acquisition module, which acquires the data to be read from the target slave device represented by the in-band interrupt command.

[0055] For a description of the features in the embodiment corresponding to the in-band interrupt device, please refer to the relevant description of the embodiment corresponding to the in-band interrupt method, which will not be repeated here.

[0056] Embodiments of this application also provide an electronic device, such as... Figure 10 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to execute the steps in any of the above-described in-band interrupt method embodiments.

[0057] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described in-band interrupt method embodiments when run.

[0058] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0059] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described in-band interrupt method embodiments.

[0060] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described in-band interrupt method embodiments.

[0061] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0062] The foregoing has provided a detailed description of an in-band interrupt system, method, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A system with in-band interrupt, characterized in that, include: The system includes a master unit and multiple slave units, which are connected via a data read / write channel. The host is used to enter an interrupt waiting mode when a task in high-speed read / write mode is completed; The slave device is used to take over the data read / write channel when the master device is in the interrupt waiting mode, so as to send an in-band interrupt command to the master device through the data read / write channel; wherein, the slave device stores the data to be read; The host terminal is also configured to, upon receiving an in-band interrupt command from any slave terminal, enter a high-speed read / write mode in response to the in-band interrupt command, and retrieve the data to be read from the target slave terminal according to the target slave terminal represented by the in-band interrupt command.

2. The in-band interrupt system according to claim 1, characterized in that, The host terminal is specifically used for: When an in-band interrupt command is received from any slave device, the in-band interrupt information of the in-band interrupt command is parsed. If the in-band interrupt information indicates that the data to be read stored on the slave device is accessible, a restart command is triggered to enter high-speed read / write mode by responding to the restart command. The target slave device is determined based on the address information represented by the in-band interrupt information; Generate the corresponding data access command based on the target slave device; Take over the data read / write channel and, in response to the data access command, obtain the data to be read from the target slave device; If the data access command is successfully responded to, the system will re-enter the interrupt waiting mode.

3. The in-band interrupt system according to claim 2, characterized in that, The host terminal is also used for: When the in-band interrupt information indicates that the data to be read stored on the slave device is not allowed to be accessed, the system enters the high-speed read / write exit mode.

4. The in-band interrupt system according to claim 2, characterized in that, The host terminal is also used for: If the data access command fails to respond, the system re-enters the high-speed read / write mode to respond to the data access command again.

5. The in-band interrupt system according to claim 2, characterized in that, The host terminal is specifically used for: When receiving in-band interrupt commands sent by the plurality of slave terminals, a target in-band interrupt command is selected from the plurality of in-band interrupt commands according to the priority label represented by the in-band interrupt information of each in-band interrupt command. The target slave device is determined based on the address information represented by the in-band interrupt information of the target in-band interrupt command.

6. The in-band interrupt system according to claim 1, characterized in that, The host terminal is also used for: In the interrupt waiting mode, if no in-band interrupt command is received from any slave device within a preset waiting time threshold, the system enters the high-speed read / write exit mode.

7. An in-band interrupt method, characterized in that, The method is applied to the host side of the in-band interrupt system as described in any one of claims 1 to 6, and the method includes: Upon completion of a task in high-speed read / write mode, the system enters interrupt wait mode. In the interrupt waiting mode, the slave device acquires an in-band interrupt command sent by the slave device; wherein, when the master device is in the interrupt waiting mode, the slave device takes over the data read / write channel to send an in-band interrupt command to the master device through the data read / write channel; wherein, the slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel; According to the target slave device represented by the in-band interrupt command, the data to be read is obtained from the target slave device.

8. A device with an internal interruption function, characterized in that, The device is applied to the host side of the in-band interrupt system as described in any one of claims 1 to 6, and the device comprises: The interrupt wait module is used to enter interrupt wait mode when a task in high-speed read / write mode is completed; The first acquisition module is used to acquire an in-band interrupt command sent by the slave device when the interrupt waiting mode is in effect; wherein, when the master device is in the interrupt waiting mode, the slave device takes over the data read / write channel to send an in-band interrupt command to the master device through the data read / write channel; wherein, the slave device stores the data to be read, and the master device and the slave device are connected through the data read / write channel. The second acquisition module is used to acquire the data to be read from the target slave device according to the target slave device represented by the in-band interrupt command.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the in-band interrupt method as described in claim 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the in-band interrupt method as described in claim 7.

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