Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel, belonging to the field of display technology, to at least improve the technical problem of large differences in coupling capacitance between interconnecting lines and clock signal lines in related technologies. The array substrate includes a substrate and a gate driving circuit, a clock signal line group, and multiple interconnecting lines located on the substrate. The clock signal line group and the gate driving circuit are arranged along a first direction and include multiple clock signal lines arranged along the first direction. The multiple interconnecting lines are disposed on a different layer from the clock signal line group. Each interconnecting line includes a first end connected to the corresponding clock signal line and a second end connected to the gate driving circuit. The interconnecting line crosses multiple clock signal lines from the first end to the second end, and at least two interconnecting lines cross the same number of clock signal lines.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] As display technology advances towards higher resolution and narrower bezels, gate drive circuits are typically integrated onto the array substrate. These gate drive circuits require timing drive signals from multiple clock signal lines; to achieve signal transmission, these clock signal lines must be connected to the corresponding gate drive circuits via connecting lines.

[0003] In related technologies, when different connection lines extend from their corresponding clock signal lines to the gate drive circuit, the number of clock signal lines they cross varies, resulting in significant differences in the coupling capacitance formed between each connection line and the clock signal line. This leads to large deviations in the transmission delay and waveform distortion of each clock signal, affecting the display uniformity of the display panel and easily causing display defects such as horizontal lines and flickering. Summary of the Invention

[0004] This application provides an array substrate and a display panel to at least improve the technical problem of large differences in coupling capacitance between each connection line and the clock signal line in the related art.

[0005] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, comprising: Substrate; The gate driving circuit is located on the substrate; A clock signal line group, located on the substrate and arranged along a first direction with the gate driving circuit, the clock signal line group comprising multiple clock signal lines arranged along the first direction; and Multiple connection lines are located on the substrate and are disposed on a different layer from the clock signal line group. Each connection line includes a first end connected to the corresponding clock signal line and a second end connected to the gate driving circuit. The connection line crosses multiple clock signal lines from the first end to the second end, and at least two connection lines cross the same number of clock signal lines.

[0006] In some embodiments, the plurality of clock signal lines include a first clock signal line, a second clock signal line, and a plurality of third clock signal lines arranged sequentially along a direction close to the gate driving circuit; the plurality of connecting lines include a first connecting line connected to the first clock signal line, a second connecting line connected to the second clock signal line, and a third connecting line connected to the third clock signal line; the third connecting line includes a first connecting segment, a second connecting segment, and a third connecting segment connected sequentially, the first connecting segment being connected to the corresponding third clock signal line and located on the side of the third clock signal line away from the gate driving circuit, and the third connecting segment being connected to the gate driving circuit.

[0007] In some embodiments, each of the third connection lines overlaps with multiple corresponding clock signal lines, and the overlap area between different third connection lines and their corresponding clock signal lines is equal.

[0008] In some embodiments, the first ends of two adjacent third connection lines partially overlap in the first direction; the third connection segment includes a first part, a second part, and a third part connected in sequence, the first part being connected to the second connection segment, and the third part being connected to the gate driving circuit; wherein the second connection segment and the second part are located on the same side of the first part.

[0009] In some embodiments, the second connection line includes a fourth connection segment, a fifth connection segment, and a sixth connection segment connected in sequence. The fourth connection segment is connected to the second clock signal line and is located on the side of the second clock signal line away from the gate driving circuit. The orthographic projection of the fifth connection segment on the plane containing the plurality of clock signal lines is located between the first clock signal line and the second clock signal line. The sixth connection segment is connected to the gate driving circuit.

[0010] In some embodiments, the first end of the second connecting line and the first end of the adjacent third connecting line partially overlap in the first direction; the sixth connecting segment includes a fourth part, a fifth part and a sixth part connected in sequence, the fourth part is connected to the fifth connecting segment and the sixth part is connected to the gate driving circuit; wherein the fifth connecting segment and the fifth part are located on the same side of the fourth part.

[0011] In some embodiments, the first connecting line includes a bent segment that bends away from the direction of the second connecting line.

[0012] In some embodiments, at least two of the first connecting line, the second connecting line, and the third connecting line have equal lengths.

[0013] In some embodiments, each of the connecting lines overlaps with multiple corresponding clock signal lines, and the overlap area between different connecting lines and their corresponding clock signal lines is equal.

[0014] According to a second aspect of this application, a display panel is provided, the display panel including the array substrate described in any embodiment of the first aspect.

[0015] In the array substrate of this application embodiment, since at least two connection lines cross the same number of clock signal lines, the overlap area of ​​these connection lines and the corresponding clock signal lines tends to be consistent. This can effectively reduce the difference in coupling interference experienced by the clock signals in these connection lines during transmission, thereby making the transmission delay and waveform distortion of each clock signal tend to be consistent, and thus improving the display uniformity of the display panel used in the array substrate.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a schematic diagram of the structure of an array substrate provided in some embodiments of this application; Figure 2 These are schematic diagrams of the array substrate provided in other embodiments of this application; Figure 3 This is a schematic diagram of the structure of the array substrate provided in some embodiments of this application; Figure 4 This is a schematic diagram of the structure of an array substrate provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0021] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are only used to distinguish different technical features. The term "multiple" and similar words indicate two or more unless otherwise expressly defined.

[0022] In this application, the descriptions of the various embodiments each have their own emphasis. Parts not described in detail in a particular embodiment can be found in the relevant descriptions of other embodiments. The embodiments, implementation methods, examples, and related technical features of this application can be combined and substituted for each other without conflict.

[0023] Some embodiments of this application provide an array substrate, such as Figures 1 to 4 As shown, the array substrate 100 includes a substrate SUB, a gate drive circuit GOA, a clock signal line group, and multiple connection lines 10 located on the substrate SUB.

[0024] The gate drive circuit GOA can be a gate-on-array (GOA) circuit integrated on the array substrate. The clock signal line group and the gate drive circuit GOA are arranged along a first direction X, with the GOA located on one side of the clock signal line group. The clock signal line group includes multiple clock signal lines CK arranged along the first direction X. Each clock signal line CK extends along a second direction Y, which intersects the first direction X; for example, the second direction Y is perpendicular to the first direction X.

[0025] Multiple connection lines 10 are disposed on different layers from the clock signal line group. For example, multiple connection lines 10 are located on a first metal layer, and the clock signal line group is located on a second metal layer, with an insulating layer separating the first and second metal layers. Each connection line 10 is connected to its corresponding clock signal line CK through a conductive via located in the insulating layer. The connection line 10 is also connected to the gate drive circuit GOA. The gate drive circuit GOA and the connection line 10 can be disposed on the same layer or on different layers. When the gate drive circuit GOA and the connection line 10 are disposed on different layers, the gate drive circuit GOA and the connection line 10 are connected through a conductive via located between them.

[0026] Each connection line 10 includes a first end 101 connected to the corresponding clock signal line CK and a second end 102 connected to the gate drive circuit GOA. The connection line 10 crosses multiple clock signal lines CK from the first end 101 to the second end 102, and at least two connection lines 10 cross the same number of clock signal lines CK.

[0027] It is worth noting that, in this embodiment, "connection line 10 crosses clock signal line CK" means that the orthographic projection of connection line 10 on substrate SUB overlaps with the orthographic projection of clock signal line CK on substrate SUB. Connection line 10 can be located on the side of clock signal line CK closer to substrate SUB, or it can be located on the side of clock signal line CK away from substrate SUB.

[0028] For the array substrate 100 provided in this application embodiment, since at least two connection lines 10 cross the same number of clock signal lines CK, the overlapping area of ​​these connection lines 10 and the corresponding clock signal lines CK tends to be consistent. This can effectively reduce the difference in coupling interference experienced by the clock signals in these connection lines 10 during transmission, thereby making the transmission delay and waveform distortion of each clock signal tend to be consistent, and thus improving the display uniformity of the display panel used by the array substrate 100.

[0029] In some examples, the clock signal lines CK in the clock signal line group have the same line width.

[0030] In some examples, multiple connecting lines 10 have the same line width.

[0031] It should be noted that in the embodiments of this application, line width refers to the width of the trace, and the width direction of the trace is perpendicular to its extension direction.

[0032] In some embodiments, please continue reading Figures 1 to 4 The multiple clock signal lines CK include a first clock signal line CK1, a second clock signal line CK2, and multiple third clock signal lines CK3 arranged sequentially along the direction close to the gate drive circuit GOA. The multiple connecting lines 10 include a first connecting line 11 connected to the first clock signal line CK1, a second connecting line 12 connected to the second clock signal line CK2, and a third connecting line 13 connected to the third clock signal lines CK3. Since there are multiple third clock signal lines CK3, there are also multiple third connecting lines 13, and each of the multiple third connecting lines 13 is connected to each of the multiple third clock signal lines CK3 in a one-to-one correspondence.

[0033] Figures 1 to 4The diagram shows twelve clock signal lines CK, where there is one first clock signal line CK1 and one second clock signal line CK2, and ten third clock signal lines CK3. In other instances, the number of clock signal lines CK can be four, eight, or other numbers, and the number of third clock signal lines CK3 can be any number other than ten. This application does not limit this.

[0034] In some examples, the third connection line 13 includes a first connection segment 131, a second connection segment 132, and a third connection segment 133 connected in sequence. The first connection segment 131 is connected to the corresponding third clock signal line CK3 and is located on the side of the third clock signal line CK3 away from the gate drive circuit GOA. The third connection segment 133 is connected to the gate drive circuit GOA.

[0035] Since the first clock signal line CK1 and the second clock signal line CK2 are farther away from the gate drive circuit GOA than the third connecting line 13, the first clock signal line CK1 and the second clock signal line CK2 will cross a larger number of clock signal lines CK (e.g., multiple third clock signal lines CK3) when connecting to the gate drive circuit GOA. In this embodiment, by setting the first connecting segment 131 to be located on the side of the corresponding third clock signal line CK3 away from the gate drive circuit GOA, the third connecting line 13 can extend in a direction away from the gate drive circuit GOA and cross a larger number of clock signal lines CK. This ensures that a portion of the third connecting line 13 can cross the same number of clock signal lines CK as another portion of the third connecting line 13 (or at least one of the first connecting line 11 and the second connecting line 12). This makes the overlap area of ​​this portion of the connecting line 10 with the corresponding clock signal line CK more consistent, thereby effectively reducing the difference in coupling interference experienced by the clock signal in this portion of the connecting line 10 during transmission, and thus improving the display uniformity of the display panel.

[0036] It is worth noting that, please refer to Figure 1 During the extension of the third connection line 13, the first connection segment 131 and the third connection segment 133 each cross the same clock signal line CK. The clock signal line CK repeatedly crossed by the third connection line 13 should be counted multiple times in the total number of clock signal lines CK crossed by the third connection line 13. For example, for Figure 1 The topmost third connection line 13 has a first connection segment 131 that crosses five clock signal lines CK, and a third connection segment 133 that crosses six clock signal lines CK. Therefore, the third connection line 13 crosses a total of eleven clock signal lines CK.

[0037] In some examples, the first connecting segment 131 and the third connecting segment 133 both extend along a first direction X, and the second connecting segment 132 extends along a second direction Y. In this case, the first connecting segment 131, the second connecting segment 132, and the third connecting segment 133 are all arranged linearly, which helps to reduce the length of the third connecting line 13, thereby reducing the impedance of the third connecting line 13.

[0038] In some examples, the number of clock signal lines CK crossed by the third connection line 13, the second connection line 12, and the first connection line 11 are all equal. For example, the number of clock signal lines CK crossed by connection line 10 is eleven.

[0039] It is worth noting that, such as Figures 1 to 4 As shown, the second connection segment 132 of part of the third connection line 13 overlaps with a corresponding third clock signal line CK3, indicating that this part of the third connection line 13 crosses the corresponding third clock signal line CK3 respectively.

[0040] In some embodiments, please continue reading Figures 1 to 4 Each third connection line 13 overlaps with multiple corresponding clock signal lines CK, and the overlap area between different third connection lines 13 and their corresponding clock signal lines CK is equal.

[0041] Since the overlap area between different third connection lines 13 and their corresponding clock signal lines CK is the same, the difference in coupling interference experienced by the clock signal during transmission within the third connection lines 13 is further reduced, thereby improving the display uniformity of the display panel. Furthermore, since the overlap area between different third connection lines 13 and their corresponding clock signal lines CK is the same, the parasitic capacitance between the third connection lines 13 and their corresponding clock signal lines CK is also the same, which also helps to improve the display uniformity of the display panel.

[0042] It is worth noting that, in the embodiments of this application, the equality of the areas of A and B includes both complete equality and approximate equality. Complete equality means that the area values ​​of the two are the same, while approximate equality means that the difference in their areas does not exceed 5% of the larger area.

[0043] In some embodiments, such as Figure 1 As shown, the third connecting segment 133 is arranged linearly, which helps to reduce the length of the third connecting segment 133, thereby reducing the impedance of the third connecting line 13.

[0044] In some embodiments, such as Figures 2 to 4As shown, the third connection segment 133 includes a first part 1331, a second part 1332, and a third part 1333 connected in sequence. The first part 1331 is connected to the second connection segment 132, and the third part 1333 is connected to the gate drive circuit GOA. The second connection segment 132 and the second part 1332 are located on the same side of the first part 1331.

[0045] This configuration allows the third connecting segment 133 to bend toward the first end 101 before extending toward the gate drive circuit GOA, which helps to improve the problem of short circuits easily occurring between the third connecting segment 133 in the third connecting line 13 and the first end 101 of the adjacent connecting line 10.

[0046] In some examples, the first portion 1331 and the third portion 1333 both extend along the first direction X, and the second portion 1332 extends along the second direction Y. In this case, the first portion 1331, the second portion 1332, and the third portion 1333 are all arranged linearly, which helps to reduce the length of the third connecting line 13, thereby reducing the impedance of the third connecting line 13.

[0047] In some examples, the second part 1332 does not overlap with multiple clock signal lines CK, which reduces the overlap area between the third connection line 13 and the corresponding clock signal line CK, thereby reducing the coupling interference of the clock signal line CK to the clock signal transmitted in the third connection line 13.

[0048] In some embodiments, such as Figure 3 and Figure 4 As shown, the first ends 101 of two adjacent third connecting lines 13 partially overlap in the first direction X. For example, the edges of the first ends 101 of two adjacent third connecting lines 13 overlap in the first direction X.

[0049] This configuration allows the first end 101 of each third connection line 13 to have a relatively large area, which helps to improve the connection stability between the third connection line 13 and the corresponding clock signal line CK. In addition, the above configuration also makes the space occupied by the first end 101 of multiple third connection lines 13 relatively small in the first direction X, which helps to reduce the space occupied by the third connection lines 13.

[0050] In some embodiments, such as Figures 1 to 4As shown, the second connection line 12 includes a fourth connection segment 121, a fifth connection segment 122, and a sixth connection segment 123 connected in sequence. The fourth connection segment 121 is connected to the second clock signal line CK2 and is located on the side of the second clock signal line CK2 away from the gate drive circuit GOA. The orthographic projection of the fifth connection segment 122 on the plane containing the multiple clock signal lines CK is located between the first clock signal line CK1 and the second clock signal line CK2. The sixth connection segment 123 is connected to the gate drive circuit GOA.

[0051] In this embodiment, by setting the fourth connecting segment 121 to the side of the second clock signal line CK2 away from the gate driving circuit GOA, the second connecting line 12 can extend in a direction away from the gate driving circuit GOA and cross the second clock signal line CK2 via the sixth connecting segment 123. This ensures that both the second connecting line 12 and the first connecting line 11 can cross the same number of clock signal lines CK, making the overlap area between the second connecting line 12 and the first connecting line 11 and their corresponding clock signal lines CK more consistent. This effectively reduces the difference in coupling interference experienced by the clock signals in the second connecting line 12 and the first connecting line 11 during transmission, thereby improving the display uniformity of the display panel. Furthermore, since the orthographic projection of the fifth connecting segment 122 on the plane containing the multiple clock signal lines CK is located between the first clock signal line CK1 and the second clock signal line CK2, the fifth connecting segment 122 does not overlap with the clock signal lines CK. This reduces the overlap area between the second connecting line 12 and its corresponding clock signal line CK, thereby reducing the coupling interference of the clock signal lines CK on the clock signals transmitted in the second connecting line 12.

[0052] In some examples, the fourth connecting segment 121 and the sixth connecting segment 123 both extend along the first direction X, and the fifth connecting segment 122 extends along the second direction Y. In this case, the fourth connecting segment 121, the fifth connecting segment 122, and the sixth connecting segment 123 are all arranged linearly, which helps to reduce the length of the second connecting line 12, thereby reducing the impedance of the second connecting line 12.

[0053] In some embodiments, such as Figures 2 to 4 As shown, the sixth connection segment 123 includes a fourth part 1231, a fifth part 1232, and a sixth part 1233 connected in sequence. The fourth part 1231 is connected to the fifth connection segment 122, and the sixth part 1233 is connected to the gate drive circuit GOA. The fifth connection segment 122 and the fifth part 1232 are located on the same side of the fourth part 1231.

[0054] This configuration allows the sixth connecting segment 123 to bend toward the first end 101 before extending toward the gate drive circuit GOA, which helps to improve the problem of short circuits easily occurring between the sixth connecting segment 123 in the second connecting line 12 and the first end 101 of the adjacent connecting line 10.

[0055] In some examples, the fourth portion 1231 and the sixth portion 1233 both extend along the first direction X, and the fifth portion 1232 extends along the second direction Y. In this case, the fourth portion 1231, the fifth portion 1232, and the sixth portion 1233 are all arranged linearly, which helps to reduce the length of the second connecting line 12, thereby reducing the impedance of the second connecting line 12.

[0056] In some embodiments, such as Figure 3 and Figure 4 As shown, the first end 101 of the second connecting line 12 partially overlaps with the first end 101 of the adjacent third connecting line 13 in the first direction X. For example, the edge of the first end 101 of the second connecting line 12 and the edge of the first end 101 of the adjacent third connecting line 13 overlap in the first direction X.

[0057] This configuration allows the first end 101 of the second connecting line 12 to have a relatively large area, which helps to improve the connection stability between the second connecting line 12 and the second clock signal line CK2. In addition, the above configuration also makes the space occupied by the first end 101 of the second connecting line 12 and the first end 101 of the adjacent third connecting line 13 in the first direction X relatively small, which helps to reduce the space occupied by the connecting line 10.

[0058] In some embodiments, such as Figures 1 to 4 As shown, at least two of the first connecting line 11, the second connecting line 12, and the third connecting line 13 have equal lengths. This ensures that the impedances of the connecting lines 10 are equal, thereby improving the uniformity of the clock signal transmitted through the connecting lines 10.

[0059] In some examples, the lengths of the first connection line 11, the second connection line 12, and the third connection line 13 are all equal. Since the second connection line 12 and the third connection line 13 are routed towards the direction close to the first connection line 11, it is possible to avoid the second connection line 12 and the third connection line 13 being routed on the side close to the gate drive circuit GOA, which helps to reduce the bezel size of the array substrate 100.

[0060] In some embodiments, please continue reading Figures 1 to 4 The first connecting line 11 includes a bent segment 111 that bends away from the direction of the second connecting line 12.

[0061] This arrangement serves two purposes: firstly, it ensures that the lengths of the first connecting line 11, the second connecting line 12, and the third connecting line 13 are equal, thereby improving the uniformity of the clock signal transmitted in the connecting line 10; secondly, it avoids the problem of short circuits easily occurring between the first connecting line 11 and the second connecting line 12 caused by the bending segment 111 bending in the direction of the second connecting line 12.

[0062] In some embodiments, please continue reading Figures 1 to 4 Each connecting line 10 overlaps with multiple corresponding clock signal lines CK, and the overlap area between different connecting lines 10 and their corresponding clock signal lines CK is equal.

[0063] Since the overlapping areas of different connecting lines 10 and their corresponding clock signal lines CK are the same, the differences in coupling interference experienced by the clock signal during transmission within the connecting lines 10 can be further reduced, thereby improving the display uniformity of the display panel. Furthermore, since the overlapping areas of different connecting lines 10 and their corresponding clock signal lines CK are the same, the parasitic capacitances between the connecting lines 10 and their corresponding clock signal lines CK are also the same, which also helps to improve the display uniformity of the display panel.

[0064] In some embodiments, such as Figure 4 As shown, each clock signal line CK has multiple openings K spaced apart along its length.

[0065] By setting the opening K, on ​​the one hand, the stress on the clock signal line CK can be released, and problems such as warping or even breakage due to excessively long traces or thermal expansion and contraction can be alleviated; on the other hand, it is also beneficial to reduce the overlap area between the connecting line 10 and the corresponding clock signal line CK, thereby reducing the parasitic capacitance between the two and the coupling interference of the clock signal line CK to the clock signal transmitted in the connecting line 10.

[0066] In some examples, multiple openings K are set at equal intervals.

[0067] In some embodiments, please continue reading Figure 4 In the case where the third connecting line 13 includes a first connecting segment 131, a second connecting segment 132, and a third connecting segment 133 connected in sequence, the orthographic projection of a portion of the second connecting segment 132 of the third connecting line 13 onto the plane containing the multiple clock signal lines CK at least partially overlaps with the corresponding opening K. This effectively reduces the overlap area between the third connecting line 13 and the corresponding clock signal line CK, thereby reducing the parasitic capacitance between them and the coupling interference of the clock signal line CK to the clock signal transmitted in the third connecting line 13.

[0068] In some examples, a low-frequency clock trace is also provided between the clock signal line group and the gate drive circuit GOA. The clock signal line CK can transmit high-frequency clock signals, while the low-frequency clock trace is used to transmit low-frequency clock signals.

[0069] Some embodiments of this application also provide a display panel, such as Figure 5 As shown, the display panel 200 includes the array substrate 100 described in any of the above embodiments.

[0070] Since it includes the array substrate 100, the display panel 200 has the technical effects of the array substrate 100 described above, which will not be repeated here.

[0071] In some examples, the display panel 200 can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, netbooks, personal digital assistants, augmented reality devices, virtual reality devices, media players, wearable devices, digital cameras, car navigation systems, etc., and this application embodiment does not limit this.

[0072] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; The gate driving circuit is located on the substrate; A clock signal line group, located on the substrate and arranged along a first direction with the gate driving circuit, the clock signal line group comprising multiple clock signal lines arranged along the first direction; and Multiple connection lines are located on the substrate and are disposed on a different layer from the clock signal line group. Each connection line includes a first end connected to the corresponding clock signal line and a second end connected to the gate driving circuit. The connection line crosses multiple clock signal lines from the first end to the second end, and at least two connection lines cross the same number of clock signal lines.

2. The array substrate according to claim 1, characterized in that, The plurality of clock signal lines include a first clock signal line, a second clock signal line, and a plurality of third clock signal lines arranged sequentially along the direction close to the gate drive circuit; The plurality of connection lines include a first connection line connected to the first clock signal line, a second connection line connected to the second clock signal line, and a third connection line connected to the third clock signal line; The third connection line includes a first connection segment, a second connection segment, and a third connection segment connected in sequence. The first connection segment is connected to the corresponding third clock signal line and is located on the side of the third clock signal line away from the gate driving circuit. The third connection segment is connected to the gate driving circuit.

3. The array substrate according to claim 2, characterized in that, Each of the third connecting lines overlaps with multiple corresponding clock signal lines, and the overlap area between different third connecting lines and their corresponding clock signal lines is equal.

4. The array substrate according to claim 2, characterized in that, The first ends of two adjacent third connecting lines partially overlap in the first direction; The third connection segment includes a first part, a second part, and a third part connected in sequence. The first part is connected to the second connection segment, and the third part is connected to the gate driving circuit. The second connection segment and the second part are located on the same side of the first part.

5. The array substrate according to claim 2, characterized in that, The second connection line includes a fourth connection segment, a fifth connection segment, and a sixth connection segment connected in sequence. The fourth connection segment is connected to the second clock signal line and is located on the side of the second clock signal line away from the gate driving circuit. The orthographic projection of the fifth connection segment on the plane containing the plurality of clock signal lines is located between the first clock signal line and the second clock signal line. The sixth connection segment is connected to the gate driving circuit.

6. The array substrate according to claim 5, characterized in that, The first end of the second connecting line partially overlaps with the first end of the adjacent third connecting line in the first direction; The sixth connection segment includes a fourth part, a fifth part, and a sixth part connected in sequence. The fourth part is connected to the fifth connection segment, and the sixth part is connected to the gate driving circuit. The fifth connection segment and the fifth part are located on the same side of the fourth part.

7. The array substrate according to claim 2, characterized in that, The first connecting line includes a bent segment that bends away from the direction of the second connecting line.

8. The array substrate according to any one of claims 2-7, characterized in that, At least two of the first connecting line, the second connecting line, and the third connecting line are of equal length.

9. The array substrate according to any one of claims 1-7, characterized in that, Each of the connecting lines overlaps with multiple corresponding clock signal lines, and the overlap area between different connecting lines and their corresponding clock signal lines is equal.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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