Image sending and displaying method and electronic device

Abstract

An image display method and electronic device are disclosed, relating to the field of terminal technology. The method includes: at a first moment, the display screen generates a first hardware TE signal; in response to detecting the first hardware TE signal, the SoC sends a first image to the display screen. At a second moment, the display screen generates a second hardware TE signal; in response to detecting the second hardware TE signal, the SoC sends a second image to the display screen. The second moment occurs after the first moment, and the second image is the next frame of the first image. Wherein, after the first moment and before the second moment, the display screen generates at least one third hardware TE signal, and the SoC does not detect at least one third hardware TE signal. This allows for accurate and timely frame rate switching and reduces power consumption during frame rate switching.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to an image display method and electronic device. Background Technology

[0002] A key component of a display screen is the display panel. Display panels can be Low Temperature Polycrystalline Oxide (LTPO) or Low Temperature Polycrystalline Silicon (LTPS) panels, among others. Furthermore, based on the number of transistors in the pixel circuitry of an LTPO display panel, displays can be classified as 7T-LTPO screens and 8T-LTPO screens. 7T refers to a pixel circuitry containing 7 transistors, and 8T refers to a pixel circuitry containing 8 transistors.

[0003] However, when configuring electronic devices with 8T-LTPO screens, unexpected frame rates can easily occur during frame rate switching. An unexpected frame rate is one that is neither the frame rate before the switch nor the frame rate after the switch. For example, when an electronic device switches the frame rate from 60FPS to 120FPS, an unexpected frame rate of 90FPS may occur. Summary of the Invention

[0004] This application provides an image display method and electronic device that can achieve accurate and timely frame rate switching and reduce power consumption during frame rate switching.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In one aspect, an image display method is provided, which is applied to an electronic device, including a SoC and a display screen. The display screen generates a hardware TE signal at a first frequency, that is, the display screen always generates a hardware TE signal at a fixed frequency, such as 360Hz.

[0007] The method includes: at a first moment, the display generates a first hardware TE signal; in response to detecting the first hardware TE signal, the SoC sends a first image to the display. At a second moment, the display generates a second hardware TE signal; in response to detecting the second hardware TE signal, the SoC sends a second image to the display. The second moment occurs after the first moment, and the second image is the next frame of the first image. Wherein, after the first moment and before the second moment, the display generates at least one third hardware TE signal, and the SoC does not detect at least one third hardware TE signal. For example, if the waveform of the hardware TE signal generated by the display includes the third hardware TE signal, but the trace graph does not include the pulse signal corresponding to the third hardware TE signal, it indicates that the SoC did not detect the third hardware TE signal.

[0008] The following text Figure 12 For example:

[0009] Case 1: The first time point is near Ta, the first hardware TE signal is TE1, and the first image is Figure A. The second time point is near Tb, the second hardware TE signal is TE2, and the second image is Figure B. At least one third hardware TE signal is a hardware TE signal between TE1 and TE2.

[0010] Case 2: The first time point is near Tb, the first hardware TE signal is TE2, and the first image is Figure B. The second time point is near Tc, the second hardware TE signal is TE3, and the second image is Figure C. At least one third hardware TE signal is a hardware TE signal between TE2 and TE3.

[0011] The following text Figure 14 For example:

[0012] Case 3: The first time point is near Td, the first hardware TE signal is TE4, and the first image is Figure D. The second time point is near Td', the second hardware TE signal is TE5, the second image is Figure E, and at least one third hardware TE signal is a hardware TE signal between TE4 and TE5.

[0013] In summary, by adopting this application, an electronic device can detect the hardware TE signal at a frequency lower than the first frequency that generates the hardware TE signal, control the rhythm of SoC side processing and sending images, thereby achieving frame rate control.

[0014] In one possible design approach of the first aspect, the time interval between the first moment and the second moment is greater than or equal to the frame length corresponding to the first frame rate. Here, the first frequency is the current image frame rate on the SoC side.

[0015] For example, in case 3 above, the time interval between the first moment and the second moment is greater than the frame length corresponding to the current frame rate, such as 16.6ms.

[0016] For example, in case 1 above, the time interval between the first moment and the second moment is equal to the frame length corresponding to the current frame rate, such as 16.6ms.

[0017] As another example, in case 2 above, the time interval between the first moment and the second moment is equal to the frame length corresponding to the current frame rate, such as 8.3ms.

[0018] In other words, the SoC can use a time interval that is longer than or equal to the frame length corresponding to the current frame rate to detect the hardware TE signal, thereby triggering image transmission based on the current frame rate.

[0019] In one possible design of the first aspect, the method further includes: at a third moment, the display generates a fourth hardware TE signal; in response to detecting the fourth hardware TE signal, the SoC sends a third image to the display, the third moment being prior to the first moment, and the third image being the previous frame of the first image. Between the third moment and the first moment, the SoC generates a frame rate switching instruction (frame-switching instruction), which may instruct the image frame rate to be switched from a second frame rate to a first frame rate; that is, the frame rate before the switch is the second frame rate, and the frame rate after the switch is the first frame rate.

[0020] Continue with Figure 12 For example: Case 4, based on Case 2 above, the third time is the time near Ta, the fourth hardware TE signal is TE1, the third image is Figure A, the frequency corresponding to the first frame rate is 120Hz, and it switches to the first frame rate near time t1.

[0021] In other words, a frame rate switch occurred during the process of obtaining the first image between the third time and the first time. The first frame rate obtained by the switch will take effect in the next frame of the first image, namely the second image, so that subsequent frames can be generated and displayed according to the switched frame rate, without affecting the generation and display of the current first image.

[0022] In one possible design of the first aspect, the above method further includes: after the third moment and before the first moment, the display generates at least one fifth hardware TE signal, and the SoC does not detect at least one fifth hardware TE signal.

[0023] For example, in case 4 above, the fifth hardware TE signal is the hardware TE signal between TE1 and TE2, on the SoC side (e.g. Figure 12 The display driver in the system did not detect these hardware TE signals.

[0024] In one possible design approach of the first aspect, the time interval between the aforementioned third moment and the first moment is greater than or equal to the frame length corresponding to the second frame rate.

[0025] For example, in case 4 above, the frequency corresponding to the second frame rate is 60Hz, and the time interval between the third moment (near moment Ta) and the first moment (near moment Tb) is equal to 16.6ms.

[0026] Of course, in cases where there is a delay in the processing of the third image, similar... Figure 14 In the case of Figure E, the interval between the third time step and the first time step will be greater than the frame length corresponding to the second frame rate.

[0027] In other words, a frame rate switch occurred during the process of processing the first image between the third and first moments. For the first image currently being processed, the SoC can still send it to the display at the second frame rate before the switch, thereby avoiding the generation of unexpected frame rates.

[0028] In one possible design approach of the first aspect, the SoC does not send a frame-slicing instruction to the display after generating the frame-slicing instruction.

[0029] In other words, the SoC can detect the hardware TE signal according to the frame rate to control the timing of image transmission. This way, even if a frame rate switching requirement arises, the SoC does not need to send a frame-switching (frame rate switching) command to the display, avoiding problems such as unexpected frame rates and untimely frame switching caused by sending frame-switching commands, thus achieving accurate and timely frame rate switching. Furthermore, not sending frame-switching commands to the display by the SoC also reduces the power consumption incurred by the SoC in sending such commands.

[0030] In one possible design of the first aspect, if the fourth moment of preparation before sending the second image is located before the expected display time (EPT) of the second image, that is, if there is no processing delay (or processing lag), the time interval between the first moment and the second moment is equal to the length of the first corresponding frame.

[0031] For example, in case 1 above, the fourth time step is T3 and the EPT is Tb. As another example, in case 2 above, the fourth time step is T4 and the EPT is Tc. Both of these cases represent situations where there is no processing delay.

[0032] In one possible design of the first aspect, if the fourth moment of preparation before sending the second image is completed is after the expected display time (EPT) of the second image, i.e., if there is a processing delay, the time interval between the first moment and the second moment is greater than the first corresponding frame length.

[0033] For example, in case 3 above, the fourth time step is T6 and EPT is Te, which is a case where there is a processing delay.

[0034] In one possible design of the first aspect, the method further includes: at a fifth moment, the SoC detects a software TE signal and does not send an image to the display screen. The fifth moment is located after the first moment and before the second moment, and the time interval between the first and fifth moments is the first corresponding frame length.

[0035] For example, in case 3 above, the fifth time is Td+16.6ms, which is theoretically the same as Te.

[0036] In one possible design of the first aspect, the method further includes: at a sixth moment, the SoC enables hardware TE signal detection; the sixth moment is located after the first moment and before the second moment. After the SoC sends a second image to the display screen in response to the detection of a second hardware TE signal, the method further includes: the SoC disables hardware TE signal detection.

[0037] For example, in case 1 above, the sixth time point is the delay time db. For example, in case 2 above, the sixth time point is the delay time dc. For example, in case 3 above, the sixth time point is the time between time T6 and time Td'.

[0038] In other words, the SoC can enable or disable hardware TE signal detection to ensure that only hardware TE signals that meet the current frame rate are detected. This way, even if the display continuously generates hardware TE signals at a fixed frequency, the SoC does not need to frequently detect the hardware TE signals, reducing the power consumption associated with hardware TE signal detection.

[0039] In one possible design approach of the first aspect, enabling hardware TE signal detection on the SoC includes: the SoC switching the image source to a hardware TE signal. Disabling hardware TE signal detection on the SoC includes: the SoC switching the image source to a software TE signal.

[0040] In other words, the SoC enables and disables hardware TE signal detection by switching the image source. Compared to directly enabling or disabling the hardware TE signal, switching the image source reduces latency, enables more timely enabling and disabling of hardware TE signal detection, and allows for more accurate detection of the hardware TE signal based on the current frame rate.

[0041] In one possible design of the first aspect, the method further includes: in response to detecting a first hardware TE signal, the SoC initializes a timer, causing the timer to start counting from a first moment, and the timer's timing duration is the frame length corresponding to the first frame rate. In response to the timing duration arriving, the SoC generates a software TE signal. Wherein, if the image source is a software TE signal, the SoC detects the software TE signal.

[0042] In other words, the software TE signal is theoretically generated at the expected display time of the next frame. Therefore, the SoC will not detect the software TE signal before the expected display time of the next frame, thus preventing the SoC from triggering image transmission due to the detection of the software TE signal before the expected display time. This allows for control over the image transmission timing to meet frame rate requirements.

[0043] In one possible design of the first aspect, if the fourth moment of preparation before sending the second image is before the expected display time (EPT) of the second image, that is, there is no processing delay, the sixth moment is before EPT, and the time interval between the sixth moment and EPT is less than the first duration.

[0044] In other words, if there is no processing delay, hardware TE signal detection can be enabled a little before the expected display time to avoid missing the hardware TE signal.

[0045] In one possible design approach of the first aspect, the first duration is shorter than the period corresponding to the first frequency. For example, if the first frequency is 360Hz, then the period is 2.7ms.

[0046] In this way, the SoC can start hardware TE signal detection a short time before the expected display time, avoiding the detection of an earlier hardware TE signal, which would cause a mismatch between the image display timing and the current frame rate.

[0047] In one possible design of the first aspect, if the fourth moment, in which preparations for sending the second image are completed, is after the expected display time (EPT) of the second image, i.e., there is a processing delay, then the sixth moment is after the fourth moment.

[0048] For example, the sixth time step is the fourth time step. In this way, even with processing delays, the SoC can start detecting the hardware TE signal in a timely manner.

[0049] In one possible design of the first aspect, the first frequency is a multiple of 120 Hz. For example, the first frequency includes 360 Hz.

[0050] In other words, the display can generate hardware TE signals at a high frequency, thus meeting various frame rate requirements.

[0051] In one possible design of the first aspect, the frequency corresponding to the first frame rate includes any one of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz and 1Hz, and the frequency corresponding to the second frame rate includes any one of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz and 1Hz, and the first frame rate and the second frame rate are different.

[0052] In one possible design of the first aspect, the display screen includes: a low-temperature polycrystalline oxide (LTPO) screen with pixel circuitry comprising eight transistors.

[0053] This can resolve the issue of unexpected frame rates or untimely frame switching when the 8T-LTPO screen switches frame rates.

[0054] In one possible design of the first aspect, before the SoC sends a second image to the display screen in response to the detection of a second hardware TE signal, the method further includes: an image compositor in the SoC calculating the expected display time (EPT) of the second image. The image compositor sends the EPT to the display driver in the SoC. The above-mentioned enabling hardware TE signal detection by the SoC at the sixth time includes: the display driver enabling hardware TE signal detection at the sixth time based on the EPT.

[0055] In this way, the image synthesizer can send the expected display time to the display driver, enabling the display driver to control the timing of detecting the hardware TE signal according to the current frame rate, thereby meeting the requirements of the current frame rate.

[0056] Of course, the image synthesizer can also directly send the frame rate to the display driver, and the display driver can determine the timing of detecting the TE signal based on the frame rate, which can also meet the frame rate requirements. This application does not make specific limitations in this regard.

[0057] Secondly, this application also provides an electronic device, which includes a System-on-a-Chip (SoC), a display screen, a memory, and one or more processors. The SoC, display screen, memory, and processors are coupled together, and the display screen generates a hardware TE signal at a first frequency. The memory stores computer program code, which includes computer instructions. When the computer instructions are executed by the processor, the electronic device performs the following steps: at a first moment, the display screen generates a first hardware TE signal, and in response to detecting the first hardware TE signal, the SoC sends a first image to the display screen; at a second moment, the display screen generates a second hardware TE signal, and in response to detecting the second hardware TE signal, the SoC sends a second image to the display screen, the second moment being after the first moment, and the second image being the next frame of the first image; wherein, after the first moment and before the second moment, the display screen generates at least one third hardware TE signal, and the SoC does not detect at least one third hardware TE signal.

[0058] In one possible design approach in the second aspect, the time interval between the first moment and the second moment is greater than or equal to the frame length corresponding to the current frame rate.

[0059] In one possible design of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: at a third moment, the display generates a fourth hardware TE signal; in response to the detection of the fourth hardware TE signal, the SoC sends a third image to the display, the third moment being prior to the first moment, and the third image being the previous frame of the first image; wherein the current frame rate is the first frame rate, and the first frame rate is the frame rate after switching between the third moment and the first moment.

[0060] In one possible design in the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: after a third moment and before a first moment, the display generates at least one fifth hardware TE signal, and the SoC does not detect at least one fifth hardware TE signal.

[0061] In one possible design approach in the second aspect, the time interval between the third moment and the first moment is greater than or equal to the frame length corresponding to the second frame rate, where the second frame rate is the frame rate before switching between the third moment and the first moment.

[0062] In one possible design approach of the second aspect, if the fourth moment of preparation before sending the second image is completed is before the expected display time (EPT) of the second image, the time interval between the first moment and the second moment is equal to the frame length corresponding to the current frame rate.

[0063] In one possible design approach of the second aspect, if the fourth moment of preparation before sending the second image is completed is after the expected display time (EPT) of the second image, the time interval between the first moment and the second moment is greater than the frame length corresponding to the current frame rate.

[0064] In one possible design approach of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: at a fifth moment, the SoC detects a software TE signal and the SoC does not send an image to the display screen; wherein the fifth moment is after the first moment and before the second moment, and the time interval between the first moment and the fifth moment is the frame length corresponding to the current frame rate.

[0065] In one possible design approach of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: at a sixth moment, the SoC enables hardware TE signal detection; the sixth moment is after the first moment and before the second moment; after the SoC sends the second image to the display screen, the SoC disables hardware TE signal detection.

[0066] In one possible design approach of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: the SoC switches the image source to a hardware TE signal; the SoC switches the image source to a software TE signal.

[0067] In one possible design approach of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: in response to the detection of a first hardware TE signal, the SoC initializes a timer, causing the timer to start timing from a first moment, and the timing period of the timer is the frame length corresponding to the current frame rate; in response to the timing period arriving, the SoC generates a software TE signal; wherein, when the image source is a software TE signal, the SoC detects the software TE signal.

[0068] In one possible design of the second aspect, if the fourth moment of preparation for sending the second image is before the expected display time (EPT) of the second image, the sixth moment is before the EPT, and the time interval between the sixth moment and the EPT is less than the first duration.

[0069] In one possible design approach in the second aspect, the first duration is less than the period corresponding to the first frequency.

[0070] In one possible design of the second aspect, if the fourth time step, which is the preparation time before sending the second image, is after the expected display time (EPT) of the second image, the sixth time step is after the fourth time step.

[0071] In one possible design approach in the second aspect, the first frequency is a multiple of 120Hz.

[0072] In one possible design approach in the second aspect, the first frequency includes 360Hz.

[0073] In one possible design approach in the second aspect, the frequency corresponding to the current frame rate includes any of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz, and 1Hz.

[0074] In one possible design of the second aspect, the display screen includes: a low-temperature polycrystalline oxide (LTPO) screen with pixel circuitry comprising eight transistors.

[0075] In one possible design approach of the second aspect, when computer instructions are executed by the processor, the electronic device performs the following steps: the image synthesizer in the SoC calculates the expected display time (EPT) of the second image; the image synthesizer sends the EPT to the display driver in the SoC; and the display driver enables hardware TE signal detection at a sixth time based on the EPT.

[0076] Thirdly, this application provides a chip system applied to an electronic device including a display panel and a memory; the chip system includes one or more interface circuits and one or more processors; the interface circuits and processors are interconnected via lines; the interface circuits are used to receive signals from the memory of the electronic device and send signals to the processor, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs the method as described in the first aspect and any of its possible design embodiments.

[0077] Fourthly, this application provides a computer storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform a method as described in the first aspect and any of its possible design embodiments.

[0078] Fifthly, this application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the method as described in the first aspect and any possible design thereof.

[0079] Understandably, the beneficial effects that the electronic device of the second aspect, the chip system of the third aspect, the computer storage medium of the fourth aspect, and the computer program product of the fifth aspect can achieve can be referred to the beneficial effects of the first aspect and any of its possible design embodiments, which will not be repeated here. Attached Figure Description

[0080] Figure 1 One of the schematic diagrams illustrating the principle of image display provided in the embodiments of this application;

[0081] Figure 2 A second schematic diagram illustrating the principle of image display provided in this application embodiment;

[0082] Figures 3A-3C A schematic diagram illustrating the principle of controlling the frame rate via the TE signal, provided for an embodiment of this application;

[0083] Figure 4 The ideal TE signal waveform diagram for switching from 60Hz to 120Hz is provided for the embodiments of this application;

[0084] Figure 5 A schematic diagram illustrating one implementation of switching from 60Hz to 120Hz provided in an embodiment of this application;

[0085] Figure 6 A schematic diagram illustrating another implementation of switching from 60Hz to 120Hz provided in this application embodiment;

[0086] Figure 7 A hardware structure diagram of the electronic device provided in the embodiments of this application;

[0087] Figure 8 Hardware and software architecture diagrams of electronic devices provided in embodiments of this application;

[0088] Figure 9 A schematic diagram illustrating the expected display time and its function as provided in the embodiments of this application;

[0089] Figure 10A This is one of the timing interaction diagrams of the image display method provided in the embodiments of this application;

[0090] Figure 10B A diagram showing the relationship between the Vsync-SF signal and the reported TE signal provided in an embodiment of this application;

[0091] Figure 10C The second timing interaction diagram of the image display method provided in the embodiments of this application;

[0092] Figure 11 The third timing interaction diagram of the image display method provided in the embodiments of this application;

[0093] Figure 12 This is one of the application example diagrams of the image display method provided in the embodiments of this application;

[0094] Figure 13 The fourth timing interaction diagram of the image display method provided in the embodiments of this application;

[0095] Figure 14 This is the second example diagram illustrating the application of the image display method provided in the embodiments of this application.

[0096] Figure 15 This is a schematic diagram of the system chip provided in an embodiment of this application. Detailed Implementation

[0097] The technical solutions of the embodiments of this application are described below with reference to the accompanying drawings. In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0098] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0099] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0100] Before introducing the embodiments of this application, the following will first combine... Figure 1 A brief introduction to the principle of image display.

[0101] See Figure 1 Electronic devices include system-on-chips (SoCs) and displays (also known as screens).

[0102] The SoC can integrate key chips such as an application processor (AP) and a baseband processor (BP, also known as a modem). Furthermore, the AP may include modules such as a surface fllinger (SF) and a display driver. The display screen may include a display control module, an image storage unit, and a display panel.

[0103] For example, the display control module may be a display driver integrated circuit (DDIC). It should be noted that the display control module may also be referred to as a display screen controller, drive circuit, etc., and this application embodiment does not specifically limit it in this way.

[0104] For example, the image storage unit can be random access memory (RAM), such as graphics RAM (GRAM).

[0105] The following explanation will use DDIC as an example, where the display control module is a display controller and GRAM is the image storage unit.

[0106] Electronic devices can perform image processing flows such as drawing, rendering, and compositing through a System-on-a-Chip (SoC) to obtain images. For example, image compositing can be performed through the SurfaceFlinger within the SoC. Then, the electronic device sends (i.e. writes) image data to the GRAM in the display screen through the display driver in the SoC. Finally, the DisplayDriver (DDIC) refreshes (i.e. reads) the image data from the GRAM onto the display panel, thus achieving image display.

[0107] Among them, DDIC can control the writing and reading of image data in GRAM through the Tear Effect (TE) signal.

[0108] See Figure 2 The TE signal can be a periodic pulse signal. When the DDIC completes a frame refresh on the display panel, it generates a TE signal, triggering the display driver to write the new frame of image data into the GRAM. For example, the display driver detects the rising edge of the TE signal, such as... Figure 2 After the TE (above) signal arrives, the image data of the new frame can be written into the GRAM within the time period of the image sending (short for sending image data from the display driver to the GRAM) flag X.

[0109] Subsequently, DDIC can refresh the image data of the new frame in GRAM onto the display panel, allowing the display panel to show the new frame of image. For example, after the falling edge of the TE signal arrives, as... Figure 2 After the TE (below) arrives, the image data of the new frame in the GRAM can be refreshed to the display panel within the time period marked by the refresh flag Y (short for refreshing the image data in the GRAM to the display panel).

[0110] The display panel can be refreshed via a source signal. See also... Figure 2 After the falling edge of the TE signal arrives, the DDIC reads image data from the GRAM. At this time, the source signal generated by the display panel is high. This high level illuminates the corresponding pixels on the display panel based on the image data read by the DDIC, thus refreshing the image on the display panel. After refreshing, the display panel can pull the source signal low to reduce power consumption when not refreshing the image. It should be noted that during the phase when the source signal is low, the image will not be refreshed; this state can be called the hold state.

[0111] It should be noted that in actual implementation, DDIC can also read image data from GRAM before the falling edge of the TE signal arrives, and complete the reading of the entire image data before the falling edge of the TE signal arrives. In this way, after the falling edge of the TE signal arrives, the display panel can quickly refresh and display the new image.

[0112] In an 8T-LTPO screen, DDIC can generate Figure 3A The image shows a TE signal with a fundamental frequency of 360Hz. The fundamental frequency refers to the highest frequency in a periodic signal, and is also the most basic frequency component of the signal. Using 360Hz as the fundamental frequency means that 360Hz harmonics can be generated, such as TE signals with frequencies of 180Hz, 120Hz, 90Hz, and 60Hz.

[0113] For example, DDIC can generate such as Figure 3B The TE signal shown. That is, in Figure 3A Based on the 360Hz base frequency shown, a TE signal is generated every two TE signals (approximately 8.3ms), resulting in a 120Hz TE signal. This allows the DDIC to control the display driver to write image data to the GRAM approximately every 8.3ms. Correspondingly, the SoC (including applications, image compositors, display drivers, etc.) should generate one frame of image data approximately every 8.3ms, meaning the frame rate should be 120FPS to ensure new image data is written every 8.3ms.

[0114] For example, DDIC can generate, as shown in the example Figure 3C The TE signal shown. That is, in Figure 3A Based on the 360Hz base frequency shown, a TE signal is generated every five TE signals (approximately 16.6ms) to obtain a 60Hz TE signal. In this way, the DDIC can control the display driver to write image data to the GRAM approximately every 16.6ms. Correspondingly, the SoC (including applications, image compositors, display drivers, etc.) should generate one frame of image approximately every 16.6ms, i.e., the frame rate should be 60FPS, to ensure that new image data is written every 16.6ms.

[0115] In other words, DDIC can match different image frame rates on the SoC side by generating TE signals of different frequencies. For example, a 120Hz TE signal can match a frame rate of 120FPS, and a 60Hz TE signal can match a frame rate of 60FPS.

[0116] It can be understood that a frame rate of x FPS means that x frames of images are generated per second, and one frame of image is generated every (1000 / x) ms, which can also be understood as the frequency of image generation being x Hz. In the following text, the frame rate is expressed in Hz, such as a frame rate of 120Hz, a frame rate of 60Hz, etc. This is simply a conversion of the unit of frame rate from FPS to Hz, and does not mean that the frame rate is expressed in refresh rate (which is also in Hz).

[0117] The image display method provided in this application can be applied to scenarios where electronic devices always generate images at the same frame rate, such as always generating images at a frame rate of 60Hz. Alternatively, it can also be applied to scenarios where electronic devices switch frame rates to display images, such as switching from a frame rate of 60Hz to a frame rate of 120Hz. This article mainly uses the scenario of switching frame rates as an example for illustration.

[0118] For example, when an electronic device switches from playing a video in the foreground to returning to the desktop, it switches from the frame rate of the video playback to the frame rate of the desktop display.

[0119] For another example, from the display of a motion effect to the display of a static image after the motion effect ends, the electronic device will switch from the frame rate of displaying the motion effect to the frame rate of displaying the static image.

[0120] In some implementations, when there is a need to switch frame rates, the display driver can send a frame rate switching command (referred to as a frame-switching command) to the DDIC. Upon receiving the frame-switching command, the DDIC can respond to the command at a frequency of 360Hz (approximately a 2.7ms period) during a phase without refreshing the image (i.e., the hold phase mentioned earlier), adjusting the frequency of the TE signal to achieve frame rate switching. However, in this implementation, since the timing of sending the frame-switching command to the DDIC is not controlled, the DDIC may respond to the command before the TE signal arrives, resulting in an unexpected frame rate after the frame rate switch.

[0121] See Figure 4 If a switching frame rate of 60Hz to 120Hz is required at time t1, then the expected TE signal generated by DDIC is as follows: until the next TE signal TE0 after time t1 arrives, a 60Hz TE signal is generated; after the arrival of the TE0 signal, the TE signal is switched to 120Hz.

[0122] In practice, see Figure 5 Before switching frame rates, the DDIC generates a 60Hz TE signal. After a request to switch from 60Hz to 120Hz is generated at time t1, the display driver sends a frame-switching command to the DDIC. Upon receiving the command, the DDIC reaches a 2.7ms interval at time t2, at which point it responds by adjusting the TE signal frequency to 120Hz. Subsequently, the DDIC generates a 120Hz TE signal. During this switch from 60Hz to 120Hz, an abnormal 90Hz frame is generated.

[0123] Obviously, with Figure 4 Compared to the expected situation shown: Figure 5 The actual situation shown is that a frame rate of 90Hz occurred, which is an unexpected frame rate.

[0124] In other implementations, when there is a need to switch frame rates, the display driver can use an asynchronous thread to send a frame-switching command to the DDIC after detecting the arrival of the TE signal; that is, sending the frame-switching command synchronously (sync-TE). Upon receiving the frame-switching command, the DDIC immediately responds by adjusting the frequency of the TE signal, thereby completing the frame rate switch. In this way, by controlling the timing of the frame-switching command, the display driver ensures that the DDIC switches the frame rate at the beginning of a new frame, thus avoiding unexpected frame rates.

[0125] See Figure 6Before switching frame rates, the DDIC generates a 60Hz TE signal. After a frame rate switching requirement from 60Hz to 120Hz is generated at time t1, the display driver, via an asynchronous thread, sends a frame-switching command to the DDIC when it detects the next TE signal TE0 at time t3. Upon receiving the frame-switching command at time t3, the DDIC responds by adjusting the frequency of the TE signal to 120Hz. Subsequently, the DDIC generates a 120Hz TE signal.

[0126] However, Figure 6 The scenario shown is only an ideal one. In practice, the implementation method of sending frame-switching instructions via asynchronous threads and synchronous TE signals may encounter the following problems:

[0127] Question 1: Asynchronous threads have lower priority and are usually more affected by system scheduling. When system resources are scarce, there are not enough resources to allocate to asynchronous threads, making it impossible for them to send frame-switching commands to DDIC at specific times (such as time t3 mentioned above), resulting in frame-switching delays.

[0128] Question 2: In some implementations, the display driver also sends backlight adjustment commands to the DDIC via the synchronous TE signal. If there is a need to adjust the backlight and also a need to switch the frame rate, the display driver may conflict when sending the backlight adjustment command and the frame switching command to the DDIC via the same synchronous TE signal. This may cause the frame switching command to be unable to be sent to the DDIC in a timely manner, resulting in frame switching delay.

[0129] Question 3: If the system enters a sleep state after the asynchronous thread is triggered, some resources used by the asynchronous thread to send frame-switching commands may be discarded, causing the frame-switching commands to fail to be sent and affecting frame rate switching. Additionally, it is unknown whether the asynchronous thread will receive the TE signal after the system enters a sleep state. If the TE signal is not received, the frame-switching command will not be sent, also causing frame-switching delay.

[0130] To address the aforementioned issues, this application provides an image display method in which the DDIC continuously generates a 360Hz TE signal without needing to adjust the TE signal frequency based on the frame rate. The display driver can detect the TE signal based on frame rate requirements, such as detecting the TE signal once every frame length corresponding to the frame rate, and then executing image display upon detection. In this way, the frame rate can be controlled by adjusting the timing of TE signal detection by the display driver.

[0131] After switching the frame rate, the display driver can detect the TE signal according to the switched frame rate, which can also meet the frame rate requirements after the switch.

[0132] For example, the frame rate before the switch is 60Hz. The display driver can detect the TE signal every 5 TE signals and send the image when the TE signal is detected, thereby meeting the frame rate requirement of 360 / (5+1)Hz (i.e., 60Hz before the switch). The frame rate after the switch is 120Hz. The display driver can detect the TE signal every 2 TE signals and send the image when the TE signal is detected, thereby meeting the frame rate requirement of 360 / (2+1)Hz (i.e., 120Hz after the switch).

[0133] In summary, by employing the embodiments of this application, the display driver does not need to send frame-switching commands to the DDIC, thereby avoiding the problems caused by the display driver sending frame-switching commands to achieve frame rate switching, and achieving accurate and timely frame rate switching. Furthermore, since the display driver does not need to send frame-switching commands to the DDIC, the power consumption on the SoC side caused by sending frame-switching commands can also be reduced.

[0134] For example, the electronic devices in this application embodiment may be mobile phones, tablets, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, and / or smart city devices, etc., that have image processing and display requirements. This application embodiment does not impose any special limitations on the specific form of the electronic device.

[0135] See Figure 7 This is a hardware structure diagram of an electronic device. For example... Figure 7 As shown, taking a mobile phone as an example, the electronic device may include a processor 210, an external memory interface 220, an internal memory (RAM) 221, a universal serial bus (USB) interface 230, a charging management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc.

[0136] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the mobile phone. In other embodiments, the mobile phone may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0137] The processor 210 may include one or more processing units, such as an application processor (AP), a modem, a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), and / or a neural network processing unit (NPU).

[0138] Different processing units can be independent devices or integrated into one or more processors. For example, an AP can integrate a CPU, GPU, etc.

[0139] In some embodiments, the processor 210 can execute an image display method by running instructions stored in the internal memory 221.

[0140] In addition, one or more processing units in the aforementioned processor 210, as well as other components of the mobile phone (such as memory, input / output interfaces, etc.), can be integrated into the SoC.

[0141] The charging management module 240 receives charging input from the charger. The power management module 241 connects the battery 242, the charging management module 240, and the processor 210. The power management module 241 receives input from the battery 242 and / or the charging management module 240, providing power to the processor 210, internal memory 221, display screen 294, camera 293, and wireless communication module 260, etc. The power management module 241 can also monitor parameters such as battery capacity, battery cycle count, and battery health status.

[0142] The wireless communication function of a mobile phone can be implemented through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, modem processor, and baseband processor.

[0143] Mobile phones can achieve display functions through GPU, display screen 294, and application processor. The GPU is a microprocessor for image processing, connecting the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering.

[0144] Mobile phones can achieve camera functions through cameras 293, ISP, video codecs, GPU, display panels 294, application processors (AP), neural network processors (NPU), etc.

[0145] Mobile phones can perform audio functions, such as music playback and recording, through an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, and an application processor.

[0146] Display screen 294 is used to display images, videos, etc. Display screen 294 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, a mobile phone may include one or more displays screens 294.

[0147] The display screen 294 also includes driving circuitry and a storage unit (such as GRAM, which will be used as an example below). The GRAM can be used to store image data of the image to be displayed.

[0148] For details on the functions and working principles of the display panel, DDIC, and GRAM, please refer to the previous text. Figure 1 and Figure 2 The details and related information will not be elaborated here.

[0149] The software system of the aforementioned electronic device (such as the software system on the AP side) can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses a layered architecture based on Android. TM Taking a system as an example, this section illustrates the software structure of an electronic device. A layered architecture divides the software system of an electronic device into several layers, each with a clear role and function, and the layers communicate with each other through software interfaces.

[0150] See Figure 8 Taking a mobile phone as an example, the hardware and software architecture of an electronic device can include the Application Layer, Application Framework Layer, Native Layer, Hardware Abstraction Layer (HAL), Kernel Layer, and Hardware Layer. Among them, the Application Layer, Application Framework Layer, Native Layer, and Hardware Abstraction Layer belong to user space, while the Kernel Layer and Hardware Layer belong to kernel space.

[0151] The application layer can accommodate various applications such as email, video player, memo, alarm clock, settings, and games. When these applications are running in the foreground, the screen can refresh to display multiple frames of images. For example, a game application can display multiple frames of game footage through screen refresh.

[0152] The application layer may also include an Adaptive Power Saving (APS) module. It should be noted that APS can also be called an adaptive energy-saving module, an adaptive low-power module, etc., and this application does not specifically limit it to these terms.

[0153] APS can be used to identify the current operating scenario of an electronic device and, based on this scenario, notify the underlying layer to perform frame rate control. For example, after APS identifies (e.g., based on information from the underlying activity manager) that the device has transitioned from the desktop to playing a video through a video player, it can notify the underlying layer to perform a frame rate switch.

[0154] APS can also be used to control the frame rate based on the temperature of the electronic device. For example, the frame rate can be limited in high-temperature conditions.

[0155] Furthermore, the APS may include the following modules: a scene recognition module, a temperature control logic module, and a frame rate control module. The scene recognition module identifies the current operating scene of the electronic device. The temperature control logic module maintains the control logic for adjusting the frame rate based on temperature, acquires the current temperature of the electronic device, and determines a control strategy in the control logic that matches the current temperature. The frame rate control module notifies the underlying layer of the identified operating scene or the determined control strategy so that the underlying layer can perform frame rate control.

[0156] The application framework layer provides the application programming interface (API) and programming framework for the application layer. The application framework layer includes some predefined functions.

[0157] The application framework layer can include system services such as the window manager, activity manager, and resource manager.

[0158] The native layer includes the advanced graphics platform (AGP), the image synthesizer (SurfaceFlinger, SF), and so on.

[0159] AGP can be used for frame rate management, refresh rate adjustment, etc. For example, AGP can determine the frame rate level (i.e., determine the frame rate) based on the current operating scenario of the electronic device and send the determined frame rate to the image synthesizer.

[0160] In some embodiments, the frame rates controlled in AGP include, but are not limited to, at least two of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz, and 1Hz. These frame rates can all be multiplied from a base frequency of 360Hz. The DDIC then generates a 360Hz TE signal. The display driver can control the timing of TE signal detection to meet the various frequency requirements in AGP. For example, detecting every two TE signals can meet the 120Hz frame rate requirement; detecting every three TE signals can meet the 90Hz frame rate requirement; detecting every five TE signals can meet the 60Hz frame rate requirement; and detecting every eleven TE signals can meet the 30Hz frame rate requirement, and so on.

[0161] Furthermore, AGP can include a smart frame rate module to determine the frame rate based on the running scenario.

[0162] The SurfaceFlinger (SF) image compositer can be used for layer compositing, backlighting, screen brightness control, etc. It should be noted that the image compositer can also be translated as surface thrower, surface drawing module, image compositing processing service, etc., and this application does not specifically limit it to these terms.

[0163] For example, the image compositor can assign compositing tasks to the layers drawn by the application, distributing these tasks to the Hardware Composer (HWC) in the Hardware Abstraction Layer or the GPU. For instance, if the compositing task includes tasks such as rounded corner cropping, it can be assigned to the GPU for image compositing; if the compositing task only includes simple layer overlay tasks, it can be assigned to the HWC. This allows for control over image compositing.

[0164] The image synthesizer can also calculate the Expected Display Time (EPT). The Expected Display Time refers to the expected time for the display driver to send a new frame of image to the display screen (simply put, the image sending time), which can also be understood as the expected processing time to obtain (generate) a new frame of image.

[0165] Expected display time is commonly used in Variable Refresh Rate (VRR) technology. In VRR, by calculating the expected display time, the image compositor can predict when to start layer composition, so that a new frame can be prepared before the expected display time, thereby avoiding frame drops or tearing.

[0166] See Figure 9 The image compositer calculates the expected display time of image A as Ta. Based on Ta, it can predict the start time for layer composition of image A as Taa. This allows all pre-display processing of image A to be completed before Ta, such as the image compositer completing layer composition of image A and the display driver completing pre-display preparations for image A. Thus, before Ta, the image compositer, display driver, etc., can complete all processing of image A. Then, after detecting the TE signal, the display driver can send the processed image A to the display screen, where image A can be displayed.

[0167] See also Figure 9 The image synthesizer calculates the expected display time of image B as Tb. Based on Tb, the time to start layer synthesis of image B can be estimated as Tbb, allowing all processing of image B before its delivery to be completed before Tb. Thus, before Tb, the image synthesizer, display driver, and other components can complete all processing of image B. Then, after detecting the TE signal, the display driver can send the processed image B to the display screen, where it can display image B.

[0168] See also Figure 9 The image synthesizer calculates the expected display time of image C as Tc. Based on Tc, the time for starting layer synthesis of image C can be estimated as Tcc, allowing all processing of image C before its delivery to the display screen to be completed before Tc. Thus, before Tc, the image synthesizer, display driver, and other components can complete all processing of image C. Then, after detecting the TE signal, the display driver can send the processed image C to the display screen, which can then display image C.

[0169] The image synthesizer can calculate the expected display time based on the frame rate (such as the frame rate determined by AGP mentioned above). For details on the specific implementation of calculating the expected display time, please refer to the relevant explanations below; further details will not be provided here.

[0170] Therefore, the following two points need to be explained:

[0171] First, the expected display time is the anticipated display time of the obtained image. Theoretically, this expected display time is the same as the moment when the display driver detects the next TE signal and triggers image transmission. Figure 9 The diagram shows the case where the expected display time equals the actual display time. However, in reality, the expected display time may deviate from the moment the display driver detects the next TE signal.

[0172] Second, after the display driver sends the image to the display screen, the display screen can refresh and display the image only after the refresh time arrives, such as after the falling edge of the TE signal. In other words... Figure 9 The time when the central display screen starts showing each frame of the image can be delayed by a certain amount.

[0173] Furthermore, the image compositer may include the following modules: a layer compositing module and a frame rate setting module. The layer compositing module is used to composite layers with content drawn by the application. The frame rate setting module is used to send the expected display time to the underlying layer (such as the display driver), allowing the underlying layer to control the timing of image delivery to meet frame rate requirements.

[0174] The Hardware Abstraction Layer (HWC) can encapsulate kernel-level drivers, providing calling interfaces to higher layers. The HWC can include HWC. HWC can be used for image compositing processing and for providing the composited image data to the display driver. It should be noted that image data obtained from GPU-composited images can also be provided to the display driver via HWC.

[0175] HWC can also be used to transmit the expected display time to the underlying layer, such as the display driver.

[0176] The kernel layer (also known as the driver layer) includes drivers that enable the hardware to function. Specifically, the kernel layer includes display control commit modules (such as CRTC commit) and display drivers (such as the LCD Driver).

[0177] The display control submission module can be used for information transfer between the upper layer and other modules in the driver layer to achieve display control. For example, the display control submission module can transmit the expected display time, image, etc., to the display driver. As another example, the display control submission module can also transmit images to the projection driver (not shown in the figure).

[0178] The display driver can be used to send the synthesized image data to the display screen. Specifically, the display driver can detect the TE signal based on the expected image transmission time and trigger the image transmission to the display screen, thus ensuring that the image transmission timing is consistent with the frame rate.

[0179] It should be noted that for the specific implementation of detecting the TE signal based on the expected delivery and display time, please refer to the following text (e.g. Figure 10A The relevant explanations (and their context) will not be elaborated on here.

[0180] It should be noted that upper layers (such as AGP or image compositors) can also send the frame rate (such as the switched frame rate) to the display driver. Subsequently, the display driver can directly detect the TE signal based on the frame rate. For example, the display driver can add the frame length corresponding to the frame rate to the time point of each TE signal detection, thereby determining the time point of the next TE signal detection. This can also meet the frame rate requirements. In the following text, the solution of this application will mainly be illustrated by taking the display driver detecting the TE signal based on the expected display delivery time as an example.

[0181] The hardware layer may include hardware such as CPU, GPU, and display screen (further including display panel, DDIC, GRAM, etc.).

[0182] It is understandable that the above Figure 7 and Figure 8 In descriptions of electronic devices, the division of hardware and software modules is exemplary and not a limitation in practice. For example, the core display driver function described in this article may be implemented by other modules or merged into other modules.

[0183] The image display method provided in this application can be executed in an electronic device having the above-described hardware and software structure. The specific implementation of the image display method will be further described in detail below with reference to the accompanying drawings.

[0184] See Figure 10A The process of sending and displaying one frame of an image includes:

[0185] The S1000 displays generate a 360Hz TE signal.

[0186] That is, the display maintains the generation of a 360Hz TE signal throughout the entire process, without needing to adjust the frequency of the TE signal generation based on frame-switching instructions.

[0187] S1001, In response to the Vsync-SF signal, the image synthesizer calculates the expected display time of the image based on the current frame rate.

[0188] The Vsync-SF signal can be used to control the image compositer to perform layer compositing.

[0189] The Vsync-SF signal can be a clock signal. After detecting the TE signal, the display driver can report it to the image compositor. The image compositor can simulate the Vsync-SF signal based on the TE signal reported by the display driver, and after generating the Vsync-SF signal, it triggers the image compositor to start layer compositing of the image, so that the frequency of the synthesized image is consistent with the frequency of the image sent to the display after the TE signal is detected.

[0190] Furthermore, there is an offset between the Vsync-SF signal simulated by the image synthesizer and the TE signal reported by the display driver. See also Figure 10B There is a 3ms offset between the Vsync-SF signal and the reported TE signal. It should be noted that this offset is pre-configured and can vary at different frame rates. For example, at a frame rate of 120Hz, the offset is 2ms, and at a frame rate of 60Hz, the offset is 3ms.

[0191] If the image compositor detects the Vsync-SF signal, it indicates that layer composition of the image can begin. The image compositor can calculate the expected display time of the image based on the current frame rate.

[0192] In scenarios with a constant frame rate, the current frame rate can be that constant frame rate, such as always being 60Hz. Alternatively, in scenarios with a variable frame rate, before switching frame rates, the current frame rate is the frame rate before the switch, such as 60Hz; after switching frame rates, the current frame rate is the frame rate after the switch, such as 120Hz.

[0193] The expected display time Ta can be used by the image synthesizer to estimate the time point for the layer synthesis of the starting image A (as shown in S1002 below), and can also be used by the display driver to determine the timing of detecting the TE signal (as shown in S1007 below).

[0194] The image synthesizer can calculate the expected display time of the image by adding the period and offset corresponding to the current frame rate to the time point at which the Vsync-SF signal is detected. See also... Figure 10B Taking the time point when the Vsync-SF signal is detected as t4, the current frame rate as 120Hz (period as 8.3ms), and the offset as 3ms as an example, the expected display time of the image = t4 + 8.3ms + 3ms.

[0195] It should be noted that the above-described implementation method for calculating the expected display time based on frame rate is merely exemplary. In actual implementation, those skilled in the art can use relevant existing technologies to calculate the expected display time based on frame rate. This application does not impose any specific limitations on this implementation.

[0196] S1002, The estimated start time for layer composition based on the expected display time.

[0197] For example, all processing before image submission (such as layer compositing, pre-submission preparation, etc.) takes approximately X time, and the image compositer can anticipate that the start time for layer compositing is before (Ta-X).

[0198] S1003. In response to the arrival time of layer composition, the image compositer performs layer composition on the layers with drawn content to obtain an image.

[0199] For example, after each application running in the foreground completes its drawing and rendering processes, it can obtain layers with drawn content. The image compositor can then obtain these layers with drawn content and composite them to create an image.

[0200] The image compositer performs layer compositing at the time of layer compositing, allowing all pre-send processing to be completed before the expected display time.

[0201] S1004, The image synthesizer sends an image to the display driver.

[0202] In this way, the display driver obtains the image to be displayed.

[0203] S1005, Display driver performs preparations before sending the image.

[0204] The preparations before sending the image include initializing the hardware image sending registers and initializing the image sending timing.

[0205] After completing the preparations before sending the image, the conditions for sending the image are met. For example, after completing the preparations before sending the image, the display driver can enter a state waiting for the TE signal, such as a wait completion event state. Based on this, it can be determined whether the preparations before sending the image are complete by whether the display driver enters the wait for the TE signal state.

[0206] S1006, The display driver obtains the expected display time from the image synthesizer.

[0207] Subsequently, the display driver can detect the TE signal based on the expected display delivery time.

[0208] It should be noted that the timing of S1006 execution is not based on... Figure 10A The above is a limited description. In practice, the image synthesizer can actively send the expected display time to the display driver at any time after calculating the expected display time (such as after S1001) and before the display driver starts detecting the TE signal (such as before S1007 below), or send the expected display time to the display driver based on the display driver's request, so that the display driver can obtain the expected display time.

[0209] S1007, The display driver detects the TE signal based on the expected display delivery time.

[0210] In some embodiments, the display driver can detect the TE signal when the expected display time arrives, thereby detecting the TE signal of the expected display time and meeting the frame rate requirements.

[0211] In other embodiments, the display driver can delay the detection of the TE signal by a preset time before the expected display time. For example, if the preset time is 2ms, the display driver can start detecting the TE signal 2ms before the expected display time. In this way, the display driver can start detecting earlier and avoid missing the TE signal.

[0212] The preset time is less than the period of the TE signal generated by DDIC. Taking 360Hz as an example, its period is 2.7ms, so the preset time is less than 2.7ms. In this way, the display driver will not mistakenly detect the TE signal generated before the expected display time, thus ensuring accurate detection of the TE signal at the expected display time and meeting the frame rate requirements.

[0213] The following text mainly uses the example of starting to detect the TE signal at a preset time before the expected display time to illustrate the solution of this application.

[0214] S1008. In response to the detection of the TE signal, the display driver sends an image to the display screen.

[0215] It should be noted that after detecting the TE signal, the display driver can also report the TE signal to the upper layer, such as the image synthesizer, so that the image synthesizer can simulate the Vsync-SF signal and calculate the expected display time of the new frame image.

[0216] S1009, The display screen shows an image.

[0217] It is understandable that the above Figure 10A The interactive flow describes the process of sending and displaying a single frame of an image. In practice, each frame of an image can be sent and displayed according to this flow, thus meeting the frame rate requirements.

[0218] In the process of displaying a frame of an image, if there is a need to switch the frame rate (denoted as switching from frame rate M to N), the image synthesizer can also obtain the switched frame rate N for displaying subsequent frames of images, such as for calculating the expected display time and detecting the TE signal.

[0219] See Figure 10C On the one hand, electronic devices can use S1000-S1009 to display one frame of image. It should be noted that before switching frame rates, the current frame rate is frame rate M. For a detailed implementation of S1000-S1009, please refer to [link to documentation / reference]. Figure 10A The relevant explanations will not be repeated here.

[0220] See also Figure 10C On the other hand, the electronic device may also employ the following S1021-S1024 to enable the image synthesizer to obtain the switched frame rate N.

[0221] S1021, APS recognizes changes in the operating scenario.

[0222] For example, after a new service is running in the foreground of an electronic device, the Activity Manager can notify the Action Planning System (APS), which then recognizes the change in the running scenario based on the new service.

[0223] Switching between foreground applications, or switching services within a currently running foreground application, will both launch a new service. For example, switching from the desktop to the main interface of a video player is equivalent to starting the service that displays the main interface of the video player. Similarly, switching from displaying a static video player interface to playing a video is equivalent to starting the service that plays the video.

[0224] S1022, APS sends the changed operating scenario to AGP.

[0225] S1023, AGP determines the frame rate N after the switch based on the changed operating scenario.

[0226] For example, AGP maintains a list of relationships between running scenarios and frame rates. By querying the frame rate corresponding to the changed running scenario, AGP can determine the frame rate N after the switch.

[0227] S1024, AGP sends frame rate N to the image synthesizer.

[0228] It should be noted that S1021-S1024 will be executed after the operating scenario changes. In other words, the execution timing of S1021-S1024 is not necessarily related to the execution timing of S1001-S1009.

[0229] After the above steps S1021-S1024, which enable the image synthesizer to obtain the switched frame rate N, the image display time can be calculated based on the frame rate N during the subsequent display of each frame. For example, steps S1000-S1009 can still be used, but the current frame rate is switched to frame rate N, which allows the detection and display of the TE signal based on frame rate N.

[0230] Furthermore, the display driver can enable or disable the detection of TE signals generated by the display screen by switching the image source.

[0231] See Figure 11 The above S1007 may further include S1101-S1102:

[0232] S1101, The display driver delays to a preset time before the expected display delivery time.

[0233] S1102. In response to the delay, the display driver switches the image source to a hardware TE signal. When the image source is a hardware TE signal, the display driver detects the TE signal generated by the display screen.

[0234] Here, the hardware TE signal refers to the TE signal generated by the display screen, such as the 360Hz TE signal generated by the DDIC mentioned above. It should be noted that unless otherwise specified, Figure 11 The TE signals mentioned earlier all refer to the TE signals generated by the display screen.

[0235] Here, "image source" refers to the trigger signal for image transmission. The image source includes the hardware TE signal. By default, the image source is the hardware TE signal. Using the hardware TE signal as the image source indicates that the TE signal generated by the display screen is used as the trigger signal for image transmission; that is, image transmission is triggered when the TE signal generated by the display screen is detected.

[0236] After the delay is reached, the display driver can start detecting the TE signal generated by the display screen by switching the image source to the hardware TE signal, thereby detecting the TE signal of the expected display time.

[0237] After detecting the TE signal generated by the display screen, the image can be sent via S1103 and the display can be performed via S1104.

[0238] S1103. In response to detecting the TE signal generated by the display screen, the display driver sends an image to the display screen.

[0239] S1104, The display screen shows an image.

[0240] After the image is sent, as in S1103, the electronic device can disable the detection of the TE signal generated by the display screen through S1105 and S1106 as described below.

[0241] S1105, The display driver initializes the software TE signal based on the current frame rate.

[0242] In some embodiments, after obtaining the current frame rate, such as obtaining frame rate M or obtaining frame rate N through the above S1024, the image synthesizer can send the current frame rate to the display driver.

[0243] The software TE signal is a software signal generated on the SoC side. The software TE signal can be a clock signal, i.e., a signal generated at a specific timing interval. Here's a brief explanation of the software TE signal and Vsync_SF: both are software signals, and both are software signals simulated based on the hardware TE signal. The software TE signal is generated by the kernel layer on the SoC side, and its generation time is the same as the time the display driver detects the hardware TE signal. The Vsync_SF signal is generated by the image compositor on the SoC side, and there is an offset between the generation time of the Vsync_SF signal and the time the display driver detects the hardware TE signal, as mentioned earlier. Figure 10B As shown.

[0244] The display driver initializes the software TE signal, mainly in two ways: First, it initializes the timer, starting the countdown from the moment the TE signal generated by the display is detected. Second, it sets the timer's duration based on the current frame rate, with the duration equal to the frame length corresponding to the frame rate. This ensures that the software TE signal is generated at the same time as the expected display time of the next frame, preventing the detection of the software TE signal and triggering image transmission before the expected display time of the next frame, thus meeting the frame rate requirements.

[0245] Taking a current frame rate of 120Hz as an example, if the display driver detects the TE signal generated by the display screen at time x0, it can initialize the timer at time x0, so that the timer starts counting from time x0, and the timing duration of the timer is 8.3ms, which corresponds to the frame length of 120Hz. Then, the time when the software TE signal is generated is 8.3ms after time x0.

[0246] S1106, The display driver switches the image source to a software TE signal. When the image source is a software TE signal, the software TE signal is detected, and the TE signal generated by DDIC is not detected.

[0247] In other words, the image transmission source also includes the software TE signal. The image transmission source being the software TE signal indicates that the software signal generated on the SoC side is used as the trigger signal for image transmission, that is, image transmission is triggered when the software TE signal is detected.

[0248] In addition, after switching the image source to the software TE signal, the display driver no longer detects the TE signal generated by the display screen, which is equivalent to turning off the detection of the TE signal generated by the display screen.

[0249] Using the above Figure 11In the interaction process, the display driver indirectly enables and disables the detection of TE signals generated by the display screen by switching the image source. Furthermore, disabling the detection of TE signals generated by the display screen allows the display driver to detect TE signals at time intervals consistent with the frame rate, without increasing the power consumption of the display driver for TE signal detection due to the generation of a 360Hz TE signal. For example, if the display screen generates a 360Hz TE signal, the period of the TE signal generation is 2.7ms. With a frame rate of 60Hz, the display driver can detect the TE signal at time intervals of approximately 16.6ms, instead of needing to detect the TE signal every approximately 2.7ms.

[0250] Therefore, it should be noted that extensive practical experience shows that directly enabling or disabling the detection of the TE signal generated by the display screen, such as turning the detection switch on or off, results in a high latency, which may lead to inaccurate detection of the TE signal. However, by switching the image source, the detection of the TE signal generated by the display screen can be quickly enabled or disabled, thereby achieving accurate detection of the TE signal.

[0251] Below, in conjunction with Figure 12 Specific examples, for the above Figures 10A-11 We will provide a complete overview of the proposed solution.

[0252] See Figure 12 Before the switch, the frame rate M was 60Hz, and after the switch, the frame rate N was 120Hz.

[0253] Before the switch, the current frame rate is 60Hz. The display process in Figure A is shown below:

[0254] Execute S1001-S1005: The image synthesizer calculates the expected display time Ta of image A based on 60Hz, synthesizes image A based on the expected display time Ta, and the display driver obtains the synthesized image A and completes the preparation for sending image A at time T1.

[0255] Execute S1006-S1101: The display driver obtains the expected display time Ta of Figure A and delays it to da = (Ta - 2ms).

[0256] Execute S1102: When the delay time da = (Ta - 2ms) is reached, the display driver switches the image source to the hardware TE signal.

[0257] Execution S1103-S1104: When TE1 is detected near time Ta, the display driver sends Figure A to the display screen for display.

[0258] Furthermore, after detecting TE1, the display driver can also switch the image source to a software TE signal, as shown below:

[0259] Execution S1105-S1106: The display driver initializes the timer, starting from the moment TE1 is detected (theoretically the same as time Ta). The timer duration is set to 16.6ms, corresponding to a frame length of 60Hz. Therefore, the time when the software TE signal is generated is approximately Ta+16.6ms, which theoretically coincides with the expected display time of the next frame (as shown in Figure B). Thus, before the expected display time of the next frame, the display driver will not trigger image transmission due to the detection of the software TE signal, thereby controlling the frame rate. Furthermore, the display driver switches the image transmission source to the software TE signal. This disables the detection of TE signals generated by the display screen, preventing the display driver from detecting TE signals in the 360Hz TE signal generated by the display screen that do not match the 60Hz frame rate, such as TE signals generated by the display screen after Ta and before Ta+16.6ms.

[0260] During the switching process, the current frame rate remains at 60Hz. The display process in Figure B is shown below:

[0261] Execute S1000-S1005: The image synthesizer calculates the expected display time Tb of image B based on 60Hz. Based on the expected display time Tb, it is expected that image B will be synthesized at time T2. The display driver obtains the synthesized image B and completes the preparation for sending image B at time T3.

[0262] Execute S1006-S1101: The display driver obtains the expected display time of Figure B as Tb and delays it to db = (Tb-2ms).

[0263] Execution S1102: When the delay time db = (Tb - 2ms) is reached, the display driver switches the image source to the hardware TE signal. It should be noted that at db = (Tb - 2ms), the generation time of the software TE signal, Ta + 16.6ms, has not yet been reached; therefore, no software TE signal is generated, and correspondingly, the display driver does not detect the software TE signal. In other words, after switching the image source to the software TE signal, no software TE signal is detected, and the driver switches back to the hardware TE signal.

[0264] Execution S1103-S1104: When TE2 is detected near time Tb, the display driver sends Figure B to the display screen for display.

[0265] Furthermore, during the display process of Figure B above, if a frame rate switching requirement arises at time t1 between time T2 and time T3, the changed frame rate of 120Hz also needs to be notified to the image synthesizer. The details are as follows:

[0266] Executions S1021-S1024: The image synthesizer obtains the switched frame rate of 120Hz. Thus, during the display of subsequent image frames (as shown in Figure C below), the expected display time can be calculated based on 120Hz. Additionally, the image synthesizer can synchronize the 120Hz frame rate to the display driver so that the display driver can initialize the software TE signal.

[0267] It should be noted that at time t1 between time T2 and time T3, a frame rate switch from 60Hz to 120Hz occurs. The image synthesizer obtains the switched frame rate, but since the processing flow of Figure B (such as compositing and preparation before image transmission) has already started from time T2, the switched frame rate of 120Hz will not be applied to the processing flow of Figure B. Furthermore, the expected transmission time Tb of Figure B is also calculated based on the original frame rate of 600Hz. When the display driver starts detecting the TE signal near time Tb (e.g., from the delay time db), it is still detecting the TE signal based on the original frame rate of 60Hz. Therefore, although a frame rate switch is required during the processing and transmission of Figure B, and both the image synthesizer and the display driver obtain (e.g., near time t1) the switched frame rate, the processing and transmission of Figure B are not affected by the switched frame rate.

[0268] Furthermore, after detecting TE2, the display driver can also switch the image source to a software TE signal, as shown below:

[0269] Execution S1105-S1106: The display driver initializes the timer, starting from the moment TE2 is detected (theoretically the same as time Tb). Based on the switched frame rate of 120Hz obtained near time t1, the timer's duration is set to the frame length of 8.3ms corresponding to 120Hz. Therefore, the software TE signal is generated at Tb+8.3ms, which theoretically coincides with the expected display time of the next frame (as shown in Figure C). Thus, before the expected display time of the next frame, the display driver will not trigger image transmission due to the detection of the software TE signal, thereby controlling the frame rate. Furthermore, the display driver switches the image transmission source to the software TE signal. This disables the detection of TE signals generated by the display screen, preventing the display driver from detecting TE signals in the 360Hz TE signals generated by the display screen that do not match the 120Hz frame rate, such as TE signals generated by the display screen after Tb but before Tb+8.3ms.

[0270] It should be noted that the software TE signal is applied to the next frame. Therefore, after switching the frame rate to 120Hz, the display driver initializes the software TE signal based on 120Hz, so that the generation time of the software TE signal matches the switched 120Hz.

[0271] After switching, the current frame rate is 120Hz. The display process in Figure C is shown below:

[0272] Execute S1000-S1006: The image synthesizer calculates the expected display time Tc of image C based on the switched frame rate of 120Hz obtained near time t1, synthesizes image C based on the expected display time Tc, and the display driver obtains the synthesized image C and completes the preparation for sending image C at time T4.

[0273] Execution S1006-S1101: The display driver obtains the expected display time Tc for image C and delays it until dc = (Tc - 2ms). Execution S1102: When the delay time dc = (Tc - 2ms) is reached, the display driver switches the image source to the hardware TE signal. It should be noted that at dc = (Tc - 2ms), the generation time Tb + 8.3ms for the software TE signal has not yet been reached; therefore, no software TE signal is generated, and correspondingly, the display driver does not detect the software TE signal. In other words, after switching the image source to the software TE signal, no software TE signal is detected, and the display driver switches back to the hardware TE signal.

[0274] Execution S1103-S1104: When TE3 is detected near time Tc, the display driver sends graph C to the display screen for display.

[0275] It should be noted that Tc is calculated based on the switched frame rate of 120Hz. The image synthesizer starts layer synthesis based on Tc, and the display driver detects the TE signal based on time Tc. This means that the switched frame rate of 120Hz is effective in Figure C.

[0276] Furthermore, after detecting TE3, the display driver can also switch the image source to a software TE signal, as shown below:

[0277] Execution S1105-S1106: The display driver initializes the timer, starting from the moment TE3 is detected (theoretically the same as time Tc). The timer duration is set to 8.3ms, corresponding to a frame length of 120Hz. Therefore, the software TE signal is generated at Tc+8.3ms, which theoretically coincides with the expected display time of the next frame. Thus, before the expected display time of the next frame, the display driver will not trigger image transmission due to the detection of the software TE signal, thereby controlling the frame rate. Furthermore, the display driver switches the image transmission source to the software TE signal. This disables the detection of TE signals generated by the display screen, preventing the display driver from detecting TE signals in the 360Hz TE signals generated by the display screen that do not match the 120Hz frame rate, such as TE signals generated by the display screen after Tc and before Tc+8.3ms.

[0278] Therefore, although the display generates a 360Hz TE signal, the display driver only detects the TE signal that matches the frequency, such as... Figure 12 As shown in TE1, TE2 and TE3, frame rate switching can be achieved.

[0279] As explained above, the image compositer can estimate the start time of layer compositing based on the expected display time, allowing all image processing to be completed and displayed before the expected display time. However, in reality, due to various factors such as load, even if layer compositing is performed from the expected start time, there may still be issues where all image processing cannot be completed before the expected display time.

[0280] To address this issue, in some embodiments, before starting image transmission, the electronic device can detect whether the current time has exceeded the expected transmission time. If it has not, the image transmission is completed using the aforementioned embodiments. Conversely, if it has exceeded the time, it indicates that it is too late, and the electronic device can immediately begin detecting the TE signal generated by the display screen, such as switching the image transmission source to a hardware TE signal, and promptly transmit the image after detecting the TE signal generated by the display screen. Of course, after image transmission, the electronic device must still disable the detection of the TE signal generated by the display screen, such as switching the image transmission source to a software TE signal.

[0281] See Figure 13 For cases where the display time exceeds the expected time, the execution of S1000-S1005 also includes:

[0282] S1300, in response to the arrival of the timing period, the display driver detects the software TE signal.

[0283] As explained above, the display driver switches the image source to the hardware TE signal only after acquiring the image and completing the preparations before sending it. This ensures that the prepared image is sent to the display screen only after the TE signal generated by the display screen is detected. However, if the expected image transmission time is exceeded, and the preparations before sending the image are completed by the expected transmission time, the driver naturally does not switch to the hardware TE signal and continues to use the software TE signal. Therefore, when the expected image transmission time (which coincides with the timing) is reached, the software TE signal is generated, and the display driver can detect the software TE signal.

[0284] It should be noted that when the display driver detects the software TE signal, it will not trigger image transmission because the image is not ready.

[0285] See also Figure 13 After the display driver completes the preparations before sending the image and obtains the expected display time, such as after S1006, it also includes:

[0286] S1301, The display driver detects whether the expected display delivery time has been exceeded.

[0287] The current time may include the moment when preparations for sending the image are completed, or the moment when preparations for sending the image are completed and the expected display time is obtained.

[0288] If the expected display sending time has not been exceeded, the display driver can delay until the expected display sending time is approaching to start detecting the TE signal generated by the display screen and triggering the image sending, as shown in S1001-S1006, which will not be described in detail here.

[0289] If the expected display time is exceeded, the display driver can quickly start detecting the TE signal generated by the display screen and trigger the display to send the image, as shown in S1302-S1306 below.

[0290] S1302, the display driver switches the image source to a hardware TE signal.

[0291] S1303, In response to detecting the TE signal generated by the display screen, the display driver sends an image to the display screen.

[0292] S1304, The display screen shows an image.

[0293] After submitting the image, the detection of the TE signal generated by the display screen must still be turned off, as shown in S1305-S1306 below:

[0294] S1305, the display driver initializes the software TE signal based on the switched frame rate.

[0295] It should be noted that the timer always starts counting from the TE signal triggered by the circuit breaker. Accordingly, the timer will start counting from the TE signal detected in S1303.

[0296] S1306, the display driver switches the image source to a software TE signal.

[0297] Using the above Figure 13 The interactive process allows the display driver to detect whether the expected display time has been exceeded, enabling timely display of images even if image processing is not completed in time, thus reducing lag.

[0298] Below, in conjunction with Figure 14 Specific examples, for the above Figure 13 This will provide a complete overview of the plan. It should be noted that... Figure 14 The example given is that no frame rate switching was required during the display of Figures D and E. However, in reality, frame rate switching might occur during the display of Figures D and E. For instance, if a frame rate switching requirement arises during the display of Figure D, then Figure D can be understood as described above. Figure 12Figure B is shown in the image above, and Figure E is the next frame of Figure B.

[0299] See Figure 14 Taking the current frame rate of 60Hz as an example, the process of sending the display signal and initializing the software TE signal in Figure D includes:

[0300] Execute S1001-S1005: The image synthesizer calculates the expected display time Td of image D based on 60Hz, synthesizes image D based on the expected display time Td, and the display driver obtains the synthesized image D and completes the preparation for sending image D at time T5.

[0301] Execute S1006-S1301: The display driver obtains the expected display time Td of graph D and detects that time T5 is before time Td.

[0302] Execution S1101-S1106: When the delay time dd = (Td - 2ms) is reached, the display driver switches the image source to the hardware TE signal. When TE4 is detected near time Td, the display driver sends image D to the display screen. Furthermore, after TE4 is detected, the timer is initialized to start counting from time Td, and the timer duration is set to the frame length of 16.6ms corresponding to 60Hz. Therefore, the software TE signal is generated at Td + 16.6ms, and the image source is switched to the software TE signal.

[0303] The process of displaying Figure E and initializing the software TE signal includes:

[0304] Execute S1001-S1005: The image synthesizer calculates the expected display time Te of image E based on 60Hz, synthesizes image E based on the expected display time Te, and the display driver obtains the synthesized image E and completes the preparation for sending image E at time T6.

[0305] During the execution of S1001-S1005, S1300 is also executed: at time Td+16.6ms, the generation time of the software TE signal is reached, and at this time the image source is the software TE signal. The display driver can detect the software TE signal generated at time Td+16.6ms.

[0306] Execute S1006-S1301: The display driver obtains the expected display time Td of Figure D and detects that time T6 is after time Td.

[0307] Execute S1302: The display driver switches to hardware TE signal as the image source.

[0308] Execution S1303-S1304: When TE5 is detected near time Td', the display driver sends graph D to the display screen for display.

[0309] Execution S1305-S1306: The display driver initializes the timer, starting from the moment TE5 is detected (theoretically the same as time Td'). The timer duration is set to 16.6ms, corresponding to a frame length of 60Hz. Therefore, the software TE signal is generated at Td'+16.6ms. This allows for a delayed generation of the software TE signal even with delayed image transmission, ensuring consistency with the frame rate. Additionally, the display driver switches the image transmission source to the software TE signal, thereby disabling the detection of TE signals generated by the display screen.

[0310] Therefore, if image processing is not completed in time, the display driver may detect the software TE signal but will not send the image. In addition, the display driver will detect the hardware TE signal at a later time than the expected display time, thus enabling timely image sending.

[0311] This application also provides an electronic device, which may include a memory and one or more processors (such as a CPU, GPU, NPU, etc.). The memory and processor are coupled. The memory is used to store computer program code, which includes computer instructions. When the processor executes the computer instructions, the electronic device can perform various functions or steps performed by the device in the above method embodiments.

[0312] This application also provides a chip system, such as... Figure 15 As shown, the chip system 1500 includes at least one processor 1501 and at least one interface circuit 1502. The processor 1501 and the interface circuit 1502 are interconnected via lines. For example, the interface circuit 1502 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 1502 can be used to send signals to other devices (e.g., the processor 1501). Exemplarily, the interface circuit 1502 can read instructions stored in memory and send those instructions to the processor 1501. When the instructions are executed by the processor 1501, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, which are not specifically limited in this application embodiment.

[0313] This application also provides a chip system including at least one processor and at least one interface circuit. The processor and the interface circuit are interconnected via lines. For example, the interface circuit can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit can be used to send signals to other devices (e.g., the processor). Exemplarily, the interface circuit can read instructions stored in the memory and send the instructions to the processor. When the instructions are executed by the processor, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and this application does not specifically limit this.

[0314] This embodiment also provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the image processing method described above.

[0315] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the image processing method described above.

[0316] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the image processing methods in the above-described method embodiments.

[0317] In this embodiment, the electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0318] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0319] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0320] The unit described as a separate component may or may not be physically separate. The component shown as a unit can be one physical unit or multiple physical units, that is, it can be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of the solution in this embodiment according to actual needs.

[0321] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0322] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0323] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. An image display method, characterized in that, Applied to an electronic device, the electronic device including a SoC and a display screen, the display screen generating a hardware TE signal at a first frequency, the method includes: At a first moment, the display screen generates a first hardware TE signal, and in response to detecting the first hardware TE signal, the SoC sends a first image to the display screen; At a second moment, the display generates a second hardware TE signal. In response to detecting the second hardware TE signal, the SoC sends a second image to the display. The second moment is after the first moment, and the second image is the next frame of the first image. Specifically, after the first moment and before the second moment, the display generates at least one third hardware TE signal, and the SoC does not detect the at least one third hardware TE signal.

2. The method according to claim 1, characterized in that, The time interval between the first moment and the second moment is greater than or equal to the frame length corresponding to the first frame rate.

3. The method according to claim 2, characterized in that, The method further includes: At the third moment, the display generates a fourth hardware TE signal. In response to detecting the fourth hardware TE signal, the SoC sends a third image to the display. The third moment is prior to the first moment, and the third image is the previous frame of the first image. Specifically, between the third time point and the first time point, the SoC generates an instruction to switch the frame rate, and the time interval between the third time point and the first time point is greater than or equal to the frame length corresponding to the second frame rate.

4. The method according to claim 3, characterized in that, The method further includes: After the third time point and before the first time point, the display generates at least one fifth hardware TE signal, and the SoC does not detect the at least one fifth hardware TE signal.

5. The method according to claim 3 or 4, characterized in that, After the SoC generates the instruction to switch the frame rate, the SoC does not send the instruction to the display screen.

6. The method according to any one of claims 2-5, characterized in that, If the fourth moment before the preparation for sending the second image is completed is before the expected display time (EPT) of the second image, the time interval between the first moment and the second moment is equal to the frame length corresponding to the first frame rate.

7. The method according to any one of claims 2-5, characterized in that, If the fourth moment of preparation before sending the second image is completed is after the expected display time (EPT) of the second image, the time interval between the first moment and the second moment is greater than the frame length corresponding to the first frame rate.

8. The method according to claim 7, characterized in that, The method further includes: At the fifth moment, the SoC detects a software TE signal and does not send an image to the display screen. The fifth moment is located after the first moment and before the second moment, and the time interval between the first moment and the fifth moment is the frame length corresponding to the first frame rate.

9. The method according to any one of claims 1-8, characterized in that, The method further includes: At the sixth moment, the SoC enables hardware TE signal detection; the sixth moment is located after the first moment and before the second moment. After the SoC sends a second image to the display screen in response to detecting the second hardware TE signal, the method further includes: The SoC disables the hardware TE signal detection.

10. The method according to claim 9, characterized in that, The SoC enables hardware TE signal detection, including: The SoC switching image source is a hardware TE signal; The SoC disables the hardware TE signal detection, including: The SoC switching image source is a software TE signal.

11. The method according to claim 10, characterized in that, The method further includes: In response to the detection of a first hardware TE signal, the SoC initializes a timer, causing the timer to start counting from the first moment, and the timing period of the timer is the frame length corresponding to the first frame rate; In response to the arrival of the specified timing period, the SoC generates a software TE signal; In the case where the image source is a software TE signal, the SoC detects the software TE signal.

12. The method according to any one of claims 9-11, characterized in that, If the fourth moment before the preparation for sending the second image is completed is before the expected display time (EPT) of the second image, then the sixth moment is before the EPT, and the time interval between the sixth moment and the EPT is less than the first duration.

13. The method according to claim 12, characterized in that, The first duration is less than the period corresponding to the first frequency.

14. The method according to any one of claims 9-13, characterized in that, If the fourth moment, in which preparations for sending the second image are completed, is after the expected display time (EPT) of the second image, the sixth moment is after the fourth moment.

15. The method according to any one of claims 1-14, characterized in that, The first frequency is a multiple of 120Hz.

16. The method according to claim 15, characterized in that, The first frequency includes 360Hz.

17. The method according to any one of claims 1-16, characterized in that, The frequency corresponding to the first frame rate includes any of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz, and 1Hz; The frequency corresponding to the second frame rate includes any of the following: 120Hz, 90Hz, 60Hz, 30Hz, 10Hz, and 1Hz; The first frame rate and the second frame rate are different.

18. The method according to any one of claims 1-17, characterized in that, The display screen includes a low-temperature polycrystalline oxide (LTPO) screen with pixel circuitry comprising eight transistors.

19. The method according to any one of claims 9-14, characterized in that, Before the SoC sends a second image to the display screen in response to detecting the second hardware TE signal, the method further includes: The image synthesizer in the SoC calculates the expected display time (EPT) of the second image; The image synthesizer sends the EPT to the display driver in the SoC; At the sixth moment, the SoC enables hardware TE signal detection, including: The display driver enables hardware TE signal detection at the sixth moment based on the EPT.

20. An electronic device, characterized in that, include: A display panel, one or more processors, and one or more memories; the one or more processors are coupled to the display panel and the one or more memories; the one or more memories are used to store computer program code, the computer program code including computer instructions that, when the one or more processors execute the computer instructions, cause the electronic device to perform the method as described in any one of claims 1-19.

21. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-19.

22. A computer program product comprising computer instructions, characterized in that, When a computer program product is run on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-19.

Images