A driving control system of an LED display device and a control method thereof

Abstract

This invention discloses a drive control system and method for an LED display device. The drive control system includes: at least two GPIO ports; at least two DMA controllers; a PWM module; and a master timer. The trigger output of the master timer is connected to the trigger inputs of all DMA controllers and the synchronization input of the PWM module to generate a synchronization trigger signal. The synchronization trigger signal is used to simultaneously trigger all DMA controllers to perform a data transfer from their corresponding buffers to their bound output data registers, while simultaneously keeping the clock signal in phase with the data transfer. This invention solves the technical problems in the prior art where, when multiple DMA controllers control multiple GPIO ports respectively, the data signals output from different groups of GPIO ports exhibit clock skew, leading to image tearing and misalignment at screen seams, and the data signal and clock signal being out of sync, causing display noise and flicker.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a drive control system and control method for an LED display device. Background Technology

[0002] In the field of LED display control technology, with the continuous improvement of display device resolution and display effect, large-scale LED display devices usually require multiple HUB interfaces (such as HUB75 interface) to drive multiple display modules in parallel. How to efficiently and stably transmit display data to these HUB interfaces has become a key technical problem for drive control systems.

[0003] In existing large-scale LED display device driving solutions, a common approach is to use General Purpose Input / Output (GPIO) ports combined with Direct Memory Access (DMA) controllers to transmit display data to multiple HUB interfaces. Specifically, the DMA controller automatically moves the display data from memory to the output data register of the GPIO port, and then outputs it from the GPIO port to the data terminal of each HUB interface. Simultaneously, a timer or PWM module generates a clock signal, which controls the display data to be stored bit by bit sequentially into the shift register on the LED display module side, thereby synchronizing the data transmission process.

[0004] However, existing drive control systems have the following problems: when multiple DMA controllers are used to control multiple GPIO ports respectively, the data signals output by different GPIO ports have clock skew, resulting in image tearing and misalignment at the screen seams; the data signal is not synchronized with the clock signal output by the PWM module, and the data setup time or hold time is insufficient, causing display noise and flicker. Summary of the Invention

[0005] This invention provides a drive control system and control method for an LED display device to solve the technical problems in the prior art where, when multiple DMA controllers are used to control multiple GPIO ports respectively, the data signals output by different groups of GPIO ports have clock skew, resulting in image tearing and misalignment at the screen seams, and the data signals and clock signals are not synchronized, causing display noise and flicker.

[0006] In a first aspect, embodiments of the present invention provide a drive control system for an LED display device, comprising: at least two GPIO ports, each GPIO port including at least 16 data pins for outputting at least 16 bits of parallel data; at least two DMA controllers, each bound to one of the at least two GPIO ports, each DMA controller being configured with a source address and a destination address, the source address pointing to a buffer in memory corresponding to the DMA controller, and the destination address pointing to the output data register of the GPIO port bound to the DMA controller, for automatically transferring display data in the buffer to the output data register; a PWM module for outputting a clock signal required to drive the LED display device; and a master timer, the trigger output of the master timer being connected to the trigger inputs of all DMA controllers and the synchronization input of the PWM module, for generating a synchronization trigger signal; the synchronization trigger signal is used to simultaneously trigger all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and simultaneously keep the clock signal and the data transfer in phase synchronization.

[0007] Optionally, each GPIO port is used to connect to a HUB interface of the LED display device in a one-to-one correspondence.

[0008] Optionally, the drive control system also includes memory, which contains multiple buffers, each of which is configured to correspond one-to-one with a DMA controller.

[0009] Optionally, the duty cycle of the clock signal output by the PWM module is 50%.

[0010] Optionally, each DMA controller is configured in a cyclic transfer mode, which automatically reloads the initial count value when the transfer counter is zero, enabling the DMA controller to continuously perform data transfer to achieve continuous scanning of the display data.

[0011] Optionally, the PWM module is configured in slave mode, which can be either gated or triggered.

[0012] Optionally, the master timer is configured to generate a synchronization trigger signal once every preset number of counts.

[0013] Secondly, embodiments of the present invention provide a driving control method for an LED display device. Optionally, this method can be applied to a driving control system provided in any embodiment of the present invention. The driving control method includes: splitting a frame of display data into multiple data blocks and filling each data block into a buffer in memory corresponding to each DMA controller; configuring the clock frequency and counting period of the master timer so that the master timer generates a periodic synchronous trigger signal according to the required pixel clock frequency; configuring a source address and a destination address for each DMA controller, where the source address points to the buffer corresponding to the DMA controller and the destination address points to the output data register of the GPIO port bound to the DMA controller, and uniformly configuring the trigger source of all DMA controllers to a synchronous trigger signal from the master timer; configuring the trigger source of the PWM module to a synchronous trigger signal from the master timer; starting the master timer so that each synchronous trigger signal generated by the master timer simultaneously triggers all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and simultaneously keeping the clock signal output by the PWM module in phase synchronization with the data transfer.

[0014] Optionally, before splitting a frame of display data into multiple data blocks and filling each data block into the buffer corresponding to each DMA controller in memory, the drive control method further includes: enabling the clocks of each group of GPIO ports, each DMA controller, the master timer, and the PWM module; configuring each GPIO port in multiplexed push-pull output mode so that it is controlled by the corresponding DMA controller.

[0015] Optionally, the step of splitting a frame of display data into multiple data blocks includes: splitting a frame of display data into multiple data blocks according to the control range of each GPIO port; wherein the control range corresponds to different areas of the screen or different color components.

[0016] The drive control system provided in this invention has the following advantages: First, by employing a parallel architecture where multiple GPIO ports are bound one-to-one with multiple DMA controllers, the data output bit width can be linearly expanded without complex interface expansion circuits or time-division transmission, thus meeting the driving requirements of large-scale LED display devices with high data bandwidth. Second, all DMA controllers are simultaneously triggered by the same synchronous trigger signal of the same master timer, fundamentally eliminating the time difference between different DMA controllers caused by independent timers or software triggers. This achieves nanosecond-level synchronization of the data signals output from multiple GPIO ports, solving the image tearing and misalignment problems when splicing multiple HUB interfaces. Third, the data transfer and the clock output of the PWM module are synchronously driven by the same hardware trigger event, ensuring that the edges of the data signal and the clock signal are naturally aligned at the hardware level. This avoids insufficient data setup or hold time caused by different trigger sources and hardware paths, significantly improving the stability of data transmission and eliminating display noise and flicker.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a drive control system for an LED display device provided in an embodiment of the present invention; Figure 2 This is a signal timing diagram of a multi-channel synchronous drive provided in an embodiment of the present invention; Figure 3 This is a flowchart of a drive control method provided in an embodiment of the present invention; Figure 4 This is a flowchart of another drive control method provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] As described in the background section, the existing drive control system has the following problems: when multiple DMA controllers are used to control multiple groups of GPIOs respectively, the data signals output by different groups of GPIO ports have clock skew, which causes image tearing and misalignment at the screen seams; at the same time, the data signal is not synchronized with the clock signal output by the PWM module, and the data setup time or hold time is insufficient, which causes display noise and flicker.

[0023] The inventor discovered through research that the cause of the above problem is: On the one hand, in existing technologies, multiple DMA controllers are typically triggered by their own independent timers. The lack of a unified clock reference between these timers results in inherent deviations in their counting start points and periods, leading to inconsistent startup times and data transfer rhythms among the DMA controllers. This causes relative offsets in the data signals output from different GPIO groups on the time axis, i.e., clock skew. When these offset data signals simultaneously drive the spliced ​​multi-hub interfaces, the image data at the seams cannot be updated at the same time, resulting in tearing and misalignment.

[0024] On the other hand, display data is typically transmitted to the GPIO port output via a DMA controller, while the clock signal used for synchronous data transmission is generated by a PWM module. Because the trigger sources for these two signal paths are independent and follow different hardware paths, it is difficult to align the edges of the data signal and the clock signal in time. This misalignment can cause insufficient data setup or hold time, leading to stability issues such as noise and flickering in the display.

[0025] To address the aforementioned problems, embodiments of the present invention provide a drive control system and control method for an LED display device. The drive control system will be described first.

[0026] Figure 1 This is a schematic diagram of the structure of a drive control system for an LED display device provided in an embodiment of the present invention. See also... Figure 1 The drive control system of the LED display device includes: At least two GPIO ports 11, each GPIO port including at least 16 data pins for outputting at least 16 bits of parallel data; At least two DMA controllers 12 are bound one-to-one with at least two GPIO ports 11. Each DMA controller 12 is configured with a source address and a destination address. The source address points to the buffer in memory corresponding to the DMA controller, and the destination address points to the output data register of the GPIO port 11 bound to the DMA controller. This is used to automatically transfer the display data in the buffer to the output data register. A PWM module TIM2 is used to output the clock signal required to drive the LED display device; A master timer TIM1 is provided. The trigger output of master timer TIM1 is connected to the trigger input of all DMA controllers 12 and the synchronization input of PWM module TIM2 to generate a synchronization trigger signal. The synchronization trigger signal is used to simultaneously trigger all DMA controllers 12 to perform a data transfer from the corresponding buffer to the bound output data register, and at the same time keep the clock signal in phase with the data transfer.

[0027] Specifically, the general-purpose GPIO port 11 refers to a digital signal interface in a microcontroller that can be configured as an input or output mode via software. This embodiment and subsequent embodiments use the STM32 series microcontroller as an example, which integrates the modules described in this embodiment. In the STM32 series microcontroller, the GPIO port 11 is organized into multiple independent port groups, such as the first GPIO port GPIOA and the second GPIO port GPIOB. Each GPIO port includes at least 16 independently configurable pins, such as pin PIN0 to pin PIN15. Each GPIO port 11 is used to output at least sixteen bits of parallel data, with each pin corresponding to one data line, collectively forming a set of parallel data output channels. The GPIO ports of the STM32 series microcontroller support multiple operating modes, including push-pull output mode, open-drain output mode, and multiplexed function mode. In the multiplexed function push-pull output mode, the pin's output signal originates from an on-chip peripheral rather than an output data register; the output is enabled and the output speed is configurable. In this embodiment, each GPIO port is configured in multiplexed function push-pull output mode, so that its output signal is controlled by the corresponding DMA controller 12. In practical applications, each GPIO port can be independently connected to a HUB interface of the LED display device to provide display data to that HUB interface.

[0028] The DMA controller 12 is a hardware module that automatically transfers data between memory and peripherals without central processing unit intervention. Taking the STM32 series microcontrollers as an example, these microcontrollers integrate at least two DMA controllers 12, designated as the first DMA controller DMA1 and the second DMA controller DMA2. Each DMA controller 12 manages multiple channels, each dedicated to handling memory access requests from one or more peripherals. Each DMA controller 12 (i.e., a direct memory access controller channel) is configured with a source address and a destination address. The source address points to the buffer in memory corresponding to that DMA controller 12, and the destination address points to the output data register (ODR) of the GPIO port 11 to which it is bound. The function of the DMA controller 12 is to automatically transfer display data from the buffer to the output data register of the bound GPIO port 11. The DMA controller 12 of the STM32 series microcontrollers supports various data transfer widths, including 8-bit, 16-bit, and 32-bit. The DMA controller 12 also supports multiple transfer modes. In the cyclic transfer mode, the initial count value is automatically reloaded when the transfer counter is zero, so that the DMA controller 12 can continuously perform data transfer to achieve continuous scanning of the display data.

[0029] The PWM module TIM2 is a hardware circuit capable of outputting pulse signals with a fixed frequency and duty cycle. In STM32 series microcontrollers, PWM signals are typically generated by the output compare channel of a general-purpose timer or an advanced timer. By configuring the timer's auto-reload register to set the pulse width modulation period and configuring the capture compare register to set the pulse width, the desired pulse width modulation waveform can be output. In this embodiment, the PWM module TIM2 is used to output the clock signal required to drive the LED display device. This clock signal is used to control the display data to be latched bit by bit into the shift register at the module end. Bit-by-bit latching means that each clock pulse stores one bit of data into the shift register, one bit at a time, and the level state on the data line is saved and maintained until the next clock pulse arrives. The "module end" refers to the LED display device side, i.e., the load end of the drive control system, including the HUB interface, shift register, output latch, and LED beads. In other words, although the data lines of the HUB interface are multi-bit parallel, each data line is serially shifted at the module end: each time the clock signal changes, the module reads one bit from the data line and places it into the least significant bit of the shift register, while the original data is shifted sequentially. After several clock pulses, an entire row of data is shifted into the shift register. Therefore, the function of this clock signal is to provide a synchronous rhythm for the serial data shift at the module end, ensuring that the display data can be transmitted correctly and stably to the LED display device. For example, the duty cycle of the clock signal output by the PWM module TIM2 is 50%.

[0030] Master Timer TIM1 is a programmable hardware timer. Master Timer TIM1 is configured to generate a synchronization trigger signal every preset number of counts. The synchronization trigger signal output by Master Timer TIM1 serves as the trigger source for PWM module TIM2. To achieve hardware synchronization, simply configure PWM module TIM2 in slave mode and select the synchronization trigger signal of Master Timer TIM1 as its trigger source. Master Timer TIM1 periodically generates the synchronization trigger signal, which simultaneously reaches all DMA controllers 12 and PWM module TIM2. Therefore, all DMA controllers 12 initiate data transfer at the same time, while the clock signal output by PWM module TIM2 maintains phase synchronization with the data transfer operation.

[0031] To facilitate understanding, the following explanation uses two GPIO ports 11 and two DMA controllers 12 as an example. Figure 1As shown, at least two GPIO ports 11 include a first GPIO port GPIOA and a second GPIO port GPIOB. Two DMA controllers 12 include a first DMA controller DMA1 and a second DMA controller DMA2. The first DMA controller DMA1 is bound to the first GPIO port GPIOA, and the second DMA controller DMA2 is bound to the second GPIO port GPIOB. The source address of the first DMA controller DMA1 points to a first buffer in memory, and its destination address points to the output data register of the first GPIO port GPIOA; the source address of the second DMA controller DMA2 points to a second buffer in memory, and its destination address points to the output data register of the second GPIO port GPIOB. The synchronization trigger signal of the master timer TIM1 is simultaneously transmitted to the trigger input of the first DMA controller DMA1, the trigger input of the second DMA controller DMA2, and the synchronization input of the PWM module TIM2. The PWM module TIM2 is configured in slave mode, and its trigger source is selected from the synchronization trigger signal of the master timer TIM1.

[0032] Slave mode refers to the operating mode where the counter behavior of the PWM module TIM2 is controlled by an external trigger signal. The timer slave modes of the STM32 series microcontrollers include gated mode and trigger mode, both of which can achieve hardware synchronization between the PWM module TIM2 and the master timer TIM1, but the control logic differs.

[0033] In gated mode, the counter enable of the slave timer (i.e., the PWM module TIM2) is controlled by the level of the synchronous trigger signal. Specifically, when the synchronous trigger signal is high, the counter clock is turned on, and the counter starts counting; when the synchronous trigger signal goes low, the counter stops counting, but the current value of the counter is not reset and remains at the value at the time it stopped. That is, the start and stop of the counter are both controlled by the level of the synchronous trigger signal.

[0034] In trigger mode, the timer counter is started by the edge of the synchronous trigger signal. Specifically, when the trigger input detects the rising edge (or falling edge, depending on the configuration) of the synchronous trigger signal, the counter immediately starts counting, but the counter continues to run after starting and will not stop due to changes in the level of the synchronous trigger signal. That is, the synchronous trigger signal provides only one start pulse, and the counter is no longer affected by the subsequent state of the synchronous trigger signal after starting.

[0035] In this embodiment, regardless of whether gated or triggered mode is used, the PWM module TIM2 uses the synchronous trigger signal output by the master timer TIM1 as its trigger source. The common effect of both modes is to maintain a fixed phase relationship between the clock signal output by the PWM module TIM2 and the synchronous trigger signal of the master timer, thereby achieving hardware-level synchronization with the data transfer operation of the DMA controller 12. The difference lies in the following: In gated mode, the PWM module TIM2 continuously outputs during the high level of the entire synchronous trigger signal, and its start and stop are controlled by the level of the synchronous trigger signal; in triggered mode, the PWM module TIM2 starts outputting once at the rising or falling edge of each synchronous trigger signal, and stops after outputting a complete clock cycle, waiting for the next synchronous trigger signal.

[0036] The working principle of this embodiment is as follows: After the system is powered on, initialization configuration is performed first. The clocks of the first GPIO port GPIOA, the second GPIO port GPIOB, the first DMA controller DMA1, the second DMA controller DMA2, the master timer TIM1, and the PWM module TIM2 are enabled. Each pin of the first GPIO port GPIOA and the second GPIO port GPIOB is configured as a multiplexed push-pull output mode, with the output speed set to the highest (e.g., 50MHz), so that their output signals are controlled by the corresponding DMA controllers. A complete frame of display data is split into two independent data blocks according to the control range of the two GPIO ports, and stored in the first buffer and the second buffer in memory respectively. The first DMA controller DMA1 and the second DMA controller DMA2 are configured so that their source addresses point to the corresponding buffers, and their destination addresses point to the output data registers of the first GPIO port GPIOA and the second GPIO port GPIOB respectively. The hardware trigger source for both is uniformly configured as the synchronous trigger signal of the master timer TIM1. The clock frequency and counting period of the master timer TIM1 are configured so that it generates periodic update events according to the required pixel clock frequency, and the update events are output through the trigger output terminal. Configure PWM module TIM2 in slave mode, selecting the synchronous trigger signal from master timer TIM1 as its trigger source. After master timer TIM1 is started, whenever master timer TIM1 generates a synchronous trigger signal, this signal simultaneously triggers the first DMA controller DMA1, the second DMA controller DMA2, and PWM module TIM2. The first DMA controller DMA1 and the second DMA controller DMA2 each move a 16-bit data from their respective buffers to the output data register of the bound GPIO port. The first GPIO port GPIOA and the second GPIO port GPIOB simultaneously output new 16-bit parallel data; at the same time, PWM module TIM2 outputs a complete clock cycle. Since all actions are synchronously started by the same hardware trigger signal, the data signals output by the first GPIO port GPIOA and the second GPIO port GPIOB are strictly aligned on the time axis, with no clock skew; at the same time, the data signals and the clock signal output by PWM module TIM2 are naturally phase-synchronized in hardware, ensuring that the data setup time and hold time meet the latching requirements of the HUB interface.

[0037] Figure 2 This is a signal timing diagram of a multi-channel synchronous drive provided in an embodiment of the present invention. (Reference) Figure 2CLK1 represents the counting clock of the master timer, providing a timing reference for its operation; TRGO represents the synchronous trigger signal periodically output by the master timer; data represents the parallel data signal output by the corresponding GPIO port controlled by each DMA controller; CLK2 represents the clock signal output by the PWM module. The master timer generates a synchronous trigger signal TRGO every preset number of counts. The rising edge of TRGO simultaneously triggers all DMA controllers to perform data transfer and update the data signal data, while also synchronously triggering the PWM module to toggle the output clock signal CLK2. This ensures edge alignment between the multiple parallel data signals data and the clock signal CLK2 at the hardware level, guaranteeing stable latching and synchronous display of data across multiple HUB interfaces.

[0038] The drive control system provided in this invention has the following advantages: First, by employing a parallel architecture where multiple GPIO ports are bound one-to-one with multiple DMA controllers, the data output bit width can be linearly expanded without complex interface expansion circuits or time-division transmission, thus meeting the driving requirements of large-scale LED display devices with high data bandwidth. Second, all DMA controllers are simultaneously triggered by the same synchronous trigger signal of the same master timer, fundamentally eliminating the time difference between different DMA controllers caused by independent timers or software triggers. This achieves nanosecond-level synchronization of the data signals output from multiple GPIO ports, solving the image tearing and misalignment problems when splicing multiple HUB interfaces. Third, the data transfer and the clock output of the PWM module are synchronously driven by the same hardware trigger event, ensuring that the edges of the data signal and the clock signal are naturally aligned at the hardware level. This avoids insufficient data setup or hold time caused by different trigger sources and hardware paths, significantly improving the stability of data transmission and eliminating display noise and flicker.

[0039] Optionally, each GPIO port is used to connect one-to-one with a HUB interface of the LED display device. For example, the first GPIO port GPIOA is connected to the first HUB interface HUB1, the second GPIO port GPIOB is connected to the second HUB interface HUB2, and so on. Each GPIO port independently drives the HUB interface it is connected to. This means that each HUB interface has its own dedicated set of parallel data lines, which come from different GPIO ports and are not shared or intersected. The advantage of this design is that each HUB interface can obtain an independent display data channel. With the synchronous trigger signal of the master timer TIM1, all HUB interfaces can simultaneously receive their respective data, thereby achieving parallel synchronous refresh of multiple interfaces.

[0040] Continue to refer to Figure 1Optionally, the drive control system also includes memory 10, which contains multiple buffers, each corresponding to a DMA controller 12. This one-to-one correspondence means that each DMA controller 12 has a dedicated buffer, the starting address of which is configured as the source address of that DMA controller 12. For example, the first DMA controller DMA1 corresponds to the first buffer, and the second DMA controller DMA2 corresponds to the second buffer. The size of each buffer is pre-allocated according to the length of the display data block. Thus, during system operation, the Central Processing Unit (CPU) only needs to write the display data required by different HUB interfaces into their respective buffers. Then, each DMA controller independently and synchronously moves the data to the output data register of its bound GPIO port, without CPU intervention. This one-to-one buffer design avoids conflicts and delays that may arise from multiple DMA controllers competing for the same memory resources, further ensuring the real-time performance and synchronization of data transmission.

[0041] Based on the same inventive concept, embodiments of the present invention also provide a driving control method for a display device, applicable to the driving control system provided in any embodiment of the present invention. Figure 3 This is a flowchart of a drive control method provided in an embodiment of the present invention. Figure 3 As shown, the drive control method includes: S101. Split a frame of display data into multiple data blocks, and fill each data block into the buffer in memory corresponding to each DMA controller.

[0042] Specifically, a frame of display data is divided into multiple data blocks according to the control range of each GPIO port; where the control range corresponds to different areas of the screen or different color components.

[0043] In LED display devices, a complete frame of image data typically contains brightness or color information for multiple pixels. Since this invention uses multiple GPIO ports to drive multiple HUB interfaces, and each GPIO port is only responsible for displaying a portion of the image, it is necessary to split the entire frame of display data.

[0044] According to the control range of each GPIO port, it means dividing the entire frame of data into several independent data blocks according to the display area corresponding to the HUB interface connected to each GPIO port, such as the left or right area of ​​the screen, or the first or second row area, or according to the color component that the GPIO port is responsible for transmitting, such as red component data, green component data, or blue component data.

[0045] The size and content of each data block are matched to the control range of the corresponding GPIO port. For example, if the first set of GPIO ports is responsible for driving the upper half of the screen, the first data block contains the display data of all pixels in the upper half; if the second set of GPIO ports is responsible for transmitting the red component, the second data block contains only the data of the red component.

[0046] After the data is split, these data blocks are stored in memory in buffers pre-allocated for each DMA controller. Each DMA controller reads data only from its own buffer, ensuring that the multiple data streams do not interfere with each other. Subsequently, they can be synchronously transmitted to their respective GPIO ports, ultimately forming a complete display on the LED screen. This splitting method not only rationally allocates the data transmission tasks for the display but also provides a data preparation foundation for synchronously driving multiple HUB interfaces.

[0047] During system operation, the data in the memory buffers is not fixed but is refreshed in real time as the displayed content is updated. Specifically, within each frame display cycle, the CPU continuously updates the data blocks stored in each buffer according to the content to be displayed. For example, when displaying the next line or the next frame of image, the CPU writes the new display data to the corresponding buffer, overwriting the old data. Since the DMA controller always points to a fixed starting address of these buffers and operates in circular transfer mode, whenever the main timer generates a synchronization trigger signal, the DMA controller automatically moves the latest data from the updated buffer to the output data register of the GPIO port, thereby driving the LED display device to refresh the displayed content. The entire update process is completed by the CPU in the background, running in parallel with the hardware synchronous transfer mechanism without interference, ensuring a continuous and smooth display effect.

[0048] S102. Configure the clock frequency and counting period of the master timer so that the master timer generates periodic synchronous trigger signals according to the required pixel clock frequency.

[0049] Specifically, the master timer is a programmable hardware counter whose operating rhythm is determined by the clock frequency and the counting period.

[0050] Clock frequency refers to how fast the reference clock input to the master timer is. For example, if the system clock is divided to obtain a 10MHz timer clock, then the timer will count 10,000,000 times per second.

[0051] The counting period refers to the number of clock cycles required for the master timer to count from 0 to a preset value (i.e., the auto-reload value). For example, if the counting period is set to 100, the master timer will overflow once every 100 counts.

[0052] By combining the clock frequency with the counting period, the frequency at which the timer generates overflow events can be precisely controlled. For example, if the master timer clock frequency is 10MHz and the period is 100, then the overflow frequency = 10MHz / 100 = 100kHz, which means it overflows once every 10 microseconds.

[0053] Each time the master timer overflows, its trigger output generates a synchronization trigger signal. Therefore, by selecting an appropriate clock frequency and counting period, the master timer can periodically output a synchronization trigger signal according to the pixel clock frequency required by the LED display device (i.e., the beat frequency required for each pixel data transmission).

[0054] S103. Configure a source address and a destination address for each DMA controller. The source address points to the buffer corresponding to the DMA controller, and the destination address points to the output data register of the GPIO port bound to the DMA controller. Configure the trigger source of all DMA controllers to be the synchronous trigger signal from the master timer.

[0055] Specifically, each DMA controller has a source address register to specify where it reads data from. In this invention, the source address is set to the starting address of the memory buffer corresponding to that DMA controller. That is, each DMA controller knows the location of its own buffer in memory.

[0056] Each DMA controller also has a destination address register, which specifies where it writes data. In this invention, the destination address is set to the output data register of the GPIO port to which the DMA controller is bound. After the CPU or DMA controller writes data to the ODR, the output level of the GPIO port changes immediately.

[0057] This invention sets the hardware trigger source for all DMA controllers to the same signal, namely the synchronization trigger signal generated by the master timer. Thus, when the master timer issues a synchronization trigger signal, all DMA controllers will be triggered simultaneously, each moving data from its own source address to its own destination address.

[0058] Each DMA controller has its own independent buffer and independent ODR, but they share the same trigger source (i.e., the master timer's synchronization trigger signal). Therefore, as long as the master timer issues a synchronization trigger signal, all DMA controllers will synchronously perform a data transfer, ensuring that multiple parallel data streams are updated simultaneously.

[0059] S104. Configure the trigger source of the PWM module to be the synchronous trigger signal from the master timer.

[0060] Specifically, each time the master timer generates a synchronization trigger signal, this signal is simultaneously transmitted to the synchronization input of the PWM module. Upon receiving the synchronization trigger signal, the PWM module responds according to its configured slave mode type (e.g., trigger mode or gated mode). In trigger mode, the rising edge of each synchronization trigger signal initiates a complete clock cycle of output from the PWM module; in gated mode, the PWM module continuously outputs during the high level of the synchronization trigger signal.

[0061] With this configuration, the PWM module is no longer an independently operating clock source, but becomes a slave device to the master timer. Its output clock signal maintains a fixed phase relationship with the master timer's synchronization trigger signal, thus achieving hardware-level synchronization with the DMA controller's data transfer operations performed under the same synchronization trigger signal. This synchronization ensures that the data signal setup and hold times meet the latching requirements of the HUB interface, avoiding display noise and flickering caused by clock and data asynchrony.

[0062] S105. Start the master timer, so that each synchronization trigger signal generated by the master timer simultaneously triggers all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and at the same time keeps the clock signal output by the PWM module in phase synchronization with the data transfer.

[0063] Specifically, once the master timer is enabled, it begins to run according to the pre-configured clock frequency and counting cycle, periodically generating a synchronization trigger signal.

[0064] Each synchronization trigger signal generated by the master timer arrives simultaneously at the trigger input of each DMA controller via internal hardware wiring. Upon receiving the synchronization trigger signal, each DMA controller immediately performs a data transfer. Because all DMA controllers are triggered simultaneously by the same synchronization trigger signal, their data transfer operations are perfectly aligned in time, with no difference in sequence.

[0065] The same synchronous trigger signal arrives simultaneously at the synchronous input terminal of the PWM module, and the PWM module generates a corresponding clock signal output according to the configured slave mode. Since the PWM module and the DMA controller share the same trigger source, their output clock signal and data transfer operation are naturally synchronized in phase in hardware, that is, the rising edge of the clock signal is aligned with the stable moment of the data output from the GPIO port.

[0066] The master timer continuously generates periodic synchronization trigger pulses, and the above process is automatically repeated without CPU intervention. Each pulse corresponds to the synchronous transmission of one line or a group of display data, thereby achieving continuous, synchronous, and stable display driving across multiple HUB interfaces.

[0067] The drive control method provided in this invention allows all DMA controllers to update the output data of their respective bound GPIO ports simultaneously, refreshing the data of all GPIO ports at the same time, fundamentally eliminating clock skew between multiple HUB interfaces. Simultaneously, the clock signal output by the PWM module maintains a fixed phase relationship with the data update time, ensuring that the data setup and hold times meet requirements, thus avoiding display noise and flicker. The entire synchronization process is automatically completed by hardware, achieving high-precision LED display driving.

[0068] Figure 4 This is a flowchart of another drive control method provided in an embodiment of the present invention. Figure 4 As shown, the drive control method includes: S201 enables the clock for each group of GPIO ports, each DMA controller, the master timer, and the PWM module.

[0069] Specifically, in the STM32 series microcontrollers, each hardware module, such as GPIO ports, DMA controllers, and timers, needs to receive a clock signal before it can operate; otherwise, it cannot respond to configuration commands or perform any operations. Enabling the clock involves setting the corresponding bit in the clock control register to connect the system clock to the target module, enabling it to enter a working state.

[0070] S202. Configure each GPIO port as a multiplexed push-pull output mode so that it is controlled by the corresponding DMA controller.

[0071] Specifically, in the STM32 series microcontrollers, each pin of the GPIO port can operate in multiple modes. Among them, the Alternate Function Push-Pull Output mode is a working mode that transfers the pin output control from the CPU to the on-chip peripheral.

[0072] This step configures each GPIO port as a single multiplexed push-pull output mode. The purpose is to delegate the output control of all pins under that port to the corresponding DMA controller. Specifically, after configuration to multiplexed push-pull output mode, the output signal of the GPIO port is no longer determined by the CPU writing to the ODR, but is directly driven by the bound DMA controller through the internal bus. The DMA controller writes display data to the ODR of the GPIO port, and the pin level is updated accordingly. Since the DMA controller has already been configured with source and destination addresses, and the trigger source is set to the synchronous trigger signal of the master timer, when the synchronous trigger pulse arrives, the DMA controller automatically reads data from the buffer and writes it to the ODR. The GPIO port immediately outputs the corresponding level in multiplexed push-pull output mode without CPU intervention. By configuring the GPIO port to multiplexed push-pull output mode, direct drive of the GPIO port by the DMA controller is achieved. Combined with hardware synchronous triggering, multiple parallel data streams can be simultaneously and stably output to the corresponding HUB interface, avoiding latency uncertainties and synchronization errors caused by CPU intervention.

[0073] S203. Split a frame of display data into multiple data blocks and fill each data block into the buffer corresponding to each DMA controller in memory.

[0074] S204. Configure the clock frequency and counting period of the master timer so that the master timer generates a periodic synchronous trigger signal according to the required pixel clock frequency.

[0075] S205. Configure a source address and a destination address for each DMA controller. The source address points to the buffer corresponding to the DMA controller, and the destination address points to the output data register of the GPIO port bound to the DMA controller. Configure the trigger source of all DMA controllers to be the synchronous trigger signal from the master timer.

[0076] S206. Configure the trigger source of the PWM module to be the synchronous trigger signal from the master timer.

[0077] S207. Start the master timer, so that each synchronization trigger signal generated by the master timer simultaneously triggers all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and at the same time keeps the clock signal output by the PWM module in phase synchronization with the data transfer.

[0078] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0079] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A drive control system for an LED display device, characterized in that, include: At least two GPIO ports, each GPIO port including at least 16 data pins for outputting at least 16 bits of parallel data; At least two DMA controllers are bound one-to-one with the at least two GPIO ports. Each DMA controller is configured with a source address and a destination address. The source address points to the buffer in memory corresponding to the DMA controller, and the destination address points to the output data register of the GPIO port bound to the DMA controller. This is used to automatically transfer the display data in the buffer to the output data register. A PWM module is used to output the clock signal required to drive the LED display device; A master timer, the trigger output of which is connected to the trigger input of all DMA controllers and the synchronization input of the PWM module, for generating a synchronization trigger signal; The synchronization trigger signal is used to simultaneously trigger all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and at the same time keep the clock signal in phase synchronization with the data transfer.

2. The drive control system for the LED display device according to claim 1, characterized in that, Each of the GPIO ports is used to connect to a HUB interface of the LED display device in a one-to-one correspondence.

3. The drive control system for the LED display device according to claim 1, characterized in that, The drive control system also includes memory, which contains multiple buffers, each of which is configured in a one-to-one correspondence with the DMA controller.

4. The drive control system for the LED display device according to claim 1, characterized in that, The clock signal output by the PWM module has a duty cycle of 50%.

5. The drive control system for the LED display device according to claim 1, characterized in that, Each of the DMA controllers is configured in a cyclic transfer mode, which automatically reloads the initial count value when the transfer counter reaches zero, enabling the DMA controller to continuously perform the data transfer to achieve continuous scanning of the display data.

6. The drive control system for the LED display device according to claim 1, characterized in that... The PWM module is configured in slave mode, which can be either gated or triggered.

7. The drive control system for the LED display device according to claim 1, characterized in that, The master timer is configured to generate a synchronization trigger signal once every preset number of counts.

8. A driving control method for an LED display device, characterized in that, The drive control method, applied to any one of claims 1 to 7, comprises: A frame of display data is split into multiple data blocks, and each data block is filled into the buffer in memory corresponding to each DMA controller. Configure the clock frequency and counting period of the master timer so that the master timer generates a periodic synchronization trigger signal according to the required pixel clock frequency; Configure a source address and a destination address for each DMA controller. The source address points to the buffer corresponding to the DMA controller, and the destination address points to the output data register of the GPIO port bound to the DMA controller. Configure the trigger source of all DMA controllers to be the synchronous trigger signal from the master timer. Configure the trigger source of the PWM module to be the synchronous trigger signal from the master timer; The master timer is started, so that each synchronization trigger signal generated by the master timer simultaneously triggers all DMA controllers to perform a data transfer from the corresponding buffer to the bound output data register, and at the same time the clock signal output by the PWM module is kept in phase synchronized with the data transfer.

9. The driving control method for an LED display device according to claim 8, characterized in that, Before the steps of splitting a frame of display data into multiple data blocks and filling each data block into the buffer corresponding to each DMA controller in memory, the drive control method further includes: Enable the clocks of each group of GPIO ports, each DMA controller, the master timer, and the PWM module; Configure each GPIO port as a multiplexed push-pull output mode so that it is controlled by the corresponding DMA controller.

10. The driving control method for an LED display device according to claim 8, characterized in that, The steps to split a frame of display data into multiple data blocks include: A frame of display data is divided into multiple data blocks according to the control range of each GPIO port; wherein, the control range corresponds to different areas of the screen or different color components.

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