A display panel, a light emission control method, and a display device.

Abstract

This application provides a display panel, a light emission control method, and a display device, relating to the field of display technology. The display panel includes a first display area and a second display area. The first display area includes a first pixel row, and the second display area includes a second pixel row. The refresh rate of the first display area is F1, and the refresh rate of the second display area is F2. If F1 > F2, within a first data frame of the display panel, the sub-pixels in the first pixel row are used to receive m data write pulses and N first-type light emission pulses in a time-division manner; the sub-pixels in the second pixel row are used to receive n data write pulses and N second-type light emission pulses in a time-division manner; the equivalent luminance of the sub-pixels in the first pixel row under the first data frame is a first equivalent luminance L1, and the equivalent luminance of the sub-pixels in the second pixel row under the first data frame is a second equivalent luminance L2, where L1 = L2. According to this application embodiment, the problem of uneven light emission in the display panel's operation can be effectively improved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel, a light emission control method, and a display device. Background Technology

[0002] With the rapid development of display technology, new types of display panels, such as Organic Light Emitting Diode (OLED) and Micro Light Emitting Diode (micro LED), are emerging in large numbers, and full-screen displays have become the development trend of mobile display devices such as smartphones. As display technology continues to advance and consumers' demands for display panels increase, the functions integrated into display panels are becoming increasingly diverse. However, at present, display panels still suffer from uneven light emission during operation. Summary of the Invention

[0003] This application provides a display panel, a light emission control method, and a display device, which can effectively improve the problem of uneven light emission in the display panel during display operation.

[0004] In a first aspect, embodiments of this application provide a display panel, which includes a first display area and a second display area. The first display area includes a first pixel row, and the second display area includes a second pixel row. The refresh rate of the first display area is F1, and the refresh rate of the second display area is F2. If F1>F2, within the first data frame of the display panel, the sub-pixels in the first pixel row are used to receive m data write pulses and N first-type light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N; The sub-pixels in the second pixel row are used to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame is the data refresh frame of the first display area and the second display area; where m is a positive integer and n≤m; Wherein, the equivalent luminance of the sub-pixels in the first pixel row under the first data frame is the first equivalent luminance L1, and the equivalent luminance of the sub-pixels in the second pixel row under the first data frame is the second equivalent luminance L2, where L1=L2.

[0005] According to an embodiment of the first aspect of this application, the first equivalent luminous intensity of a sub-pixel in the first pixel row in the first data frame is the sum of the products of the pulse width of each first type of luminous pulse and the luminous intensity of the sub-pixel in each first type of luminous pulse. The second equivalent luminance of the sub-pixels in the second pixel row in the first data frame is the sum of the products of the pulse width of each second type of luminous pulse and the luminance of the sub-pixel in each second type of luminous pulse.

[0006] According to the first aspect of the present application, the sum of the pulse widths of N first-type light-emitting pulses is the first pulse width, and the sum of the pulse widths of N second-type light-emitting pulses is the second pulse width; The first pulse width is equal to the second pulse width.

[0007] According to the first aspect of the present application, the sum of the N luminance values ​​of the sub-pixels in the first pixel row under N first type of luminous pulses is the first luminance value, and the sum of the N luminance values ​​of the sub-pixels in the second pixel row under N second type of luminous pulses is the second luminance value. The first luminous intensity is equal to the second luminous intensity.

[0008] According to the first aspect of the present application, in the first data frame, the first target light emission pulse is defined as the i-th first type light emission pulse of N first type light emission pulses, and the second target light emission pulse is defined as the i-th second type light emission pulse of N second type light emission pulses, i≤N, where i is a positive integer; The time interval between the midpoint of the first target emission pulse and the start time of the first data writing pulse among the m data writing pulses is the first duration; The time interval between the midpoint of the second target emission pulse and the start time of the first data writing pulse among the n data writing pulses is the second duration; where the first duration is equal to the second duration.

[0009] According to the first aspect of the present application, if F1>F2, in the second data frame of the display panel, the sub-pixels in the first pixel row are used to receive m data writing pulses and N first type of light emission pulses in a time-division manner; The sub-pixels in the second pixel row are used to receive N second-type emission pulses in a time-division manner; The second data frame consists of a data refresh frame for the first display area and a data hold frame for the second display area.

[0010] According to an embodiment of the first aspect of this application, the plurality of data frames of the display panel include at least two consecutive first data frames.

[0011] According to an embodiment of the first aspect of this application, among the N first-type light emission pulses, at least two of the first-type light emission pulses have different pulse widths.

[0012] According to the implementation of the first aspect of this application, among the N first-type light-emitting pulses, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse, 1 < j ≤ N, and j is a positive integer; In the N type II emission pulses, the pulse width of each type II emission pulse is the same.

[0013] According to the implementation of the first aspect of this application, among the N first-type light-emitting pulses, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse, 1 < j ≤ N, and j is a positive integer; In N type II emission pulses, the pulse width of the (j-1)th type II emission pulse is less than the pulse width of the jth type II emission pulse.

[0014] According to the first aspect of the present application, among the N first-type light-emitting pulses, the pulse width of each first-type light-emitting pulse is the same; In the N type II emission pulses, the pulse width of each type II emission pulse is the same.

[0015] According to an embodiment of the first aspect of this application, the display panel further includes a non-display area, in which a first gate driving circuit, a second gate driving circuit, and a signal gating circuit are disposed, and the signal gating circuit is electrically connected to the first gate driving circuit and the second gate driving circuit respectively. If F1 > F2, the first gate driving circuit is configured to output a first type of light emission pulse to the sub-pixel of the first display area; The first gate driving circuit or the second gate driving circuit is configured to output a second type of light emission pulse to the sub-pixel of the second display area; The signal gating circuit is configured to, under the control of the gating control line, transmit a first type of light-emitting pulse provided by the first gate driving circuit as a second type of light-emitting pulse to a sub-pixel of the second display area, or transmit a second type of light-emitting pulse provided by the second gate driving circuit to a sub-pixel of the second display area.

[0016] According to an embodiment of the first aspect of this application, the first gate driving circuit includes a plurality of cascaded first shift registers, the second gate driving circuit includes a plurality of cascaded second shift registers, and the signal gating circuit includes at least one signal gating unit; The control terminal of the signal gating unit is electrically connected to the gating control line. The first input terminal and the second input terminal of the signal gating unit are electrically connected to the output terminals of the corresponding first shift register and the second shift register, respectively. The output terminal of the signal gating unit is electrically connected to the target pixel row in the second display area.

[0017] According to an embodiment of the first aspect of this application, the signal gating unit includes a first switch and a second switch, and the gating control line includes a first gating control line and a second gating control line; The control terminal of the first switch is electrically connected to the first gating control line, the first terminal of the first switch is connected to the output terminal of the corresponding first shift register, and the second terminal of the first switch is electrically connected to the target pixel row. The control terminal of the second switch is electrically connected to the second gating control line, the first terminal of the second switch is connected to the output terminal of the corresponding second shift register, and the second terminal of the second switch is electrically connected to the target pixel row.

[0018] According to an embodiment of the first aspect of this application, the signal gating unit includes a first switch and a second switch; The control terminal of the first switch is electrically connected to the gating control line, the first terminal of the first switch is connected to the output terminal of the corresponding first shift register, and the second terminal of the first switch is electrically connected to the target pixel row. The control terminal of the second switch is electrically connected to the gating control line, the first terminal of the second switch is connected to the output terminal of the corresponding second shift register, and the second terminal of the second switch is electrically connected to the target pixel row. One of the first and second switches is an N-type transistor, and the other is a P-type transistor.

[0019] According to an embodiment of the first aspect of this application, if F2=F, the signal gating circuit is configured to transmit the first type of light emission pulse provided by the first gate driving circuit as the second type of light emission pulse to the sub-pixel of the second display area under the control of the gating control line; Where F is the refresh rate of the display panel during normal high-frequency display.

[0020] According to an embodiment of the first aspect of this application, the first pixel row and the second pixel row include a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device, the pixel circuit including: The driver module is used to drive the light-emitting device to emit light. The data writing module is used to transmit the data voltage provided by the data signal line to the drive module in response to the data writing pulse; The light-emitting control module is used to turn on in response to a first type of light-emitting pulse or a second type of light-emitting pulse, so as to transmit the driving current provided by the driving module to the light-emitting device.

[0021] Based on the same inventive concept, in a second aspect, embodiments of this application provide a method for controlling the light emission of a display panel, applied to a display panel as described in any of the embodiments of the first aspect of this application. The display panel includes a first display area and a second display area, the first display area including a first pixel row, and the second display area including a second pixel row; the refresh rate of the first display area is F1, and the refresh rate of the second display area is F2; ​​the method for controlling the light emission of the display panel includes: If F1>F2, within the first data frame of the display panel, control the sub-pixels in the first pixel row to receive m data write pulses and N first-type light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N; The sub-pixels in the second pixel row are controlled to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame is the data refresh frame of the first display area and the second display area; where m is a positive integer and n≤m; Wherein, the equivalent luminance of the sub-pixels in the first pixel row under the first data frame is the first equivalent luminance L1, and the equivalent luminance of the sub-pixels in the second pixel row under the first data frame is the second equivalent luminance L2, where L1=L2.

[0022] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device, including a display panel as described in any of the first aspects of the embodiments described above.

[0023] As described above, the present application provides a display panel, a light emission control method, and a display device. The display panel includes a first display area and a second display area. The first display area includes a first pixel row, and the second display area includes a second pixel row. The refresh rate of the first display area is F1, and the refresh rate of the second display area is F2. If F1>F2, within a first data frame of the display panel, the sub-pixels in the first pixel row are used to receive m data write pulses and N first-type light emission pulses in a time-division manner, where N≥2 and m≤N. The sub-pixels in the second pixel row are used to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame is a data refresh frame for the first and second display areas, where n≤m. The equivalent luminous intensity of the sub-pixels in the first pixel row under the first data frame is a first equivalent luminous intensity L1, and the equivalent luminous intensity of the sub-pixels in the second pixel row under the first data frame is a second equivalent luminous intensity L2, where L1=L2.

[0024] Compared with the related art, a display panel, a light emission control method and a display device according to an embodiment of the present application set m data writing pulses and N first type light emission pulses (N≥2, m≤N) for the first pixel row in the high-frequency region in the first data frame, and at the same time set n data writing pulses and N second type light emission pulses (n≤m) for the second pixel row in the low-frequency region. In this way, although the number of data writing pulses in the low-frequency region is reduced (n<m, and can even be reduced to n = 1), the number of light emission pulses N remains the same as that in the high-frequency region, making the adjustment of the data writing frequency independent of the maintenance of the light emission frequency, so as to maintain the light emission continuity while reducing power consumption. Further, the embodiment of the present application provides the uniformity of the display brightness through the equalization control of the equivalent light emission brightness. By making the equivalent light emission brightness L1 of the high-frequency region under the first data frame equal to the equivalent light emission brightness L2 of the low-frequency region, the light energy output by the high-frequency region and the low-frequency region within the same frame period reaches consistency. In this way, even if the number of data writing times in the low-frequency region is reduced, the visual brightness basically consistent with that of the high-frequency region can be achieved through the total equivalent light emission amount, so as to effectively improve the problem of uneven light emission existing in the display work of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present application; Figure 2 It is a schematic timing diagram of a display panel provided by an embodiment of the present application; Figure 3 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 4 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 5 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 6 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 7 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 8 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 9 It is a schematic timing diagram of another display panel provided by an embodiment of the present application; Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 11 This is a partial structural diagram of a display panel provided in an embodiment of this application; Figure 12 This is a partial structural diagram of a display panel provided in an embodiment of this application; Figure 13 This is a partial structural diagram of another display panel provided in an embodiment of this application; Figure 14 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application; Figure 15 This is a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 16 This is a schematic flowchart of a display panel light emission control method provided in an embodiment of this application; Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0027] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0029] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0030] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0031] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0032] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0033] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: With the rapid development of display technology, and to meet consumers' increasing demands for display panel functionality, the functions integrated into display panels are becoming increasingly diversified. In related technologies, to reduce the power consumption of display panels, a partitioned driving scheme is typically adopted, dividing the display panel into a high-frequency driving area and a low-frequency driving area. In the high-frequency area, both the data writing frequency and the emission frequency are relatively high; in the low-frequency area, power consumption is reduced by decreasing the data input frequency, while maintaining the emission frequency, thereby achieving energy-saving effects while maintaining display brightness.

[0034] However, the inventors of this application have discovered that for displays driven by multi-frame PWM (Pulse Width Modulation), such as Micro-LED, existing OLED zone driving schemes are difficult to apply directly because each complete emission requires multiple data inputs. Specifically, while reducing the data writing frequency in the low-frequency region, it is impossible to maintain the same emission frequency as the high-frequency region. In other words, it is difficult to maintain the emission frequency while reducing the data writing frequency in the low-frequency region, resulting in uneven emission between the low-frequency and high-frequency regions. This leads to a decrease in the overall display quality of the display panel, resulting in display abnormalities such as inconsistent brightness and screen flickering.

[0035] To address the issue of display abnormalities in the display panel under partitioned driving conditions, the inventors of this application first researched and analyzed the root causes of the aforementioned technical problems. The specific research and analysis process is as follows: For example, Micro-LED displays employ a multi-subframe PWM driving method. Each data frame requires multiple data writes and multiple emission pulses, and the required grayscale is achieved by adjusting the emission time and brightness of each subframe. Existing OLED zone driving schemes only reduce the data input frequency in the low-frequency region while maintaining the emission frequency. However, for Micro-LED multi-subframe PWM driving, simply reducing the data write frequency cannot maintain the original multi-subframe emission sequence. This results in a mismatch between the emission frequency, emission time, or brightness in the low-frequency region and the high-frequency region, causing uneven display between the high-frequency and low-frequency regions.

[0036] Therefore, there is an urgent need for a zone scanning scheme suitable for Micro-LED displays, which can reduce the data writing frequency in low-frequency regions while maintaining the same equivalent luminous brightness and stable luminous timing as high-frequency regions, thereby solving the problem of uneven display between high and low frequency regions.

[0037] This application provides a display panel, specifically as follows: Figure 1 As shown, Figure 1 A schematic diagram of the structure of a display panel 100 provided in an embodiment of this application is shown. Figure 1As shown, the display panel 100 includes a first display area AA1 and a second display area AA2. The first display area AA1 includes a first pixel row Line1, and the second display area AA2 includes a second pixel row Line2. The refresh rate of the first display area AA1 is F1, and the refresh rate of the second display area AA2 is F2.

[0038] Please see below. Figure 2 If F1>F2, in the first data frame H1 of the display panel 100, the sub-pix Px in the first pixel row Line1 is used to receive m data writing pulses and N first type of light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N. The sub-pixel Px in the second pixel row Line2 is used to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame H1 is the data refresh frame of the first display area AA1 and the second display area AA2; where m is a positive integer and n≤m; Wherein, the equivalent luminous brightness of sub-pix Px in the first pixel row Line1 under the first data frame H1 is the first equivalent luminous brightness L1, and the equivalent luminous brightness of sub-pix Px in the second pixel row Line2 under the first data frame H1 is the second equivalent luminous brightness L2, and L1=L2.

[0039] In specific implementation, combined with Figure 1 and Figure 2 As shown, the display panel 100 includes a first display area AA1 and a second display area AA2. The refresh rate of the first display area AA1 is F1, and the refresh rate of the second display area AA2 is F2. F1 > F2; for example, F1 is 120Hz and F2 is 60Hz. The first display area AA1, as a high-frequency area, can be used to display dynamic content; the second display area AA2, as a low-frequency area, can be used to display static content or low-dynamic content, thereby reducing overall power consumption while meeting display requirements.

[0040] The first display area AA1 includes the first pixel row Line1, and the second display area AA2 includes the second pixel row Line2. When F1 is greater than F2, the two display areas adopt differentiated timing control strategies within the first data frame H1 of the display panel 100. The sub-pixels Px in the first pixel row Line1 receive m data write pulses and N first-type light emission pulses in a time-division manner. The high-frequency area needs to perform multiple data writes and multiple light emission within each data frame, thereby performing multi-sub-frame PWM drive.

[0041] In the second pixel row, Line2, sub-pixel Px receives n data write pulses and N second-type light emission pulses in a time-division manner, where n is less than or equal to m. This indicates that the number of data writes in the low-frequency region does not exceed that in the high-frequency region, but the number of light emission pulses remains the same at N. In this way, the data write frequency is reduced in the low-frequency region while maintaining the same light emission frequency as during normal high-frequency display.

[0042] In practical applications, for example, if n is less than m, the data writing frequency of the low-frequency zone in the data refresh frame is directly lower than that of the high-frequency zone, thus achieving low-frequency drive; if n equals m, the data frame after the first data frame H1 in the low-frequency zone can be used as a data holding frame, which only maintains light emission and does not receive new data writing, thus ensuring that the overall data writing frequency of the low-frequency zone is lower than that of the high-frequency zone.

[0043] It should be noted that the first data frame H1 can be used as a data refresh frame for both display areas.

[0044] Based on this, this application achieves visual consistency through balanced control of equivalent luminous intensity. Specifically, the equivalent luminous intensity of sub-pixel Px in the first pixel row Line1 under the first data frame H1 is L1, and the equivalent luminous intensity of sub-pixel Px in the second pixel row Line2 under the first data frame H1 is L2, where L1 equals L2. This equivalent luminous intensity can, for example, be determined by the sum of the products of the pulse width of each luminous pulse and the corresponding luminous intensity.

[0045] In actual equivalent brightness control, the display driver chip can control the brightness by controlling the data writing, or adjust the pulse width of the shift register light control drive signal to ensure that the equivalent brightness of high and low frequencies is basically the same under a data frame.

[0046] In this embodiment, based on the brightness superposition characteristic, the data writing frequency is reduced in the low-frequency region while maintaining the same light emission frequency as during normal high-frequency display. Therefore, even with a reduction in the number of data writes in the low-frequency region, the same brightness and stable light emission as in the high-frequency region can be achieved.

[0047] Therefore, by maintaining the first equivalent luminous brightness and the second equivalent luminous brightness at the same level, this application reduces the data writing frequency in the low-frequency region while maintaining the same luminous frequency as during normal high-frequency display, thereby solving the problem in the prior art that it is difficult to maintain the luminous frequency while reducing the data writing frequency, and achieving the technical effect of improving uneven luminous emission.

[0048] In summary, for a display panel 100 according to an embodiment of the present application, by setting m data writing pulses and N first type light emitting pulses (N≥2, m≤N) for the first pixel row Line1 in the high-frequency region within the first data frame H1, and simultaneously setting n data writing pulses and N second type light emitting pulses (n≤m) for the second pixel row Line2 in the low-frequency region. In this way, although the number of data writing pulses in the low-frequency region is reduced (n<m, and can even be reduced to n = 1), the same number of light emitting pulses N as in the high-frequency region is still maintained, making the adjustment of the data writing frequency independent of the maintenance of the light emitting frequency, so as to maintain the light emitting continuity while reducing power consumption. Further, the embodiment of the present application provides the uniformity of display brightness through the equalization control of the equivalent light emitting brightness. By making the equivalent light emitting brightness L1 of the high-frequency region under the first data frame H1 equal to the equivalent light emitting brightness L2 of the low-frequency region, the light energy output by the high-frequency region and the low-frequency region within the same frame period is made consistent. In this way, even if the number of data writing times in the low-frequency region is reduced, the visual brightness substantially consistent with that of the high-frequency region can be achieved through the total equivalent light emission amount, thereby effectively improving the problem of uneven light emission existing in the display operation of the display panel 100.

[0049] Continuing with the combination of Figure 2 As shown, optionally, according to some embodiments of the present application, the first equivalent light emitting brightness of the sub-pixel Px in the first pixel row Line1 in the first data frame H1 is the sum value of the product of the pulse width of each first type light emitting pulse and the light emitting brightness of the sub-pixel Px in each first type light emitting pulse; The second equivalent light emitting brightness of the sub-pixel Px in the second pixel row Line2 in the first data frame H1 is the sum value of the product of the pulse width of each second type light emitting pulse and the light emitting brightness of the sub-pixel Px in each second type light emitting pulse.

[0050] In this embodiment, what is perceived by the human eye is the integrated light energy per unit time, rather than the instantaneous brightness change. Therefore, the equivalent light emitting brightness can be calculated following the superposition of brightness over time. Specifically, the first equivalent light emitting brightness of the sub-pixel Px in the first pixel row Line1 in the first data frame H1 is the sum of the products of the pulse width of each first type light emitting pulse and the light emitting brightness of the sub-pixel Px in each first type light emitting pulse.

[0051] Correspondingly, the second equivalent light emitting brightness of the sub-pixel Px in the second pixel row Line2 in the first data frame H1 is the sum of the products of the pulse width of each second type light emitting pulse and the light emitting brightness of the sub-pixel Px in each second type light emitting pulse.

[0052] Therefore, the equivalent luminous brightness can be regulated by two factors: luminous time and luminous intensity. When actually adjusting the equivalent luminous brightness, by regulating the product combination of these two luminous time and luminous intensity, the brightness balance control in the high and low frequency regions can be reliably achieved.

[0053] It should be added that, in specific implementation, exemplarily, the above regulation of the equivalent brightness can be achieved through a display driving chip. For example, by keeping the duty cycle of each luminous pulse consistent and regulating the luminous brightness of each sub-frame by changing the data writing voltage. Also, for example, by keeping the luminous current of each sub-frame constant and changing the luminous time by adjusting the pulse width of the luminous control signal of the shift register. Again, for example, simultaneously regulating the pulse width and the luminous brightness, which helps to obtain more gray-scale combinations and finer brightness control, and specific limitations are not made here.

[0054] Please refer to the following Figure 3 , optionally, according to some embodiments of the present application, the sum of the pulse widths of N first-type luminous pulses is the first pulse width, and the sum of the pulse widths of N second-type luminous pulses is the second pulse width; wherein, the first pulse width is equal to the second pulse width.

[0055] In this embodiment, setting the first pulse width equal to the second pulse width ensures that the total luminous time in the high and low frequency regions within a single data frame is equal, thereby reducing the complexity of the consistency regulation of the equivalent luminous brightness through the consistency in the time dimension.

[0056] Combined with Figure 3 shown, taking N = 3 as an example, that is, a data frame contains three sub-frame luminous pulses. For the first pixel row Line1 in the high frequency region, the pulse widths of the three first-type luminous pulses are T1, T2, and T3 respectively, then the first pulse width is T1 + T2 + T3. For the second pixel row Line2 in the low frequency region, the pulse widths of the three second-type luminous pulses can all be T4, then the second pulse width is 3 × T4. In this way, by constraining T1 + T2 + T3 = 3 × T4, the total luminous time of the two regions is made equal. In this case, combined with the regulation of the luminous brightness, the equivalent luminous brightness of the two regions can be made basically consistent.

[0057] It should be added that the first-type luminous pulses in the high frequency region can adopt the method of gradually increasing the pulse width, and satisfy T1 < T2 < T3. This increasing duty cycle modulation can improve the dynamic display ability and make the high frequency region more suitable for displaying fast-changing picture content. Also, the second-type luminous pulses in the low frequency region can adopt the method of uniform pulse width, that is, the pulse widths of the three luminous pulses are all T4, and T1 + T2 + T3 = 3 × T4. This uniform duty cycle modulation can improve the display stability of the low frequency display region and make it more suitable for displaying static content.

[0058] Alternatively, in some embodiments, the second type of light-emitting pulses in the low-frequency region may also adopt the same increasing duty cycle modulation as that in the high-frequency region, that is, the pulse widths also satisfy the relationship of T1 < T2 < T3, and the total light-emitting time remains the same. This helps to improve the uniformity of the overall display and ensure the synchronization of the light-emitting timings in the high- and low-frequency regions. Or, the second type of light-emitting pulses in the low-frequency region may also adopt a decreasing duty cycle modulation, or a modulation method with randomly varying pulse widths, which is not limited herein.

[0059] Optionally, according to some embodiments of the present application, the sum of the N light-emitting brightnesses of the sub-pixel Px in the first pixel row Line1 under N first type of light-emitting pulses is the first light-emitting brightness, and the sum of the N light-emitting brightnesses of the sub-pixel Px in the second pixel row Line2 under N second type of light-emitting pulses is the second light-emitting brightness; wherein, the first light-emitting brightness is equal to the second light-emitting brightness.

[0060] In this embodiment, by constraining the first light-emitting brightness to be equal to the second light-emitting brightness, in terms of light-emitting brightness, it is ensured that the total light energy benchmarks output in the high- and low-frequency regions within a single data frame are consistent, reducing the complexity of the consistency adjustment of the equivalent light-emitting brightness. The display driving chip can achieve the above-mentioned regulation of the equivalent brightness in various ways. One way is to fix the pulse width and adjust the light-emitting brightness: that is, keep the duty cycles of each light-emitting pulse consistent, and adjust the light-emitting brightness of each sub-frame by changing the data writing voltage.

[0061] Taking specific values as an example for illustration. Suppose there are three light-emitting pulses (N = 3) in a data frame. For the first pixel row Line1 in the high-frequency region, the light-emitting brightnesses under the three first type of light-emitting pulses are L1, L2, and L3 respectively, then the first light-emitting brightness is L1 + L2 + L3. For the second pixel row Line2 in the low-frequency region, the light-emitting brightnesses under the three second type of light-emitting pulses can all be L4, then the second light-emitting brightness is 3×L4. By constraining L1 + L2 + L3 = 3×L4, the total light-emitting brightnesses of the two regions are made equal.

[0062] It should be added that L1, L2, and L3 increase successively, so that the high-frequency region can improve the dynamic display ability by gradually increasing the brightness, and the low-frequency region ensures the display stability by a constant brightness.

[0063] In addition, in addition to the above example showing the differential light-emitting brightness setting in the high-frequency region and the uniform light-emitting brightness in the low-frequency region, when setting the light-emitting brightness of the high- and low-frequencies, both the high- and low-frequency regions adopt a uniform light-emitting brightness, which helps to simplify the driving control logic and is beneficial to reducing the circuit design complexity. Or, both the high- and low-frequency regions adopt a differential light-emitting brightness design, which is not strictly limited herein.

[0064] Therefore, in this embodiment, by setting the first luminous brightness to be equal to the second luminous brightness, the total luminous intensity of the high and low frequency regions remains consistent, which helps to achieve the consistency of the equivalent luminous brightness partitions and thus helps to reduce the brightness difference between the high and low frequency regions.

[0065] Please see below. Figure 4 Optionally, according to some embodiments of this application, in the first data frame H1, the first target light emission pulse is defined as the i-th first type light emission pulse of N first type light emission pulses, and the second target light emission pulse is defined as the i-th second type light emission pulse of N second type light emission pulses, i≤N, where i is a positive integer; The time interval between the midpoint of the first target emission pulse and the start time of the first data writing pulse among the m data writing pulses is the first duration t1; The time interval between the midpoint of the second target emission pulse and the start time of the first data writing pulse among the n data writing pulses is the second duration t2; where the first duration t1 is equal to the second duration t2.

[0066] In this embodiment, the time center point of the high-frequency region's light emission area and the time center point of the low-frequency region's light emission area are consistent relative to the data input time. In other words, the light emission pulses with corresponding sequence numbers are at the same relative time position within their respective data frames, thereby achieving synchronous alignment of the light emission timing of the two regions.

[0067] Therefore, the relative temporal stability of the emission time center point contributes to more stable emission in both high and low frequency regions, reducing visual flickering that may result from misaligned emission times. The timing alignment of the emission pulse center points ensures the stability and balance of emission in both high and low frequency regions. Furthermore, this aligned timing design also reduces the complexity of the timing design.

[0068] The following is combined with Figure 5 As shown, optionally, according to some embodiments of this application, if F1>F2, in the second data frame H2 of the display panel 100, the sub-pixel Px in the first pixel row Line1 is used to receive m data writing pulses and N first type of light emission pulses in a time-division manner; The sub-pix Px in the second pixel row Line2 is used to receive N second-type emission pulses in a time-division manner; Among them, the second data frame H2 is the data refresh frame of the first display area AA1 and the data hold frame of the second display area AA2.

[0069] In this embodiment, when F1 is greater than F2, a differentiated frame type setting is used in the second data frame H2 to further optimize power consumption. Specifically, the second data frame H2 is the data refresh frame for the first display area AA1 and the data hold frame for the second display area AA2. Within this frame period (second data frame H2), the sub-pixel Px in the first pixel row Line1 continues to receive m data write pulses and N first-type light emission pulses in a time-division manner to maintain normal dynamic display in the high-frequency area; while the sub-pixel Px in the second pixel row Line2 only receives N second-type light emission pulses and no longer receives new data write pulses. In this case, n can be equal to m.

[0070] In this way, since the low-frequency region has already completed data refresh (receiving n data write pulses) in the previous first data frame H1, the data voltage stored in its pixel circuit 101 remains valid in the second data frame H2, thus maintaining light emission without repeated writing. This omitting of the low-frequency region's data write operation achieves the effect of reducing power consumption.

[0071] The following is combined with Figure 6 As shown, optionally, according to some embodiments of this application, the plurality of data frames of the display panel 100 include at least two consecutive first data frames H1.

[0072] In this embodiment, the multiple data frames of the display panel 100 include at least two consecutive first data frames H1. Thus, the second display area AA2 for low-frequency display adopts a data refresh frame rather than a data hold frame operating mode. This is achieved by setting n to be less than m, for example... Figure 6 Even with n=1, low-frequency drive can still be achieved.

[0073] Specifically, in two consecutive first data frames H1, both the first display area AA1 and the second display area AA2 operate as data refresh frames. The sub-pixel Px in the first pixel row Line1 receives m data write pulses and N type-1 emission pulses in a time-division multiplexing manner within each first data frame H1, maintaining high-frequency dynamic display. Similarly, the sub-pixel Px in the second pixel row Line2 receives n data write pulses and N type-2 emission pulses in a time-division multiplexing manner within each first data frame H1, but n is less than m, thus achieving low-frequency driving.

[0074] For example, N=3, m=3, n=1. Within the first data frame H1, the high-frequency region performs three data writes and three emission operations, while the low-frequency region performs one data write and three emission operations. Within the second data frame H1, both regions repeat the same timing pattern. This reduces the data write frequency in the low-frequency region, thus helping to achieve low-frequency power-saving display driving.

[0075] Please refer to the following: Figure 7As shown, optionally, according to some embodiments of this application, among the N first-type light emission pulses, at least two of the first-type light emission pulses have different pulse widths.

[0076] In this embodiment, for the first display area AA1 of high-frequency display, the dynamic display capability is improved by differentiating the N first type of light emission pulses of the first display area AA1.

[0077] Please continue reading Figure 7 Optionally, according to some embodiments of this application, among the N first-type light-emitting pulses, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse, 1 < j ≤ N, and j is a positive integer; In the N type II emission pulses, the pulse width of each type II emission pulse is the same.

[0078] In this embodiment, the first display area AA1 can also employ light-emitting pulses with progressively increasing pulse widths. This further enhances dynamic display capabilities by subdividing the time dimension and distributing light-emitting energy output differently, facilitating high-frequency dynamic display and improving display effects. During actual display, earlier subframes quickly establish brightness, while later subframes accumulate light energy, resulting in better response characteristics and visual smoothness for rapidly changing screen content, thus facilitating high-frequency dynamic display.

[0079] Furthermore, in this embodiment, the second display area AA2 used for low-frequency display employs multiple light-emitting pulses with equal pulse widths, which can also improve the display stability of the low-frequency display area.

[0080] As a concrete example, combined with Figure 7 As shown, taking N=3 as an example, the pulse widths of the three first-type emission pulses in the high-frequency region can be set to T1=1μs, T2=2μs, and T3=3μs, forming an increasing sequence; the pulse widths of the three second-type emission pulses in the low-frequency region are all T4=2μs. By constraining the first pulse width to be equal to the second pulse width, T1+T2+T3=3×T4=6μs, thus achieving equal total emission times for both regions.

[0081] Combination Figure 8 As shown, optionally, according to some embodiments of this application, in N first-type light emission pulses, the pulse width of the (j-1)th first-type light emission pulse is less than the pulse width of the jth first-type light emission pulse, 1 < j ≤ N, and j is a positive integer; In N type II emission pulses, the pulse width of the (j-1)th type II emission pulse is less than the pulse width of the jth type II emission pulse.

[0082] In this embodiment, the same pulse width increment strategy is used in both high-frequency and low-frequency regions. Specifically, for the first display area AA1 of high-frequency display, the N first-type light-emitting pulses adopt a successively increasing pulse width distribution, that is, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse. For the second display area AA2 of low-frequency display, the N second-type light-emitting pulses also adopt a successively increasing pulse width distribution, that is, the pulse width of the (j-1)th second-type light-emitting pulse is less than the pulse width of the jth second-type light-emitting pulse.

[0083] As a concrete example, taking N=3, the pulse widths of the three first-type emission pulses in the high-frequency region can be set to T1=1μs, T2=2μs, and T3=3μs; the pulse widths of the three second-type emission pulses in the low-frequency region are also set to T1'=1μs, T2'=2μs, and T3'=3μs. By constraining the first pulse width to be equal to the second pulse width, the total emission time in both regions is naturally equal, both being 6μs.

[0084] Therefore, this embodiment synchronizes the emission timing of high and low frequency regions, ensuring that the start, center, and end times of emission for corresponding subframes remain consistent, thus improving the overall display uniformity. Both high and low frequencies utilize emission pulses with progressively increasing pulse widths, with the low-frequency emission time and high-frequency emission time allocated identically, further enhancing overall display uniformity. Furthermore, by employing the same timing control logic to generate both types of emission pulses during actual timing control, circuit complexity and manufacturing costs are reduced.

[0085] Combination Figure 9 As shown, optionally, according to some embodiments of this application, the pulse width of each of the N first-type light-emitting pulses is the same; In the N type II emission pulses, the pulse width of each type II emission pulse is the same.

[0086] In this embodiment, multiple light-emitting pulses with the same pulse width are used for both high and low frequencies, which can improve the display stability of the low-frequency display area. For example, taking N=3 as an example, the pulse width of the three first-type light-emitting pulses in the high-frequency area is T=2μs, and the total light-emitting time is 6μs; the pulse width of the three second-type light-emitting pulses in the low-frequency area is also T'=2μs, and the total light-emitting time is also 6μs.

[0087] By aligning the low-frequency and high-frequency emission times, overall display uniformity is improved. The consistent pulse width across all emission pulses in both the low-frequency and high-frequency regions ensures stable display and excellent performance across both frequencies. Furthermore, the identical pulse settings simplify timing control logic and reduce production complexity.

[0088] Combination Figure 10As shown, optionally, according to some embodiments of this application, the display panel 100 further includes a non-display area NA, in which a first gate driving circuit Emit1, a second gate driving circuit Emit2 and a signal gating circuit Mux are disposed, and the signal gating circuit Mux is electrically connected to the first gate driving circuit Emit1 and the second gate driving circuit Emit2 respectively. If F1 > F2, the first gate driving circuit Emit1 is configured to output a first type of light emission pulse to the sub-pix Px of the first display area AA1; The first gate driving circuit Emit1 or the second gate driving circuit Emit2 is configured to output a second type of light emission pulse to the sub-pix Px of the second display area AA2; The signal gating circuit Mux is configured to, under the control of the gating control line select, transmit the first type of light emission pulse provided by the first gate driving circuit Emit1 as the second type of light emission pulse to the sub-pixel Px of the second display area AA2, or transmit the second type of light emission pulse provided by the second gate driving circuit Emit2 to the sub-pixel Px of the second display area AA2.

[0089] In this embodiment, the display panel 100 employs a dual-gate driving circuit architecture and a signal gating mechanism in the non-display area NA to support flexible implementation of zone driving. Specifically, the non-display area NA includes a first gate driving circuit Emit1, a second gate driving circuit Emit2, and a signal gating circuit Mux. The signal gating circuit Mux is electrically connected to both the first gate driving circuit Emit1 and the second gate driving circuit Emit2, forming selectable light-emitting pulse transmission paths. It should be noted that the signal gating circuit Mux can be configured for all pixel rows or for specific pixel rows in key low-frequency display areas; this is not limited here.

[0090] When F1 is greater than F2, the first gate driving circuit Emit1 is configured to output a first type of light-emitting pulse to the sub-pix Px of the first display area AA1, directly driving the light emission control of the high-frequency area. For the second type of light-emitting pulse of the second display area AA2, either the first gate driving circuit Emit1 or the second gate driving circuit Emit2 can be configured to output a second type of light-emitting pulse to the sub-pix Px of the second display area AA2.

[0091] The aforementioned signal gating circuit Mux, under the control of the gating control line select, implements two working modes: one is to transmit the first type of light emission pulse provided by the first gate driving circuit Emit1 as the second type of light emission pulse to the sub-pixel Px of the second display area AA2, so that the low-frequency area reuses the light emission control signal of the high-frequency area; the other is to transmit the second type of light emission pulse provided by the second gate driving circuit Emit2 to the sub-pixel Px of the second display area AA2, in which case the low-frequency area uses the independently generated light emission control signal.

[0092] Thus, for example, when the timing characteristics of the first type of light-emitting pulse and the second type of light-emitting pulse are consistent (e.g., both use a uniform pulse width or the same increasing pulse width), for example, when the refresh rates of the first display area AA1 and the second display area AA2 are equal and both are high-frequency areas, combined with Figure 11 As shown, the output of the first gate driving circuit Emit1 can be directly multiplexed to the low-frequency region, enabling the high and low frequency regions to share the same light-emitting control circuit. Alternatively, the signal gating circuit Mux can be activated to select one of the first gate driving circuits Emit1 and the second gate driving circuit Emit2 to transmit to the low-frequency region.

[0093] In other embodiments, when the first type of light-emitting pulse and the second type of light-emitting pulse require different timing characteristics (e.g., using an increasing pulse width in the high-frequency region and a uniform pulse width in the low-frequency region), the second type of light-emitting pulse can be generated independently by the second gate driving circuit Emit2, and switched to this independent path by the signal gating circuit Mux to meet specific display and driving requirements.

[0094] Therefore, in this embodiment, two gate driving circuits are set up: the first gate driving circuit Emit1 and the second gate driving circuit Emit2, and combined with the signal gating circuit Mux to realize the reliable generation of the first type of light emission pulse and the second type of light emission pulse received in the high and low frequency regions.

[0095] It should be added that when the first type of light emission pulse and the second type of light emission pulse are the same, the first gate driving circuit Emit1 and the second gate driving circuit Emit2 are the same gate driving circuit. This can reduce redundant circuit design, lower panel manufacturing costs, and reduce bezel width.

[0096] Optionally, according to some embodiments of this application, the first gate driving circuit Emit1 includes a plurality of cascaded first shift registers 10, the second gate driving circuit Emit2 includes a plurality of cascaded second shift registers 20; and the signal gating circuit Mux includes at least one signal gating unit 30. Combination Figure 12As shown, the control terminal of the signal gating unit 30 is electrically connected to the gating control line select. The first input terminal and the second input terminal of the signal gating unit 30 are electrically connected to the output terminals of the corresponding first shift register 10 and the second shift register 20, respectively. The output terminal of the signal gating unit is electrically connected to the target pixel row in the second display area AA2.

[0097] In this embodiment, the first gate driving circuit Emit1 includes multiple cascaded first shift registers 10, and the second gate driving circuit Emit2 includes multiple cascaded second shift registers 20. The specific cascaded structure can generate corresponding timing scan signals. The signal gating circuit Mux includes at least one signal gating unit 30, thereby enabling the selection output from either the first gate driving circuit Emit1 or the second gate driving circuit Emit2 to the second display area AA2.

[0098] In terms of circuit connections, the control terminal of the signal gating unit 30 is electrically connected to the gating control line select, which can be led out from the driver chip to achieve reliable control. The first input terminal of the signal gating unit 30 is electrically connected to the output terminal of the corresponding first shift register 10, and the second input terminal is electrically connected to the output terminal of the corresponding second shift register 20, thereby simultaneously acquiring the light emission control signals of the first shift register 10 and the second shift register 20. The output terminal of the signal gating unit 30 is electrically connected to the target pixel row in the second display area AA2, responsible for transmitting the selected light emission pulse to the specific pixel driving circuit.

[0099] Taking a specific application scenario as an example, when the target pixel row needs to receive the first type of emission pulse synchronized with the high-frequency region, the select control line outputs a corresponding level, and the signal selection unit 30 opens the transmission path from the first input terminal to its output terminal, transmitting the emission control signal output by the first shift register 10 as the second type of emission pulse to the target pixel row. When the target pixel row needs to receive the independently generated second type of emission pulse, the select control line switches its level state, and the signal selection unit 30 opens the transmission path from the second input terminal to its output terminal, transmitting the emission control signal output by the second shift register 20 to the target pixel row.

[0100] Therefore, through the first gate driving circuit Emit1, the second gate driving circuit Emit2, and the signal gating circuit Mux, high and low frequency light emission control scanning can be effectively realized, so that the high frequency region is directly driven by the first gate driving circuit Emit1, while the low frequency region is dynamically selected between the two types of light emission pulses through the signal gating circuit Mux, thus optimizing the driving architecture of the display panel 100 in the case of high and low frequency partition driving.

[0101] Combination Figure 13As shown, optionally, according to some embodiments of this application, the signal gating unit 30 includes a first switch T1 and a second switch T2, and the gating control line select includes a first gating control line select1 and a second gating control line select2; The control terminal of the first switch T1 is electrically connected to the first gating control line select1, the first terminal of the first switch T1 is connected to the output terminal of the corresponding first shift register 10, and the second terminal of the first switch T1 is electrically connected to the target pixel row. The control terminal of the second switch T2 is electrically connected to the second gating control line select2. The first terminal of the second switch T2 is connected to the output terminal of the corresponding second shift register 20. The second terminal of the second switch T2 is electrically connected to the target pixel row.

[0102] In this embodiment, the signal gating unit 30 includes a first switch T1 and a second switch T2. The first switch T1 and the second switch T2 are respectively gating controlled by the corresponding first gating control line select1 and the second gating control line select2, thereby realizing flexible switching of the outputs of the two sets of gate driving circuits.

[0103] Specifically, in terms of circuit connections, the control terminal of the first switch T1 is electrically connected to the first gating control line select1, the first end of the first switch T1 is connected to the output terminal of the corresponding first shift register 10, and the second end of the first switch T1 is electrically connected to the target pixel row, thereby forming a signal transmission path from the first gate driving circuit Emit1 to the low-frequency pixel row. The control terminal of the second switch T2 is electrically connected to the second gating control line select2, the first end of the second switch T2 is connected to the output terminal of the corresponding second shift register 20, and the second end of the second switch T2 is electrically connected to the target pixel row, thereby forming a signal transmission path from the second gate driving circuit Emit2 to the low-frequency pixel row.

[0104] In practical operation, for example, when the first type of light-emitting pulse provided by the first gate driving circuit Emit1 needs to be selected, the first gating control line select1 outputs a valid level (e.g., high level), the first switch T1 is turned on, and the output signal of the first shift register 10 is transmitted to the target pixel row through the first switch T1; at this time, the second gating control line select2 outputs an invalid level (e.g., low level), the second switch T2 is turned off, thereby disconnecting the output path of the second shift register 20. Conversely, when the second type of light-emitting pulse provided by the second gate driving circuit Emit2 needs to be selected, the second gating control line select2 outputs a valid level, the second switch T2 is turned on, the first gating control line select1 outputs an invalid level, and the first switch T1 is turned off, realizing flexible and reliable switching of the transmission path.

[0105] Therefore, through the first switch T1 and the second switch T2, the signal gating circuit Mux can stably and efficiently complete the switching function of the output of the first gate drive circuit Emit1 and the second gate drive circuit Emit2.

[0106] Combination Figure 14 As shown, optionally, according to some embodiments of this application, the signal gating unit 30 includes a first switch T1 and a second switch T2; The control terminal of the first switch T1 is electrically connected to the select control line, the first terminal of the first switch T1 is connected to the output terminal of the corresponding first shift register 10, and the second terminal of the first switch T1 is electrically connected to the target pixel row. The control terminal of the second switch T2 is electrically connected to the select control line; the first terminal of the second switch T2 is connected to the output terminal of the corresponding second shift register 20; and the second terminal of the second switch T2 is electrically connected to the target pixel row. One of the first switch T1 and the second switch T2 is an N-type transistor, and the other is a P-type transistor.

[0107] In this embodiment, one of the first switch T1 and the second switch T2 is an N-type transistor, and the other is a P-type transistor. The N-type transistor has a high on-level and a low off-level; the P-type transistor has a low on-level and a high off-level.

[0108] Thus, when the select control line outputs a high level, the N-type transistor is turned on and the P-type transistor is turned off. One output of either the first gate drive circuit Emit1 or the second gate drive circuit Emit2 is transmitted to the target pixel row, while the other is cut off. When the select control line outputs a low level, the P-type transistor is turned on and the N-type transistor is turned off, thereby switching the selection state.

[0109] In this way, by setting the switch types of the first switch T1 and the second switch T2 to be opposite, only one select control line is needed to select the two switches, thereby simplifying the wiring layout of the select control line, reducing the complexity of the control timing, reducing the timing deviation that may be caused by the control of two select signal lines, and improving the synchronization and reliability of the selection process.

[0110] Optionally, according to some embodiments of this application, if F2=F, the signal gating circuit Mux is configured to transmit the first type of light emission pulse provided by the first gate driving circuit Emit1 as the second type of light emission pulse to the sub-pix Px of the second display area AA2 under the control of the gating control line select; Where F is the refresh rate of the display panel 100 during normal high-frequency display.

[0111] In this embodiment, when the refresh frequency F2 of the second display area AA2 is equal to the refresh frequency F of the display panel 100 during normal high-frequency display, for example, F2 is equal to the refresh frequency of 120Hz of the display panel 100 during normal high-frequency display, the second display area AA2 enters the same normal high-frequency display state as the first display area AA1. At this time, it is not necessary to use the second gate driving circuit Emit2 to generate an independent second type of light emission pulse, but the output of the first gate driving circuit Emit1 is directly multiplexed to the second display area AA2 through the signal gating circuit Mux.

[0112] In this way, the first display area AA1 and the second display area AA2 share the same set of light emission control timing, ensuring display synchronization at a unified refresh rate. This also reduces redundant startup of the second gate drive circuit Emit2, lowers power consumption in normal display mode, and reduces potential timing deviations between the first gate drive circuit Emit1 and the second gate drive circuit Emit2, thereby helping to improve the uniformity of the full-screen display.

[0113] Combination Figure 15 As shown, optionally, according to some embodiments of this application, the first pixel row Line1 and the second pixel row Line2 include a plurality of sub-pixels Px, each sub-pixel Px including a pixel circuit 101 and a light-emitting device D, the pixel circuit 101 including: The driving module 110 is used to drive the light-emitting device D to emit light; The data writing module 120 is used to transmit the data voltage provided by the data signal line to the drive module 110 in response to the data writing pulse. The light-emitting control module 130 is used to turn on in response to a first type of light-emitting pulse or a second type of light-emitting pulse, so as to transmit the driving current provided by the driving module 110 to the light-emitting device D.

[0114] In this embodiment, both the first pixel row Line1 and the second pixel row Line2 include multiple sub-pixels Px. In the pixel circuit 101 of the sub-pixels Px, the driving module 110 is used to drive the light-emitting device D to emit light, and can generate a corresponding driving current according to the received data voltage to drive the light-emitting device D to emit light.

[0115] The aforementioned data writing module 120 is used to transmit the data voltage provided by the data signal line to the driver module 110 in response to a data writing pulse, thereby completing the refresh operation of the display data. When the data writing pulse arrives, the data writing module 120 is turned on, and the voltage on the data signal line is sampled and stored in the storage node (such as a capacitor) of the driver module 110.

[0116] The aforementioned light-emitting control module 130 is used to turn on in response to a first type of light-emitting pulse or a second type of light-emitting pulse, so as to transmit the driving current provided by the driving module 110 to the light-emitting device D. When the light-emitting pulse arrives, the light-emitting control module 130 turns on, and the driving current flows through the light-emitting device D to make it emit light; after the light-emitting pulse ends, the light-emitting control module 130 turns off, and the light-emitting device D stops emitting light.

[0117] Taking a specific working sequence as an example, during the data refresh phase, when the data write pulse arrives, the data write module 120 is turned on, and the data voltage is written to the drive module 110. Subsequently, during the light emission phase, when either the first type of light emission pulse or the second type of light emission pulse arrives, the light emission control module 130 is turned on, and the drive module 110 generates a drive current according to the data voltage, driving the light emission device D to emit light during the duration of the light emission pulse.

[0118] Therefore, through the driving module 110, data writing module 120 and light emission control module 130 in the pixel circuit 101, the pixel circuit 101 in different display areas can flexibly and reliably respond to differentiated partition driving control.

[0119] Understandably, considering that the 7T1C pixel circuit 101 is a relatively conventional pixel circuit 101, for the sake of simplicity, it will not be discussed further here. Figure 15 The pixel circuit 101 in the diagram will be explained in detail.

[0120] It should be noted that the display panel 100 provided in this application embodiment can be an organic light-emitting diode (OLED) display panel 100. Those skilled in the art should understand that in other implementations of this application, the display panel 100 can also be a micro light-emitting diode (Micro LED) display panel 100, a quantum dot display panel 100, etc.

[0121] Based on the same inventive concept, this application provides a method for controlling the light emission of a display panel, applicable to any of the display panels provided in the foregoing embodiments of this application. The display panel includes a first display area and a second display area. The first display area includes a first pixel row, and the second display area includes a second pixel row. The refresh rate of the first display area is F1, and the refresh rate of the second display area is F2. Please refer to the following... Figure 16 , Figure 16 This is a schematic flowchart illustrating a method for controlling the light emission of a display panel according to an embodiment of this application. Figure 16 As shown, the light emission control method of this display panel includes: S1601, if F1>F2, within the first data frame of the display panel, control the sub-pixels in the first pixel row to receive m data writing pulses and N first-type light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N; S1602, control the sub-pixels in the second pixel row to receive n data write pulses and N second-type light emission pulses in a time-division manner, the first data frame is the data refresh frame of the first display area and the second display area; where m is a positive integer, n≤m; where the equivalent light emission brightness of the sub-pixels in the first pixel row under the first data frame is the first equivalent light emission brightness L1, and the equivalent light emission brightness of the sub-pixels in the second pixel row under the first data frame is the second equivalent light emission brightness L2, L1=L2.

[0122] In practical implementation, when F1 is greater than F2, within the first data frame of the display panel, the sub-pixels in the first pixel row are controlled to receive m data write pulses and N first-type light emission pulses in a time-division manner, and the sub-pixels in the second pixel row are controlled to receive n data write pulses and N second-type light emission pulses in a time-division manner. Furthermore, the equivalent luminous intensity of the sub-pixels in the first pixel row under the first data frame is controlled to be the first equivalent luminous intensity L1, which is equal to the equivalent luminous intensity of the sub-pixels in the second pixel row under the first data frame being the second equivalent luminous intensity L2.

[0123] Taking a specific control process as an example, at the beginning of the first data frame, the display driver chip outputs m data write pulses to the first pixel row. After or simultaneously with each data write pulse, it starts outputting the corresponding first-type light emission pulse, forming a sequence of N first-type light emission pulses. For the second pixel row, the display driver chip outputs n data write pulses and N second-type light emission pulses, maintaining the same number of light emission pulses as the high-frequency region. By adjusting the pulse width and brightness of each light emission pulse, the sum of the equivalent brightness products of the two regions is made equal, thereby achieving consistency in the brightness perceived by the human eye.

[0124] Therefore, by differentiating the number of data writing pulses, the data refresh rate in the low-frequency region is reduced, thereby optimizing power consumption. By ensuring the same number of light emission pulses, the light emission frequency of the two regions is maintained. Furthermore, by ensuring consistent equivalent light emission brightness, the visual effect of the high- and low-frequency regions is made basically consistent. This solves the problem in existing technologies that it is difficult to maintain the light emission frequency while reducing the data writing frequency, and achieves the technical effect of improving uneven light emission.

[0125] In summary, the light emission control method for a display panel according to an embodiment of this application controls the supply of m data write pulses and N first-type light emission pulses to the first pixel row in the high-frequency region, while simultaneously controlling the supply of n data write pulses and N second-type light emission pulses to the second pixel row in the low-frequency region. This reduces the number of data write pulses in the low-frequency region, making the adjustment of the data write frequency independent of the maintenance of the light emission frequency, thereby reducing power consumption while maintaining continuous light emission. Furthermore, uniformity of display brightness is provided through balanced control of equivalent light emission brightness. By controlling the equivalent light emission brightness L1 of the high-frequency region in the first data frame to be equal to the equivalent light emission brightness L2 of the low-frequency region, the light energy output by the high-frequency and low-frequency regions within the same frame period is made consistent. Thus, even if the number of data writes in the low-frequency region is reduced, the visual brightness can still be basically consistent with that of the high-frequency region through the equivalent total light emission, thereby effectively improving the problem of uneven light emission in the display panel operation.

[0126] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 17 , Figure 17 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 17 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 17 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 100 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments. These descriptions will not be repeated here.

[0127] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0128] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0129] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, The display panel includes a first display area and a second display area. The first display area includes a first pixel row, and the second display area includes a second pixel row. The refresh rate of the first display area is F1, and the refresh rate of the second display area is F2. If F1>F2, in the first data frame of the display panel, the sub-pixels in the first pixel row are used to receive m data write pulses and N first-type light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N; The sub-pixels in the second pixel row are used to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame is the data refresh frame of the first display area and the second display area; where m is a positive integer and n≤m; Wherein, the equivalent luminance of the sub-pixels in the first pixel row under the first data frame is the first equivalent luminance L1, and the equivalent luminance of the sub-pixels in the second pixel row under the first data frame is the second equivalent luminance L2, where L1=L2.

2. The display panel according to claim 1, characterized in that, The first equivalent luminous intensity of the sub-pixel in the first pixel row in the first data frame is the sum of the products of the pulse width of each first type of luminous pulse and the luminous intensity of the sub-pixel in each first type of luminous pulse; The second equivalent luminance of the sub-pixel in the second pixel row in the first data frame is the sum of the products of the pulse width of each second type of luminous pulse and the luminance of the sub-pixel in each second type of luminous pulse.

3. The display panel according to claim 1, characterized in that, The sum of the pulse widths of the N first-type light-emitting pulses is the first pulse width, and the sum of the pulse widths of the N second-type light-emitting pulses is the second pulse width; Wherein, the first pulse width is equal to the second pulse width.

4. The display panel according to claim 1, characterized in that, The sum of the N luminance values ​​of the sub-pixels in the first pixel row under the N first type of luminous pulses is the first luminance value, and the sum of the N luminance values ​​of the sub-pixels in the second pixel row under the N second type of luminous pulses is the second luminance value; Wherein, the first luminous intensity is equal to the second luminous intensity.

5. The display panel according to claim 1, characterized in that, In the first data frame, the first target luminous pulse is defined as the i-th first type luminous pulse among the N first type luminous pulses, and the second target luminous pulse is defined as the i-th second type luminous pulse among the N second type luminous pulses, where i ≤ N and i is a positive integer; The time interval between the midpoint of the first target emission pulse and the start time of the first data writing pulse among the m data writing pulses is the first duration; The time interval between the midpoint of the second target emission pulse and the start time of the first data write pulse among the n data write pulses is the second duration; wherein, the first duration is equal to the second duration.

6. The display panel according to claim 1, characterized in that, If F1>F2, in the second data frame of the display panel, the sub-pixels in the first pixel row are used to receive the m data writing pulses and the N first type of light emission pulses in a time-division manner; The sub-pixels in the second pixel row are used to receive the N second type of emission pulses in a time-division manner; The second data frame is a data refresh frame for the first display area and a data hold frame for the second display area.

7. The display panel according to claim 1, characterized in that, The display panel includes at least two consecutive first data frames among its multiple data frames.

8. The display panel according to claim 1, characterized in that, Of the N type I light-emitting pulses, at least two type I light-emitting pulses have different pulse widths.

9. The display panel according to claim 8, characterized in that, Among the N first-type light-emitting pulses, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse, 1 < j ≤ N, and j is a positive integer; Among the N second-type light-emitting pulses, the pulse width of each second-type light-emitting pulse is the same.

10. The display panel according to claim 8, characterized in that, Among the N first-type light-emitting pulses, the pulse width of the (j-1)th first-type light-emitting pulse is less than the pulse width of the jth first-type light-emitting pulse, 1 < j ≤ N, and j is a positive integer; Among the N second-type light emission pulses, the pulse width of the (j-1)th second-type light emission pulse is smaller than the pulse width of the jth second-type light emission pulse.

11. The display panel according to claim 1, characterized in that, Among the N first-type light-emitting pulses, the pulse width of each first-type light-emitting pulse is the same; Among the N second-type light-emitting pulses, the pulse width of each second-type light-emitting pulse is the same.

12. The display panel according to any one of claims 1-11, characterized in that, The display panel also includes a non-display area, in which a first gate driving circuit, a second gate driving circuit, and a signal gating circuit are disposed, and the signal gating circuit is electrically connected to the first gate driving circuit and the second gate driving circuit respectively. If F1 > F2, the first gate driving circuit is configured to output the first type of light emission pulse to the sub-pixel of the first display area; The first gate driving circuit or the second gate driving circuit is configured to output the second type of light emission pulse to the sub-pixel of the second display area; The signal gating circuit is configured to, under the control of the gating control line, transmit the first type of light-emitting pulse provided by the first gate driving circuit as the second type of light-emitting pulse to the sub-pixel of the second display area, or transmit the second type of light-emitting pulse provided by the second gate driving circuit to the sub-pixel of the second display area.

13. The display panel according to claim 12, characterized in that, The first gate driving circuit includes multiple cascaded first shift registers, and the second gate driving circuit includes multiple cascaded second shift registers; the signal gating circuit includes at least one signal gating unit. The control terminal of the signal gating unit is electrically connected to the gating control line. The first input terminal and the second input terminal of the signal gating unit are electrically connected to the output terminals of the corresponding first shift register and the second shift register, respectively. The output terminal of the signal gating unit is electrically connected to the target pixel row in the second display area.

14. The display panel according to claim 13, characterized in that, The signal gating unit includes a first switch and a second switch, and the gating control line includes a first gating control line and a second gating control line; The control terminal of the first switch is electrically connected to the first gating control line, the first terminal of the first switch is connected to the output terminal of the corresponding first shift register, and the second terminal of the first switch is electrically connected to the target pixel row. The control terminal of the second switch is electrically connected to the second gating control line, the first terminal of the second switch is connected to the output terminal of the corresponding second shift register, and the second terminal of the second switch is electrically connected to the target pixel row.

15. The display panel according to claim 13, characterized in that, The signal gating unit includes a first switch and a second switch; The control terminal of the first switch is electrically connected to the gating control line, the first terminal of the first switch is connected to the output terminal of the corresponding first shift register, and the second terminal of the first switch is electrically connected to the target pixel row. The control terminal of the second switch is electrically connected to the gating control line, the first terminal of the second switch is connected to the output terminal of the corresponding second shift register, and the second terminal of the second switch is electrically connected to the target pixel row. One of the first switch and the second switch is an N-type transistor, and the other is a P-type transistor.

16. The display panel according to claim 12, characterized in that, If F2=F, the signal gating circuit is configured to transmit the first type of light emission pulse provided by the first gate driving circuit as the second type of light emission pulse to the sub-pixel of the second display area under the control of the gating control line; Wherein, F is the refresh rate of the display panel during normal high-frequency display.

17. The display panel according to any one of claims 1-11, characterized in that, The first pixel row and the second pixel row each include a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device, the pixel circuit including: A driving module is used to drive the light-emitting device to emit light; A data writing module is used to transmit the data voltage provided by the data signal line to the driving module in response to the data writing pulse; A light-emitting control module is configured to conduct in response to a first type of light-emitting pulse or a second type of light-emitting pulse, so as to transmit the driving current provided by the driving module to the light-emitting device.

18. A method for controlling the light emission of a display panel, characterized in that, Applied to a display panel as described in any one of claims 1-17, characterized in that the display panel includes a first display area and a second display area, the first display area includes a first pixel row, and the second display area includes a second pixel row; the refresh rate of the first display area is F1, and the refresh rate of the second display area is F2; ​​the method includes: If F1>F2, within the first data frame of the display panel, the sub-pixels in the first pixel row are controlled to receive m data write pulses and N first-type light emission pulses in a time-division manner, where m and N are positive integers, N≥2, and m≤N; The sub-pixels in the second pixel row are controlled to receive n data write pulses and N second-type light emission pulses in a time-division manner. The first data frame is the data refresh frame of the first display area and the second display area; where m is a positive integer and n≤m; Wherein, the equivalent luminance of the sub-pixels in the first pixel row under the first data frame is the first equivalent luminance L1, and the equivalent luminance of the sub-pixels in the second pixel row under the first data frame is the second equivalent luminance L2, where L1=L2.

19. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-17.

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