A latch-type sense amplifier and a timing control method therefor

Abstract

This invention relates to a latch-type sense amplifier and a timing control method therefor, belonging to the field of memory technology. It solves the problem that the insufficient mismatch resistance of single-gate TFTs prevents a fundamental breakthrough in overall sensing speed and accuracy. The sense amplifier includes: a reset switch pair connected between the power supply voltage and the output node and between the power supply voltage and the inverting output node; a first positive feedback loop connected in parallel with the seventh and ninth transistors between the power supply voltage and the output node and the inverting output node; a second positive feedback loop connected via its drain to the drains of the sixth and eighth transistors; and an input transistor pair, whose source is connected to ground via the first transistor and whose drain is connected to the source of the fourth and fifth transistors. The second and third transistors are both independent dual-gate IDG indium gallium zinc oxide IGZO field-effect transistors (FETs). An adjustable threshold voltage can be provided using the top gate of the IDG IGZO TFT.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a latch-type sense amplifier and a timing control method therefor. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in various electronic systems due to its high integration and low cost. With the continuous development of integrated circuit technology, the size of DRAM memory cell arrays has increased dramatically, leading to a continuous rise in the parasitic capacitance of bit lines and word lines. This has highlighted the growing contradiction between memory read / write speed and power consumption. Furthermore, process mismatch and low-voltage power supply environments place more stringent demands on the readout circuitry. In the memory readout path, the sense amplifier (SA) is the core of the DRAM readout path. Its main function is to level the bit line voltage during the precharge phase and rapidly boost the millivolt-level bit line differential voltage to the full swing level during the sensing phase. Its performance directly affects the memory's access latency, static and dynamic power consumption, and the reliability of data readout.

[0003] like Figure 1 , Figure 2 and Figure 3 As shown, commonly used sense amplifiers are mainly divided into three types: operational amplifier type, cross-coupled type, and latch type. Operational amplifier (OPA) sense amplifiers have the advantages of high amplification and high sensitivity, but their speed is relatively slow. Furthermore, because OPA sense amplifiers have dual-input, single-output characteristics, they are often used in pairs, occupying a large layout area. While cross-coupled sense amplifiers overcome the shortcomings of OPA structures and increase amplification speed, their gain and sensitivity are very low, and their power consumption is also high. Basic latch-type amplifier structures are generally not used in DRAM due to their parasitic capacitance and high power consumption. To address these shortcomings, an improved STRONG ARM latch-type sense amplifier has been proposed. This amplifier introduces positive feedback through cross-coupling of PMOS and NMOS transistors, allowing a small differential voltage to be exponentially amplified to saturation level within nanoseconds. This structure achieves significant improvements in bandwidth and noise suppression, but because the upper-layer input transistor cannot be completely turned off during the pre-charge standby phase, leakage current increases; simultaneously, process mismatch is amplified during positive feedback, introducing a large initial offset voltage. This necessitates additional offset correction circuitry or redundant design to ensure sensing accuracy, thereby increasing circuit complexity and layout costs. Some solutions introduce single-gate thin-film transistors (TFTs) to isolate leakage during the precharge stage, but the mismatch immunity of single-gate TFTs is insufficient, preventing a fundamental breakthrough in overall sensing speed and accuracy. As process nodes shrink and memory density increases, bit line capacitance and parasitic impedance rise, requiring sensing amplifiers to achieve higher sensing accuracy, lower quiescent power consumption, and better mismatch immunity. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a latch-type sensing amplifier and a timing control method therefor, in order to solve the problem that the introduction of a single-gate thin-film transistor (TFT) to isolate leakage in the pre-charge stage, but the single-gate TFT has insufficient mismatch resistance, which prevents a fundamental breakthrough in the overall sensing speed and sensing accuracy.

[0005] On one hand, embodiments of the present invention provide a latch-type sense amplifier, comprising: a reset switch pair, including a seventh transistor and a ninth transistor, for being respectively connected between a power supply voltage and an output node and between the power supply voltage and an inverting output node; a first positive feedback loop, including a sixth transistor and an eighth transistor, connected in parallel with the seventh transistor and the ninth transistor between the power supply voltage and the output node and between the power supply voltage and the inverting output node; a second positive feedback loop, including a fourth transistor and a fifth transistor, the drain of the fourth transistor being connected to the drain of the sixth transistor and the drain of the fifth transistor being connected to the drain of the eighth transistor; and an input transistor. The transistor pair includes a second transistor and a third transistor, the sources of which are connected to ground via a first transistor. The drain of the second transistor is connected to the source of the fourth transistor, and the drain of the third transistor is connected to the source of the fifth transistor. The gate connection node of the fourth transistor and the sixth transistor is connected to the drain connection node of the eighth transistor and the fifth transistor as an output node. The gate connection node of the eighth transistor and the fifth transistor is connected to the drain connection node of the fourth transistor and the sixth transistor as an inverting output node. The second transistor and the third transistor are both independent dual-gate indium gallium zinc oxide (IGZO) field-effect transistors (FETs).

[0006] The beneficial effects of the above technical solution are as follows: For the first time, an independent dual-gate IGZO TFT is used to replace the traditional Si NMOS in the differential input stage of a STRONG-ARM latching sense amplifier, and it can be integrated with Si-CMOS positive feedback stages (M4-M9). The top gate of the IDG IGZO TFT can provide an adjustable threshold voltage, directly compensating for the increased offset voltage caused by mismatch during manufacturing with gate bias, eliminating the need for additional correction circuitry.

[0007] Based on a further improvement of the above-described device, the threshold voltage of the second transistor or the third transistor is adjusted by applying a bias voltage to the top gate of the second transistor or the third transistor.

[0008] Based on further improvements to the above-described device, as the bias voltage applied to the top gate of the second transistor or the third transistor increases, the threshold voltage of the second transistor or the third transistor decreases.

[0009] Based on further improvements to the above-mentioned device, the independent dual-gate IDG indium gallium zinc oxide IGZO field-effect transistor FET is buried in the interconnect layer through back-end processes, or directly stacked on top of the memory array.

[0010] Based on further improvements to the above-mentioned device, the first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are silicon-based field-effect transistors.

[0011] Based on further improvements to the above-mentioned device, the first transistor is a tail-end NMOS bias transistor; the fourth and fifth transistors are NMOS transistors; and the sixth, seventh, eighth, and ninth transistors are PMOS transistors.

[0012] Based on a further improvement of the above-described device, the back gate of the second transistor is connected to a bit line, through which an input signal is received; and the back gate of the third transistor receives a reference signal; the gates of the first transistor, the seventh transistor, and the ninth transistor all receive control signals.

[0013] On the other hand, embodiments of the present invention provide a timing control method for a latch-type sense amplifier, comprising: during the sensing amplification phase of the latch-type sense amplifier described above, adjusting the threshold voltage of the second transistor or the third transistor by applying different bias voltages to the top gate of the second transistor or the third transistor.

[0014] Based on a further improvement of the above method, the operating stages of the latch-type sense amplifier include a pre-charge stage, a row selection and sampling stage, a sense amplification stage, and a reset stage. In the pre-charge stage, the seventh and ninth transistors in the reset switch pair are turned on based on a high-level control signal, pulling the voltages of the output node and the inverting output node up to the power supply voltage. The gates of the second and third transistors in the input transistor pair receive equal input voltages and reference voltages, respectively. In the row selection and sampling stage, during the selection of a memory cell row, the storage capacitor in the memory cell charges and discharges the bit line through the storage transistor, causing an imbalance in the bit line pair. The input voltage is different from the reference voltage. The gate of the second transistor is connected to the bit line, while the gate of the third transistor... The first transistor is connected to the anti-phase line. During the sensing amplification phase, the seventh and ninth transistors are turned off according to a low-level control signal, and the first transistor at the tail is turned on according to a low-level control signal, so that the sources of the second and third transistors are grounded through the turned-on first transistor. The turned-on second and third transistors convert the voltage difference between the input voltage and the reference voltage into a current difference. The first positive feedback loop and the second positive feedback loop are used to amplify the input signal. During the reset phase, one of the output node and the inverting output node is close to zero, and the other is close to the power supply voltage. The control signal is low, the first transistor is turned off, and the seventh and ninth transistors are turned on, so that the output node and the inverting output node are reset to the power supply voltage.

[0015] Based on a further improvement of the above method, the first positive feedback loop includes a sixth transistor and an eighth transistor, which are respectively connected between the power supply voltage and the output node and between the power supply voltage and the inverting output node; the second positive feedback loop includes a fourth transistor and a fifth transistor, the drain of the fourth transistor is connected to the inverting output node and its source is connected to the drain of the second transistor, the drain of the fifth transistor is connected to the output node and its source is connected to the drain of the third transistor, wherein, when the input voltage is greater than the reference voltage, the fourth transistor and the eighth transistor are turned on, such that the turned-on fourth transistor and the eighth transistor amplify the input signal; when the input voltage is less than the reference voltage, the fifth transistor and the sixth transistor are turned on, such that the turned-on fifth transistor and the sixth transistor amplify the input signal.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] (1) The differential input stage of the STRONG-ARM latching sense amplifier uses an independent dual-gate IGZO TFT to replace the traditional Si NMOS for the first time, and can be integrated with the Si-CMOS positive feedback stage (M4-M9). The top gate of the IDG IGZO TFT can provide an adjustable threshold voltage, and the gate bias can directly compensate for the increased offset voltage caused by mismatch in the manufacturing process without the need for additional correction circuitry.

[0018] (2) By relying on the dual isolation of the input IGZO TFT and the enable switch, the static power consumption of the amplifier during the precharge stage is significantly lower than that of the pure Si-CMOS solution. The IGZO TFT has BEOL compatibility and can be embedded in 3D-DRAM through vertical stacking, further saving the layout area of ​​the sense amplifier. This sense amplifier can achieve a combination of performance indicators such as an initial offset voltage of less than ±10 mV and a sense delay in the nanosecond range at a low voltage of 1.5 V.

[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0021] Figure 1 This is a basic structural diagram of an existing operational amplifier-type sense amplifier; Figure 2 This is a basic structural diagram of an existing cross-coupled sense amplifier; Figure 3 This is a basic structural diagram of an existing latch-type sense amplifier; Figure 4 This is a schematic diagram of a STRONG ARM latch-type sensitive amplifier structure composed of a hybrid IDG IGZO FET and Si FET according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the operating waveforms of the sense amplifier in four stages when the input signal VRBL < the reference voltage VREF, according to an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the working principle of the sensing amplifier during the pre-charge stage according to an embodiment of the present invention. Figure 7This is a schematic diagram illustrating the working principle of the sensing amplifier during the row selection and sampling stages according to an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the working principle of the sensing amplifier VRBL when VRBL is less than VREF during the sensing amplification stage according to an embodiment of the present invention. Figure 9 This is a schematic diagram illustrating the working principle of the sensing amplifier VRBL when VRBL is greater than VREF during the sensing amplification stage according to an embodiment of the present invention. Figure 10 This is a schematic diagram illustrating the working principle of the sensing amplifier during the reset phase according to an embodiment of the present invention. Figure 11 The present invention provides simulation results and a schematic diagram of offset voltage after independent top-gate bias adjustment following mismatch according to an embodiment of the present invention. Detailed Implementation

[0022] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0023] refer to Figure 4A specific embodiment of the present invention discloses a latch-type sense amplifier comprising: a reset switch pair including a seventh transistor M7 and a ninth transistor M9, respectively connected between the power supply voltage VDD and the output node VOUT, and between the power supply voltage VDD and the inverting output node VOUTB; a first positive feedback loop 401 including a sixth transistor M6 and an eighth transistor M8, connected in parallel with the seventh transistor M7 and the ninth transistor M9 between the power supply voltage VDD and the output node VOUT, and between the power supply voltage VDD and the inverting output node VOUTB; and a second positive feedback loop 402 including... The transistors include a fourth transistor M4 and a fifth transistor M5, which are connected to the drains of a sixth transistor M6 and an eighth transistor M8, respectively, via their drains. Specifically, the drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6, and the drain of the fifth transistor M5 is connected to the drain of the eighth transistor M8. The input transistor pair 403 includes a second transistor M2 and a third transistor M3. The sources of both the second transistor M2 and the third transistor M3 are connected to the ground terminal via a first transistor M1, and the drain of the second transistor M2 is connected to the source of the fourth transistor M4, and the drain of the third transistor M3 is connected to the source of the fifth transistor M5. The gate connection nodes of the fourth transistor M4 and the sixth transistor M6 are connected to the drain connection nodes of the eighth transistor M8 and the fifth transistor M5 as output node VOUT. The gate connection nodes of the eighth transistor M8 and the fifth transistor M5 are connected to the drain connection nodes of the fourth transistor M4 and the sixth transistor M6 as inverting output node VOUTB. Specifically, the gate of the fourth transistor M4 is connected to the gate of the sixth transistor M6, the drain of the eighth transistor M8 is connected to the drain of the fifth transistor M5, and the drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6. The second transistor M2 and the third transistor M3 are both independent dual-gate IDG indium gallium zinc oxide IGZO field-effect transistors (FETs).

[0024] The sources of the second transistor M2 and the third transistor M3 are both connected to the ground terminal via the first transistor M1. Furthermore, the sources of the second transistor M2 and the third transistor M3 are both connected to the drain of the first transistor M1, and the source of the first transistor M1 is connected to the ground terminal.

[0025] The mismatch between the two sides of the sense amplifier mainly originates from random process deviations during transistor manufacturing. This mismatch leads to an increase in the offset voltage, which reduces the sensitivity of the sense amplifier. The offset voltage of the sense amplifier circuit is defined as: the minimum input voltage difference ΔV required for the sense amplifier to produce a correct readout. min When the input voltage difference of the circuit exceeds the offset voltage range, the SA circuit can achieve correct reading.

[0026] Threshold voltage mismatch is a major cause of asymmetry at both ends of a circuit. Many random deviations in the manufacturing process can cause the threshold voltages of transistors at the left and right ends of the circuit to be different, which in turn leads to different currents flowing through the left and right ends of the circuit, resulting in circuit-level mismatch. Examples include geometric deviations, minute errors in channel length (L) and width (W) during photolithography and etching; mobility fluctuations caused by the randomness of lattice stress or surface scattering; and differences in oxide capacitance caused by minute inhomogeneities in gate oxide thickness.

[0027] Independent dual-gate devices enable dynamic control of the device's threshold voltage. Because the back gate and top gate electrodes can be biased separately, the top gate bias voltage can attract or repel charges in the active layer, altering the potential distribution in the channel and causing carrier accumulation or depletion, thus affecting the device's threshold voltage. The threshold voltage decreases (both positive and negative) as the top gate bias voltage increases, and the device gradually transitions from enhancement-mode to depletion-mode. This relationship is approximately linear. Therefore, by appropriately setting the top gate bias voltage, the threshold voltage drift problem in circuit design can be solved, reducing circuit mismatch.

[0028] For example, refer to Figure 11 In a sensing amplifier circuit, if the sensing amplifier generates an erroneous reading during a 0-read operation, and the output is incorrectly read as 1, it indicates that the threshold voltage of the input transistor on the left side of the circuit is lower than that on the right side. In this case, an additional negative bias voltage should be applied to increase the threshold voltage of the left transistor until the mismatch is minimized. If the absolute value of this applied additional negative voltage is too large, it will cause overcompensation, resulting in an erroneous reading during a 1-read operation, and the output will be incorrectly read as 0.

[0029] The threshold voltage of the second transistor M2 or the third transistor M3 is adjusted by applying a bias voltage to the top gate of the second transistor M2 or the third transistor M3. Specifically, the threshold voltage of the second transistor M2 is adjusted by applying a bias voltage to the top gate of the second transistor M2. The threshold voltage of the third transistor M3 is adjusted by applying a bias voltage to the top gate of the third transistor M3.

[0030] As the bias voltage applied to the top gate of the second transistor M2 or the third transistor M3 increases, the threshold voltage of the second transistor M2 or the third transistor M3 decreases.

[0031] Independent dual-gate IDG indium gallium zinc oxide IGZO field-effect transistors (FETs) are buried in the interconnect layer through back-end process BEOL (Back End of Line), or directly stacked on top of the memory array.

[0032] The first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are silicon-based field-effect transistors.

[0033] The first transistor M1 is a tail-end NMOS bias transistor. The fourth transistor M4 and the fifth transistor M5 are NMOS transistors. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are PMOS transistors.

[0034] The back gate of the second transistor M2 is connected to the bit line, through which the input signal VRBL is received. The back gate of the third transistor M3 receives the reference signal VREF. The gates of the first transistor M2, the seventh transistor M7, and the ninth transistor M9 all receive the control signal VSAE.

[0035] In traditional silicon-based sensitive amplifier circuits, a larger stacking height introduces significant noise, leading to decreased input signal accuracy. Furthermore, the large leakage current of the silicon-based input transistor during the sensitive transistor's turn-off period increases the amplifier's quiescent power consumption. While IGZO TFTs have become a mature choice in the display panel industry, their application in logic circuits still faces significant challenges. The high density of defects in IGZO materials can cause instability in thin-film transistor performance; if the circuit uses only oxide thin-film transistors, its performance will degrade. Therefore, the hybrid integrated sensitive amplifier circuit proposed in this case offers the following advantages: it retains the low leakage current characteristics of back-end process-compatible input transistors, reducing the interference of large vertical stacking on read signal accuracy; it utilizes the maturity and stability of silicon technology, simplifying the circuit structure and avoiding the disadvantages of lacking high-performance p-type IGZO transistors, thus eliminating the need for special design adjustments; and the adjustable threshold voltage of the independent dual-gate IGZO transistors can counteract the inherent unreliability of IGZO transistors, enhancing circuit stability.

[0036] The latch-type sense amplifier of this invention is a STRONG ARM latch-type sense amplifier structure that combines a dual-gate IGZO TFT input transistor with a cross-coupled CMOS load. Advances in nanoscale integration have spurred the exploration of materials or architectures to meet the requirements of next-generation memories. Nanoscale oxide thin-film transistors (e.g., IGZO thin-film transistors) are back-to-end (BEOL) compatible and can be vertically stacked to reduce the footprint of 3D DRAM. However, for high-density DRAM layers, the increased series wire resistance and the number of stacked layers introduce significant noise, degrading the read accuracy of the input signal. This significantly impacts the speed and power consumption of the DRAM array due to its sensitivity to parameter mismatch and power consumption. To address this issue, this invention proposes a FEOL / BEOL co-integrated sense amplifier implemented using a hybrid of independent dual-gate (IDG) IGZO FETs and Si FETs. The back gates of the two IDG IGZO TFTs are directly connected to the DRAM read bit line and reference bit line, respectively, and an independent top gate introduces an externally adjustable bias to compensate for offset voltage caused by manufacturing mismatch without adding any external correction circuitry. Compared to single-gate FETs, IDG IGZO FETs offer higher analog performance and lower leakage current for optimized input transistors in sense amplifiers, reducing static power consumption. Furthermore, the threshold voltage of the input-stage IDG IGZO FET can be adjusted by applying a voltage to an independent top gate, a significant advantage of this device. Manufacturing process-induced circuit mismatch issues can increase the amplifier's offset voltage, reducing the accuracy of the sense amplifier. The adjustable threshold voltage of the independent dual-gate device can compensate for circuit mismatches, mitigating their impact. Experimental and simulation results demonstrate that the sense amplifier proposed in this embodiment supports operation at a low voltage of 1.5V with an initial offset voltage below ±10mV, outperforming existing technologies and meeting the stringent requirements of next-generation low-voltage, high-density DRAM for high speed, low power consumption, and high reliability.

[0037] Specifically, such as Figure 4As shown. The amplifier includes the following structures: a two-stage dual-gate IGZO input tube (M2, M3), a pair of cross-coupled PMOS loads (M6, M8), a tail NMOS bias tube (M1), and two groups of reset switches (M7, M9), consisting of a total of nine transistors. The four PMOS tubes are M6, M7, M8, and M9 respectively; the three NMOS tubes are M1, M4, and M5 respectively; the two independent dual-gate IGZO FETs are M2 and M3 respectively. Among them, the source of M6 is connected to the power supply voltage VDD, the gate is connected to the gates of M4 and M5 and the drain of M5, and is connected to the output signal VOUT, and the drain is connected to the drain of M4 and is connected to the output signal VOUTB; the source of M7 is connected to the power supply voltage VDD, the gate is connected to the enable signal VSAE, the drain is connected to the drain of M4 and is connected to the output signal VOUTB; the source of M8 is connected to the power supply voltage VDD, the gate is connected to the gates of M5 and M4 and the drain of M4, and is connected to the output signal VOUTB, and the drain is connected to the drain of M5 and is connected to the output signal VOUT; the source of M9 is connected to the power supply voltage VDD, the gate is connected to the enable signal VSAE, the drain is connected to the drain of M8 and is connected to the output signal VOUT; the source of M4 is connected to the drain of M2, and the source of M5 is connected to the drain of M3; the back gate electrode of M2 is connected to the input voltage VRBL of the read bit line in the DRAM, the top gate electrode is connected to the independent top gate bias voltage VTG1, and the source is connected to the drain of M1; the back gate electrode of M3 is connected to the reference voltage VRBL of the read bit line in the DRAM, the top gate electrode is connected to the independent top gate bias voltage VTG2, and the source is connected to the drain of M1; the source of M1 is connected to the enable signal VSAE and the source is connected to GND. The substrates of all PMOS tubes are connected to the power supply, the substrates of NMOS tubes are grounded, and the initial bias voltages of the independent top gates of the two IGZO FETs are both 0V. Compared with the prior art, the technical solution provided by the present invention has the following advantages: the input transistors are two IDG IGZO FETs, which reduces the static power consumption of the circuit, improves the sensing accuracy of the circuit, the initial offset voltage is lower than ±10mV, and a compensation method is provided for the mismatch problem that may be caused during the process manufacturing.

[0038] Compared with the prior art, in the latch-type sense amplifier provided in this embodiment, (1) "independent dual-gate IGZO TFT" is first used to replace the traditional Si NMOS in the differential input stage of the STRONG-ARM latch-type sense amplifier, and can be mixed and integrated with the Si-CMOS positive feedback stage (M4-M9). The top gate of the IDG IGZO TFT can provide an adjustable threshold voltage, and the gate bias directly compensates for the increased offset voltage caused by mismatch during the process manufacturing, without an additional correction circuit.

[0039] (2) By relying on the dual isolation of the input IGZO TFT and the enable switch, the static power consumption of the amplifier during the precharge stage is significantly lower than that of the pure Si-CMOS solution. The IGZO TFT has BEOL compatibility and can be embedded in 3D-DRAM through vertical stacking, further saving the layout area of ​​the sense amplifier. This sense amplifier can achieve a combination of performance indicators such as an initial offset voltage of less than ±10 mV and a sense delay in the nanosecond range at a low voltage of 1.5 V.

[0040] The timing control method for a latch-type sense amplifier according to embodiments of the present invention will be described in detail below.

[0041] In the above embodiment, the latch-type sense amplifier adjusts the threshold voltage of the second transistor M2 or the third transistor M3 by applying different bias voltages to the top gate of the second transistor M2 or the third transistor M3 during the sense amplification phase.

[0042] The operating stages of a latch-type sense amplifier include (1) pre-charge stage, (2) row selection and sampling stage, (3) sense amplification stage and (4) reset stage. Each operating stage will be described in detail below.

[0043] (1) During the pre-charging phase, the seventh transistor M7 and the ninth transistor M9 in the reset switch pair are turned on based on a high-level control signal, pulling up the voltages of the output node VOUT and the inverting output node VOUTB to the power supply voltage VDD. Meanwhile, the gates of the second transistor M2 and the third transistor M3 in the input transistor pair receive equal input voltages VDD and VDD, respectively. RBL and reference voltage V REF .

[0044] Specifically, during the pre-charge phase: VSAE is low, M7 and M9 are turned on, pulling the left and right output nodes high to VDD; the input voltage VRBL is equal to the reference voltage VREF, both being VDD / 2. Since the tail current source is turned off, the leakage current of the input transistor is extremely low, so the static power consumption of the circuit is very small during this phase.

[0045] (2) During the row selection and sampling phase, in the process of selecting the row of the memory cell, the storage capacitor in the memory cell charges and discharges the bit line through the storage transistor, causing an imbalance in the bit line pairs, and the input voltage V RBL With reference voltage V REF The difference lies in that the gate of the second transistor M2 is connected to the bit line, while the gate of the third transistor M3 is connected to the anti-phase line.

[0046] Specifically, in the row selection and sampling stage: after the word line is enabled, the storage capacitor in the selected memory cell for read and write operations charges and discharges the bit line through the storage transistor, causing a minimal imbalance in the bit line pair, i.e., the input voltage VRBL is slightly greater than or less than the reference voltage. At this time, the amplifier is still not enabled to ensure that the circuit is not triggered prematurely.

[0047] (3) During the sensing amplification stage, the seventh and ninth transistors are turned off according to the low-level control signal, and the first transistor at the tail is turned on according to the low-level control signal, so that the sources of the second and third transistors are grounded through the turned-on first transistor. The turned-on second and third transistors convert the voltage difference between the input voltage and the reference voltage into a current difference. The first positive feedback loop and the second positive feedback loop are used to amplify the input signal.

[0048] Specifically, the first positive feedback loop includes a sixth transistor and an eighth transistor, which are connected between the power supply voltage and the output node, and between the power supply voltage and the inverting output node, respectively. The second positive feedback loop includes a fourth transistor and a fifth transistor, with the drain of the fourth transistor connected to the inverting output node and its source connected to the drain of the second transistor, and the drain of the fifth transistor connected to the output node and its source connected to the drain of the third transistor. When the input voltage is greater than the reference voltage, the fourth and eighth transistors are turned on, amplifying the input signal; when the input voltage is less than the reference voltage, the fifth and sixth transistors are turned on, amplifying the input signal.

[0049] Specifically, in the sensing and amplification stage: After the differential input signal in the previous stage reaches the SA node, the control signal VSAE rises, M1 is turned on, connecting the differential pair to the ground, M7 and M9 are turned off, and M2 and M3 convert the voltage difference between the input voltage VRBL and VREF into a current difference. The cross-coupled M4-M8 form a positive feedback amplification loop. The positive feedback mechanism is as follows: If VRBL < VREF, the drain current of M3 is larger. Since the loads of the two output nodes are symmetric, the voltage on the side with a larger discharge current drops faster under the same load impedance, and a tiny voltage change of a few millivolts will occur between VOUT and VOUTB. At this time, the positive feedback mechanism will be activated: The cross-coupled NMOS (M4 / M5) forms the first loop of positive feedback. The gate of M5 is connected to the higher-potential VOUT, making M5 conduct more strongly and pulling down the VOUT voltage more. Since the gate of M4 is connected to the continuously decreasing VOUT node, M4 is caused to turn off. This phenomenon makes the voltage of the right VOUT node lower and lower, the gate-drain voltage difference of M5 larger and larger, and the conduction stronger and stronger, accelerating the decrease of the VOUT voltage until the VOUT node voltage drops to 0. The cross-coupled PMOS (M6 / M8) forms the second loop of positive feedback. Since the gate voltage VOUT of M6 drops more and more, M6 conducts stronger and pulls up the VOUTB voltage continuously. As VOUTB, which is the gate voltage of M8, rises continuously, M8 is turned off, which makes the voltage of the left VOUTB node higher and higher, and the gate-drain voltage difference of M6 also increases continuously, and the conduction stronger and stronger, accelerating the pull-up of the VOUTB voltage until the VOUTB node voltage is pulled up to the power supply voltage VDD. When VRBL > VREF, similarly, it can be concluded that finally the VOUT voltage is pulled up to VDD and the VOUTB voltage is pulled down to 0.

[0050] (4) In the reset stage, one of the output node and the inverted output node is close to zero and the other is close to the power supply voltage. The control signal is at a low level, the first transistor is turned off while the seventh and ninth transistors are turned on, so that the output node and the inverted output node are reset to the power supply voltage.

[0051] Specifically, in the reset stage: When the amplification is completed, one of the two output nodes VOUT and VOUTB is close to VDD and the other is close to 0. At this time, the SAE signal becomes low level, the tail current source M1 is turned off, and the reset switches M7 and M9 are turned on, resetting both output signals to VDD. At this time, the read bit line input voltage VRBL of the DRAM cell selected for read / write operations is still in the charged or discharged state, waiting for the stage when VRBL is equal to the VREF voltage in the pre-charge state.

[0052] Advances in nanoscale integration have spurred the exploration of materials and architectures to meet the requirements of next-generation memories. Nanoscale oxide thin-film transistors (e.g., IGZO thin-film transistors) are back-to-end (BEOL) compatible and can be vertically stacked to reduce the footprint of 3D DRAM. However, for high-density DRAM layers, the increased series wire resistance and the number of stacked layers introduce significant noise, degrading the read accuracy of the input signal. This significantly impacts the speed and power consumption of DRAM arrays due to their sensitivity to parameter mismatch and power consumption. To mitigate this issue, a FEOL / BEOL co-integrated sense amplifier is implemented using a hybrid of independent dual-gate (IDG) IGZO FETs and Si FETs. The back gates of the two IDG IGZO TFTs are directly connected to the DRAM read bit line and reference bit line, respectively, while the independent top gate introduces an externally adjustable bias to compensate for offset voltages caused by manufacturing mismatches without adding any external correction circuitry. Compared to single-gate FETs, IDG IGZO FETs offer higher analog performance and lower leakage current for optimized input transistors of the sense amplifier, reducing the circuit's quiescent power consumption. Furthermore, the threshold voltage of the input-stage IDG IGZO FET can be adjusted by applying a voltage to an independent top gate, which is a significant advantage of this device. Circuit mismatch issues caused by the manufacturing process can lead to increased amplifier offset voltage, reducing the accuracy of the sense amplifier. The adjustable threshold voltage of the independent dual-gate device can compensate for circuit mismatches, mitigating their impact. Experimental and simulation results show that the sense amplifier proposed in this invention supports operation at a low voltage of 1.5V with an initial offset voltage below ±10mV, outperforming existing technologies and meeting the stringent requirements of next-generation low-voltage, high-density DRAM for high speed, low power consumption, and high reliability.

[0053] To more intuitively understand the working principle of this amplifier, let's take an example where the input signal VRBL < the reference voltage VREF. Figure 5 The diagram illustrates the waveforms of the sensing amplifier in four stages. (Reference) Figures 6 to 10 The specific working principle of the four time periods is as follows: the symbol "×" indicates that the transistor is not working in this stage. Through the precise timing control of the above four stages, the sensing amplifier can switch between precharge-row selection and sampling-amplification-reset, realizing rapid detection of millivolt-level small differential voltages (nanosecond-level response), while minimizing static power consumption during precharge and reset. At the same time, it fully utilizes the ultra-low leakage current characteristics of dual-gate IGZO TFT and the high gain bandwidth advantage of silicon-based CMOS, meeting the stringent requirements of modern DRAM for high speed, low power consumption and high reliability.

[0054] In actual circuit manufacturing, mismatch may occur between the left and right sides of the circuit due to process limitations, potentially increasing the offset voltage to the level of hundreds of millivolts and reducing the circuit's sensing accuracy. In this case, an additional bias voltage ΔVTG can be applied to the independent top gate of M2 to change the threshold voltage of the input transistor, compensating for the circuit and reducing the magnitude of the offset voltage increase caused by mismatch. If ΔVTG is properly selected, the offset voltage can be reduced to less than ±10mV, almost identical to the offset voltage before mismatch occurs. The specific results are shown in the figure below. Figure 11 As shown. This compensation method does not require additional compensation circuitry, demonstrating the flexibility and advantages of using independent dual-gate devices as input-stage transistors.

[0055] Example 1: Next-generation high-density 3D stacked DRAM Application Background: As semiconductor process miniaturization approaches its physical limits, the improvement of storage density in traditional planar DRAM has encountered a bottleneck. The industry is turning to vertically stacked 3D DRAM architectures, which can multiply capacity without increasing chip area. However, silicon-based transistors require high-temperature processes and are difficult to manufacture directly on top of metal interconnect layers, limiting the number of stacked layers. Advantages of this Patent: This invention uses IGZO (Indium Gallium Zinc Oxide) thin-film transistors as the input stage of the sense amplifier. BEOL Compatibility: The low thermal budget of IGZO material allows it to be manufactured in back-to-line (BEOL) processes, meaning the input portion of the sense amplifier can be "buried" in the interconnect layer or directly stacked on top of the memory array, thus saving area of ​​the underlying silicon.

[0056] Example 2: Ultra-low power IoT and in-memory computing AI chips Application Background: In IoT sensors, wearable devices, and edge AI inference chips, devices spend most of their time in standby mode. Frequent DRAM refreshes and static leakage current in the sense amplifier are the main factors affecting battery life. Traditional silicon-based SAs have leakage paths during the pre-charge phase, leading to unnecessary static power consumption. Advantages of this patent: It utilizes the extremely low leakage current characteristic of IGZO devices. During the pre-charge (standby) phase, the use of a dual-gate IGZO input transistor effectively isolates the leakage path. Low-voltage operation: The circuit supports operation at a low voltage of 1.5V. Combined with the low leakage current characteristics of IGZO, it is ideally suited for low-power memory applications with extremely high energy efficiency requirements.

[0057] Example 3: High-precision and high-reliability memory using advanced manufacturing processes Application Background: In advanced processes below 10nm, transistor process mismatch becomes extremely severe. Sensing amplifiers require extremely high symmetry between the left and right transistors; even minute manufacturing differences can lead to increased offset voltage and read errors. Traditional solutions typically require complex calibration circuits or redundant designs, sacrificing area and speed. Advantages of this Patent: The Independent Dual Gate (IDG) structure designed in this invention allows for dynamic adjustment of the input transistor's threshold voltage by applying a top-gate voltage, thereby compensating for mismatch. This adjustment does not require complex external digital correction circuitry; offset voltages as high as hundreds of millivolts can be reduced to within ±10mV directly through gate bias. This is crucial for high-precision automotive electronics or server-grade memory, as it significantly improves chip yield and noise immunity. To address thermal stability and process variations, novel transistor architectures (such as the oxide semiconductor transistor used in this case) are a key path to ensuring the reliability of future DRAM.

[0058] This sensing amplifier has four operating stages: pre-charge stage, row selection and sampling stage, sensing amplification stage, and reset stage. To better understand the amplifier's working principle, let's take an input signal VRBL < reference voltage VREF as an example. Figure 5 The diagram illustrates the waveforms of the sensing amplifier during its four stages. The specific working principles of each stage are as follows: Figure 6 , 7 As shown in Figures 8 and 10, the × symbol indicates that the transistor is not working at this stage.

[0059] 1. Pre-charge stage: Timing control corresponds to Figure 5 The dashed line 1 in the diagram represents the transistor's operating state. Figure 6 When VSAE is low (0V), all transistors except M7 and M9 are turned off, and M7 and M9 are turned on, pulling the output node VOUT high to VDD (1.5V). The input voltage VRBL is equal to the reference voltage VREF, both being VDD / 2. Since the tail current source M1 is turned off and the leakage current of the input transistors is extremely low, the static power consumption of the circuit in this stage is very small. 2. Row selection and sampling stage: Timing control corresponding to Figure 5 The dashed line 2 in the diagram represents the transistor's operating state. Figure 7 After the word line is enabled, the storage capacitor in the selected memory cell for read and write operations charges and discharges the bit line through the storage transistor, causing a minimal imbalance in the bit line pair, i.e., the input voltage VRBL is less than the reference voltage. At this time, the amplifier is still not enabled (i.e., the enable signal VSAE is still low (0V)). All transistors except M7 and M9 are turned off, M7 and M9 are turned on, and the output node VOUT is still VDD (1.5V), ensuring that the circuit is not triggered prematurely.

[0060] 3. Sensing and amplification stage: Timing control corresponds to... Figure 5 The dashed line 3 in the diagram represents the transistor's operating state. Figure 8 After the differential input signal is generated in the previous stage, the control signal VSAE rises (1.5V), M1 turns on, connecting the differential pair to ground, M7 and M9 turn off, and M2 and M3 turn on, converting the voltage difference between the input voltages VRBL and VREF into a current difference. Because the input signal VRBL < the reference voltage VREF, the drain current of M3 is larger. Due to the symmetrical load of the two output nodes, the voltage on the side with a larger discharge current drops faster under the same load impedance. A small voltage change of a few millivolts will be generated between VOUT and VOUTB. At this time, a positive feedback mechanism will be activated: the cross-coupled NMOS M4 and M5 form the first loop of positive feedback. The gate of M5 is connected to the higher potential VOUTB, which strengthens the conduction of M5 and pulls down the VOUT voltage more. Since the gate of M4 is connected to the continuously decreasing VOUT node, M4 is turned off. This phenomenon makes the voltage of the right VOUT node lower and lower, the gate-drain voltage difference of M5 becomes larger and larger, the conduction becomes stronger and stronger, and the drop in VOUT voltage is accelerated until the VOUT node voltage drops to 0. Cross-coupled PMOS transistors M6 and M8 form a second loop of positive feedback. As the gate voltage VOUT of M6 decreases more and more, M6 conducts more strongly, continuously pulling up the VOUTB voltage. Meanwhile, VOUTB, the gate voltage of M8, continues to rise, causing M8 to turn off. This results in the left-side VOUTB node voltage becoming increasingly higher, and the gate-drain voltage difference of M6 also continuously increases, making it conduct more strongly and accelerating the pull-up of the VOUTB voltage until the VOUTB node voltage is pulled up to the power supply voltage VDD.

[0061] 4. Reset Phase: Timing control corresponds to Figure 5 The dashed lines in section 4 represent the schematic diagram of the transistor's operating state. Figure 10 When amplification is complete, the two output nodes VOUT and VOUTB are close to 0 and VDD, respectively. At this time, the SAE signal becomes low (0V), the tail constant current source M1 is turned off, and the reset switches M7 and M9 are turned on. All other transistors except M7 and M9 are turned off, and both output signals are reset to VDD. At this time, the read bit line input voltage VRBL of the DRAM cell selected for read / write operation is still in the charging or discharging state, waiting for the stage when the voltages VRBL and VREF are equal during the pre-charge state.

[0062] Figure 9This diagram shows the circuit operation during the sensing amplification stage when VRBL > VREF. When VRBL > VREF, the transistor operation states in the other three stages of the sensing amplifier are the same as when the input signal VRBL < the reference voltage VREF, except that during the sensing amplification stage, transistors M1-M4 are on, M5-M7 are off, M8 is on, and M9 is off. For a detailed explanation of the operating principle, refer to the textual description of the sensing amplification stage when the input signal VRBL < the reference voltage VREF. By swapping the state descriptions of M5 and M4, and M6 and M8, we can deduce that the final VOUT voltage is pulled up to VDD, and the VOUTB voltage is pulled down to 0.

[0063] Figure 11 Simulation results are shown for applying different additional bias voltages (ΔVTG, x-axis) to the independent top gate of M2 under different input voltage differences (input signal VRBL - reference voltage VREF, denoted as ΔV, ordinate) when mismatch occurs on the left and right sides of the circuit. The simulation focuses on the cases where ΔV is within ±100 mV and ΔVTG is between 0 and -900 mV. Figure 11 In the diagram, blue represents an incorrect reading result, and green represents a correct reading result. When the input voltage difference ΔV > 0, the correct reading result should be a high level, denoted as 1; when ΔV < 0, the correct reading result should be a low level, denoted as 0. The offset voltage of the sensing amplifier circuit is defined as the minimum input voltage difference (ΔVmin) that enables the sensing amplifier to produce a correct reading result. In the diagram, the vertical axis corresponding to the boundary between all reading error states and the first correct read / write state (i.e., the dark blue line) for each horizontal axis ΔVTG is the range of the vertical axis (the vertical axis ranges from 0 to the boundary line, i.e., the range enclosed by the dark blue line). When the input voltage difference of the circuit exceeds the offset voltage range, the sensing amplifier can achieve a correct reading. It can be seen that the offset voltage corresponding to -300mV on the horizontal axis is compensated to a range of less than ±10mV. This simulation is only an example to illustrate the compensation effect of this case for a small mismatch. It does not mean that the offset voltage is compensated to a range of less than ±10mV for all mismatch cases. The corresponding additional bias voltage ΔVTG (horizontal axis) applied to the independent top gate of M2 is -300mV. The appropriate ΔVTG should be flexibly found according to the specific mismatch case.

[0064] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0065] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A latch-type sensing amplifier, characterized in that, include: A reset switch pair, including a seventh transistor and a ninth transistor, is used to be connected between the power supply voltage and the output node and between the power supply voltage and the inverting output node, respectively. The first positive feedback loop includes a sixth transistor and an eighth transistor, which are connected in parallel with the seventh transistor and the ninth transistor, respectively, between the power supply voltage and the output node and between the power supply voltage and the inverting output node; The second positive feedback loop includes a fourth transistor and a fifth transistor, wherein the drain of the fourth transistor is connected to the drain of the sixth transistor and the drain of the fifth transistor is connected to the drain of the eighth transistor. as well as The input transistor pair includes a second transistor and a third transistor, the sources of which are both connected to ground via a first transistor. The drain of the second transistor is connected to the source of the fourth transistor, and the drain of the third transistor is connected to the source of the fifth transistor. The gate connection node of the fourth transistor and the sixth transistor is connected to the drain connection node of the eighth transistor and the fifth transistor as an output node. The gate connection node of the eighth transistor and the fifth transistor is connected to the drain connection node of the fourth transistor and the sixth transistor as an inverting output node. The second transistor and the third transistor are both independent dual-gate indium gallium zinc oxide (IGZO) field-effect transistors (FETs).

2. The latch-type sensing amplifier according to claim 1, characterized in that, The threshold voltage of the second transistor or the third transistor is adjusted by applying a bias voltage to the top gate of the second transistor or the third transistor.

3. The latch-type sensing amplifier according to claim 2, characterized in that, As the bias voltage applied to the top gate of the second transistor or the third transistor increases, the threshold voltage of the second transistor or the third transistor decreases.

4. The latch-type sensing amplifier according to claim 2, characterized in that, The independent dual-gate IDG indium gallium zinc oxide IGZO field-effect transistors (FETs) are buried in the interconnect layer through back-end processes or directly stacked on top of the memory array.

5. The latch-type sensing amplifier according to claim 2, characterized in that, The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are silicon-based field-effect transistors.

6. The latch-type sensing amplifier according to claim 5, characterized in that, The first transistor is a tail-end NMOS biased transistor; The fourth and fifth transistors are NMOS transistors; The sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors.

7. The latch-type sensing amplifier according to claim 1, characterized in that, The back gate of the second transistor is connected to a bit line, through which an input signal is received; and The back gate of the third transistor receives the reference signal; The gates of the first transistor, the seventh transistor, and the ninth transistor all receive control signals.

8. A timing control method for a latch-type sense amplifier, characterized in that, include: The latch-type sense amplifier according to any one of claims 1 to 7 adjusts the threshold voltage of the second transistor or the third transistor by applying different bias voltages to the top gate of the second transistor or the third transistor during the sense amplification phase.

9. The timing control method for a latch-type sense amplifier according to claim 8, characterized in that, The operating phases of the latch-type sense amplifier include a pre-charge phase, a row selection and sampling phase, a sense amplification phase, and a reset phase. During the pre-charging phase, the reset switch pairs the seventh and ninth transistors are turned on based on a high-level control signal, pulling up the voltages of the output node and the inverting output node to the power supply voltage. The gates of the second and third transistors in the input transistor pair receive equal input voltages and reference voltages, respectively. During the row selection and sampling phase, in the process of selecting a row of memory cells, the storage capacitor in the memory cell charges and discharges the bit line through the storage transistor, causing an imbalance in the bit line pair. The input voltage is different from the reference voltage. The gate of the second transistor is connected to the bit line while the gate of the third transistor is connected to the anti-phase line. During the sensing amplification stage, the seventh and ninth transistors are turned off according to a low-level control signal, and the first transistor at the tail is turned on according to a low-level control signal, so that the sources of the second and third transistors are grounded through the turned-on first transistor. The turned-on second and third transistors convert the voltage difference between the input voltage and the reference voltage into a current difference. The first positive feedback loop and the second positive feedback loop are used to amplify the input signal. During the reset phase, one of the output node and the inverting output node is close to zero, and the other is close to the power supply voltage. The control signal is low, the first transistor is turned off, and the seventh transistor and the ninth transistor are turned on, so that the output node and the inverting output node are reset to the power supply voltage.

10. The timing control method for a latch-type sense amplifier according to claim 9, characterized in that, When the input voltage is greater than the reference voltage, the fourth transistor and the eighth transistor are turned on, causing the turned-on fourth transistor and the eighth transistor to amplify the input signal; When the input voltage is less than the reference voltage, the fifth transistor and the sixth transistor are turned on, causing the turned-on fifth and sixth transistors to amplify the input signal.

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