Hard disk failure processing method, array controller, and hard disk

Abstract

This invention discloses a hard disk failure handling method, an array controller, and a hard disk, relating to the field of storage technology. Each hard disk includes a first partition and a second partition, which are isolated from each other. The first partition stores data, and the second partition stores the logical addresses corresponding to the data. The array controller sends a first instruction to the first hard disk where a data loss event has occurred to obtain the first abnormal logical address of the data page in the first hard disk where the data loss occurred. After obtaining the first abnormal logical address, the array controller repairs the data corresponding to the first logical address in the first hard disk based on the data associated with the first abnormal logical address in multiple hard disks. In this way, the data requiring data repair is quickly located using logical addresses, the amount of data to be repaired is relatively small, avoiding the long repair time caused by repairing the entire disk, reducing the interruption time of data access services caused by hard disk failure, and facilitating rapid data repair.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a hard disk failure handling method, an array controller, and a hard disk. Background Technology

[0002] Solid-state drives (SSDs) use non-volatile memory chips as their storage medium and interact with storage arrays / servers to achieve persistent data storage. When the storage array / server writes data to the SSD, the write request carries the data and its corresponding logical address. The SSD then caches the data and its logical address in its Double Data Rate (DDR) memory. The SSD periodically persists the cached data to the non-volatile memory chips, thereby improving its input and output (I / O) performance.

[0003] However, due to the high failure rate of DDR, which is prone to Uncorrected Error Block (UNC) errors, data cached in DDR is susceptible to loss. After a DDR UNC error occurs on a solid-state drive (SSD), the SSD is reclassified as a control drive, no longer providing I / O services. The storage array / server then uses other drives in the storage pool to repair all data on the SSD. With large SSD capacities, full-disk data repair can be time-consuming, resulting in prolonged service interruptions for data access. Summary of the Invention

[0004] This application provides a hard disk failure handling method, an array controller, and a hard disk to shorten the data recovery time after data loss from a solid-state drive and achieve rapid data recovery.

[0005] Firstly, this application provides a hard disk failure handling method. For each hard disk in a storage array, it includes a first area for storing data and a second area for storing the logical address corresponding to the data, with the first and second areas isolated. During hard disk failure handling, the array controller of the storage array acquires the first hard disk from among multiple hard disks that has experienced a data loss event, and sends a first instruction to the first hard disk to obtain the first abnormal logical address of the data page in the first hard disk where data loss occurred. After obtaining the first abnormal logical address in the first hard disk, the array controller repairs the data corresponding to the first logical address in the first hard disk based on the data associated with the first abnormal logical address in the multiple hard disks.

[0006] Compared to methods that repair the entire disk's data, the method provided in the first aspect repairs data only at the first abnormal logical address of the data page where data loss occurred. This requires repairing a relatively small amount of data, thus shortening the repair time. Furthermore, the first data storage area on the hard drive is isolated from the corresponding logical address area in the second area. Data loss in the first area does not affect the logical addresses of the data in the second area. This allows for quick location of the data requiring repair using logical addresses, avoiding the long repair time associated with repairing the entire disk. It also reduces data access interruption caused by hard drive failures, facilitating rapid data recovery.

[0007] In one optional implementation, the first command and first response message are implemented based on the communication protocol between the array controller and the hard disk, and the logical address of the data page in the first hard disk where data loss has occurred and at least one first abnormal logical address are carried by an extension protocol of the communication protocol.

[0008] Optionally, the header of the first command includes: an opcode and a list identifier. The header of the first response message includes a list identifier, and the data field of the first response message includes: at least one first exception logical address.

[0009] The opcode indicates the hard drive responding to the first command. The list identifier indicates the operation of retrieving the logical address of the data page in the first hard drive where data loss occurred.

[0010] Based on this optional implementation, the array controller uses an extended protocol to obtain the logical address of the data page in the hard drive where data loss has occurred, and then can perform redundant repair of the lost data based on the logical address, thus achieving data loss correction.

[0011] In one optional implementation, the process of identifying the first hard drive among multiple hard drives that experienced a data loss event is as follows: the array controller receives an Error Report (AER) event sent by a second hard drive. The second hard drive can be any one of the multiple hard drives; the AER event includes the event type experienced by the second hard drive. If the event type of the second hard drive indicates data loss, the array controller identifies the second hard drive as the first hard drive where the data loss event occurred.

[0012] In this way, the first hard drive notifies the array controller of the data loss event, enabling the array controller to promptly obtain the logical address of the data page that was lost on the first hard drive and use other hard drives to repair the data on the lost page. This ensures that the first hard drive does not need to be converted into a separate control drive. Furthermore, data repair based on logical addresses improves the repair efficiency of the first hard drive.

[0013] In one optional implementation, the array controller sends a second command to any one of the multiple hard drives, designated as a third hard drive. This second command instructs the array controller to retrieve the logical address of the data page on the third hard drive where data loss occurred. The array controller then receives a second response message from the third hard drive. If the second response message includes at least one second abnormal logical address, the array controller repairs the data page indicated by the second abnormal logical address on the third hard drive based on the data associated with that address on the multiple hard drives.

[0014] Based on this optional implementation, the array controller can proactively acquire abnormal logical addresses in the hard drive, identify the data pages where data loss has occurred, and then repair the data pages. In this way, the amount of data to be repaired is relatively small, thus shortening the data repair time.

[0015] In one optional implementation, the data associated with the first abnormal logical address in the multiple hard disks includes: copies of the first abnormal logical address stored on the other hard disks besides the first hard disk, and / or, the redundancy erasure codes corresponding to the first abnormal logical address stored on the other hard disks.

[0016] Based on this optional implementation, the array controller uses redundant copies or redundant erasure codes in other hard drives to repair the data corresponding to the abnormal logical address in the first hard drive, ensuring that the first hard drive does not need to be turned into a separate control disk.

[0017] Secondly, this application provides a hard disk failure handling method. For each hard disk in a storage array, it includes a first area for storing data and a second area for storing logical addresses corresponding to the data, with the first and second areas isolated. During hard disk failure handling, the first hard disk in the storage array receives and responds to a first command from the array controller. The array controller sends a first response message to the array controller based on the logical address where data loss occurred.

[0018] Optionally, the first command is used to instruct the retrieval of the logical address on the first hard disk where data loss has occurred. The first response message includes: at least one first abnormal logical address; and the data page indicated by the first abnormal logical address has experienced data loss.

[0019] Compared to methods that repair the entire disk's data, the method provided in the first aspect involves the first hard drive providing the array controller with the first abnormal logical address of the data page where data loss occurred. This allows the array controller to repair data at the first abnormal logical address. The amount of data requiring repair is relatively small, thus shortening the data repair time. Furthermore, the first data storage area on the first hard drive is isolated from the corresponding logical address area. Data loss in the first area does not affect the logical addresses corresponding to the data in the second area. This allows for quick location of the data requiring repair using logical addresses, avoiding the long repair time associated with repairing the entire disk. It also reduces data access interruption caused by hard drive failure, facilitating rapid data repair.

[0020] In one optional implementation, the first area and the second area are different logical storage areas; or, the first area and the second area are different physical storage areas.

[0021] In this way, by using partitioning to store data and its corresponding logical address separately, if data is lost in the first partition, the logical address cached in the second partition will not be affected because the first and second partitions are isolated. Therefore, the lost data can be quickly located based on its logical address.

[0022] In one optional implementation, the specific implementation is as follows: the first hard disk stores multiple logical address lists; different logical address lists in the multiple logical address lists are stored in different storage areas of the first hard disk, and the data between the different logical address lists in the multiple logical address lists is synchronized, and each logical address list includes the logical address corresponding to multiple data pages.

[0023] Based on this optional implementation, a redundant logical address list is stored in the first hard disk to ensure the reliability of the logical address list.

[0024] In one optional implementation, the specific implementation is as follows: before receiving the first command from the array controller, the first hard disk reads the logical address of the first data page from the first logical address list and reads the data of the first data page. Here, the first logical address list is any one of multiple logical address lists located in the second region. The first data page is any one of multiple data pages. If reading the first data page fails, the first hard disk sends an Error Report (AER) event to the array controller. The AER event includes the event type sent by the first hard disk.

[0025] Optionally, the event type may include one or more of the following: UNC error, Uncorrectable Read / write Error, physical damage, or bit transition.

[0026] Based on this optional implementation, the first hard drive notifies the array controller of the data loss event, enabling the array controller to promptly obtain the logical address of the data page that was lost on the first hard drive and utilize other hard drives to repair the lost data page. This ensures that the first hard drive does not need to be converted into a separate control drive. Furthermore, data repair based on logical addresses improves the repair efficiency of the first hard drive.

[0027] In one optional implementation, specifically, after the first hard disk reads the logical address of the first data page from the first logical address list and reads the data of the first data page, if reading the logical address of the first data page from the first logical address list fails, the first hard disk obtains a second logical address list and reads the logical address of the first data page from the second logical address list. If reading the logical address of the first data page from the second logical address list fails, the first hard disk controls itself to be in control disk mode and sends a refurbishment request to the array controller. If reading the logical address of the first data page from the second logical address list succeeds but reading the data of the first data page fails, the first hard disk sends an Error Report (AER) event to the array controller.

[0028] The second logical address list consists of multiple logical address lists that are separate from the first logical address list. The refurbishment request instructs the array controller to repair all data on the first hard drive; the control disk status instructs the hard drive to stop processing read and write requests.

[0029] Based on this optional implementation, if the first hard drive fails to read a logical address, it uses a redundant list of logical addresses to reread it. This use of a redundant list ensures the reliability of the logical addresses, and thus, in the event of data page loss, it can provide the array controller with the logical address of the lost data page, ensuring that the array controller can accurately repair the data page corresponding to a single logical address.

[0030] In one optional implementation, the first hard disk records the logical addresses of one or more data pages that have been lost before receiving the first command from the array controller. After receiving the first command, the first hard disk sends a first response message to the array controller based on the logical addresses of the lost data pages.

[0031] Based on this optional implementation, the first hard disk provides the array controller with the logical address of the data page that has been lost, ensuring that the array controller can perform redundant repair of the lost data based on the logical address, thus achieving data loss correction.

[0032] Thirdly, this application provides an array controller. The storage array in which the array controller is located also includes multiple hard disks, each hard disk including storage space for caching data and the logical address corresponding to the data. The storage space includes: a first area for storing data and a second area for storing the logical address corresponding to the data, the first area and the second area being isolated.

[0033] The array controller includes a transceiver and a processor.

[0034] The transceiver is used to send a first command to the first hard disk and to receive a first response message returned by the first hard disk based on the first command.

[0035] The processor is used to acquire the first hard drive among multiple hard drives where a data loss event has occurred, and to repair the data page indicated by the first abnormal logical address in the first hard drive based on the data associated with the first abnormal logical address in the multiple hard drives.

[0036] Optionally, the first command is used to instruct: obtain the logical address of the data page in the first hard disk where data loss has occurred; the first hard disk is one of multiple hard disks where the data loss event has occurred, and the first response message includes: at least one first abnormal logical address; the data page indicated by the first abnormal logical address has experienced data loss.

[0037] In one optional implementation, the first command and first response message are implemented based on the communication protocol between the array controller and the hard disk, and the logical address of the data page in the first hard disk where data loss has occurred and at least one first abnormal logical address are carried by an extension protocol of the communication protocol.

[0038] Optionally, the header of the first command includes: an opcode and a list identifier. The header of the first response message includes a list identifier, and the data field of the first response message includes: at least one first exception logical address.

[0039] The opcode indicates the hard drive responding to the first command. The list identifier indicates the operation of retrieving the logical address of the data page in the first hard drive where data loss occurred.

[0040] In one alternative implementation, the transceiver is further configured to receive Error Report (AER) events sent by the second hard drive. The second hard drive can be any one of multiple hard drives; the AER event includes the type of event that occurred on the second hard drive. The processor is further configured to identify the second hard drive as the first hard drive where the data loss event occurred if the event type on the second hard drive indicates data loss.

[0041] In one optional implementation, the transceiver is further configured to send a second command to any one of the multiple hard disks (a third hard disk) and receive a second response message returned by the third hard disk. The second command instructs the processor to retrieve the logical address of the data page in the third hard disk where data loss has occurred. The processor is also configured to, if the second response message includes at least one second abnormal logical address, perform data repair on the data page indicated by the second abnormal logical address in the third hard disk, based on the data associated with the second abnormal logical address in the multiple hard disks.

[0042] In one optional implementation, the data associated with the first abnormal logical address in the multiple hard disks includes: copies of the first abnormal logical address stored on the other hard disks besides the first hard disk, and / or, the redundancy erasure codes corresponding to the first abnormal logical address stored on the other hard disks.

[0043] Fourthly, this application provides a hard disk. The hard disk includes: a storage device, memory, a communication interface, and a processor.

[0044] Among them, the memory is used to persistently store data;

[0045] Memory consists of a first area for storing data and a second area for storing the logical addresses corresponding to the data.

[0046] The communication interface is used to receive the first command from the array controller. This first command indicates the need to retrieve the logical address of the data page where data loss occurred.

[0047] The processor is configured to persistently store data in memory into storage, and in response to a first command, send a first response message to the array controller via a cooperative communication interface based on the logical address of the data page in memory where data loss has occurred. Optionally, the first response message includes at least one first abnormal logical address. The first abnormal logical address indicates that data loss has occurred in the data page.

[0048] In one optional implementation, the first area and the second area are different logical storage areas; or, the first area and the second area are different physical storage areas.

[0049] In one alternative implementation, multiple logical address lists are stored in the memory or RAM; different logical address lists in the multiple logical address lists are stored in different storage areas of the memory or RAM, and data is synchronized between the different logical address lists in the multiple logical address lists; each logical address list includes the logical addresses corresponding to multiple data pages.

[0050] In an optional implementation, the processor is further configured to read the logical address of a first data page from a first logical address list and read the data of the first data page before receiving the first command from the array controller. The first logical address list can be any one of multiple logical address lists, and the first data page can be any one of multiple data pages. The processor is further configured to send an error report (AER) event to the array controller via a communication interface in the event of a failure to read the first data page. The AER event includes the event type sent by the first hard disk.

[0051] Optionally, the event type may include one or more of the following: UNC error, Uncorrectable Read / write Error, physical damage, or bit transition.

[0052] In one optional implementation, after reading the logical address of the first data page from the first logical address list and reading the data of the first data page, the processor is further configured to, if the logical address of the first data page in the first logical address list fails to be read, obtain a second logical address list and read the logical address of the first data page from the second logical address list. The processor is further configured to, if the logical address of the first data page in the second logical address list fails to be read, control the first hard disk to be in a control disk state and send a refurbishment request to the array controller via the communication interface. And, if the logical address of the first data page in the second logical address list is successfully read but the data of the first data page fails to be read, the processor is further configured to, via the communication interface, send an error report (AER) event to the array controller.

[0053] The second logical address list consists of multiple logical address lists that are separate from the first logical address list. The refurbishment request instructs the array controller to repair all data on the first hard drive; the control disk status instructs the hard drive to stop processing read and write requests.

[0054] In an alternative implementation, the processor is further configured to record the logical addresses of one or more data pages in the first hard disk that have experienced data loss before receiving the first command from the array controller. Additionally, the communication interface is further configured to, after receiving the first command, send a first response message to the array controller based on the logical addresses of the one or more data pages that have experienced data loss, in response to the first command.

[0055] Fifthly, this application provides a storage system comprising a plurality of hard disks as described in the fourth aspect or any implementation thereof, and an array controller as described in the third aspect or any implementation thereof. Each of the plurality of hard disks includes storage space for caching data at logical addresses corresponding to the data. The storage space includes a first area for storing data and a second area for storing logical addresses corresponding to the data, wherein the first area and the second area are isolated from each other.

[0056] Any one of the multiple hard drives is used to execute the method in the second aspect or any implementation thereof described above, providing the array controller with the logical address of the data page where the data loss event occurred.

[0057] The array controller is used to perform data repair based on the logical address of the data page where the data loss event occurred, by executing the method in the first aspect or any implementation thereof.

[0058] Sixthly, this application provides a storage controller, including an interface circuit and a control circuit. The interface circuit is used to receive a first command. The control circuit is used to, in conjunction with the interface circuit, execute the method in the second aspect or any implementation thereof, described above, according to the first command.

[0059] Alternatively, the interface circuitry is used to send a first command and receive a first response message returned based on the first command. The control circuitry, in conjunction with the interface circuitry, executes the method described in the first aspect or any implementation thereof, according to the first response message.

[0060] In a seventh aspect, this application provides a computer program product that, when an instruction is executed by a storage controller, causes the storage controller to perform the method in the first aspect or any optional implementation thereof, or causes the storage controller to perform the method in the second aspect or any optional implementation thereof.

[0061] Eighthly, this application provides a computer-readable storage medium including computer program instructions. When the computer program instructions are executed by a storage controller, the storage controller executes the instructions in the computer program stored in the computer-readable storage medium to perform the method in the first aspect or any optional implementation thereof, or to perform the method in the second aspect or any optional implementation thereof.

[0062] Regarding the technical effects of the third aspect or any implementation thereof, please refer to the technical effects of the first aspect or any optional implementation thereof. Regarding the technical effects of the fourth aspect or any implementation thereof, please refer to the technical effects of the second aspect or any optional implementation thereof. Regarding the technical effects of any implementation of the fifth to eighth aspects, please refer to the technical effects of the first aspect or any optional implementation thereof, or refer to the technical effects of the second aspect or any optional implementation thereof. Further details are omitted here. Based on the implementations provided in the above aspects, this application can be further combined to provide more implementations. Attached Figure Description

[0063] Figure 1 A diagram illustrating persistent data storage on a solid-state drive;

[0064] Figure 2 A schematic diagram of the data access system provided in this application;

[0065] Figure 3 This is a schematic diagram of the hard disk structure provided in this application;

[0066] Figure 4 A schematic diagram illustrating the interaction between the hard disk and the array controller provided in this application;

[0067] Figure 5 Flowchart of the hard disk fault identification method provided in this application Figure 1 ;

[0068] Figure 6 Message format illustration of the extended protocol provided in this application Figure 1 ;

[0069] Figure 7 Message format illustration of the extended protocol provided in this application Figure 2 ;

[0070] Figure 8 A storage diagram of the first and second zones provided in this application;

[0071] Figure 9 The flowchart for detecting data loss on a hard drive provided in this application Figure 1 ;

[0072] Figure 10 A schematic diagram of the message format for AER events provided in this application;

[0073] Figure 11 The flowchart for detecting data loss on a hard drive provided in this application Figure 2 ;

[0074] Figure 12 Flowchart of the hard disk fault identification method provided in this application Figure 2 ;

[0075] Figure 13 This is a schematic diagram of the array controller provided in this application. Detailed Implementation

[0076] Solid-state drives (SSDs) temporarily cache data written to them in memory. Once the memory is full or the cache duration is reached, the data in memory is persistently stored in non-volatile memory chips. For example... Figure 1 As shown, the process of persistently storing data to a solid-state drive (SSD) includes three stages: Stage ①: The storage array sends a write request to the SSD. Stage ②: The SSD responds to the write request, caching the data carried in the write request and the corresponding logical address in memory. Stage ③: The SSD periodically persists the cached data in memory to non-volatile memory (NAND) chips.

[0077] like Figure 1 As shown, data and its corresponding logical address are stored together in memory in a single data + logical address format. When a DDR UNC error occurs in memory, both the data and the logical address are lost simultaneously. The system cannot detect the lost data pages or storage areas on the SSD, and will attempt to recover the data using a full-disk data recovery method. However, with large SSD capacities, full-disk data recovery can be time-consuming, resulting in prolonged service interruptions for data access.

[0078] Based on this, to shorten the data recovery time after data loss from solid-state drives (SSDs) and achieve rapid data recovery, this application provides a hard drive failure handling method. In the hard drive failure handling process, compared to methods that repair all data on the entire disk, this application repairs data only at the first abnormal logical address of the data page where data loss occurred. The amount of data to be repaired is relatively small, thus shortening the data recovery time and avoiding the long recovery time caused by repairing the entire disk. This also reduces the interruption time of data access services caused by hard drive failures. Furthermore, the first data storage area on the hard drive is isolated from the second logical address area corresponding to the stored data. Data loss in the first area will not affect the logical address corresponding to the data in the second area. This allows for quick location of the data requiring repair using logical addresses, facilitating rapid data recovery.

[0079] Specifically, each hard drive in the storage array includes a first area for storing data and a second area for storing the logical address corresponding to the data, with the first and second areas isolated. During hard drive failure handling, the array controller of the storage array identifies the first hard drive among multiple hard drives that has experienced a data loss event and sends a first instruction to the first hard drive to obtain the first abnormal logical address of the data page in the first hard drive where data loss occurred. After obtaining the first abnormal logical address in the first hard drive, the array controller repairs the data corresponding to the first logical address in the first hard drive based on the data associated with the first abnormal logical address in multiple hard drives.

[0080] This application can be applied not only to solid-state drives (SSDs), but also to hard disk drives (HDDs), heterogeneous drives, irregularly shaped drives, and other media drives. Alternatively, it can be applied to storage arrays, storage servers, and storage systems that utilize memory for data caching. Furthermore, the technical solutions involved in this application can be applied not only to current storage arrays, storage servers, hard disk technologies, or storage systems, but also to future hard disk technologies or storage devices, or storage systems that include hard disks or storage devices.

[0081] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. A brief introduction to some concepts that may be involved in this application is given below.

[0082] Hard drives are the primary storage medium in computers, capable of storing large amounts of binary data and retaining it even when power is off. Hard drives can include hard disk drives (HDDs), solid-state drives (SSDs), or other media that provide persistent data storage. A disk refers to a storage device that uses magnetic recording technology to store data. Solid-state drives use flash memory for recording. The following examples illustrate some types of hard drives.

[0083] Disk enclosure: This includes storage arrays employing Redundant Array of Independent Disks (RAID) technology. RAID combines multiple independent hard drives (physical hard drives) in different ways to form a disk group (logical hard drive), thereby providing higher storage performance and data redundancy than a single hard drive. RAID partitions data within the array and provides data recovery functionality through hard drive parity data. When a hard drive fails due to bad sectors, the lost data in the bad sectors can be calculated based on parity data and data from other hard drives in the array, thus enabling bad sector repair.

[0084] The disk enclosure can manage the disks internally, running disk management algorithms such as RAID or Erasure Code (EC). EC is a data protection algorithm that segments data, expands and encodes redundant data blocks, and stores them in different locations, such as hard drives, storage nodes, or other geographical locations. For example, it can add m more data to n original data sets and restore the original data from any n+m sets of data. That is, if any m or fewer data sets fail, the original data can still be restored from the remaining data.

[0085] Solid-state drives (SSDs) are memory devices that use flash memory chips as their medium. For example, an SSD may include a flash controller and multiple NAND flash chips. The flash controller, implemented through a control chip, is used to execute write data requests to write data to the flash chips or read data requests to read data from the flash chips. Write data requests and read data requests can be collectively referred to as I / O requests.

[0086] The flash controller contains a flash translation layer (FTL). The FTL maintains the mapping between the logical addresses and physical addresses of data. Therefore, the FTL is used to translate the logical addresses in I / O requests into the actual addresses of the data in the solid-state drive.

[0087] The logical address of data is assigned by the device initiating the I / O request, such as the host, and can include a subset of a segment's logical address range. The logical address of data includes a starting logical address and a length. The starting logical address indicates the location of the data within the segment, and the length represents the size of the data. The actual address of the data can be the physical address of the data on the solid-state drive (SSD), or it can be a virtualized address visible only to the flash memory controller.

[0088] Logical block address (LBA): Also known as logical address or logical storage address. The LBA abstracts the physical address on the storage medium (such as the solid-state drive mentioned above) into a series of contiguous storage blocks (or storage regions), and assigns a unique number to each storage block (or storage region), which can also be called the access address. The LBA corresponding to data is used to indicate the access address of the storage region or storage block where the data resides; this storage region is the logical storage space.

[0089] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0090] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0091] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0092] The application scenarios of the embodiments of this application will be described below with reference to the accompanying drawings.

[0093] Figure 2 This application provides a schematic diagram of the structure of a data access system 100. The data access system 100 includes: a storage system 110 and multiple data access devices for accessing the storage system 110, such as... Figure 2 Data access devices 1 and 2 are shown. One or more storage arrays in the storage system can be deployed within a computing device that can provide more computing resources to the storage system, or the computing functions on the storage array can be offloaded to an external acceleration device to improve the data access performance of the storage system 110.

[0094] Data access devices can utilize a network to access the storage array in storage system 110 to retrieve data; the communication functionality of this network can be implemented by a switch or router. In one possible example, the data access device can also communicate with the storage array via a wired connection, such as a peripheral component interconnect express (PCIe) bus, compute express link (CXL), universal serial bus (USB) protocol, or other protocol buses.

[0095] Data access devices include a host and a computing device, such as data access device 1 including a host 1 and a computing device 131, and data access device 2 including a host 2 and a computing device 132. Figure 2In this document, the computing device is represented by a DPU card, but this should not be construed as limiting the scope of this application. The computing device may include one or more processing units, which can be not only a DPU, but also a central processing unit (CPU), other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor. The computing device may also be a dedicated processor for artificial intelligence (AI), such as a neural processing unit (NPU) or a graphics processing unit (GPU). Physically, the one or more processing units included in the computing device can be packaged into a card, such as... Figure 2 The DPU card can be connected to the host via a PCIe interface, CXL interface, unified bus (UB) interface, NVlink interface or other communication interface. The host can offload some data processing functions to the DPU card.

[0096] For example, the host is a computer running an application. For instance, if the computer running the application is a physical computing device, the physical computing device can be a server or a terminal. The terminal can also be called a terminal device, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. The terminal can be a mobile phone, tablet computer, laptop computer, desktop computer, personal communication service (PCS) phone, desktop computer, wireless terminal in a smart city, wireless terminal in a smart home, etc. The embodiments of this application do not limit the specific technology or device form used by the host. In some optional implementations, Figure 2 The host shown can also refer to the client.

[0097] The storage system provided in this application embodiment can be a distributed storage system or a centralized storage system.

[0098] In one possible scenario, Figure 2 The storage system 110 shown can be a distributed storage system. For example... Figure 2 As shown, the distributed storage system provided in this embodiment includes a storage cluster that integrates computing and storage (in-memory computing). The storage cluster includes one or more storage arrays (such as... Figure 2 The storage arrays 110A and 110B shown can communicate with each other.

[0099] In some alternative implementations, the storage array included in storage system 110 may also be referred to as a hard disk enclosure. Here, we will use... Figure 2 The storage array 110A shown is used for illustration. Storage array 110A is a device that possesses both computing and storage capabilities, such as a server or desktop computer. For example, an Advanced Reduced Instruction Set Computer (ARM) server or an x86 server could serve as storage array 110A. Figure 2 As shown, the storage array 110A includes at least an array controller 112, memory 113, network interface card 114, and hard disk 105. The array controller 112, memory 113, network interface card 114, and hard disk 105 are connected via a bus. The array controller 112 and memory 113 provide computing resources. Specifically, the array controller 112 is a CPU used to process data access requests (such as write or read requests) from outside the storage array 110A (application servers or other servers), and also to process requests generated internally by the storage array 110A. For example, when the array controller 112 receives write log requests, it temporarily stores the data in these write log requests in memory 113. When the total amount of data in memory 113 reaches a certain threshold, the array controller 112 sends the data stored in memory 113 to the hard disk 105 for persistent storage. In addition, the array controller 112 is also used for data computation or processing. Figure 2 Only one array controller 112 is shown in this embodiment. In practical applications, there are often multiple array controllers 112, and each array controller 112 has one or more CPU cores. This embodiment does not limit the number of CPUs or the number of CPU cores.

[0100] Memory 113 refers to internal memory that directly exchanges data with the array processor. It can read and write data at any time at high speed, serving as temporary data storage for the operating system or other running programs. Memory includes at least two types of memory. For example, memory can be random access memory, such as dynamic random access memory (DRAM), or storage class memory (SCM). DRAM is a semiconductor memory and, like most random access memory (RAM), is a type of volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but its access speed is slower than DRAM, and it is also cheaper than DRAM. However, DRAM and SCM are only illustrative examples in this embodiment; memory can also include other random access memories, such as static random access memory (SRAM).

[0101] Alternatively, memory 113 can be a dual in-line memory module (DIMM), i.e., a module composed of dynamic random access memory (DRAM), or a solid state disk (SSD). In practical applications, multiple memory modules 113, and different types of memory modules 113, can be configured in storage array 110A. This embodiment does not limit the number or type of memory modules 113. Furthermore, memory modules 113 can be configured to have a power-saving function. The power-saving function means that when the system experiences a power outage and then power is restored, the data stored in memory modules 113 will not be lost. Memory with a power-saving function is called non-volatile memory.

[0102] Hard disk 105 provides storage resources, such as storing data and information about the data access status of various data access devices (or the host). Data can be stored on hard disk 105 or in memory 113 in the form of objects or files. The hard disk can be a disk or other type of storage media, such as a solid-state drive (SSD) or a shingled magnetic recording hard disk. For example, hard disk 105 can be a solid-state drive based on the Non-Volatile Memory Express (NVMe) host controller interface specification, such as an NVMe SSD.

[0103] The network interface card 114 in storage array 110A is used to communicate with the host or other application servers (such as... Figure 2 The storage array 110B shown communicates.

[0104] In one implementation, the functions of the array controller 112 can be offloaded to the network interface card 114. In other words, in this implementation, the array controller 112 does not perform service data processing operations, but the network interface card 114 performs service data processing, address translation, and other calculation functions.

[0105] In some application scenarios, the network interface card 114 may also have persistent memory media, such as persistent memory (PM), non-volatile random access memory (NVRAM), or phase change memory (PCM). The CPU is used to perform address translation and log reading / writing operations. Memory is used to temporarily store data to be written to the hard disk 105, or to read data from the hard disk 105 to be sent to the controller. It can also be a programmable electronic component, such as a data processing unit (DPU). The DPU has the versatility and programmability of a CPU, but is more specialized, and can run efficiently on network packets, storage requests, or analysis requests. The DPU is distinguished from the CPU by its high degree of parallelism (the need to process a large number of requests). Optionally, the DPU here can also be replaced by a GPU, NPU, or other processing chip. There is no ownership relationship between the network card 114 and the hard drive 105. The network card 114 can access any hard drive 105 in the storage array 110B where the network card 114 is located. Therefore, it is more convenient to expand the hard drive when the storage space is insufficient.

[0106] Figure 2 This is merely an example provided in the embodiments of this application. The storage system 110 may also include more storage arrays, memory or hard disks, etc. This application does not limit the number or specific form of servers, memory and hard disks.

[0107] In another possible scenario, the storage system provided in this application embodiment can also be a storage cluster with separate computing and storage. This storage cluster includes a computing device cluster and a storage device cluster. The computing device cluster includes one or more computing devices, which can communicate with each other. A computing device can be a single type of computing device, such as a server, desktop computer, or a storage array controller. In terms of hardware, a computing device can include a processor, memory, and a network interface card (NIC). The processor is a CPU used to process data access requests from outside the computing device or requests generated internally by the computing device. For example, when the processor receives a write request from a user, it temporarily stores the data carried in these write requests in memory. When the total amount of data in memory reaches a certain threshold, the processor sends the data stored in memory to the storage device for persistent storage. In addition, the processor is also used for data computation or processing, such as metadata management, deduplication, data compression, virtualization of storage space, and address translation.

[0108] As an optional implementation, the storage system provided in this application embodiment can also be a centralized storage system. A centralized storage system is characterized by a unified entry point through which all data from external devices must pass; this entry point is the engine of the centralized storage system. The engine is the most crucial component of the centralized storage system, and many advanced functions of the storage system are implemented within it.

[0109] For example, an engine can have one or more controllers. In one possible example, if the engine has multiple controllers, any two controllers can have a mirroring channel, enabling any two controllers to back each other up, thus preventing hardware failures from causing the centralized storage system to become unavailable. The engine also includes a front-end interface and a back-end interface. The front-end interface is used to communicate with computing devices in the centralized storage system, thereby providing storage services to the computing devices. The back-end interface is used to communicate with hard drives to expand the capacity of the centralized storage system. Through the back-end interface, the engine can connect more hard drives, thus forming a very large storage resource pool (referred to as a memory pool).

[0110] The following is based on the above. Figure 2 Taking the storage array 110A as an example, the structure of the array controller 112 in the storage array 110A is described.

[0111] Please continue reading. Figure 2 The array controller 112 includes a transceiver 1121 and a processor 1122.

[0112] The transceiver 1121 can be a communication interface or network card, or other component with data transmission and reception capabilities. The specific implementation of the transceiver is not limited in this embodiment. The transceiver can receive data access requests from external devices (e.g., servers, data access devices) of the storage system, such as receiving read or write requests sent by the data access device. The transceiver can also be used to receive requests generated internally within the storage system, such as sending control commands to the hard disk. Furthermore, the transceiver can be used for data interaction within the storage system, such as writing data from a write request to the hard disk or reading data from the hard disk.

[0113] Processor 1122 is a central processing unit (CPU) used to process data access requests from outside the storage system (server or other storage systems), and also to process requests generated within the storage system. For example, processor 1122 receives write requests sent by data access devices via transceiver 1121, and uses transceiver 1121 to write the data in the write request to the hard disk. Alternatively, processor 1122 receives data reported by the hard disk via transceiver 1121, and uses transceiver 1121 to send control commands to the hard disk, etc.

[0114] Additionally, the array controller 112 may also include memory ( Figure 2 (not shown in the image), and the above Figure 2 The memory 113 in the array controller 112 performs a similar function. The memory in the array controller 112 refers to the internal memory that directly exchanges data with the processor 1122 in the array controller 112, and is used to store temporary data of the processor 1122 during operation.

[0115] It is worth noting that, Figure 2 The array controller 112 is merely an exemplary structure. In other embodiments, the array controller 112 may have other structures, which are not limited in this application. Furthermore, the above... Figure 2 This is merely an example provided for the embodiments of this application. The storage array may also include more array controllers or hard disks and other devices. This application does not limit the number or specific form of array controllers or hard disks.

[0116] As an optional implementation method, the above Figure 2 The hard drive 105 shown can be a solid-state drive (SSD). The following will be combined with... Figure 3 Regarding the above Figure 2 The structure of the hard drive in the example is illustrated below.

[0117] Please see Figure 3 , Figure 3This is a schematic diagram of the hard disk structure provided in an embodiment of this application. The hard disk 105 shown includes: a memory 1054, a RAM 1053, a communication interface 1052, and a processor 1051. The memory 1054, RAM 1053, communication interface 1052, and processor 1051 are connected via a bus.

[0118] The communication interface 1052 is used to receive data access requests (such as write data requests or read data requests) from outside the hard disk 105 (array controller or data access device), and also to transmit data or requests from inside the hard disk 105 to the external device. The external device can refer to the aforementioned... Figure 2 The array controller 112 in the diagram, or the external device, can also refer to the above. Figure 2 The data access device or other device in this application embodiment is not limited to this.

[0119] The processor 1051 is used to provide computing resources, manage data storage, and maintain hard disk performance. Specifically, the processor 1051 is a CPU used to process data access requests (such as write data requests or read data requests) from outside the hard disk 105 (array controller 112 or data access device), and also to process requests generated internally by the hard disk 105. Figure 3 Only one processor 1051 is shown in this embodiment. In practical applications, there are often multiple processors 1051, and each processor 1051 has one or more CPU cores. This embodiment does not limit the number of CPUs or the number of CPU cores.

[0120] Memory 1053 is used to cache data that needs to be written to memory. For example, memory 1053 caches data and its corresponding logical address.

[0121] In an optional structure, such as Figure 3 As shown, memory 1053 includes a first area and a second area that are isolated from each other. The first area caches data, and the second area caches the logical addresses corresponding to the data. Thus, hard disk 105 uses memory partitioning to store data and its corresponding logical addresses separately. If data is lost in the first area, the isolation between the first and second areas will not affect the logical addresses cached in the second area. Therefore, lost data can be quickly located based on its logical address.

[0122] In the embodiments of this application, the meaning of "mutually isolated first and second regions" may include: the first region and the second region are different logical storage regions, or the first region and the second region are different physical storage regions.

[0123] Here, different logical storage areas can refer to the first and second areas being different sub-partitions within the same storage area. For example, the hard disk's memory includes a write cache for caching data and its corresponding logical addresses. This write cache is divided into two storage sub-partitions: the first area and the second area.

[0124] Different physical storage areas can refer to the first and second areas being located in different storage areas. For example, the first area is the cache area in memory, and the second area is the flash memory chip (NAND Flash) in the hard drive.

[0125] The memory 1054 is used for persistent storage of data and provides data reading and writing functions to the processor 1051.

[0126] In an alternative scenario, the memory 1054 can be a non-volatile storage medium, FLASH. For example... Figure 3 As shown, the memory 1054 includes multiple flash memory chips 10541. The processor 1051 communicates through several channel controllers ( Figure 3 (Not shown in the image) Parallel operation of multiple flash memory chips 10541 improves the underlying bandwidth. For example, assuming there are 8 channels between the processor 1051 and the FLASH chips, the processor 1051 can read and write data to 8 flash memory chips 10541 in parallel through these 8 channels.

[0127] In one alternative scenario, the array controller 112 accesses the hard disk 105 via LBAs, where each LBA represents a sector (e.g., 512B). Internally, the processor 1051 accesses the SSD in units of pages (e.g., 4KB). Therefore, each time the array controller 112 writes data, the SSD processor 1051 locates a page to write the data; the address of the page is called the Physical Block Address (PBA). The SSD internally maintains a mapping between LBAs and PBAs. When the array controller 112 needs to read data from a specific logical address, the SSD determines the physical address of the data in the flash memory chip based on the LBA-to-PBA mapping.

[0128] In one alternative implementation, the hard disk uses a Flash Translation Layer (FTL) (… Figure 3 (Not shown in the image) The SSD maintains the mapping relationship from LBA to PBA. The FTL is located in the firmware of the processor 1051. Every time the processor 1051 writes new data, it generates a new mapping relationship, which is added to (on the first write) or modified (overwrite write) the FTL. When reading data, the SSD first looks up the PBA corresponding to the LBA of that data in the FTL, and then reads the corresponding data according to the PBA.

[0129] The following is combined Figure 3 Taking a write request as an example, this paper provides an exemplary description of the interaction process between the hard drive and the array controller.

[0130] like Figure 4 As shown, in stage ①, the array controller 112 sends a write request to the hard disk 105, carrying the data to be written and the corresponding logical address. In stage ②, the communication interface 1052 in the hard disk 105 receives the write request, writes the data in the write request to the first area, and writes the logical address in the write request to the second area. In stage ③, the hard disk 105 performs persistent writing, reads the corresponding data from the first area based on the logical address cached in the second area, writes the data to the memory 1054, and updates the mapping relationship from LBA to PBA in the FTL based on the physical address of the data written.

[0131] In one optional implementation, data cached in the memory 1053 of the hard disk 105 is only persistently stored in the memory 1054 after the total amount of cached data reaches a certain threshold or the data caching duration reaches a preset duration. Since the memory 1053 has a high failure rate and is prone to data loss, the hard disk 105 can detect whether the cached data is lost. After detecting data loss, the hard disk 105 executes the hard disk failure handling method provided in this application and provides the array controller 112 with the logical address of the data loss. The array controller 112 performs data repair based on the logical address of the data loss.

[0132] Based on the interaction logic between the hard disk 105 and the array controller 112 described above, the hard disk 105 and the array controller 112 can also collaboratively repair lost data in the memory 1053 of the hard disk 105. The hard disk fault handling method provided in this application can be implemented in the process of collaboratively repairing lost data in the memory 1053 of the hard disk 105. The following describes the process of repairing lost data in the memory of the hard disk in conjunction with... Figures 5 to 12 An example is provided.

[0133] like Figure 5 As shown, Figure 5 This is a flowchart illustrating the hard disk failure handling method provided in this application. This hard disk failure handling method can be applied to... Figure 2 The storage system shown, or the hard drive fault identification method, can also be applied to... Figure 2 The storage array shown is (storage array 110A or storage array 110B). Exemplarily, a hard disk failure identification method is applied... Figure 2 Taking the storage array 110A as an example, the implementation of the hard disk failure handling method provided in this application will be explained.

[0134] For example, with Figure 2 Taking the interaction between the array controller and hard disks 1, 2, and 3 in the storage array 110A as an example, the implementation of the hard disk fault handling method provided in this application will be explained. Hard disks 1, 2, and 3 have the aforementioned... Figure 3 The provided hard disk 105 has the same structure. In some alternative implementations, hard disk 1 may also be referred to as the first hard disk, the faulty hard disk, the hard disk that has lost data, or other names; this application embodiment does not limit this. Hard disk 2 may also be referred to as the second hard disk, the faulty hard disk, the hard disk that has lost data, or other names; this application embodiment does not limit this. Similarly, in an alternative implementation, array controller 112 may also be referred to as the host, control node, master node, master controller, or other names; this application embodiment does not limit this.

[0135] like Figure 5 As shown, this is performed using array controller 112 and hard disk 1. Figure 5 Taking the method as an example, the steps of this hard disk failure handling method include steps S310 to S350.

[0136] S310, Array Controller 112 acquires the first hard drive among multiple hard drives where a data loss event has occurred.

[0137] In one alternative implementation, "the first hard drive where the data loss event occurred" can refer to a hard drive that experienced one or more of the following abnormal events, causing the cached data on the hard drive to fail to be read: UNC error, uncorrectable read / write error, physical damage, or bit transition. Among these, UNC error, uncorrectable read / write error, physical damage, and bit transition all result in data loss.

[0138] UNC errors, also known as DDR UNC errors, refer to errors that occur in memory and cannot be corrected by the built-in Error Correction Code (ECC).

[0139] Uncorrectable read / write errors refer to errors that occur on a hard drive and cannot be automatically corrected by the built-in error correction mechanism.

[0140] Bit transition refers to a single bit or multiple bits in the data stored in memory changing from 1 to 0, or from 0 to 1.

[0141] Physical damage can refer to hardware failure within the hard drive. Examples include damaged magnetic tapes, faulty memory cells, or damaged read / write heads.

[0142] In one alternative implementation, physical damage may cause UNC errors or uncorrectable read / write errors. Alternatively, uncorrectable read / write errors may occur simultaneously with UNC errors on the hard drive, thus the data loss event on the first hard drive may be caused by multiple abnormal events. For example, damage to the read / write head in the first hard drive may cause UNC errors and uncorrectable read / write errors on the first hard drive.

[0143] In one alternative implementation, the array controller 112 can actively query the first hard drive among multiple hard drives where a data loss event has occurred.

[0144] In a first embodiment, the array controller 112 sends query requests to multiple hard drives to check whether the aforementioned abnormal event has occurred on the hard drives. The array controller 112 receives the query results returned by each hard drive and identifies the hard drive whose query results indicate an abnormal event as the first hard drive where the data loss event occurred.

[0145] The array controller 112 can send query requests to multiple hard drives via broadcast, or it can query each hard drive in the multiple hard drives sequentially in an end-to-end manner.

[0146] In the second implementation, if a disk malfunctions, causing a failure to read cached data, the disk records the logical address of the data page that was lost. The array controller 112 sends logical address query requests to multiple disks. These requests indicate whether the disks record the logical address of the lost data page. The array controller 112 receives the logical address query results returned by the disks. The disk whose logical address query result indicates the record of the logical address of the lost data page is identified as the first disk where the data loss event occurred.

[0147] In both of the above implementation methods, the array controller 112 can send query requests or logical address query requests to multiple hard drives according to a preset period. The period can be set by the array controller 112 itself or configured by the user; this application does not limit this. The period can be 24 hours, one hour, or other values; this application does not limit the specific value of the period.

[0148] Furthermore, the above two implementations are merely different ways in which the array controller 112 actively acquires the first hard drive among multiple hard drives that has experienced a data loss event. In other implementations, the hard drives actively report data loss events, and the array controller 112 determines the hard drive that actively reports the data loss event as the first hard drive. The implementation method for the hard drive actively reporting data loss events can be referred to below. Figure 10The embodiments provided are not described in detail here.

[0149] S320, the array controller 112 sends the first command to the first hard disk.

[0150] The first command is used to instruct: obtain the logical address of the data page in the first hard disk where data loss has occurred. In this embodiment, the logical address of the data page where data loss has occurred may also be referred to as the corrupted logical address, the data-corrupted logical address, or the logical address where data reading failed, etc., and this embodiment does not limit it in this way.

[0151] In one alternative implementation, the first command carries both hard disk information and command information. For example, the first command may include a hard disk information field and a command information field.

[0152] The hard disk information is used to indicate the hard disk that executes the first command, and includes, but is not limited to: the hard disk identifier, the hard disk interface port, and the hard disk access address.

[0153] Command information is used to indicate the operation performed by the first command. Understandably, when the first command is used to indicate other operations, the command information can indicate other types of operations. For example, when the first command is used to indicate retrieving the logical addresses of all data pages in the first hard disk, the command information in the first command indicates that the operation performed by the first command is to retrieve the logical addresses of all data pages.

[0154] In another alternative implementation, the first command includes an opcode and a list identifier. The opcode indicates the hard drive responding to the first command, and the list identifier indicates the logical address type that the first command needs to retrieve.

[0155] For example, when the first command is used to instruct the retrieval of the logical address of the data page in the first hard disk where data loss has occurred, the opcode is used to indicate the hard disk information of the first hard disk, and the list identifier is used to indicate that the logical address to be retrieved is the logical address of the data page in the first hard disk where data loss has occurred.

[0156] The following example uses the opcode to illustrate its implementation. Similarly, the implementation of the list identifier code can be found by referring to the implementation of the opcode.

[0157] In the first alternative example, the opcode includes an identifier, for example, the opcode carried in the first command is: OPCode:C0H. Here, "C0" is used to indicate the identifier "192" of the hard drive responding to the first command, and "H" is used to indicate that "C0" is a hexadecimal number.

[0158] In the second optional example, the opcode also includes a field. For example, the opcode carried in the first command is: OPCode:Dx disk information. Here, "Dx disk information" indicates information about the hard drive Dx responding to the first command.

[0159] In the third optional example, the opcode includes an identifier and a field. For example, the opcode carried in the first command is: OPCode(C0H): Dx disk information.

[0160] It should be noted that the above three examples are merely different implementations of the opcode. In other embodiments, the opcode may have other implementations, such as the identifier in the opcode being other content. This application does not limit this.

[0161] The above mainly provides an illustrative example of the content carried by the first command. To better illustrate the implementation of the first command, the following will combine... Figure 6 The message format of the first command is explained.

[0162] In one alternative implementation, the array controller 112 may send a first command to the first hard disk based on the communication protocol between the array controller 112 and the hard disk. For example, the array controller 112 may encapsulate the first command based on the communication protocol between the array controller 112 and the hard disk, and define the aforementioned opcode and list identifier code in the header of the first command.

[0163] The communication protocol includes any one of the following: SCIS protocol, Advanced Technology Attachment (ATA) protocol, or NVMe protocol.

[0164] In an alternative implementation, the array controller 112 may also send a first command to the first hard disk based on an extended protocol.

[0165] The extended protocol can refer to the transmission protocol by which the array controller 112 in this embodiment obtains logical addresses from the hard disk.

[0166] In an optional scenario, the extended protocol provided in this application embodiment may be based on the SCIS protocol, ATA protocol, or NVMe protocol, with the addition of a command to obtain a logical address. Thus, during the process of the array controller 112 obtaining the logical address where data loss has occurred, the array controller 112 may encapsulate the first command with reference to the message format of the extended protocol.

[0167] In one example, such as Figure 6As shown, when sending the first command, the message format of this extended protocol includes a header and a data field. The header, also known as the command header, carries the function the message is intended to perform. The data field carries the data that the message needs to transmit, which can specifically be a logical address on the hard drive.

[0168] The size of the header and data fields can be customized by the user or the system, such as using storage methods like 512+8 bytes, 2048+8 bytes, 4096+8 bytes, or 4096+64 bytes. This application does not impose any restrictions on these sizes.

[0169] like Figure 6 As shown, the header of an extended protocol message includes: an opcode field (OPCode), a list identifier field (PageCode), and a page length field (Page Length).

[0170] OPCode carries the opcode mentioned above, and PageCode carries the list identifier code mentioned above. The size of OPCode and PageCode in bytes can be set by the user or the system; for example, both OPCode and PageCode can occupy 1 byte.

[0171] Page Length indicates the maximum reserved page length, which is the maximum length of data that the message can transmit. For example, a Page Length of 2048 indicates that the maximum length of data that the message can transmit is 2048 bytes. The size of the Page Length in bytes can be set by the user or the system; for example, a Page Length of 2 bytes.

[0172] In another case, such as Figure 6 As shown, the header of an extended protocol message can also include: Reserve bytes, Status field, etc.

[0173] The size of the reserved bytes can be set by the user or the system. For example, the reserved bytes can occupy 4 bytes, or more or fewer bytes. This application embodiment does not limit this.

[0174] The status field is used to indicate the execution status of a command, including the specific error code indicating whether the command was executed successfully or failed.

[0175] For example, taking the first command to obtain the logical address where data loss occurred on hard disk 1 as an example, such as... Figure 6As shown, the header fields in this first command are: OPCode(C0H):**; PageCode(36h): retrieve the corrupted LBA; PageLength(2048); Reserve; Status. The "**" indicates the hard drive information of hard drive 1, including the hard drive identifier, interface port, and access address.

[0176] based on Figure 6 In the provided embodiment, the array controller 112 uses an extended protocol to obtain the logical address of the data page in the hard disk where data loss has occurred, and then can perform redundant repair of the lost data based on the logical address. This enables data loss correction.

[0177] It should be noted that the above Figure 6 The message format of the provided extended protocol is merely illustrative and does not constitute a limitation on the extended protocol provided in this application. In other embodiments, the extended protocol may also include more than those described above. Figure 6 The extended protocol header may provide more or fewer fields; for example, it may include one or more of the following fields: command identifier, command-specific fields, queue identifier, etc. For example, the extended protocol may include the opcode field and list identifier field mentioned above. And for example, Figure 6 The status field can also be located in the data field, but this application embodiment does not limit this.

[0178] Furthermore, in some alternative implementations, the extended protocol can be based on the SCIS, ATA, or NVMe protocols, with the addition of extended fields. These extended fields include the opcode field and list identifier field mentioned above.

[0179] S330, the first hard disk responds to the first command of the array controller 112 and sends a first response message to the array controller 112 based on the logical address of the data page where the data loss occurred.

[0180] The first response message carries a first abnormal logical address, which indicates that the data page has been lost.

[0181] In one alternative implementation, the first response message may also be based on the following Figure 7 It is obtained by encapsulating the provided extended protocol.

[0182] The following combination Figure 7 The message format of the extended protocol in the scenario of returning a response message (hereinafter referred to as the first response message) is illustrated by example.

[0183] With the above Figure 6 The message format of the extended protocol under the provided first command is similar, in Figure 7 The provided first response message format also includes the aforementioned list identifier field and page length field in the header. The list identifier field indicates that the response message is a response to the aforementioned first command. In some examples, the header of the first response message may also include the aforementioned opcode field (…). Figure 7 (Not shown in the image). In some other examples, the header of the first response message does not contain the opcode field described above.

[0184] In addition, unlike the above Figure 6 The message format of the extended protocol under the first command is provided in Figure 7 In the first response message, the data field includes at least one first abnormal logical address.

[0185] In one optional scenario, the data field of the first response message includes at least one address data entry, with each address data entry carrying a first abnormal logical address. The size of each address data entry in bytes can be preset by the user or configured by the system itself. In this embodiment, the size of each address data entry in bytes is not limited; for example, each address data entry occupies 8 bytes.

[0186] like Figure 7 As shown, the data field of the first response message includes three address data entries: LBA:abnormal LBA0, LBA:abnormal LBA1, and LBA:abnormal LBA2. Among them, "LBA:abnormal LBAx" indicates that the first abnormal logical address is LBAx. LBAx is the identifier of the logical address. Figure 7 The first response message shown indicates that the first abnormal logical addresses in the first hard disk include: LBA0, LBA1, and LBA2.

[0187] based on Figure 7 In the provided embodiment, the first hard disk returns a first abnormal logical address to the array controller 112 based on an extended protocol. This enables the array controller 112 to promptly repair the data page corresponding to the first abnormal logical address, achieving data loss correction.

[0188] It should be noted that the above Figure 7 The provided first response message format is merely illustrative and does not constitute a limitation on the message format of the extended protocol provided in the embodiments of this application. In other embodiments, the extended protocol may have other message formats; for example, the reply message of the extended protocol may also carry the above-mentioned... Figure 6The status field in the first response message indicates that the first command was successfully processed. For example, the data field of the first response message may not carry address data. Here, "the data field of the first response message does not carry address data" could mean that there are no data pages on the first hard disk that have been lost. This application does not limit the message format of the extended protocol.

[0189] The following is an example of how to obtain the logical address of the data page where data loss has occurred.

[0190] In the first alternative implementation, the first hard disk can obtain the logical address of the data page where the data loss occurred from the hard disk's log.

[0191] In the second alternative implementation, the first hard disk stores the logical addresses of the data pages that have been lost. The first hard disk responds to the first command by reading the stored logical addresses of the data pages that have been lost.

[0192] In the third alternative implementation, for a data page that has been lost, the first hard disk marks the logical address of that data page as corrupted. The first hard disk responds to the first command by retrieving the logical addresses marked as corrupted from its cache.

[0193] The three optional implementation methods described above are merely different ways of obtaining the logical address of the data page where data loss has occurred from the first hard disk. In other embodiments, there may be other ways to obtain the logical address of the data page where data loss has occurred, and this application does not limit these methods.

[0194] S340, the array controller 112 receives the first response message returned by the first hard disk based on the first command.

[0195] Corresponding to the processing procedure of S340, the first hard disk sends a first response message to the array controller 112.

[0196] In one alternative implementation, the first hard disk may return a first response message to the array controller 112, which carries all the first abnormal logical addresses in the first hard disk.

[0197] Alternatively, in an alternative implementation, the first hardware may also return multiple first response messages to the array controller 112, each first response message carrying a first abnormal logical address in the first hard disk.

[0198] S350, the array controller 112 repairs the data page indicated by the first abnormal logical address in the first hard disk based on the data associated with the first abnormal logical address in multiple hard disks.

[0199] In one alternative implementation, data repair may also be referred to as data reconstruction, data recovery, data restoration, etc., and this application embodiment does not limit this.

[0200] Here, "repairing the data page indicated by the first abnormal logical address in the first hard disk" can refer to recovering the data in the data page indicated by the first abnormal logical address in the first hard disk using data associated with the first abnormal logical address from other hard disks. For example... Figure 5 As shown, taking the first hard disk as hard disk 1 as an example, the array controller 112 uses the data in hard disk 2 associated with the first abnormal logical address to recover the data in the data page indicated by the first abnormal logical address in hard disk 1.

[0201] In one alternative implementation, the data associated with the first abnormal logical address may include copies of the first abnormal logical address stored on other hard drives besides the first hard drive.

[0202] The array controller 112 performs data repair on the data page indicated by the first abnormal logical address in the first hard disk, including: the array controller 112 reads the copy corresponding to the first abnormal logical address stored on other hard disks, and generates an update request to the first hard disk. This update request carries the first abnormal logical address and the copy corresponding to the first abnormal logical address. The update request instructs the first hard disk to perform data repair on the data page indicated by the first abnormal logical address based on the copy corresponding to the first abnormal logical address carried in the request.

[0203] The first hard disk receives the update request and uses the copy corresponding to the first abnormal logical address as the data in the data page indicated by the first abnormal logical address.

[0204] In an alternative example, if there is a copy of the first abnormal logical address stored on a hard disk, the array controller 112 can send an update request based on the copy of the first abnormal logical address stored on that hard disk.

[0205] In another alternative example, if there are replicas corresponding to the first abnormal logical address stored on two or more hard drives, the array controller 112 can send an update request based on the replica corresponding to the first abnormal logical address on any one of the hard drives. Alternatively, the array controller 112 can form a complete replica based on the replica corresponding to the first abnormal logical address on each hard drive. The array controller 112 uses the complete replica as the replica corresponding to the first abnormal logical address and sends an update request.

[0206] Among them, a complete copy can be a copy generated after removing redundant information from the copy corresponding to the first abnormal logical address in each hard disk.

[0207] The above mainly uses the copy corresponding to the first abnormal logical address stored on other hard drives as an example to illustrate the implementation of repairing the data page indicated by the first abnormal logical address in the first hard drive. In other embodiments, the data associated with the first abnormal logical address in multiple hard drives may also include: erasure coding (EC) corresponding to the first abnormal logical address stored on other hard drives.

[0208] Among them, the redundancy erasure code can also be called erasure code. The array controller 112 uses the erasure code mechanism to divide the data into at least two data segments and calculates the parity segments of at least two data segments according to a certain verification algorithm. At this time, when one of the two data segments is lost, the data can be recovered using the other data segment and the parity segment (i.e., data reconstruction).

[0209] For example, array controller 112 divides a data into data A and data B. Data A is written to hard disk 1, and data B is written to hard disk 2. Then, logical operations are performed based on data A and data B to obtain check data C. If hard disk 1 is the first hard disk, and the data in the data page indicated by the first abnormal logical address is data A, array controller 112 retrieves check data C and data B from hard disk 2, performs logical operations on check data C and data B to reconstruct new data A, and then sends the new data A to hard disk 1.

[0210] It is worth noting that the above description primarily uses the example of a copy of the first abnormal logical address stored on another hard drive or the redundant erasure code corresponding to the first abnormal logical address to illustrate the implementation method of the array controller 112 repairing the data page indicated by the first abnormal logical address in the first hard drive. In other embodiments, the array controller 112 can also use other implementation methods to repair the data page indicated by the first abnormal logical address in the first hard drive. For example, if another hard drive stores a copy of the first abnormal logical address and a redundant erasure code, the array controller 112 can reconstruct the data of the data page indicated by the first abnormal logical address in the first hard drive based on the redundant erasure code and the copy. As another example, the array controller 112 can use a content generation algorithm to reconstruct the data of the data page indicated by the first abnormal logical address in the first hard drive; this application does not limit this approach.

[0211] based on Figure 5The provided embodiment, during hard disk failure handling, performs data repair on the first abnormal logical address of the data page where data loss occurred. The amount of data to be repaired is relatively small, thus shortening the data repair time. Furthermore, the first data storage area on the hard disk is isolated from the second logical address area corresponding to the stored data. Data loss in the first area will not affect the logical address corresponding to the data in the second area. This allows for quick location of the data requiring repair using logical addresses, thereby achieving rapid data recovery.

[0212] It is worth noting that the above Figure 5 This application describes the hard disk failure handling method provided in this application from the perspective of the interaction between the array controller 112 and the hard disk in the storage system. In some optional implementations, the hard disk failure handling method provided in this application embodiment can also be executed by other storage devices. For example, the storage device may include, but is not limited to: a centralized storage system, a storage resource pool with computing functions, a storage server, a computing node or computing device with storage functions, or other electronic devices or clusters that can execute the hard disk failure handling method provided in this application embodiment.

[0213] In addition, the above Figure 5 The logical address is illustrated using a data page as an example. In some optional implementations, the storage unit can also be a block, a data segment, a persistent log (Plog), or a namespace provided by an SSD that supports zoned namespaces (ZNS). The Plog is a storage space that supports append-only writes. The ZNS SSD divides the logical address space of a namespace into zones. Basic zone operations include read, append write, zone management, and getting log pages. Optionally, data can be written sequentially within each zone. Correspondingly, the storage unit indicated by the logical address can also be a block, a data segment, a Plog, or a ZNS SSD.

[0214] The following example uses hard disk 1 to illustrate how hard disk 1 stores data and the logical address corresponding to the data.

[0215] In one alternative implementation, hard disk 1 can determine the isolation method between the first and second partitions based on the remaining storage space of the write cache in memory.

[0216] For example, if the remaining storage space in the memory write cache is greater than a preset threshold, hard disk 1 divides the memory write cache into a first area and a second area, which are logically isolated from each other. If the remaining storage space in the memory write cache is less than the preset threshold, hard disk 1 uses the memory write cache as the first area and the NAND Flash in hard disk 1 as the second area. The first area and the second area are physically isolated. If the remaining storage space in the memory write cache is equal to the preset threshold, hard disk 1 can divide the memory write cache into a first area and a second area, or if the remaining storage space in the memory write cache of hard disk 1 is less than the preset threshold, hard disk 1 uses the memory write cache as the first area and the NAND Flash in hard disk 1 as the second area. This application embodiment does not limit the specific value of the preset threshold.

[0217] In one optional scenario, after receiving a write request, hard disk 1 creates a first partition and a second partition. After persistently storing the data in the write request, hard disk 1 reclaims the first and second partitions. In another optional scenario, hard disk 1 creates the first and second partitions before receiving a write request, and hard disk 1 does not reclaim the first and second partitions. "Before receiving a write request" can refer to when the array controller 112 establishes a connection with hard disk 1, or when hard disk 1 starts up; this embodiment of the application does not limit this to either.

[0218] In one alternative implementation, hard disk 1 writes data to the first area and the corresponding logical address to the second area, maintaining a mapping between data and logical addresses. Thus, when performing persistent data storage or detecting data loss, hard disk 1 can quickly retrieve data based on this mapping.

[0219] The following combination Figure 8 An example is given to illustrate the mapping relationship between data and logical addresses.

[0220] In the first alternative example, the mapping relationship between data and logical addresses is maintained using the order of data in the first region and the order of logical addresses in the list.

[0221] For example, hard disk 1 stores the logical addresses of different data in the second partition in the form of a list. Figure 8 As shown, the second region stores a list of logical addresses, with logical address LBA0, logical address LBA1, and logical address LBA2 stored sequentially from head to tail. The first region stores data data0, data data1, and data data2 in ascending order of address. That is, the data corresponding to the logical address LBA0 at the beginning of the list in the second region is the data data0 in the lower address of the first region.

[0222] In the second optional example, a mapping relationship between data and logical addresses is maintained using data identifiers and logical address identifiers. The logical address identifier corresponding to the data identifier is used as the logical address corresponding to the data.

[0223] For example, when hard disk 1 writes data to the first area and the corresponding logical address to the second area, it can encode the data to generate a data identifier and a logical address identifier. In this way, hard disk 1 can identify the data pointed to by the data identifier that is the same as the logical address identifier as the data pointed to by the logical address.

[0224] For example, after hard disk 1 writes data to the first area, it will assign the logical address corresponding to the data to the second area. Hard disk 1 can assign data identifiers based on the data writing order and assign logical address identifiers based on the logical address writing order.

[0225] The two examples above are merely optional ways of mapping the data to logical addresses provided in this application. In other embodiments, the mapping relationship between data and logical addresses can also be implemented in other ways, which are not limited in this application.

[0226] In one alternative implementation, to improve the reliability of logical addresses stored on the hard disk, hard disk 1 can back up the logical addresses in the second partition. Thus, by utilizing redundant logical addresses, the reliability of the logical addresses is ensured.

[0227] The following example, using the storage of logical addresses in the form of a logical address list, illustrates how to implement backup logical addresses.

[0228] In the first optional example, the second partition of hard disk 1 is divided into at least two sub-partitions, each storing a list of logical addresses. During the process of writing logical addresses to the second partition in a write request from hard disk 1, the logical addresses are written to each sub-partition respectively.

[0229] In this process, hard disk 1 can divide the second partition into at least two sub-partitions during the creation of the first and second partitions. Alternatively, hard disk 1 can divide the second partition into at least two sub-partitions upon receiving a write request. This application does not impose any limitations on this.

[0230] In a second alternative example, hard disk 1 synchronizes the logical address list in the second region to the NAND Flash. For example, in the process of hard disk 1 writing a logical address in a write request to the second region, the logical address is written to both the second region and the NAND Flash storing a copy of the logical address list. Another example is that when hard disk 1 detects a logical address write, it synchronizes the newly written logical address to the NAND Flash storing a copy of the logical address list. The NAND Flash storing the copy of the logical address list can be any free NAND Flash memory in hard disk 1's storage.

[0231] In the process of creating the first and second partitions, hard disk 1 can determine the NAND Flash memory in its storage for backing up the logical address list copy. Alternatively, hard disk 1 can select the NAND Flash memory from its multiple NAND Flash memory locations to store the logical address list copy upon receiving a write request.

[0232] The two optional examples described above are merely different implementations of the logical address backup method for hard disk 1. In other embodiments, hard disk 1 can also use other implementations to back up the logical address. For example, hard disk 1 obtains the remaining storage space in the second region. If the remaining storage space in the second region is sufficient, hard disk 1 stores multiple logical address lists in the second region. If the remaining space in the second region is insufficient, hard disk 1 synchronizes the logical address lists in the second region to the NAND Flash. Another example is that hard disk 1 stores multiple logical address lists in the second region and stores copies of the logical address lists in the NAND Flash.

[0233] In one alternative implementation, similar to the above-described recycling of the first and second zones, after hard disk 1 has completed the persistent storage of data in the first zone, hard disk 1 can erase the copy of the logical address.

[0234] After data is written to the first partition of hard disk 1, the data stored in the first partition can be persistently stored at preset intervals. Alternatively, when the amount of data in the first partition of hard disk 1 reaches a certain threshold, the data stored in the first partition will be persistently stored.

[0235] In one alternative implementation, to ensure the reliability of data in hard disk 1, hard disk 1 identifies whether a data loss event has occurred based on the logical address in the second zone.

[0236] The following is an example of how hard disk 1 identifies whether a data loss event has occurred.

[0237] In one alternative implementation, there are several ways to trigger the identification of whether a data loss event has occurred, for example:

[0238] In the first implementation, hard disk 1 identifies whether a data loss event has occurred in persistent data storage.

[0239] In the second implementation, hard disk 1 periodically checks for data loss events. The preset period can be user-set, set by hard disk 1 itself, or automatically configured by the array controller 112; this application does not limit this. Furthermore, this application does not limit the specific value of the preset period in its embodiments.

[0240] In the third implementation, when hard disk 1 receives a detection command, it identifies whether a data loss event has occurred. The detection command can be sent by an external device of hard disk 1 (such as the data access device or the array controller 112 mentioned above). This detection command instructs hard disk 1 to detect whether a data loss event has occurred on hard disk 1.

[0241] The above three implementation methods are simply different triggering methods for hard disk 1 to identify whether a data loss event has occurred. In other embodiments, hard disk 1 may have other triggering methods to identify whether a data loss event has occurred, and this application embodiment does not limit this.

[0242] The following example, using the reading of data from the first data page in the first partition of hard disk 1, illustrates how hard disk 1 identifies whether a data loss event has occurred. Here, the first data page can be any one of the multiple data pages in the first partition.

[0243] like Figure 9 As shown, the first data page includes data data0, and the logical address corresponding to the first data page is LBA0. Hard disk 1 reads the logical address LBA0 corresponding to the first data page from the second partition and reads the data data0 of the first data page corresponding to the logical address from the first partition (S901). If the reading of data data0 in the first data page fails, it is determined that a data loss event has occurred in the first data page (S902). If the reading of data data0 in the first data page is successful, it is determined that no data loss event has occurred in the first data page (S903).

[0244] Data read failures include, but are not limited to: DDR UNC errors occurring in the first zone, uncorrectable read / write errors occurring in the first zone, physical damage occurring in the first zone, or bit transitions occurring in the data in the first zone.

[0245] In one alternative implementation, such as Figure 9As shown, taking the processor in hard disk 1 reading data from the first data page in memory as an example, the processor of hard disk 1 sends a read command to the memory of hard disk 1 to read the data of the first data page. The memory of hard disk 1 responds to the read command and attempts to read the data of the first data page from the first area. If the read is successful, the memory of hard disk 1 returns the data of the first data page to the processor of hard disk 1. If the read fails, the memory of hard disk 1 returns a reply message indicating that the read failed to the processor of hard disk 1. Upon receiving the reply message indicating that the read failed to read the data, the processor of hard disk 1 determines that the data in the first data page has failed to be read.

[0246] The response information includes the reason for the data read failure. The reasons for the data read failure include, but are not limited to: a DDR UNC error in the first zone, an uncorrectable read / write error, physical damage, or a bit transition in the data within the first zone.

[0247] In one optional implementation, if data reading from the first data page fails, hard disk 1 can reread the data of the first data page in the first region based on the logical address corresponding to the first data page. If the data reading of the first data page fails again, hard disk 1 determines that no data loss event has occurred in the first data page.

[0248] In one alternative implementation, upon detecting a data loss event, hard disk 1 can send a data loss event to the array controller 112, causing the array controller 112 to perform steps S320 to S350 to repair the data.

[0249] The following is combined Figure 10 The method by which hard disk 1 sends a data loss event to the array controller 112 is described.

[0250] In an alternative implementation, hard disk 1 can send a data loss event to the array controller 112 using an error reporting (AER) event.

[0251] like Figure 10 As shown, Figure 10 This is a schematic diagram of the message format of the AER event provided in the embodiments of this application. The message format includes: an event type (Activity Event Type, AET) field and an event information (Activity EventIdentifier, AEI) field.

[0252] The AET field indicates the type of abnormal event that occurred, including but not limited to: data loss, system error, network error, application error, security event, performance problem, or configuration error.

[0253] The AEI field indicates specific information about the abnormal event, including error messages or the time of occurrence. The error message explains the specific content of the event. For example, in the case of data loss, the error message might include: "Data read failed," "UNC error occurred in data," or "Bit transition occurred in data," etc.

[0254] In one optional approach, the size of the AET and AEI fields can be preset by the user or configured by the system itself. This embodiment of the application does not limit the size of the AET and AEI fields. For example, the AET field may occupy 1 byte, and the AEI field may occupy 1 byte.

[0255] In an optional case, such as Figure 10 As shown, the message of an AER event may also include an event identifier field, an event sequence identifier (SQ Identifier) ​​field, an event headpointer (SQ Head Pointer) field, a status field, and a command identifier field.

[0256] The event identifier field is used to indicate the identifier of the hard drive that sent the AER event, or to indicate the unique identifier of the AER event.

[0257] The SQ Identifier field indicates the event sequence to which the AER event belongs. The SQ Head Pointer field indicates that the AER event is the first event in the event sequence. The Status Field indicates the status of the AER event, including: event processing successful, event processing in progress, or event processing failed. The Command Identifier field indicates the command or operation related to the AER event. For example, if the AER event indicates that hard disk 1 has experienced data loss, the Command Identifier field instructs the array controller 112 to execute the command or operation of sending the first command.

[0258] In one alternative approach, the size of the event identifier field, SQ Identifier field, SQ Head Pointer field, Status Field, and Command Identifier field in bytes can be preset by the user or configured by the system itself. This embodiment does not limit the size of the event identifier field, SQ Identifier field, SQ Head Pointer field, Status Field, and Command Identifier field in bytes. For example, the event identifier field may occupy 1 byte, the SQ Identifier field 2 bytes, the SQ Head Pointer field 2 bytes, the Status Field 2 bytes, and the Command Identifier field 2 bytes.

[0259] based on Figure 10 In the provided embodiment, hard disk 1 notifies array controller 112 of the data loss event, enabling array controller 112 to promptly obtain the logical address of the data page in hard disk 1 where data loss occurred, and to utilize other hard disks to repair the data page where data loss occurred. Consequently, hard disk 1 does not need to be converted into a separate control disk mode, improving the repair efficiency of hard disk 1.

[0260] It should be noted that the above Figure 10 The provided AER event message format is merely an exemplary description. In other embodiments, the AER event message format may have other formats, such as adding reserved fields. This application embodiment does not limit this. In an optional implementation, after the hard disk 1 sends a data loss event to the array controller 112, the array controller 112 sends a first command. In response to the first command, the hard disk 1 sends a first response message to the array controller 112 based on the recorded logical address where the data loss event occurred.

[0261] The above description primarily uses the example of hard disk 1 sending a data loss event to the array controller 112. In some embodiments, when hard disk 1 detects a data loss event, it can record the logical address where the data loss event occurred and not report the data loss event to the array controller 112. Upon receiving a first command from the array controller 112, hard disk 1 responds to the first command by sending a first response message to the array controller 112 based on the recorded logical address where the data loss event occurred. Alternatively, in other embodiments...

[0262] above Figures 8 to 10This application primarily uses a data loss event as an example to illustrate the hard disk failure handling method provided. In other embodiments, logical addresses may also be lost or corrupted, causing logical address read failures. In the event of a logical address read failure, hard disk 1 can utilize redundant logical addresses for logical address repair.

[0263] The following combination Figure 11 An exemplary method for handling hard disk failures in the event of a logical address read failure is provided.

[0264] Taking reading data 0 from the first data page of the first partition of hard disk 1 as an example, please refer to [link / reference]. Figure 11 Compared to the above Figure 9 In the provided embodiment, hard disk 1 obtains a first logical address list (e.g., ...) from multiple logical address lists. Figure 11 The logical address list 1 shown is shown (S1101). Hard disk 1 reads the logical address LBA0 corresponding to the first data page from logical address list 1, and reads the data data0 of the first data page corresponding to logical address LBA0 from the first region (S1102). If reading the logical address LBA0 corresponding to the first data page fails, hard disk 1 obtains the second logical address list (such as...). Figure 11 (S1102) If the logical address LBA0 corresponding to the first data page is read successfully, but the data data0 in the first data page fails to be read, then it is determined that a data loss event has occurred in the first data page (S1104). If the logical address LBA0 corresponding to the first data page is read successfully, and the data data0 in the first data page is read successfully, then it is determined that no data loss event has occurred in the first data page (S1105).

[0265] The first logical address list is any logical address list stored in the first region, and the second logical address list is a list of logical addresses other than the first logical address list. For example, the second logical address list can be a copy of the logical address list stored in the NAND Flash, or it can be a copy of the logical address list stored in the second region.

[0266] In one optional implementation, hard disk 1 stores two logical address lists. After obtaining the second logical address list, hard disk 1 reads the logical address corresponding to the first data page from the second logical address list. If the logical address corresponding to the first data page is read successfully, it is determined whether the first data page read failed. If the logical address corresponding to the first data page fails to be read, hard disk 1 enters the control disk state and sends a refurbishment request to the array controller 112. The array controller 112 responds to the refurbishment request and performs data repair on all data in hard disk 1 according to the data repair method in S350. The control disk state is used to instruct hard disk 1 to stop processing read requests and stop processing write requests. The refurbishment request is used to instruct the array controller 112 to perform data repair on all data in hard disk 1.

[0267] Alternatively, in one implementation, hard disk 1 stores at least three logical address lists. After obtaining the second logical address list, hard disk 1 reads the logical address corresponding to the first data page from the second logical address list. If reading the logical address corresponding to the first data page fails, hard disk 1 reads the third logical address list from the remaining logical address lists. Hard disk 1 then reads the logical address corresponding to the first data page from the third logical address list. If reading the logical address corresponding to the first data page fails in each of the multiple logical address lists, hard disk 1 enters control disk state and sends a refurbishment request to the array controller 112. If there is a logical address list in the multiple logical address lists where the logical address corresponding to the first data page was successfully read, hard disk 1 determines whether the first data page read failed.

[0268] In one optional implementation, if the logical address corresponding to the first data page is successfully read based on the second logical address list or the third logical address list, hard disk 1 can synchronize the second logical address list or the third logical address list to the first logical address list to obtain a new first logical address list. Alternatively, hard disk 1 can use the second logical address list or the third logical address list as the new first logical address list. Subsequently, during the processing of reading subsequent second data pages from the first data page, hard disk 1 uses the new first logical address list to read the logical address of the second data page.

[0269] based on Figure 11 In the provided embodiment, if the hard disk 1 fails to read a logical address, it uses a redundant list of logical addresses to reread the address. This use of a redundant list ensures the reliability of the logical addresses, and thus, in the event of data page loss, provides the array controller 112 with the logical address of the data page that was lost, ensuring that the array controller 112 can accurately repair the data page corresponding to a single logical address.

[0270] The above Figures 5 to 11 This paper primarily uses a data loss event on a hard drive as an example to illustrate the implementation of the hard drive failure handling method provided in this application. In other embodiments, the array controller 112 can send commands to multiple hard drives to obtain the fault logical address in each hard drive. For each hard drive, if no data loss event has occurred, the response message returned by the hard drive to the array controller 112 does not carry the abnormal logical address. If a data loss event has occurred, the response message returned by the hard drive to the array controller 112 carries the abnormal logical address, and the array controller 112 performs data repair based on the abnormal logical address carried in the response message.

[0271] Taking the interaction between the array controller 112 and the hard disk 3 as an example, the implementation method of the array controller 112 actively acquiring the abnormal logical address is explained. In some embodiments, the hard disk 3 can also be referred to as a third hard disk.

[0272] like Figure 12 As shown, Figure 12 A flowchart illustrating the hard disk failure handling method provided in this application embodiment. Figure 2 The hard drive failure handling method includes steps S121 to S124.

[0273] S121, the array controller 112 sends a second command to the hard disk 3.

[0274] In an alternative implementation, similar to the first command described above, the second command is used to obtain the logical address of the data page on hard disk 3 where data loss occurred. Similarly, the message format of the second command is the same as described above. Figure 6 The message format of the first command provided is similar, and will not be described in detail here.

[0275] In one alternative implementation, the array controller 112 may send a second command to the hard disk 3 with reference to the above-described S320, which will not be described in detail here.

[0276] S122, hard disk 3 receives and sends a second command, and returns a second response message to array controller 112.

[0277] In one alternative implementation, the format of the second response message is the same as described above. Figure 7 The format of the first response message provided is similar, and will not be repeated here.

[0278] In one alternative implementation, if the hard disk 3 records the logical address where the data loss occurred, the hard disk 3 can return a second response message to the array controller 112 based on the logical address where the data loss occurred, referring to the above step S330. This embodiment of the application will not be described in detail here.

[0279] In one alternative implementation, if the logical address where data loss occurred is not recorded in hard disk 3, the second response message returned by hard disk 3 does not carry the logical address.

[0280] S123, the array controller 112 receives the second response message returned by the hard disk 3.

[0281] Corresponding to the processing step S123, hard disk 3 sends a second response message to array controller 112.

[0282] S124, if the second response message includes at least one second abnormal logical address, the array controller 112 repairs the data page indicated by the second abnormal logical address in the hard disk 3 based on the data associated with the second abnormal logical address in the multiple hard disks.

[0283] In one alternative implementation, such as Figure 11 As shown, the array controller 112 obtains data associated with the second abnormal logical address from hard disk 1 and hard disk 2, and performs data repair on the data page indicated by the second abnormal logical address in hard disk 3 with reference to the above S350. The embodiments of this application will not be described in detail here.

[0284] In one optional implementation, if the second response message does not contain the second abnormal logical address, the array controller 112 sends the second command to the next hard disk. Alternatively, the array controller 112 sends the second command to hard disk 3 again after a preset time interval.

[0285] based on Figure 12 In the provided embodiment, the array controller 112 can proactively acquire abnormal logical addresses in the hard disk, determine the data pages on the hard disk where data loss has occurred, and then repair the data pages. Thus, the amount of data to be repaired is relatively small, thereby shortening the data repair time.

[0286] The above Figures 5 to 12 This application primarily describes the technical solution from the perspective of the interaction between the array controller 112 and the hard disk in a storage array. It is understood that a storage array includes hardware structures and / or software modules corresponding to the execution of various functions. Those skilled in the art will readily recognize that, based on the algorithm steps of the examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0287] This application embodiment can group the storage array into functional modules according to the above method example. For example, each functional group can correspond to a functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the naming and grouping of modules in this application embodiment are illustrative and only represent one logical functional grouping. In actual implementation, there may be other grouping methods.

[0288] For example, such as Figure 13 As shown, Figure 13 This is a schematic diagram of the array controller provided in an embodiment of this application. The array controller 112 includes a storage pool management module 141, a disk management module 142, and an I / O management module 143. The storage pool management module 141, the disk management module 142, and the I / O management module 143 are connected to each other via a bus.

[0289] The IO management module 143 is used to receive read or write requests sent by external devices (servers or the aforementioned data access devices), return processing results to external devices, and send read or write requests to one or more hard drives among multiple hard drives.

[0290] Disk management module 142 is connected to multiple hard drives in the storage array and is used to manage the multiple hard drives, as well as to send a first command to the first hard drive that has experienced a data loss event and receive a first response message from the first hard drive. For example, the disk management module performs the above... Figure 5 Steps S320 and S340 in the process.

[0291] The storage pool management module 141 is connected to multiple hard drives in the storage array and is used to repair data on the data page indicated by the first abnormal logical address in the first hard drive based on the data associated with the first abnormal logical address in the multiple hard drives. For example, the storage management module is used to perform the above... Figure 5 The S350 in the middle.

[0292] The storage pool management module 141, disk management module 142, and IO management module 143 can be implemented in software or hardware. For example, the implementation of disk management module 142 will be described below. Similarly, the implementation of storage pool management module 141 and IO management module 143 can refer to the implementation of disk management module.

[0293] As an example of a software functional unit, the disk management module 142 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the disk management module 142 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0294] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0295] As an example of a hardware functional unit, the disk management module 142 may include at least one computing device, such as a server. Alternatively, the disk management module 142 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0296] The disk management module 142 includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the multiple computing devices included in the disk management module 142 can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the disk management module 142 can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0297] It should be noted that, in other embodiments, the disk management module 142 can be used to execute any step in the hard disk fault identification method. The storage pool management module 141 can be used to execute any step in the hard disk fault identification method. The I / O management module 143 can be used to execute any step in the hard disk fault identification method. The storage pool management module 141, disk management module 142, and I / O management module 143 can all be used to execute any step in the hard disk fault identification method. The steps implemented by the storage pool management module 141, disk management module 142, and I / O management module 143 can be specified as needed. By implementing different steps in the hard disk fault identification method through the storage pool management module 141, disk management module 142, and I / O management module 143, all functions of the array controller 112 are realized.

[0298] It should be understood that the array controller 112 described above can be implemented by a storage controller. The array controller 112 according to the embodiments of this application can correspond to executing the methods described in the embodiments of this application, and the above and other operations and / or functions of each unit and module in the array controller 112 are respectively for implementing the corresponding processes of the various methods in the foregoing figures. For the sake of brevity, they will not be described again here.

[0299] Alternatively, the aforementioned hard disk (first hard disk or hard disk 1) can also be implemented using a storage controller. The hard disk according to the embodiments of this application can correspond to executing the methods described in the embodiments of this application, and the above and other operations and / or functions of each unit and module in the hard disk are respectively for implementing the corresponding processes of the various methods in the foregoing figures. For the sake of brevity, they will not be described again here.

[0300] For example, a storage controller includes control circuitry and interface circuitry. The interface circuitry receives data from devices other than the storage controller and transmits it to the control circuitry, or sends data from the control circuitry to devices other than the storage controller. For example, the interface circuitry performs the above-described actions. Figure 5 S320 and S340 in the above. The control circuit performs the functions of the array controller 112 in the aforementioned hard disk fault identification method through logic circuits or executing code instructions and interface circuits, such as performing the above. Figure 5S310 and S350 in the example. For instance, the interface circuit executes the above... Figure 5 The S330 in the diagram. The control circuit executes the functions of the first hard drive in the aforementioned hard drive fault identification method through logic circuits or executed code instructions and interface circuits, such as performing the aforementioned... Figure 5 The S330 in the middle.

[0301] The method steps in this embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a computing device. Of course, the processor and storage medium can also exist as discrete components in a network device or terminal device.

[0302] This application also provides a computer program product containing instructions. The computer program product may be software or program products containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product runs on at least one computing device, it causes the at least one computing device to perform the aforementioned hard disk fault identification method.

[0303] For example, when a computer program product is run on at least one computing device, it causes the at least one computing device to perform... Figure 5 The hard drive fault identification method shown.

[0304] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. This program can be stored in the computer-readable storage medium, and when executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be a terminal of any of the foregoing embodiments, such as an internal storage unit including a data transmission end and / or a data receiving end, like a hard disk or memory of the terminal. The computer-readable storage medium can also be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the terminal. Further, the computer-readable storage medium can include both the internal storage unit and the external storage device of the terminal. The computer-readable storage medium is used to store the computer program and other programs and data required by the terminal. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0305] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0306] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hard disk failure handling method, characterized in that, The method is executed by the array controller of the storage array, which includes multiple hard disks. Each hard disk includes storage space for caching data and the logical address corresponding to the data. The storage space includes a first area for storing the data and a second area for storing the logical address corresponding to the data, wherein the first area and the second area are isolated from each other. The method includes: Identify the first hard drive among the plurality of hard drives where the data loss event occurred; Send a first command to the first hard disk; the first command is used to instruct: obtain the logical address of the data page in the first hard disk where data loss has occurred; Receive a first response message returned by the first hard disk based on the first command; the first response message includes: at least one first abnormal logical address, the data page indicated by the first abnormal logical address has been lost; Based on the data associated with the first abnormal logical address in the plurality of hard disks, data repair is performed on the data page indicated by the first abnormal logical address in the first hard disk.

2. The method according to claim 1, characterized in that, The first command and the first response message are implemented based on the communication protocol between the array controller and the hard disk. The acquisition of the logical address of the data page in the first hard disk where data loss has occurred and the at least one first abnormal logical address are carried by the extended protocol of the communication protocol. The header of the first command includes: an opcode and a list identifier; the opcode is used to indicate the hard disk responding to the first command; the list identifier is used to indicate the operation of obtaining the logical address of the data page in the first hard disk where data loss has occurred. The header of the first response message includes the list identifier code, and the data field of the first response message includes: the at least one first abnormal logical address.

3. The method according to claim 1 or 2, characterized in that, The step of acquiring the first hard drive among the plurality of hard drives where a data loss event occurred includes: Receive an Error Report (AER) event sent by a second hard drive; the second hard drive is any one of the plurality of hard drives; the AER event includes: the type of event that occurred on the second hard drive; In the event type indicating data loss, the second hard drive is identified as the first hard drive.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Send a second command to the third hard drive, the second command being used to instruct: obtain the logical address of the data page in the third hard drive where data loss has occurred, the third hard drive being any one of the plurality of hard drives; Receive the second response message returned by the third hard disk; If the second response message includes at least one second abnormal logical address, data repair is performed on the data page indicated by the second abnormal logical address in the third hard disk based on the data associated with the second abnormal logical address in the plurality of hard disks.

5. The method according to any one of claims 1 to 4, characterized in that, The data associated with the first abnormal logical address in the plurality of hard disks includes: copies of the first abnormal logical address stored on the other hard disks besides the first hard disk, and / or, the redundancy erasure codes corresponding to the first abnormal logical address stored on the other hard disks.

6. A hard disk failure handling method, characterized in that, The storage array includes an array controller and multiple hard disks. Each hard disk includes storage space for cached data and the logical address corresponding to the data. The storage space includes a first area for storing the data and a second area for storing the logical address corresponding to the data, wherein the first area and the second area are isolated. The method is executed by the first hard disk among the multiple hard disks, and the method includes: Receive a first command from the array controller; the first command is used to instruct: obtain the logical address where data loss occurred in the first hard disk; In response to the first command, a first response message is sent to the array controller based on the logical address where data loss occurred; the first response message includes: at least one first abnormal logical address; the data page indicated by the first abnormal logical address has experienced data loss.

7. The method according to claim 6, characterized in that, The first area and the second area are different logical storage areas; or, the first area and the second area are different physical storage areas.

8. The method according to claim 6 or 7, characterized in that, The first hard disk stores multiple logical address lists; different logical address lists in the multiple logical address lists are stored in different storage areas of the first hard disk, and the data between the different logical address lists in the multiple logical address lists is synchronized. Each logical address list includes logical addresses corresponding to multiple data pages. Before receiving the first command from the array controller, the method further includes: Data in the first data page is obtained based on the first logical address list; the first logical address list is any one of the multiple logical address lists located in the second area; the first data page is any one of the multiple data pages; In the event that the first data page read fails, an Error Report (AER) event is sent to the array controller; the AER event includes the event type that occurred on the first hard drive.

9. The method according to claim 8, characterized in that, After obtaining the data in the first data page based on the first logical address list, the method further includes: If reading the logical address of the first data page fails in the first logical address list, the data in the first data page is obtained based on the second logical address list; the second logical address list is a list of logical addresses that are excluded from the first logical address list. If the logical address of the first data page in the second logical address list fails to be read, the first hard disk is controlled to be in control disk state and a refurbishment request is sent to the array controller; the refurbishment request is used to instruct the array controller to repair all data in the first hard disk; the control disk state is used to instruct the hard disk to stop processing read requests and write requests; If the logical address of the first data page is read successfully but the first data page fails to be read, an AER event is sent to the array controller.

10. The method according to any one of claims 6 to 9, characterized in that, Before receiving the first command from the array controller, the method further includes: Record the logical addresses of one or more data pages in the first hard disk that have experienced data loss; After receiving the first command from the array controller, the method further includes: In response to the first command, the first response message is sent to the array controller based on the logical address of one or more data pages where data loss has occurred.

11. An array controller, characterized in that, The storage array where the array controller is located also includes multiple hard disks. Each hard disk includes storage space for caching data with the logical address corresponding to the data. The storage space includes: a first area for storing the data and a second area for storing the logical address corresponding to the data. The first area and the second area are isolated from each other. The array controller includes: A transceiver is used to send a first command to a first hard disk and to receive a first response message returned by the first hard disk based on the first command. Wherein, the first command is used to instruct: obtain the logical address of the data page in the first hard disk where data loss has occurred; the first hard disk is the hard disk among the plurality of hard disks where the data loss event has occurred, and the first response message includes: at least one first abnormal logical address; the data page indicated by the first abnormal logical address has experienced data loss; The processor is configured to acquire the data of the first hard disk in the plurality of hard disks that has experienced a data loss event, and to repair the data page indicated by the first abnormal logical address in the first hard disk based on the data associated with the first abnormal logical address in the plurality of hard disks.

12. A hard disk, characterized in that, include: Memory, used for persistent storage of data; The memory includes a first area and a second area, wherein the first area is used to store the data and the second area is used to store the logical address corresponding to the data; A communication interface is used to receive a first command from the array controller, the first command being used to instruct: obtain the logical address of the data page where data loss has occurred; The processor is configured to persistently store the data in the memory into the storage device, and in response to the first command, based on the logical address of the data page in the memory where the data was lost, coordinate with the communication interface to send a first response message to the array controller. The first response message includes: at least one first abnormal logical address; The data page indicated by the first abnormal logical address has been lost.

13. A storage system, characterized in that, The storage system includes multiple hard disks and an array controller communicatively connected to the multiple hard disks. Each of the multiple hard disks includes a storage space for caching data with logical addresses corresponding to the data. The storage space includes a first area for storing the data and a second area for storing logical addresses corresponding to the data, wherein the first area and the second area are isolated from each other. The first hard drive among the plurality of hard drives that experienced a data loss event provides the array controller with the abnormal logical address of the data page that was lost. The array controller is configured to repair the data page indicated by the abnormal logical address in the first hard disk based on the logical address of the data page that has been lost and the data associated with the abnormal logical address in the plurality of hard disks.

14. A storage controller, characterized in that, include: Interface circuit and control circuit; The interface circuit is used to receive the first command; The control circuit is used to perform the method of any one of claims 6 to 10 in cooperation with the interface circuit according to the first command; Alternatively, the interface circuit is used to send a first command and receive a first response message returned based on the first command; The control circuit, based on the first response message, and the interface circuit, jointly execute the method of any one of claims 1 to 5.

15. A computer program product of instructions, characterized in that, When the instruction is executed by the storage controller, the storage controller performs the method as described in any one of claims 1 to 10.

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