Parallel-to-serial conversion circuit and its control method
By adopting a phase-shifted clock parallel-to-serial conversion circuit and control method, the problems of high time consumption and complexity in traditional parallel-to-serial conversion circuits are solved, achieving more efficient data conversion and lower circuit cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING GIGACHIP TECH CO LTD
- Filing Date
- 2026-03-02
- Publication Date
- 2026-06-02
AI Technical Summary
In traditional parallel-to-serial conversion circuits, each parallel-to-serial conversion is triggered by the same-phase clock, which requires the addition of delay circuits, increasing time consumption, circuit complexity, power consumption, and layout area overhead.
A clock with phase-shifting characteristics is used as the working clock. N parallel-to-serial conversions are performed through a sampling sub-circuit and a parallel-to-serial conversion sub-circuit. The delay circuit is eliminated, and data conversion is performed using clocks with different phases and frequencies.
It greatly reduces the time consumed in the parallel-to-serial conversion process, lowers the power consumption and layout area overhead of the circuit, and improves the feasibility and efficiency of the circuit.
Smart Images
Figure CN122137401A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a parallel-to-serial conversion circuit and a control method for the parallel-to-serial conversion circuit. Background Technology
[0002] To improve data transmission rates and the amount of data transmitted in a single transmission, communication between high-speed communication devices (such as data converters, field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs)) has gradually shifted from traditional parallel data transmission to serial data transmission. To achieve serial data transmission, the transmitting device needs to convert multiple parallel low-frequency data streams (or groups of parallel data streams) into a single serial high-frequency data stream (or group of parallel data streams) before outputting data. This parallel-to-serial conversion is typically implemented by an internal parallel-to-serial conversion circuit within the device.
[0003] For parallel-to-serial conversion circuits using a tree structure, if it is necessary to convert 2 N Converting low-frequency parallel data to high-frequency serial data requires N parallel-to-serial conversions, where N is a positive integer. For example, converting 8 sets of low-frequency parallel data to high-frequency serial data requires three parallel-to-serial conversions. In the first conversion, four multiplexers (MUX) convert the 8 sets of low-frequency parallel data into 4 sets. In the second conversion, two multiplexers convert the 4 sets into 2 sets. In the third conversion, one multiplexer converts the 2 sets into 1 set of high-frequency serial data, and so on. Traditional parallel-to-serial conversion circuits perform each conversion based on a synchronous clock, meaning each conversion operation is triggered in the same phase of the operating clock. This necessitates inserting delay circuits between adjacent conversion operations for timing constraints. However, this method of using delay circuits for timing constraints significantly increases the conversion time, circuit complexity, power consumption, and layout area overhead. Summary of the Invention
[0004] This application provides a parallel-to-serial conversion circuit and a control method for the parallel-to-serial conversion circuit, in order to solve the technical problem in the related technology that each parallel-to-serial conversion is based on the in-phase clock trigger, so a delay circuit needs to be added between two adjacent parallel conversions, which increases the time consumed in the parallel conversion process, and also increases the circuit complexity, power consumption and layout area overhead.
[0005] This application provides a parallel-to-serial conversion circuit, the circuit comprising:
[0006] The sampling sub-circuit receives 2 N A set of parallel data and multiple first target clocks are provided, wherein the parallel data corresponds to the first target clocks, and the multiple first target clocks have different phases. Based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; The parallel-to-serial conversion sub-circuit receives the sampled data and N second clock groups, and performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1≤m≤N.
[0007] In one embodiment of this application, the frequency of the serial data is F, and the frequency of the parallel data is F / 2. N The number of the first target clocks is 2. N-2 Each set of four parallel data points corresponds to one of the first target clocks. N -2 The circuit further includes circuits where the phases of the first target clocks are different, and the circuit also includes: The clock frequency divider and phase shifter circuit receives the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, it performs frequency division and phase shifting processing to obtain and output 2. N-2 One first target clock and N second clock groups.
[0008] In one embodiment of this application, the frequency of the first target clock is the same as the frequency of the parallel data, and the phase difference between adjacent first target clocks is 2π / 2. N-2 The sampling sub-circuit includes 2 N One sampling unit; The sampling unit corresponds to any set of parallel data. Based on the first target clock, the sampling unit samples the corresponding set of parallel data to obtain a set of sampled data; in 2 N If all of the aforementioned sampling units have completed sampling, then 2 N The sampled data described in the group.
[0009] In one embodiment of this application, the sampling unit samples the parallel data of the corresponding group at the rising edge of the first target clock to obtain a set of sampled data.
[0010] In one embodiment of this application, the sampling unit includes a D flip-flop, which samples the parallel data of the corresponding group based on the first target clock to obtain a set of sampled data.
[0011] In one embodiment of this application, the frequency of the second target clock in the m-th second clock group is F / 2. N -m+1 The phase difference between adjacent second target clocks in the m-th second clock group is 2π / 2. N+1-m ; The parallel-to-serial converter sub-circuit includes 2 N -1 parallel-to-serial conversion unit, using 2 in the m-th parallel-to-serial conversion process. N-m Each of the parallel-to-serial conversion units corresponds one-to-one with the second target clock. Based on the corresponding second target clock, the parallel-to-serial conversion unit converts the two sets of input data it receives into one set of output data.
[0012] In one embodiment of this application, the parallel-to-serial conversion unit includes a multiplexer that receives two sets of input data and a corresponding second target clock. When the corresponding second target clock is high, it outputs the first set of input data; when the corresponding second target clock is low, it outputs the second set of input data to complete one parallel-to-serial conversion.
[0013] In one embodiment of this application, the first second target clock in the m-th second clock group is the first comparison clock, and the first second target clock in the (m+1)-th second clock group is the second comparison clock. The rise edge delay time of the first comparison clock and the second comparison clock is 2. N-m-2 T, where T represents the period of the serial data.
[0014] In one embodiment of this application, the first first target clock is a third comparison clock, the first second target clock in the first second clock group is a fourth comparison clock, and the rising edge delay time of the third comparison clock and the fourth comparison clock is a target delay time, wherein the target delay time is greater than 0 and less than (2π / 2). N -2 -1.5) T.
[0015] This application also provides a control method for a parallel-to-serial conversion circuit as described in any of the preceding claims, the method comprising: The clock frequency division and phase shift sub-circuit in the parallel-to-serial conversion circuit is controlled to receive the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, frequency division and phase shifting processing is performed to obtain and output 2. N-2 One first target clock and N second clock groups; Control the sampling sub-circuit to receive 2 N A set of parallel data and multiple first target clocks are provided, wherein the parallel data corresponds to the first target clocks, and the multiple first target clocks have different phases. Based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; The control circuit receives the sampled data and N second clock groups, and performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1≤m≤N.
[0016] The beneficial effects of this application: This application proposes a parallel-to-serial conversion circuit and a control method for the parallel-to-serial conversion circuit. The circuit includes: a sampling sub-circuit, which receives 2 N The system consists of a set of parallel data and multiple first target clocks. The parallel data corresponds to a first target clock, and the multiple first target clocks have different phases. Based on the first target clock, the corresponding parallel data is sampled to obtain 2... N A set of sampled data; a parallel-to-serial conversion sub-circuit, which receives the sampled data and N second clock groups, performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion. The m-th second clock group includes 2 N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different, where N is a positive integer, 1 ≤ m ≤ N. Both the sampling sub-circuit and the parallel-to-serial conversion sub-circuit in this circuit use a clock with phase-shifting characteristics as the operating clock. The parallel-to-serial conversion sub-circuit does not require a delay circuit to achieve the desired result for two target clocks. N Parallel-to-serial conversion of parallel data. This configuration greatly reduces the time consumed in the parallel-to-serial conversion process, and lowers the power consumption and layout area overhead of the parallel-to-serial conversion circuit. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0018] In the attached diagram: Figure 1 This is a schematic diagram of the parallel-to-serial conversion circuit provided in one embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the parallel-to-serial conversion circuit provided in one embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the sampling unit in a parallel-to-serial conversion circuit provided in one embodiment of this application; Figure 4 This is a schematic diagram of the operating timing of the sampling unit in a parallel-to-serial conversion circuit provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of a multiplexer in a parallel-to-serial conversion circuit provided in one embodiment of this application; Figure 6 This is a timing diagram of the multiplexer in a parallel-to-serial conversion circuit provided in one embodiment of this application. Figure 7 This is a schematic diagram of the parallel-to-serial conversion circuit with N=4 provided in one embodiment of this application; Figure 8 This is a schematic diagram of the phase relationship between different first target clocks when N=4, provided in one embodiment of this application; Figure 9 This is a schematic diagram of the phase relationship between different second target clocks in the first second clock group when N=4, provided in one embodiment of this application; Figure 10 This is a schematic diagram of the phase relationship between different second target clocks in the second second clock group when N=4, provided in one embodiment of this application; Figure 11 This is a schematic diagram of the phase relationship between different second target clocks in the third second clock group when N=4, provided in one embodiment of this application; Figure 12 This is a timing diagram illustrating the parallel-to-serial conversion process using an in-phase clock when N=4, provided in one embodiment of this application. Figure 13 This is a timing diagram illustrating the parallel-to-serial conversion process using a phase-shifting clock when N=4, provided in one embodiment of this application. Detailed Implementation
[0019] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.
[0022] Please see Figure 1 , Figure 1 A schematic diagram of the parallel-to-serial conversion circuit provided in an embodiment of this application. Figure 1 ,like Figure 1 As shown, the circuit includes: The sampling sub-circuit receives 2 N Group parallel data (such as) Figure 1 DATA0, DATA1...DATA2 N -1) and multiple first target clocks, the parallel data corresponding to the first target clocks, the multiple first target clocks having different phases, based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; The parallel-to-serial conversion sub-circuit receives the sampled data and N second clock groups (CP1-CPN), and performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1≤m≤N.
[0023] In some examples of this embodiment, the parallel-to-serial converter sub-circuit adopts a tree structure to convert the input 2 N The sampled data is processed through N parallel-to-serial conversions to obtain and output a set of serial data. In this embodiment, both the sampling sub-circuit and the parallel-to-serial conversion sub-circuit use a clock with phase-shifting characteristics (different phases) as their operating clock. Therefore, no delay circuit is needed in the parallel-to-serial conversion sub-circuit to achieve the processing of 2... N Parallel-to-serial conversion of parallel data. This setup significantly reduces the time consumed in the parallel-to-serial conversion process, lowers the power consumption and layout area overhead of the parallel-to-serial conversion circuit, and has lower cost and higher feasibility.
[0024] In some embodiments, the frequency of the serial data is F, and the frequency of the parallel data is F / 2. N The number of the first target clocks is 2. N-2 Each set of four parallel data points corresponds to one of the first target clocks. N-2 The phases of the first target clocks are different.
[0025] In some examples of this embodiment, 2 N-2 The first target clock includes: the first first target clock CLK[1], the second first target clock CLK[2]...the last first target clock CLK[2] N-2 ]. 2 N-2 The first target clock has a phase difference.
[0026] Figure 2 This is a schematic diagram of the parallel-to-serial conversion circuit provided in one embodiment of this application. Figure 2 Please refer to Figure 2 In some embodiments, the circuit further includes: The clock frequency divider and phase shifter circuit receives the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, it performs frequency division and phase shifting processing to obtain and output 2. N-2 One first target clock and N second clock groups.
[0027] Understandably, by setting up the aforementioned clock frequency divider and phase shifter circuit, it is easy to perform frequency division and phase shifting processing on the original clock, thereby obtaining 2 N-2 One first target clock and N second clock groups.
[0028] In some embodiments, the frequency of the first target clock is the same as the frequency of the parallel data, and the phase difference between adjacent first target clocks is 2π / 2. N-2 The sampling sub-circuit includes 2 N One sampling unit; The sampling unit corresponds to any set of parallel data. Based on the first target clock, the sampling unit samples the corresponding set of parallel data to obtain a set of sampled data; in 2 N If all of the aforementioned sampling units have completed sampling, then 2 N The sampled data described in the group.
[0029] In some examples of this embodiment, there is a one-to-one correspondence between the sampling unit and the parallel data, that is, each sampling unit corresponds to a set of parallel data, and each sampling unit samples the corresponding set of parallel data based on its corresponding first target clock.
[0030] In some examples of this embodiment, the frequency of the first target clock is the same as the frequency of the parallel data, that is, the frequency of the first target clock is F / 2. N .
[0031] In some examples of this embodiment, 2 N The period of the parallel input data is T 2 N T represents the period of the serial data. " indicates a multiplication sign. The period T of the first target clock. CLK =2 N T.
[0032] In some examples of this embodiment, the phase difference between adjacent first target clocks is 2π / 2. N-2 For example, the rising edge phase difference between the first target clock CLK[1] and the second target clock CLK[2] is 2π / 2. N-2 The rising edge phase difference between the second first target clock CLK[2] and the third first target clock CLK[3] is 2π / 2. N-2 ..., 2nd N-2 -1 first target clock CLK[2] N-2 -1] and the last first target clock CLK[2 N-2 The phase difference at the rising edge is 2π / 2. N-2 The first CLK[1] and the last CLK[2] N-2 The rising edge phase difference is (2 N-2 -1) 2π / 2 N-2 .
[0033] In some embodiments, the sampling unit samples the parallel data of the corresponding group at the rising edge of the first target clock to obtain a set of sampled data.
[0034] Understandably, this method facilitates the sampling of parallel data.
[0035] In some embodiments, the sampling unit includes a D flip-flop (DFF) that samples the parallel data of the corresponding group based on the first target clock to obtain a set of sampled data.
[0036] Understandably, using D flip-flops as sampling units facilitates the sampling of parallel data.
[0037] Figure 3 This is a schematic diagram of the sampling unit in a parallel-to-serial conversion circuit provided in one embodiment of this application. Please refer to... Figure 3 , Figure 3 Taking DFF as an example, the first input terminal of DFF is connected to parallel data DATA, and the second input terminal of DFF is connected to the first target clock CLK. Based on the first target clock CLK, the parallel data DATA is sampled to obtain sampled data D.
[0038] Figure 4 This is a timing diagram of the sampling unit in a parallel-to-serial conversion circuit provided in one embodiment of this application. Please refer to... Figure 4 DFF samples the input parallel data DATA at the rising edge of the first target clock CLK, and obtains and outputs the sampled data D.
[0039] In some embodiments, the frequency of the second target clock in the m-th second clock group is F / 2. N-m+1 The phase difference between adjacent second target clocks in the m-th second clock group is 2π / 2. N+1-m ; The parallel-to-serial converter sub-circuit includes 2 N -1 parallel-to-serial conversion unit, using 2 in the m-th parallel-to-serial conversion process. N-m Each of the parallel-to-serial conversion units corresponds one-to-one with the second target clock. Based on the corresponding second target clock, the parallel-to-serial conversion unit converts the two sets of input data it receives into one set of output data.
[0040] In some examples of this embodiment, the period T of the second target clock in the m-th second clock group CPm =2 N-m+1 T.
[0041] In some examples of this embodiment, in the parallel-to-serial conversion sub-circuit, the frequency of the data doubles each time it undergoes a parallel-to-serial conversion. After N parallel-to-serial conversions, the frequency of the output serial data is F.
[0042] In some examples of this embodiment, the m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2 N-m The second target clocks, which have different phases but the same frequency, are CPm[1], CPm[2], ..., CPm[3]. N-m It is understandable that CPm[1] is the first second target clock in the m-th second clock group, CPm[2] is the second second target clock in the m-th second clock group, and CPm[2] is the second target clock in the m-th second clock group. N-m ] is the last second target clock in the m-th second clock group.
[0043] In some examples of this embodiment, the phase difference between adjacent second target clocks in the m-th second clock group is 2π / 2. N+1-m For example, the rising edge phase difference between CPm[1] and CPm[2] is 2π / 2. N+1-m The rising edge phase difference between CPm[2] and CPm[3] is 2π / 2. N+1-m ..., CPm[2 N-m -1] and CPm[2 N-m The rising edge phase difference is 2π / 2. N+1-m CPm[1] and CPm[2] N-m The rising edge phase difference is (2) N-m -1) 2π / 2 N+1-m .
[0044] Understandably, the above settings facilitate parallel-to-serial conversion and help improve the accuracy of the conversion.
[0045] In some embodiments, the parallel-to-serial conversion unit includes a multiplexer that receives two sets of input data and a corresponding second target clock. When the corresponding second target clock is high, it outputs the first set of input data; when the corresponding second target clock is low, it outputs the second set of input data to complete one parallel-to-serial conversion.
[0046] In some examples of this embodiment, the multiplexer can be a 2-to-1 multiplexer.
[0047] Understandably, the above settings can effectively achieve parallel-to-serial conversion.
[0048] Figure 5 This is a schematic diagram of the structure of the multiplexer in a parallel-to-serial conversion circuit provided in one embodiment of this application. Please refer to... Figure 5The first input terminal of the MUX is connected to the first set of input data A0 (this first set of input data can be the sampled data output by the sampling sub-circuit, or the output data of any of the multiplexers in the previous parallel-to-serial conversion). The second input terminal of the MUX is connected to the second set of input data A1 (this second set of input data can be the sampled data output by the sampling sub-circuit, or the output data of any of the multiplexers in the previous parallel-to-serial conversion). The third input terminal of the MUX is connected to the corresponding second target clock CP. Based on the second target clock CP, the first set of input data A0 and the second set of input data A1 are converted from parallel to serial, and the converted data Q is output.
[0049] Figure 6 This is a timing diagram of the multiplexer in a parallel-to-serial conversion circuit provided in one embodiment of this application. Please refer to... Figure 6 When the second target clock CP is high, the MUX outputs the first set of input data A0; when the second target clock CP is low, it outputs the second set of input data A1 to complete one parallel-to-serial conversion.
[0050] In some embodiments, the first second target clock in the m-th second clock group is the first comparison clock, and the first second target clock in the (m+1)-th second clock group is the second comparison clock. The rise edge delay time of the first comparison clock and the second comparison clock is 2. N-m-2 T, where T represents the period of the serial data.
[0051] Understandably, the above settings help improve the accuracy of parallel-to-serial conversion.
[0052] In some embodiments, the first first target clock is a third comparison clock, the first second target clock in the first second clock group is a fourth comparison clock, and the rising edge delay time between the third comparison clock and the fourth comparison clock is a target delay time t0, wherein the target delay time is greater than 0 and less than (2π / 2). N-2 -1.5) T.
[0053] In some examples of this embodiment, 0 < t0 < (2 N-2 -1.5) T. This setup helps improve the accuracy and reliability of the parallel-to-serial conversion circuit.
[0054] The following explanation uses N=4 as an example to illustrate the structure and timing of the parallel-to-converter circuit.
[0055] Figure 7This is a schematic diagram of the parallel-to-serial conversion circuit with N=4 provided in one embodiment of this application. Please refer to... Figure 7 When N=4, the parallel-to-serial conversion circuit includes 16 DFFs and 15 MUXs. The 16 DFFs are connected to the corresponding parallel data and the corresponding first target clock CLK. Specifically, the first to fourth DFFs are connected to the first first target clock CLK[1], the fifth to eighth DFFs are connected to the second first target clock CLK[2], the ninth to twelfth DFFs are connected to the third first target clock CLK[3], and the thirteenth to sixteenth DFFs are connected to the fourth first target clock CLK[4]. Based on the connected first target clock CLK, the 16 DFFs perform phase-shift sampling on the connected parallel data to obtain and output 16 sets of sampled data. The 16 sets of sampled data output by the 16 DFFs are D0, D1, D2...D15.
[0056] D0, D1, D2...D15 undergo four parallel-to-serial conversions to obtain a set of serial data. Specifically, the first parallel-to-serial conversion uses eight MUXs, whose operating clock is the first second clock group CP1. CP1 includes eight second target clocks with different phases, namely CP1[1], CP1[2], CP1[3], CP1[4], CP1[5], CP1[6], CP1[7], and CP1[8]. The second parallel-to-serial conversion uses four MUXs, whose operating clock is the second second clock group CP2. CP2 includes four second target clocks with different phases, namely CP2[1], CP2[2], CP2[3], and CP2[4]. The third parallel-to-serial conversion uses two MUXs, whose operating clock is the third second clock group CP3. CP3 includes two second target clocks with different phases, namely CP3[1] and CP3[2]. The number of MUXs in the fourth parallel-to-serial conversion is 1, and its working clock is the second target clock CP4 in the fourth second clock group[1].
[0057] The frequency characteristics of the first target clock CLK and CP1-CP4 are as follows: F CLK =F CP1 =F / 16, F CP2 =F / 8, F CP3 =F / 4, F CP4 =F / 2 Among them, F CLK F represents the frequency of the first target clock CLK. CP1 F represents the frequency of the first second clock group CP1. CP2 F represents the frequency of the second clock group CP2. CP3 F represents the frequency of the third second clock group CP3.CP4 This indicates the frequency of the fourth second clock group, CP4.
[0058] The periodic characteristics of the first target clock CLK and CP1-CP4 are as follows: T CLK =T CP1 =16 T, T CP2 =8 T, T CP3 =4 T, T CP4 =2 T Among them, T CLK T represents the period of the first target clock CLK. CP1 T represents the period of the first second clock group CP1. CP2 T represents the period of the second clock group CP2. CP3 T represents the period of the third second clock group CP3. CP4 This indicates the period of the fourth second clock group CP4.
[0059] Figure 8 This is a schematic diagram illustrating the phase relationship between different first target clocks when N=4, provided in one embodiment of this application. Please refer to... Figure 8 The phase difference between adjacent CLKs is 2π / 4, that is, the phase difference between the rising edges of CLK[1] and CLK[2] is 2π / 4, the phase difference between the rising edges of CLK[2] and CLK[3] is 2π / 4, and the phase difference between the rising edges of CLK[3] and CLK[4] is 2π / 4. The phase difference between the rising edges of CLK[1] and CLK[4] is 6π / 4.
[0060] Figure 9 This is a schematic diagram illustrating the phase relationship between different second target clocks in the first second clock group when N=4, provided in one embodiment of this application. Please refer to... Figure 9 The phase difference between adjacent CP1s is 2π / 16, that is, the rising edge phase difference between CP1[1] and CP1[2] is 2π / 16, the rising edge phase difference between CP1[2] and CP1[3] is 2π / 16, ..., the rising edge phase difference between CP1[7] and CP1[8] is 2π / 16. The rising edge phase difference between CP1[1] and CP1[8] is 14π / 16.
[0061] Figure 10 This is a schematic diagram illustrating the phase relationship between different second target clocks in the second second clock group when N=4, provided in one embodiment of this application. Please refer to... Figure 10The phase difference between adjacent CP2 is 2π / 8, that is, the rising edge phase difference between CP2[1] and CP2[2] is 2π / 8, the rising edge phase difference between CP2[2] and CP2[3] is 2π / 8, and the rising edge phase difference between CP2[3] and CP2[4] is 2π / 8. The rising edge phase difference between CP2[1] and CP2[4] is 6π / 8.
[0062] Figure 11 This is a schematic diagram illustrating the phase relationship between different second target clocks in the third second clock group when N=4, provided in one embodiment of this application. Please refer to... Figure 11 The phase difference between adjacent CP3 is 2π / 4, that is, the phase difference between the rising edges of CP3[1] and CP3[2] is 2π / 4.
[0063] The clock rising edge delay times of CLK[1] and CP[1] are greater than 0 and less than 2.5 seconds. T.
[0064] Figure 12 This is a timing diagram illustrating the parallel-to-serial conversion process using an in-phase clock when N=4, provided in one embodiment of this application. Please refer to... Figure 12 If both the sampling sub-circuit and the parallel-to-serial conversion sub-circuit use the same clock, then a delay circuit needs to be added for timing constraints. In this case, the clock rising edge delay time of CP1 and CP2 (the clock rising edge delay time of CP1[1] and CP2[1]) t1=4T.
[0065] The clock rising edge delay time of CP2 and CP3 (the clock rising edge delay time of CP2[1] and CP3[1]) t2=2 T.
[0066] The clock rising edge delay time of CP3 and CP4 (the clock rising edge delay time of CP3[1] and CP4[1]) t3=1 T.
[0067] The total clock delay from CP1 to CP4 (the total clock delay from CP1[1] to CP4[1]) t = t1 + t2 + t3 = 7 T. The total clock delay is relatively long. Figure 12 The paper provides an example of the data D0-D15 processed under the corresponding time series.
[0068] Figure 13 This is a timing diagram illustrating the parallel-to-serial conversion process using a phase-shifting clock when N=4, provided in one embodiment of this application. Please refer to... Figure 13, 0<t0<2.5T, t0 represents the clock rising edge delay time of CLK[1] and CP[1]. The clock delay characteristics between the working clock CPm[1] of the m-th parallel-to-serial conversion and the working clock CPm+1[1] of the (m+1)-th parallel-to-serial conversion are (1≤m≤3): The clock rising edge delay time of CP1 and CP2 (the clock rising edge delay time of CP1[1] and CP2[1]) t1=2 T.
[0069] The clock rising edge delay time of CP2 and CP3 (the clock rising edge delay time of CP2[1] and CP3[1]) t2=1 T.
[0070] The clock rising edge delay time of CP3 and CP4 (the clock rising edge delay time of CP3[1] and CP4[1]) t3=0.5 T.
[0071] The total clock delay from CP1 to CP4 (the total clock delay from CP1[1] to CP4[1]) t = t1 + t2 + t3 = 3.5 Compared to the traditional parallel-to-serial conversion method based on in-phase clock, the total clock delay time from CP1 to CP4 is greatly reduced, and no delay circuit is required in the parallel-to-serial conversion circuit, which reduces the power consumption and layout area overhead of the parallel-to-serial conversion circuit. Figure 13 The text also provides an example of the data D0-D15 processed under the corresponding time series.
[0072] This embodiment also provides a control method for the parallel-to-serial conversion circuit as described in any of the above claims, the method comprising: S1410: Control the clock frequency division and phase shift sub-circuit in the parallel-to-serial conversion circuit to receive the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, perform frequency division and phase shift processing to obtain and output 2. N-2 One first target clock and N second clock groups; S1420: Control the sampling sub-circuit to receive 2 N A set of parallel data and multiple first target clocks are provided, wherein the parallel data corresponds to the first target clocks, and the multiple first target clocks have different phases. Based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; S1430: Control the parallel-to-serial conversion sub-circuit to receive the sampled data and N second clock groups, and perform N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1 ≤ m ≤ N. The control method in this embodiment can perform highly accurate timing control on the above-mentioned parallel-to-serial conversion circuit.
[0073] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A parallel-to-serial conversion circuit, characterized in that, The circuit includes: The sampling sub-circuit receives 2 N A set of parallel data and multiple first target clocks are provided, wherein the parallel data corresponds to the first target clocks, and the multiple first target clocks have different phases. Based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; The parallel-to-serial conversion sub-circuit receives the sampled data and N second clock groups, and performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1≤m≤N.
2. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The frequency of the serial data is F, and the frequency of the parallel data is F / 2. N The number of the first target clocks is 2. N-2 Each set of four parallel data points corresponds to one of the first target clocks. N-2 The circuit further includes circuits where the phases of the first target clocks are different, and the circuit also includes: The clock frequency divider and phase shifter circuit receives the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, it performs frequency division and phase shifting processing to obtain and output 2. N-2 One first target clock and N second clock groups.
3. The parallel-to-serial conversion circuit according to claim 1 or 2, characterized in that, The frequency of the first target clock is the same as the frequency of the parallel data, and the phase difference between adjacent first target clocks is 2π / 2. N-2 The sampling sub-circuit includes 2 N One sampling unit; The sampling unit corresponds to any set of parallel data. Based on the first target clock, the sampling unit samples the corresponding set of parallel data to obtain a set of sampled data; in 2 N If all of the aforementioned sampling units have completed sampling, then 2 N The sampled data described in the group.
4. The parallel-to-serial conversion circuit according to claim 3, characterized in that, The sampling unit samples the corresponding group of parallel data at the rising edge of the first target clock to obtain a set of sampled data.
5. The parallel-to-serial conversion circuit according to claim 3, characterized in that, The sampling unit includes a D flip-flop, which samples the parallel data of the corresponding group based on the first target clock to obtain a set of sampled data.
6. The parallel-to-serial conversion circuit according to claim 2, characterized in that, The frequency of the second target clock in the m-th second clock group is F / 2 N-m+1 The phase difference between adjacent second target clocks in the m-th second clock group is 2π / 2. N+1-m ; The parallel-to-serial converter sub-circuit includes 2 N -1 parallel-to-serial conversion unit, using 2 in the m-th parallel-to-serial conversion process. N-m Each of the parallel-to-serial conversion units corresponds one-to-one with the second target clock. Based on the corresponding second target clock, the parallel-to-serial conversion unit converts the two sets of input data it receives into one set of output data.
7. The parallel-to-serial conversion circuit according to claim 6, characterized in that, The parallel-to-serial conversion unit includes a multiplexer, which receives two sets of input data and the corresponding second target clock, and outputs the first set of input data when the corresponding second target clock is high. When the corresponding second target clock is low, the second set of input data is output to complete one parallel-to-serial conversion.
8. The parallel-to-serial conversion circuit according to claim 1, characterized in that, The first second target clock in the m-th second clock group is the first comparison clock, and the first second target clock in the (m+1)-th second clock group is the second comparison clock. The rise edge delay time of the first comparison clock and the second comparison clock is 2. N-m-2 T, where T represents the period of the serial data.
9. The parallel-to-serial conversion circuit according to claim 8, characterized in that, The first target clock is the third comparison clock, and the first second target clock in the first second clock group is the fourth comparison clock. The rising edge delay time between the third comparison clock and the fourth comparison clock is the target delay time. The target delay time is greater than 0 and less than (2π / 2). N-2 -1.5) T.
10. A control method for a parallel-to-serial conversion circuit as described in any one of claims 1 to 9, characterized in that, The method includes: The clock frequency division and phase shift sub-circuit in the parallel-to-serial conversion circuit is controlled to receive the original clock, the frequency of which is the same as the frequency of the serial data. Based on the original clock, frequency division and phase shifting processing is performed to obtain and output 2. N-2 One first target clock and N second clock groups; Control the sampling sub-circuit to receive 2 N A set of parallel data and multiple first target clocks are provided, wherein the parallel data corresponds to the first target clocks, and the multiple first target clocks have different phases. Based on the first target clocks, the corresponding parallel data is sampled to obtain 2 N Group sampling data; The control circuit receives the sampled data and N second clock groups, and performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion, and the m-th second clock group includes 2... N-m There are two second target clocks with different phases but the same frequency. The phases and frequencies of the second target clocks in different second clock groups are all different. N is a positive integer, and 1≤m≤N.