Ethernet rate adaptive reconfiguration system, method and terminal
By implementing an Ethernet rate adaptive reconfiguration system in an FPGA design, the first terminal A adaptively sets its rate according to the transmission rate of the second terminal B, which solves the multi-rate compatibility problem, reduces resource utilization, improves system flexibility and reliability, and reduces communication preparation time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NARI TECH CO LTD
- Filing Date
- 2026-02-04
- Publication Date
- 2026-06-02
AI Technical Summary
In FPGA design, existing technologies lack high-speed compatibility for Ethernet multi-rate compatibility. Existing solutions have high resource consumption, high development complexity, high hardware cost, high difficulty in collaborative development, and insufficient real-time performance and reliability.
An Ethernet rate adaptive reconfiguration system is provided. Through communication between a first terminal A and a second terminal B, the first terminal A adaptively sets the transmission rate according to the transmission rate of the second terminal B. The system utilizes a transmission module, a loading configuration module, a receiving verification module, and a response module to achieve adaptive rate switching, thereby reducing FPGA resource utilization and improving system flexibility and reliability.
It enables flexible adaptation to Ethernet communication at different speeds, reduces FPGA resource utilization, improves system flexibility and reliability, reduces communication preparation time, and enhances user experience.
Smart Images
Figure CN122137499A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power system automation, and particularly relates to an Ethernet rate adaptive reconfiguration system, method and terminal. Background Technology
[0002] FPGA (Field-Programmable Gate Array) is a product of further development based on programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solved the shortcomings of custom circuits but also overcame the limitation of the limited number of gate circuits in the original programmable devices.
[0003] Reconfiguration technology is a technique where software configures hardware with variable circuit structures to flexibly switch between different functions. Partial reconfiguration is a core feature of FPGAs, referring to reconfiguring only a portion of the FPGA, rather than the entire chip. Its advantage is that it allows modification of only the necessary area without halting other parts of the operation, enabling hardware function changes at runtime. Adaptive technology detects Ethernet speeds adaptively and loads corresponding firmware, reducing manual operation and increasing the intelligence of devices.
[0004] However, in FPGA design, the core contradiction facing Ethernet's multi-rate compatibility is the lack of high-rate compatibility. That is, due to differences in protocol layers (such as encoding methods and clock architecture) and hardware resource limitations, it is impossible to directly implement an adaptive mechanism similar to 1Gbps for rates above 1Gbps (such as 2.5Gbps, 5Gbps, 10Gbps).
[0005] Existing solutions include: manual firmware updates, redundant logic design, and external controller management. Manual firmware updates involve designing independent firmware image (Bitstream) for different speeds and burning it via JTAG after determining the peer interface speed. This method determines the existing Ethernet firmware speed, loads the pre-stored firmware for the corresponding speed (e.g., IP core configurations for different speeds), and resets and initializes the interface to manually update the firmware. This method is highly flexible and supports arbitrary speed combinations; however, it is time-consuming, with firmware switching requiring tens of milliseconds of latency, impacting real-time scenarios. It also has high development complexity, requiring the maintenance of independent firmware versions for each speed, leading to complex version management. Furthermore, it poses reliability risks; frequent firmware updates may cause state machine errors or link interruptions.
[0006] Redundant logic design involves instantiating multiple Ethernet IP cores (such as 1G / 2.5G dual IPs) simultaneously within the FPGA, selecting the active interface through logic switching. This method allocates independent logic regions and transceivers, such as GT / GTH channels, for each rate at the hardware level, and triggers rate switching through state machines or external signals at the control level. This method offers fast identification speeds, reaching nanosecond levels, making it suitable for high real-time requirements. However, this approach incurs significant resource overhead. Due to the additional LUTs, BRAMs, and SerDes resources occupied by multiple IP cores, chip resource utilization decreases by 30%-50%, power consumption increases, and idle IP cores may still generate static power consumption, affecting energy efficiency ratio. Layout and routing are also more difficult, and multiple IP cores require strict isolation of timing domains, increasing the difficulty of design convergence.
[0007] External controller management dynamically configures the FPGA firmware file through external controllers such as MCUs / CPLDs; the controller updates the configuration memory (such as Flash) through interfaces such as SPI. This method can reduce the logic complexity of FPGA and is suitable for heterogeneous systems. However, this method increases the hardware cost due to the increased space for controller chips and PCB routing. It also requires the simultaneous development of FPGA, controller and communication protocol, which prolongs the development cycle, makes collaborative development difficult, and has latency issues. External communication latency may affect the rate switching response time. Summary of the Invention
[0008] Purpose of the Invention: This invention provides an Ethernet rate adaptive reconfiguration system, method, and terminal, aiming to solve the multi-rate compatibility problem of Ethernet in the prior art. The provided Ethernet rate adaptive reconfiguration system, method, and terminal include a first terminal A and a second terminal B. The first terminal A and the second terminal B are connected via Ethernet. The second terminal B has a fixed Ethernet transmission rate. The first terminal A can adaptively set its own transmission rate according to the transmission rate of the second terminal B, thereby realizing communication between the first terminal A and the second terminal B.
[0009] Technical solution: The present invention provides an Ethernet rate adaptive reconfiguration system, comprising: a first terminal A, a second terminal B, a transmission module, a loading configuration module, a receiving verification module, and a response module; the Ethernet transmission rate of the second terminal B is fixed, and the first terminal A contains local configuration files for multiple Ethernet transmission rates;
[0010] The transmission module is used to send Ethernet data frames containing the Ethernet transmission rate of the second terminal B to the first terminal A.
[0011] The loading configuration module is used to guide the first terminal A to load any one of the local configuration files for various Ethernet transmission rates;
[0012] The receiving verification module is used for the first terminal A to receive and verify the Ethernet data frame sent by the second terminal B. If the first terminal A does not receive the Ethernet data frame sent by the second terminal B within a certain period of time or the Ethernet data frame verification is incorrect, the first terminal A will be guided to load the Ethernet local configuration file of the next speed version and re-verify. If the first terminal A receives the Ethernet data frame sent by the second terminal B and the verification is successful, the first terminal A will send a response data frame to the second terminal B.
[0013] The response module is used for the second terminal B to receive and verify the response data frame sent by the first terminal A; if the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification fails, the second terminal B resends an Ethernet data frame containing the Ethernet transmission rate of the second terminal B; if the second terminal B receives the response data frame sent by the first terminal A and the verification is successful, then communication between the first terminal A and the second terminal B is carried out at the Ethernet transmission rate of the second terminal B.
[0014] Furthermore, the first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module is used to store local configuration files for various Ethernet transmission rates; the FPGA module is used to boot and load the Ethernet local configuration files of multiple rate versions stored in the FLASH module; and the SFP optical module is used to perform photoelectric conversion of Ethernet transmit and receive signals.
[0015] Furthermore, the second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
[0016] Furthermore, in the configuration loading module, the local configuration files for various Ethernet transmission rates stored in the bootloader FLASH module include: selecting the local configuration file for the corresponding Ethernet transmission rate from the FLASH module using the ICAP primitive, and loading the local configuration file into the FPGA for execution through the configuration interface.
[0017] The present invention also provides an Ethernet rate adaptive reconfiguration method, comprising:
[0018] Define a system including a first terminal A and a second terminal B; the Ethernet transmission rate of the second terminal B is fixed, and the first terminal A contains local configuration files with multiple Ethernet transmission rates.
[0019] The second terminal B sends an Ethernet data frame containing the Ethernet transmission rate of the second terminal B to the first terminal A.
[0020] The first terminal A is booted and loaded with any one of the local configuration files for various Ethernet transmission rates;
[0021] First terminal A receives and verifies Ethernet data frames sent by second terminal B. If first terminal A does not receive Ethernet data frames sent by second terminal B within a certain period of time or the Ethernet data frame verification fails, it will load the Ethernet local configuration file of the next speed version. If first terminal A receives Ethernet data frames sent by second terminal B and the verification is successful, first terminal A will send a response data frame to second terminal B.
[0022] The second terminal B receives and verifies the response data frame sent by the first terminal A. If the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification fails, the second terminal B resends an Ethernet data frame containing the Ethernet transmission rate of the second terminal B. If the second terminal B receives the response data frame sent by the first terminal A and verifies it successfully, then communication between the first terminal A and the second terminal B is carried out at the Ethernet transmission rate of the second terminal B.
[0023] Furthermore, the first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module is used to store local configuration files for various Ethernet transmission rates; the FPGA module is used to boot and load the Ethernet local configuration files of multiple rate versions stored in the FLASH module; and the SFP optical module is used to perform photoelectric conversion of Ethernet transmit and receive signals.
[0024] Furthermore, the second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
[0025] Furthermore, the bootloader FLASH module stores various Ethernet transmission rate local configuration files, including: selecting the corresponding Ethernet transmission rate local configuration file from the FLASH module using ICAP primitives, and loading the local configuration file into the FPGA for execution through the configuration interface.
[0026] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.
[0027] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method.
[0028] Beneficial effects: The method of the present invention can flexibly adapt to Ethernet communication application scenarios with different rates, effectively reduce the actual utilization rate of FPGA resources, and improve system flexibility; the system can automatically switch Ethernet firmware files without manual operation by the user, effectively saving preparation time before communication and improving user experience. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of the system composition of the present invention.
[0030] Figure 2 This is a schematic diagram of the system functional modules of the present invention.
[0031] Figure 3 This is a schematic diagram of the Ethernet rate adaptive reconfiguration process of the present invention.
[0032] Figure 4 This is a specific Ethernet data frame structure for the present invention. Detailed Implementation
[0033] Example 1
[0034] like Figure 1 As shown, the Ethernet rate adaptive reconfiguration system of the present invention includes:
[0035] The system comprises a first terminal A, a second terminal B, a transmission module, a loading configuration module, a receiving verification module, and a response module; the Ethernet transmission rate of the second terminal B is fixed.
[0036] The first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module stores a global configuration file and local configuration files for various Ethernet transmission rates. The global configuration file includes a basic communication module configuration file and a reconfiguration control module configuration file; the local configuration files for various Ethernet transmission rates include, for example, a 1G Ethernet local configuration file and a 2.5G Ethernet local configuration file. This embodiment takes a 1G Ethernet local configuration file and a 2.5G Ethernet local configuration file as examples.
[0037] The FLASH memory is divided into three areas to store the global configuration file, the 1G Ethernet local configuration file, and the 2.5G Ethernet local configuration file, respectively. The first terminal A needs to partition the FLASH memory appropriately according to the file size and burn the three files. Commonly used FLASH memory types include Dual SPI Flash, Quad SPI Flash, and Parallel NOR Flash. Typical models are shown in Table 1.
[0038] Table 1 Comparison of Flash Models
[0039]
[0040] like Figure 2 As shown, the FPGA module is responsible for basic network communication functions such as protocol processing. In this invention, it is used to bootstrap and load Ethernet local configuration files of multiple speed versions stored in the FLASH module to complete the Ethernet speed adaptive reconstruction function. The FPGA module includes an Ethernet communication module and a speed configuration and reconstruction module. The Ethernet communication module is responsible for basic communication functions such as data reception, data parsing, data verification, response data generation, data framing, and data transmission, i.e., protocol processing and message sending and receiving. Upon power-up, it loads and runs an Ethernet local configuration file of a certain speed. Within a certain period of time, if the Ethernet module receives an Ethernet data frame with specific content sent by the other side (second terminal B) and the verification is correct (considering that the currently configured Ethernet speed is consistent with the other side), it sends a response data frame, and communication is established; otherwise, the Ethernet module sends information to the speed configuration and reconstruction module that the current speed is inconsistent and needs to be reconstructed.
[0041] The rate configuration and reconfiguration module is responsible for configuring the default Ethernet communication rate upon power-up (by booting a local Ethernet configuration file of a specific rate from the FLASH memory); it is also responsible for reconfiguring the Ethernet communication rate when necessary. When it receives information from the Ethernet communication module indicating the rate to be reconfigured, it performs the reconfiguration operation, boots the next local configuration file from the FLASH memory to overwrite the current local configuration file, and runs it. The FPGA external Ethernet interface has the following options: 1G and below via ordinary I / O or SerDes channel; above 1G only via SerDes channel. Since the device in this embodiment needs to simultaneously support 1G and 2.5G rates, the Ethernet interface design can only be implemented via the FPGA SerDes channel.
[0042] The SFP optical module is used for photoelectric conversion of Ethernet transceiver signals; the second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
[0043] The second terminal B includes a processor and an SFP optical module. The processor is responsible for basic network communication functions such as protocol processing, including data generation, data framing, data transmission, data reception, data parsing, and data verification. In this invention, upon power-on, the processor begins periodically sending Ethernet data frames with specific content, which contain the Ethernet transmission rate of the second terminal B. Communication is established only after the processor receives and correctly verifies the response frame from the first terminal A. The SFP optical module is typically a small, hot-pluggable optical transceiver module responsible for photoelectric conversion of Ethernet signals.
[0044] The transmission module is used for the second terminal B to periodically send Ethernet data frames containing the Ethernet transmission rate of the second terminal B to the first terminal A, such as... Figure 4 As shown, the data content changes accordingly depending on the Ethernet speed. For example, the data content for 1G Ethernet is 46'h3CE29A5D, and the data content for 2.5G Ethernet is 46'hA62C9F17.
[0045] The configuration loading module is used by the FPGA module of the first terminal A to guide the FLASH module to load any one of the local configuration files of various Ethernet transmission rates stored therein; this step needs to be completed using primitives provided by the FPGA manufacturer. Taking Xilinx FPGA as an example, its complete design includes: design preparation module, configuration bitstream generation module, bitstream persistence module, and dynamic loading module.
[0046] Design preparation module: divided into module division, project configuration, and physical constraints.
[0047] Module division: The global configuration file defines the non-reconfigurable logical parts, including the basic communication module and the reconfiguration control module; the local configuration file is the reconfigurable module (RM), which defines the dynamically replaceable logical blocks, including the 1G Ethernet local configuration file and the 2.5G Ethernet local configuration file.
[0048] Project configuration: First, create a Vivado project and select an FPGA model that supports partial reconfiguration; then enable partial reconfiguration mode in Vivado via Tools->Enable Partial Reconfiguration; finally, define partitions, mark each RM as a reconfigurable partition, and bind it to a physical region (Pblock).
[0049] Physical constraints: Draw Pblocks, allocate logical resources (such as LUTs, FFs, BRAMs, DSPs, etc.) to each RM in the Floorplanning view, and perform resource redundancy, reserving 10%~20% of extra resources to prevent layout failure.
[0050] The configuration bitstream generation module: Each Resource Management (RM) is synthesized separately, generating a .dcp file; a top-level synthesis design (including static logic and RM) is used, followed by placement and routing, and timing closure to ensure that the static interface timing meets requirements. Bitstreams are generated, including complete bitstreams and partial bitstreams; the complete bitstream includes a global configuration file, generated in Vivado via PROGRAM AND DEBUG -> Generate Bitstream; partial bitstreams are generated using the Partial Reconfiguration Wizard to create a difference file for each RM, i.e., PROGRAM AND DEBUG -> Generate Bitstream is run separately for each RM to generate a bitstream containing only the logic of that RM.
[0051] Bitstream fixing module: Allocates FLASH storage space and fixes the complete bitstream and partial bitstream generated by S3.2 into FLASH according to the allocated address space. The complete bitstream is the global configuration file, and the partial bitstream is the local configuration file.
[0052] Dynamic loading module: Initial configuration loads the global configuration file; after partial reconstruction is triggered, the reconstruction control module in the global configuration file receives the reconstruction loading command, selects the corresponding local configuration file from FLASH using the ICAP primitive, and loads the selected configuration file into the FPGA for execution through the configuration interface.
[0053] The receive verification module is used by the first terminal A to receive and verify the Ethernet data frames sent by the second terminal B;
[0054] If the first terminal A does not receive an Ethernet data frame sent by the second terminal B within a certain period of time or the Ethernet data frame check error occurs, then return to S3 and load the local configuration file for the next Ethernet transmission rate.
[0055] If the first terminal A receives the Ethernet data frame sent by the second terminal B and the verification is successful, the first terminal A sends a response data frame to the second terminal B. The data content of the response data frame is changed accordingly according to the Ethernet speed. For example, the data content of 1G Ethernet is 46'hC31D65A2, and the data content of 2.5G Ethernet is 16'h59D360E8.
[0056] The response module is used by the second terminal B to receive and verify the response data frame sent by the first terminal A;
[0057] If the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification is incorrect, then return to S2;
[0058] If the second terminal B receives the response data frame sent by the first terminal A and verifies it successfully, then the second terminal B stops sending Ethernet data frames with preset content to the first terminal A, and the communication link between the first terminal A and the second terminal B is established.
[0059] Communication between the first terminal A and the second terminal B is performed using the Ethernet transmission rate of the second terminal B.
[0060] In this embodiment, the second terminal B represents data acquisition devices with different sampling accuracies, which transmit the acquired data to the first terminal A via Ethernet at different rates. The first terminal A performs real-time analysis and processing on the data sent by the second terminal B, and makes reasonable responses based on the analysis results, thereby ensuring the safe and stable operation of the power system.
[0061] This invention can effectively reduce the actual utilization rate of FPGA resources, improve system reliability and flexibility; the system can adaptively switch between firmware files without manual operation by the user, greatly saving preparation time before communication and improving user experience.
[0062] Example 2
[0063] like Figure 3 As shown, the Ethernet rate adaptive reconfiguration method of the present invention includes:
[0064] S1. The system is powered on. The system includes a first terminal A and a second terminal B. The second terminal B has a fixed Ethernet transmission rate.
[0065] like Figure 1 As shown, the first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module stores a global configuration file and local configuration files for various Ethernet transmission rates. The global configuration file includes a basic communication module configuration file and a reconfiguration control module configuration file; the local configuration files for various Ethernet transmission rates include, for example, a 1G Ethernet local configuration file and a 2.5G Ethernet local configuration file. This embodiment takes a 1G Ethernet local configuration file and a 2.5G Ethernet local configuration file as examples.
[0066] The FLASH memory is divided into three areas to store the global configuration file, the 1G Ethernet local configuration file, and the 2.5G Ethernet local configuration file, respectively. The first terminal A needs to partition the FLASH memory appropriately according to the file size and burn the three files. Commonly used FLASH memory types include Dual SPI Flash, Quad SPI Flash, and Parallel NOR Flash. Typical models are shown in Table 1.
[0067] Table 1 Comparison of Flash Models
[0068]
[0069] like Figure 2 As shown, the FPGA module is responsible for basic network communication functions such as protocol processing. In this invention, it is used to bootstrap and load Ethernet local configuration files of multiple speed versions stored in the FLASH module to complete the Ethernet speed adaptive reconstruction function. The FPGA module includes an Ethernet communication module and a speed configuration and reconstruction module. The Ethernet communication module is responsible for basic communication functions such as data reception, data parsing, data verification, response data generation, data framing, and data transmission, i.e., protocol processing and message sending and receiving. Upon power-up, it loads and runs an Ethernet local configuration file of a certain speed. Within a certain period of time, if the Ethernet module receives an Ethernet data frame with specific content sent by the other side (second terminal B) and the verification is correct (considering that the currently configured Ethernet speed is consistent with the other side), it sends a response data frame, and communication is established; otherwise, the Ethernet module sends information to the speed configuration and reconstruction module that the current speed is inconsistent and needs to be reconstructed.
[0070] The rate configuration and reconfiguration module is responsible for configuring the default Ethernet communication rate upon power-up (by booting a local Ethernet configuration file of a specific rate from the FLASH memory); it is also responsible for reconfiguring the Ethernet communication rate when necessary. When it receives information from the Ethernet communication module indicating the rate to be reconfigured, it performs the reconfiguration operation, boots the next local configuration file from the FLASH memory to overwrite the current local configuration file, and runs it. The FPGA external Ethernet interface has the following options: 1G and below via ordinary I / O or SerDes channel; above 1G only via SerDes channel. Since the device in this embodiment needs to simultaneously support 1G and 2.5G rates, the Ethernet interface design can only be implemented via the FPGA SerDes channel.
[0071] The SFP optical module is used for photoelectric conversion of Ethernet transceiver signals; the second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
[0072] The second terminal B includes a processor and an SFP optical module. The processor is responsible for basic network communication functions such as protocol processing, including data generation, data framing, data transmission, data reception, data parsing, and data verification. In this invention, upon power-on, the processor begins periodically sending Ethernet data frames with specific content, which contain the Ethernet transmission rate of the second terminal B. Communication is established only after the processor receives and correctly verifies the response frame from the first terminal A. The SFP optical module is typically a small, hot-pluggable optical transceiver module responsible for photoelectric conversion of Ethernet signals.
[0073] S2. The second terminal B periodically sends Ethernet data frames containing the Ethernet transmission rate of the second terminal B to the first terminal A, such as... Figure 4 As shown, the data content changes accordingly depending on the Ethernet speed. For example, the data content for 1G Ethernet is 46'h3CE29A5D, and the data content for 2.5G Ethernet is 46'hA62C9F17.
[0074] S3. The FPGA module of the first terminal A guides the FLASH module to load any one of the stored local configuration files for various Ethernet transmission rates. This step requires the use of primitives provided by the FPGA manufacturer. Taking Xilinx FPGA as an example, its complete design flow is as follows:
[0075] The S3.1 design preparation phase is divided into module division, project configuration, and physical constraints.
[0076] Module division: The global configuration file defines the non-reconfigurable logical parts, including the basic communication module and the reconfiguration control module; the local configuration file is the reconfigurable module (RM), which defines the dynamically replaceable logical blocks, including the 1G Ethernet local configuration file and the 2.5G Ethernet local configuration file.
[0077] Project configuration: First, create a Vivado project and select an FPGA model that supports partial reconfiguration; then enable partial reconfiguration mode in Vivado via Tools->Enable Partial Reconfiguration; finally, define partitions, mark each RM as a reconfigurable partition, and bind it to a physical region (Pblock).
[0078] Physical constraints: Draw Pblocks, allocate logical resources (such as LUTs, FFs, BRAMs, DSPs, etc.) to each RM in the Floorplanning view, and perform resource redundancy, reserving 10%~20% of extra resources to prevent layout failure.
[0079] S3.2 Generate Configuration Bitstream: Each Resource Management Stream (RM) is synthesized separately, generating a .dcp file. A top-level synthesis design (including static logic and RMs) is employed, along with placement and routing, and timing closure to ensure static interface timing meets requirements. Bitstreams are generated, including complete and partial bitstreams. The complete bitstream contains a global configuration file and is generated in Vivado via PROGRAM AND DEBUG -> Generate Bitstream. Partial bitstreams are generated using the Partial Reconfiguration Wizard to create a difference file for each RM; that is, PROGRAM AND DEBUG -> Generate Bitstream is run separately for each RM to generate a bitstream containing only the logic of that RM.
[0080] S3.3 Solidify Bitstream: Allocate FLASH storage space and solidify the complete bitstream and partial bitstream generated in S3.2 into FLASH according to the allocated address space. The complete bitstream is the global configuration file, and the partial bitstream is the local configuration file.
[0081] S3.3 Dynamic Loading
[0082] The initial configuration loads the global configuration file; after a partial refactoring is triggered, the refactoring control module in the global configuration file receives the refactoring loading command, selects the corresponding local configuration file from FLASH using the ICAP primitive, and loads the selected configuration file into the FPGA for execution through the configuration interface.
[0083] S4. The first terminal A receives the Ethernet data frame sent by the second terminal B and performs verification.
[0084] If the first terminal A does not receive an Ethernet data frame sent by the second terminal B within a certain period of time or the Ethernet data frame check error occurs, then return to S3 and load the local configuration file for the next Ethernet transmission rate.
[0085] If the first terminal A receives the Ethernet data frame sent by the second terminal B and the verification is successful, the first terminal A sends a response data frame to the second terminal B. The data content of the response data frame is changed accordingly according to the Ethernet speed. For example, the data content of 1G Ethernet is 46'hC31D65A2, and the data content of 2.5G Ethernet is 16'h59D360E8.
[0086] S5. The second terminal B receives the response data frame sent by the first terminal A and performs verification.
[0087] If the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification is incorrect, then return to S2;
[0088] If the second terminal B receives the response data frame sent by the first terminal A and verifies it successfully, then the second terminal B stops sending Ethernet data frames with preset content to the first terminal A, and the communication link between the first terminal A and the second terminal B is established.
[0089] S6. Communication between the first terminal A and the second terminal B is performed at the Ethernet transmission rate of the second terminal B.
[0090] In this embodiment, the second terminal B represents data acquisition devices with different sampling accuracies, which transmit the acquired data to the first terminal A via Ethernet at different rates. The first terminal A performs real-time analysis and processing on the data sent by the second terminal B, and makes reasonable responses based on the analysis results, thereby ensuring the safe and stable operation of the power system.
[0091] This invention can effectively reduce the actual utilization rate of FPGA resources, improve system reliability and flexibility; the system can adaptively switch between firmware files without manual operation by the user, greatly saving preparation time before communication and improving user experience.
Claims
1. An Ethernet rate adaptive reconfiguration system, characterized in that, include: First terminal A, second terminal B, transmission module, loading configuration module, receiving verification module, and response module; The Ethernet transmission rate of the second terminal B is fixed, while the first terminal A contains local configuration files with multiple Ethernet transmission rates. The transmission module is used to send Ethernet data frames containing the Ethernet transmission rate of the second terminal B to the first terminal A. The loading configuration module is used to guide the first terminal A to load any one of the local configuration files for various Ethernet transmission rates; The receiving verification module is used for the first terminal A to receive and verify the Ethernet data frames sent by the second terminal B. If the first terminal A does not receive the Ethernet data frames sent by the second terminal B within a certain period of time or the Ethernet data frame verification is incorrect, the first terminal A will be guided to load the Ethernet local configuration file of the next rate version and re-verify. If the first terminal A receives the Ethernet data frame sent by the second terminal B and the verification is successful, then the first terminal A sends a response data frame to the second terminal B. The response module is used for the second terminal B to receive and verify the response data frame sent by the first terminal A; If the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification is incorrect, the second terminal B will resend an Ethernet data frame containing the Ethernet transmission rate of the second terminal B. If the second terminal B receives the response data frame sent by the first terminal A and verifies it successfully, then communication between the first terminal A and the second terminal B will proceed at the Ethernet transmission rate of the second terminal B.
2. The Ethernet rate adaptive reconfiguration system according to claim 1, characterized in that, The first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module is used to store local configuration files for various Ethernet transmission rates; the FPGA module is used to boot and load the Ethernet local configuration files for multiple rate versions stored in the FLASH module; and the SFP optical module is used to perform photoelectric conversion of Ethernet transmit and receive signals.
3. The Ethernet rate adaptive reconfiguration system according to claim 2, characterized in that, The second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
4. The Ethernet rate adaptive reconfiguration system according to claim 3, characterized in that, In the configuration loading module, the local configuration files for various Ethernet transmission rates stored in the bootloader FLASH module include: selecting the local configuration file for the corresponding Ethernet transmission rate from the FLASH module using the ICAP primitive, and loading the local configuration file into the FPGA for execution through the configuration interface.
5. An Ethernet rate adaptive reconfiguration method, characterized in that, include: Define the system, including a first terminal A and a second terminal B; The Ethernet transmission rate of the second terminal B is fixed, while the first terminal A contains local configuration files with multiple Ethernet transmission rates. The second terminal B sends an Ethernet data frame containing the Ethernet transmission rate of the second terminal B to the first terminal A. The first terminal A is booted and loaded with any one of the local configuration files for various Ethernet transmission rates; First terminal A receives and verifies Ethernet data frames sent by second terminal B. If first terminal A does not receive Ethernet data frames sent by second terminal B within a certain period of time or the Ethernet data frame verification fails, it will be guided to load the Ethernet local configuration file of the next speed version. If the first terminal A receives the Ethernet data frame sent by the second terminal B and the verification is successful, then the first terminal A sends a response data frame to the second terminal B. The second terminal B receives the response data frame sent by the first terminal A and performs verification; If the second terminal B does not receive the response data frame sent by the first terminal A within a certain period of time or the response data frame verification is incorrect, the second terminal B will resend an Ethernet data frame containing the Ethernet transmission rate of the second terminal B. If the second terminal B receives the response data frame sent by the first terminal A and verifies it successfully, then communication between the first terminal A and the second terminal B will proceed at the Ethernet transmission rate of the second terminal B.
6. The Ethernet rate adaptive reconfiguration method according to claim 5, characterized in that, The first terminal A includes an FPGA module, a FLASH module, and an SFP optical module; the FLASH module is used to store local configuration files for various Ethernet transmission rates; the FPGA module is used to boot and load the Ethernet local configuration files for multiple rate versions stored in the FLASH module; and the SFP optical module is used to perform photoelectric conversion of Ethernet transmit and receive signals.
7. The Ethernet rate adaptive reconfiguration method according to claim 6, characterized in that, The second terminal B includes a processor and an SFP optical module; the processor loads various functional module files for network communication; the SFP optical module is used for photoelectric conversion of Ethernet transceiver signals.
8. The Ethernet rate adaptive reconfiguration method according to claim 7, characterized in that, The bootloader FLASH module stores various Ethernet transmission rate local configuration files, including: selecting the corresponding Ethernet transmission rate local configuration file from the FLASH module using ICAP primitives, and loading the local configuration file into the FPGA for execution through the configuration interface.
9. A computer terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 5 to 8.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 8.