A method, apparatus, device, and storage medium for synchronous signal processing based on differential symmetric polarization sequences.

Abstract

This application discloses a synchronization signal processing method based on differential symmetric polarization sequences, comprising: the transmitter performing m symmetric polarization processing on the basic sequence to generate a signal of length 2. m The symmetric polarization sequence; through differential polarization modulation, the M basic sequences are combined to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the basic sequence; the receiving end performs time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain a filtered signal; the filtered signal is split into two paths, one path is passed directly, and the other path is delayed by N clock cycles. The two signals are multiplied by conjugate, and the resulting primary processed signal is subjected to m iterations of delay-shift phase addition and subtraction processing to output the final correlation peak and determine the synchronization position. This invention also discloses a synchronization signal processing device, corresponding equipment, and storage medium based on differential symmetric polarization sequences. This application effectively overcomes carrier frequency offset and DC bias interference, saving hardware logic resources.

Description

Technical Field

[0001] This application relates to the field of telecommunications technology, and more specifically, to a method, apparatus, device, and storage medium for synchronous signal processing based on differential symmetric polarization sequences. Background Technology

[0002] In wireless communication systems, reliable timing synchronization is a prerequisite for accurate data reception and recovery. Especially in complex channel environments, such as low signal-to-noise ratios, multipath effects, residual carrier frequency offsets, and DC bias, achieving fast and robust synchronization acquisition presents a significant challenge. Therefore, designing a synchronization signal processing scheme that can withstand these adverse factors while possessing low complexity has always been a core issue and a direction for continuous optimization in the physical layer design of wireless communication.

[0003] Existing synchronization techniques generally employ frame structures based on specific training sequences, such as using one or more repeating ZC or PN sequences as synchronization headers. However, these traditional synchronization frame structures have significant shortcomings. They perform poorly at low signal-to-noise ratios (SNR), suffer from correlation peak ambiguity, are affected by DC bias or frequency offset resulting in inconsistent correlation peak sizes, or experience large processing delays and computational complexity, consuming substantial hardware resources. Therefore, providing a synchronization frame structure suitable for wireless communication systems that overcomes the limitations of existing synchronization frame structures, such as high SNR requirements, correlation peak ambiguity, and the effects of DC bias or carrier frequency offset, is a pressing issue that needs to be addressed. Summary of the Invention

[0004] In view of at least one defect or improvement requirement of the prior art, the present invention provides a method, apparatus, device and storage medium for synchronous signal processing based on differential symmetric polarization sequence, which can solve at least one of the problems existing in the background art.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a synchronization signal processing method based on differential symmetric polarization sequences is provided, the method comprising: The transmitter performs m symmetric polarization processes on the basic sequence to generate a sequence of length 2. m Symmetric polarization sequence; Based on the symmetric polarization sequence, differential polarization modulation is used to combine M segments of the basic sequence to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The receiving end performs time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The filtered signal is divided into two paths. One path is passed directly, and the other path is delayed by N clock cycles. The two signals are multiplied by their conjugate to obtain the primary processed signal. The primary processed signal is subjected to m iterations of delay-shift phase addition and subtraction processing, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; After m iterations of delay-shift phase addition and subtraction processing, the final correlation peak is output to determine the synchronization position.

[0006] Furthermore, in the above-mentioned synchronization signal processing method based on differential symmetric polarization sequences, the symmetric polarization processing specifically includes: Multiply each element of the current sequence by -1 to reverse its polarity, and then concatenate the reversed sequence with the original sequence in order to generate a new sequence.

[0007] Furthermore, in the above-mentioned synchronization signal processing method based on differential symmetric polarization sequences, the differential polarity modulation specifically includes: The polarity of the first basic sequence remains unchanged. The polarity of the (i+1)th basic sequence is determined by the sign of the i-th value of the symmetric polarization sequence, which determines whether it is the same as or opposite to the polarity of the i-th basic sequence. Here, i is from 1 to 2. m Positive integers.

[0008] Furthermore, in the above-mentioned synchronization signal processing method based on differential symmetric polarization sequences, the basic sequence is a ZC sequence or a PN sequence.

[0009] Furthermore, in the above-mentioned synchronization signal processing method based on differential symmetric polarization sequences, the basic sequence is pre-stored in a read-only memory, and is read in sequence and differential polarization modulation is performed when constructing a synchronization frame.

[0010] Furthermore, in the above-mentioned synchronous signal processing method based on differential symmetric polarization sequences, the rules for the addition or subtraction operations used in each iteration are determined by the symmetry law of the symmetric polarization sequence.

[0011] Furthermore, in the above-mentioned synchronization signal processing method based on differential symmetric polarization sequences, the synchronization frame generation method at the transmitting end and the synchronization acquisition method at the receiving end are implemented on an FPGA platform.

[0012] According to a second aspect of the present invention, a synchronization signal processing apparatus based on a differential symmetric polarization sequence is also provided, comprising: The symmetric polarization sequence generation module is used by the transmitter to perform m symmetric polarization processes on the basic sequence, generating a sequence of length 2. m Symmetric polarization sequence; The modulation module is used to combine M segments of the basic sequence according to the symmetric polarization sequence through differential polarization modulation to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The filtering module is used by the receiving end to perform time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The first signal processing module is used to divide the filtered signal into two paths, one path is passed directly and the other path is delayed by N clock cycles, and the two signals are multiplied by conjugate to obtain the primary processed signal. The second signal processing module is used to perform m iterations of delay-shift phase addition and subtraction processing on the primary processed signal, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; The synchronization frame determination module is used to output the final correlation peak after m iterations of delay-shift phase addition and subtraction processing to determine the synchronization position.

[0013] According to a third aspect of the present invention, a synchronization signal processing device based on a differential symmetric polarization sequence is also provided, comprising at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program that, when executed by the processing unit, causes the processing unit to perform the steps of any of the methods described above.

[0014] According to a fourth aspect of the invention, a storage medium is also provided, which stores a computer program executable by a synchronization signal processing device based on a differential symmetric polarization sequence, which, when run on the synchronization signal processing device based on a differential symmetric polarization sequence, causes the synchronization signal processing device based on a differential symmetric polarization sequence to perform the steps of any of the methods described above.

[0015] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: The synchronization signal processing method based on differential symmetric polarization sequence provided in this application effectively overcomes carrier frequency offset and DC bias interference through the synchronization frame structure constructed by differential polarity modulation. It is easy to implement on hardware platforms such as FPGA, significantly reduces processing latency, greatly saves hardware logic resources, provides advantages for the miniaturization and low power consumption design of communication equipment, and can ensure the link reliability of wireless communication system under harsh conditions. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a synchronization signal processing method based on differential symmetric polarization sequences provided in this application embodiment; Figure 2 This is a schematic diagram of the synchronous frame symmetric polarization sequence generation process provided in an embodiment of this application; Figure 3 A schematic diagram of the process of generating a synchronization frame using symmetric sequence difference is provided for an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0019] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0020] Figure 1 A flowchart illustrating a synchronization signal processing method based on differential symmetric polarization sequences provided in this application is shown below. Figure 1 As shown in the figure, this application provides a synchronization signal processing method based on differential symmetric polarization sequences, including the following steps: The transmitter performs m symmetric polarization processes on the basic sequence to generate a sequence of length 2. m Symmetric polarization sequence; Based on the symmetric polarization sequence, differential polarization modulation is used to combine M segments of the basic sequence to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The receiving end performs time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The filtered signal is divided into two paths. One path is passed directly, and the other path is delayed by N clock cycles. The two signals are multiplied by their conjugate to obtain the primary processed signal. The primary processed signal is subjected to m iterations of delay-shift phase addition and subtraction processing, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; After m iterations of delay-shift phase addition and subtraction processing, the final correlation peak is output to determine the synchronization position.

[0021] Specifically, this embodiment provides a synchronization signal processing method based on differential symmetric polarization sequence. The method includes processing steps at the transmitting end and the receiving end. The steps are explained below.

[0022] At the transmitting end, symmetric polarization sequence generation is first performed. A basic sequence (such as a ZC sequence or a PN sequence) undergoes m symmetric polarization processes to generate a sequence of length 2. m The symmetric polarization sequence is obtained by multiplying each element of the current sequence by -1 to reverse its polarity, and then concatenating the reversed sequence with the original sequence in order to form a new sequence with doubled length. This process is repeated m times to finally obtain the desired symmetric polarization sequence.

[0023] Next, synchronization frame construction is performed. Based on the symmetric polarization sequence, M basic sequences are combined using differential polarization modulation to generate a synchronization frame of length M×N, where M=2. m +1, where N is the length of the base sequence. Differential polarity modulation means that the polarity of the first base sequence remains unchanged, and the polarity of the subsequent (i+1)th base sequence is determined by the sign of the i-th value of the symmetric polarization sequence. If the value is positive, the (i+1)th segment has the same polarity as the i-th segment; if it is negative, the polarity is opposite. i ranges from 1 to 2. m Positive integers. This process implements a special structure for synchronization frames through polarity control to enhance anti-interference capabilities.

[0024] At the receiving end, matched filtering is first performed. Based on the locally stored base sequence, the received signal is subjected to time-domain matched filtering to enhance the correlation of the signal and obtain the filtered signal.

[0025] Then, conjugate multiplication is performed, splitting the filtered signal into two paths: one path passes directly, while the other is delayed by N clock cycles. The two paths are then multiplied by their conjugates to obtain the primary processed signal. This step helps suppress the effects of carrier frequency offset and noise.

[0026] Multi-level iterative delay-shift phase addition and subtraction processing is performed, with m iterations applied to the primary processed signal. The k-th processing step involves combining the current sequence with a delay L. k The sequence after each data point is added or subtracted, where the delay length L k = (M-1)×N / 2k, meaning that the first iteration involves shifting the conjugate multiplication result by (M-1)×N / 2 bits according to the symmetric polarity of the synchronization frame, and then adding or subtracting it from the original conjugate multiplication result. The second iteration involves performing the same shifting and delaying process on the result from the first iteration, with a shift length of (M-1)×N÷4. This process continues until m iterations of shifting and delaying are completed, with the shift length for the k-th iteration being (M-1)×N÷2k, where k is a positive integer, k≥1 and k≤m. The addition or subtraction rule for each iteration is determined by the symmetry of the symmetric polarization sequence generated by the transmitter, thereby gradually sharpening the correlation peak. After m iterations, the final correlation peak is output, which is sharp and clear, used to accurately determine the synchronization position of the signal.

[0027] The synchronization signal processing method based on differential symmetric polarization sequences provided in this application involves only addition, subtraction, inversion, and a small number of multiplication operations. It is applicable to communication systems on various hardware platforms, requires minimal hardware resources, has low cost, and consumes almost no storage resources, saving storage space. By using differential symmetric polarization sequences to differentially polarize and accumulate multiple correlation peaks, the influence of carrier frequency offset and channel effects is eliminated. This is equivalent to weighted filtering of the results of multiple conjugate multiplication correlation peaks to reduce the influence of Gaussian white noise, thereby improving the accuracy of simultaneous synchronization position. Through the above steps, this application achieves low-complexity, highly robust synchronization acquisition, effectively overcoming the influence of carrier frequency offset, DC offset, and multipath channels. Compared with traditional estimation methods, under carrier frequency offset conditions, statistical results from 10,000 trials show that the synchronization correlation peaks of the synchronization frame structure using differential symmetric polarization sequences are sharper, the position accuracy is higher, and the synchronization success rate can be increased from 95% to 99.99%; under multipath channels, it can also be increased from 90% to 99%.

[0028] The synchronization signal processing method based on differential symmetric polarization sequence provided in this application effectively overcomes carrier frequency offset and DC bias interference through the synchronization frame structure constructed by differential polarity modulation. It is easy to implement on hardware platforms such as FPGA, significantly reduces processing latency, greatly saves hardware logic resources, provides advantages for the miniaturization and low power consumption design of communication equipment, and can ensure the link reliability of wireless communication system under harsh conditions.

[0029] Optionally, the synchronization signal processing method based on differential symmetric polarization sequences provided in this application embodiment specifically includes the following symmetric polarization processing: Multiply each element of the current sequence by -1 to reverse its polarity, and then concatenate the reversed sequence with the original sequence in order to generate a new sequence.

[0030] Specifically, such as Figure 2 As shown, each element of the current sequence (initially the base sequence) is multiplied by -1 to reverse the polarity of the entire sequence, resulting in a sequence with completely opposite polarities. Then, the new sequence obtained after this polarity reversal is concatenated with the original sequence before the reversal operation in a predefined order to generate a new sequence with double the length. The concatenation order is usually the original sequence first, followed by the reversed sequence, but can be chosen according to actual needs. This reversal-concatenation operation constitutes a complete symmetric polarization process.

[0031] The above process is iterated m times. That is, the new sequence obtained from each processing will be used as the input sequence for the next processing, and the polarity reversal and sequence concatenation operations will be repeated. After m iterations, a sequence of length 2 is finally generated. m The symmetric polarization sequence contains an m-layer polar symmetric structure, the symmetry of which will be used by subsequent differential polar modulation steps to construct the synchronization frame.

[0032] Optionally, the synchronization signal processing method based on differential symmetric polarization sequences provided in this application embodiment specifically includes the differential polarization modulation as follows: The polarity of the first basic sequence remains unchanged. The polarity of the (i+1)th basic sequence is determined by the sign of the i-th value of the symmetric polarization sequence, which determines whether it is the same as or opposite to the polarity of the i-th basic sequence. Here, i is from 1 to 2. m Positive integers.

[0033] Specifically, such as Figure 3 As shown, the polarity of the initial segment of the synchronization frame is determined. The polarity of the first basic sequence remains unchanged and serves as the polarity reference for the entire synchronization frame. Subsequently, differential modulation is performed on the polarity of each subsequent basic sequence segment. For the (i+1)th basic sequence segment, its polarity is determined by querying the i-th value of the symmetric polarization sequence. If the value is positive, the polarity of the (i+1)th basic sequence segment must be consistent with the polarity of the immediately preceding segment, i.e., the i-th basic sequence segment; if the value is negative, the polarity of the (i+1)th basic sequence segment must be opposite to the polarity of the i-th basic sequence segment. Here, i ranges from 1 to 2. m Positive integers.

[0034] This process is repeated sequentially until all M basic sequences have been processed, ultimately generating a complete synchronization frame, where M=2. m +1. Through this differential modulation rule based on the polarity and control sequence values ​​of the preceding segment, a clear polarity change pattern is contained within the synchronization frame. This pattern strictly corresponds to the processing algorithm at the receiving end, jointly ensuring that the system achieves high-precision and low-complexity synchronization acquisition under adverse channel conditions.

[0035] Optionally, in the synchronization signal processing method based on differential symmetric polarization sequences provided in the embodiments of this application, the base sequence is a ZC sequence or a PN sequence.

[0036] Optionally, in the synchronization signal processing method based on differential symmetric polarization sequence provided in this application embodiment, the basic sequence is pre-stored in a read-only memory, and is read in sequence and differential polarization modulation is performed when constructing a synchronization frame.

[0037] Optionally, in the synchronization signal processing method based on differential symmetric polarization sequences provided in this application embodiment, the rules for the addition or subtraction operations used in each iteration are determined by the symmetry law of the symmetric polarization sequence.

[0038] Specifically, during the multi-level synchronization acquisition process at the receiving end, when performing the k-th iteration of delay shift addition and subtraction processing on the primary processing signal, the selected addition or subtraction operation is not arbitrarily specified, but uniquely determined by the inherent symmetry law of the symmetric polarization sequence on which the transmitting end generates the synchronization frame.

[0039] This symmetry principle originates from the m-fold iterative process of generating the symmetric polarization sequence itself. During the k-th iteration, the operational rules must match the polarity symmetry pattern established by the k-th inversion-concatenation operation that generates the symmetric polarization sequence. For example, if the symmetric polarization sequence is a concatenation of the original and reverse sequences at the k-th layer of symmetry, then during the k-th iteration at the receiving end, a delay L is correspondingly specified. k The sequence following a data point is added to the current sequence; conversely, if the symmetry patterns are different, a subtraction operation may be specified. Through this strictly corresponding addition and subtraction operation, the processing can accurately match and enhance the specific signal structure embedded in the synchronization frame through differential polarity modulation, while effectively canceling or suppressing interference introduced by channel noise, carrier frequency offset, and DC bias.

[0040] Optionally, in the synchronization signal processing method based on differential symmetric polarization sequence provided in this application embodiment, the synchronization frame generation method at the transmitting end and the synchronization acquisition method at the receiving end are implemented on an FPGA platform.

[0041] Optionally, embodiments of this application also provide a synchronization signal processing device based on a differential symmetric polarization sequence, comprising: The symmetric polarization sequence generation module is used by the transmitter to perform m symmetric polarization processes on the basic sequence, generating a sequence of length 2. m Symmetric polarization sequence; The modulation module is used to combine M segments of the basic sequence according to the symmetric polarization sequence through differential polarization modulation to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The filtering module is used by the receiving end to perform time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The first signal processing module is used to divide the filtered signal into two paths, one path is passed directly and the other path is delayed by N clock cycles, and the two signals are multiplied by conjugate to obtain the primary processed signal. The second signal processing module is used to perform m iterations of delay-shift phase addition and subtraction processing on the primary processed signal, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; The synchronization frame determination module is used to output the final correlation peak after m iterations of delay-shift phase addition and subtraction processing to determine the synchronization position.

[0042] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0043] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0044] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0045] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0046] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0047] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0048] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0049] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0050] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A synchronization signal processing method based on differential symmetric polarization sequences, characterized in that, Includes the following steps: The transmitter performs m symmetric polarization processes on the basic sequence to generate a sequence of length 2. m Symmetric polarization sequence; Based on the symmetric polarization sequence, differential polarization modulation is used to combine M segments of the basic sequence to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The receiving end performs time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The filtered signal is divided into two paths. One path is passed directly, and the other path is delayed by N clock cycles. The two signals are multiplied by their conjugate to obtain the primary processed signal. The primary processed signal is subjected to m iterations of delay-shift phase addition and subtraction processing, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; After m iterations of delay-shift phase addition and subtraction processing, the final correlation peak is output to determine the synchronization position.

2. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 1, characterized in that, The symmetric polarization process specifically includes: Multiply each element of the current sequence by -1 to reverse its polarity, and then concatenate the reversed sequence with the original sequence in order to generate a new sequence.

3. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 1, characterized in that, The differential polarity modulation specifically includes: The polarity of the first basic sequence remains unchanged. The polarity of the (i+1)th basic sequence is determined by the sign of the i-th value of the symmetric polarization sequence, which determines whether it is the same as or opposite to the polarity of the i-th basic sequence. Here, i is from 1 to 2. m Positive integers.

4. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 1, characterized in that, The base sequence is a ZC sequence or a PN sequence.

5. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 1, characterized in that, The basic sequence is pre-stored in a read-only memory and is read in sequence during the construction of the synchronization frame to perform the differential polarity modulation.

6. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 5, characterized in that, The rules for the addition or subtraction operations used in each iteration are determined by the symmetry of the symmetric polarization sequence.

7. The synchronization signal processing method based on differential symmetric polarization sequences as described in claim 1, characterized in that, The synchronization frame generation method of the transmitting end and the synchronization acquisition method of the receiving end are implemented on the FPGA platform.

8. A synchronization signal processing device based on differential symmetric polarization sequences, characterized in that, include: The symmetric polarization sequence generation module is used by the transmitter to perform m symmetric polarization processes on the basic sequence, generating a sequence of length 2. m Symmetric polarization sequence; The modulation module is used to combine M segments of the basic sequence according to the symmetric polarization sequence through differential polarization modulation to generate a synchronization frame of length M×N, where M=2. m +1, N is the length of the base sequence; The filtering module is used by the receiving end to perform time-domain matched filtering on the received signal based on the locally stored basic sequence to obtain the filtered signal; The first signal processing module is used to divide the filtered signal into two paths, one path is passed directly and the other path is delayed by N clock cycles, and the two signals are multiplied by conjugate to obtain the primary processed signal. The second signal processing module is used to perform m iterations of delay-shift phase addition and subtraction processing on the primary processed signal, wherein the k-th delay-shift phase addition and subtraction processing is to combine the current sequence with a delay L. k Add or subtract the sequences following each sequence, where the delay length L k It is (M-1)×N / 2k, where k is a positive integer from 1 to m; The synchronization frame determination module is used to output the final correlation peak after m iterations of delay-shift phase addition and subtraction processing to determine the synchronization position.

9. A synchronization signal processing device based on differential symmetric polarization sequences, characterized in that, The method includes at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program that, when executed by the processing unit, causes the processing unit to perform the steps of the method according to any one of claims 1 to 7.

10. A storage medium, characterized in that, It stores a computer program executable by a synchronization signal processing device based on a differential symmetric polarization sequence, which, when run on the synchronization signal processing device based on a differential symmetric polarization sequence, causes the synchronization signal processing device based on a differential symmetric polarization sequence to perform the steps of the method according to any one of claims 1 to 7.

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