Spike suppression for FSK demodulation

Abstract

This disclosure relates to glitch suppression for FSK demodulation. According to an embodiment, a glitch suppression circuit includes a first-stage averaging circuit with programmable length, a second-stage averaging circuit, and a hysteresis comparator. The first stage uses a FIFO buffer to implement recursive shifting and averaging to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses a programmable threshold set based on the peak signal value to generate a clean output signal. This circuit removes glitches from the input signal of the frequency shift keying (FSK) demodulator while maintaining signal integrity at high bit rates. The programmable parameters allow for optimization based on desired glitch characteristics and system requirements.

Description

Technical Field

[0001] This disclosure generally relates to demodulation, and in certain embodiments to glitch suppression for a high bitrate FSK demodulator. Background Technology

[0002] In wireless power transmission systems, communication between transmitter and receiver devices often employs Frequency Shift Keying (FSK) modulation. FSK modulation encodes digital information by changing the frequency of the carrier signal. For wireless charging applications, the transmitter can modulate its power signal frequency to send data to the receiver.

[0003] The FSK demodulation circuitry in the receiver extracts the transmitted information from the modulated power signal. One FSK demodulation scheme uses a counter-based method, which measures the frequency of the incoming FSK signal by counting cycles of a known system clock within each period of the FSK signal. The resulting count value corresponds to the transmitted frequency and can be used to determine the digital data.

[0004] The voltage from the rectifier circuitry of the receiver is used as the input to the FSK demodulation process. However, this voltage may contain glitches—unwanted short-duration pulses or transitions. Glitches can occur near the boundaries of frequency transitions and can be caused by factors such as component selection, coil coupling, and load characteristics. Glitches in the input signal can pose a challenge to accurate FSK demodulation, especially at high data rates. Summary of the Invention

[0005] The technical advantages are generally achieved by embodiments of this disclosure, which describe glitches suppression for high bit-rate FSK demodulators.

[0006] The first aspect relates to a circuit for glitch suppression in a frequency shift keying (FSK) demodulator, the circuit being configured to receive a binary input signal sampled at a system frequency, the circuit including a first-stage averaging circuit having a programmable length; a second-stage averaging circuit coupled to the output of the first-stage averaging circuit; and a hysteresis comparator coupled to the output of the second-stage averaging circuit, wherein the circuit is configured to output a glitch-free clock signal.

[0007] The second aspect relates to a system for high bit rate frequency shift keying (FSK) demodulation, the system comprising: a glitch suppression circuit configured to receive an input signal from a zero-crossing comparator and generate a glitch-free output, the glitch suppression circuit including a first-stage averaging circuit having a programmable length, a second-stage averaging circuit coupled to the output of the first-stage averaging circuit, and a hysteresis comparator having programmable high and low thresholds; a conditioning circuit configured to perform blanking, filtering, or bypassing operations in response to an operating mode of the conditioning circuit; and an FSK demodulator counter circuit configured to receive the glitch-free output from the glitch suppression circuit.

[0008] The third aspect relates to a method for glitch suppression in a frequency shift keying (FSK) demodulator, the method comprising receiving a binary input signal sampled at a system frequency; processing the binary input signal through a first-stage averaging circuit having a programmable length; processing the output of the first-stage averaging circuit through a second-stage averaging circuit; applying a hysteresis comparator to the output of the second-stage averaging circuit; and outputting a glitch-free clock signal for use by a counter in the FSK demodulator.

[0009] The implementation can be carried out in hardware, software, or any combination thereof. Attached Figure Description

[0010] To more fully understand this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of the wireless power system of the embodiment;

[0012] Figure 2 This is a block diagram of the receiving device in an embodiment;

[0013] Figure 3 This is a block diagram of the circuit in the embodiment;

[0014] Figure 4 This is a block diagram of a glitch suppression circuit;

[0015] Figure 5 This is a flowchart of an embodiment of a method for glitch suppression in FSK demodulation;

[0016] Figure 6 This is a block diagram of the first moving average (MA) level of the embodiment;

[0017] Figure 7 This is a block diagram of the second moving average (MA) level in the embodiment;

[0018] Figure 8 This is a block diagram of the hysteresis comparator stage in the embodiment;

[0019] Figure 9 This is a block diagram of the first synchronous circuit; and

[0020] Figure 10 This is a block diagram of the second synchronization circuit. Detailed Implementation

[0021] This disclosure provides numerous applicable inventive concepts that can be implemented in a wide variety of specific contexts. Specific embodiments are merely illustrative of particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form other embodiments. Various embodiments are illustrated in the accompanying drawings, wherein the same components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0022] The variations or modifications described in one embodiment can also be applied to other embodiments. Furthermore, various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure as defined in the appended claims.

[0023] While the inventive aspects are primarily described in the context of wireless power transmission systems, particularly in the context of systems used in personal electronic products and embedded applications such as smartphones, tablets, headsets, earbuds, and smartwatches, it should be recognized that these inventive aspects can also be applied to other communication systems.

[0024] The glitch suppression techniques described herein can be particularly beneficial in compact electronic devices where efficient power delivery and reliable communication are advantageous. In particular, aspects of this disclosure can be similarly applied to any digital communication system employing high bit-rate FSK demodulation in the presence of signal glitches or noise, extending beyond wireless charging to potentially include other short-range wireless communication protocols used in consumer electronics and Internet of Things (IoT) devices.

[0025] Embodiments of this disclosure provide a system for glitch suppression in a frequency shift keying (FSK) demodulator, which can be particularly advantageous for high bit rate applications. The proposed system implements a normalized low-pass filter that can operate at high frequencies while maintaining programmability and efficiency. The filter includes a first-stage moving average circuit with a programmable length, a second-stage moving average circuit, and a hysteresis comparator with a programmable threshold.

[0026] In this embodiment, the first stage of the filter utilizes a recursive moving average technique, which can be implemented using an accumulator and a first-in-first-out (FIFO) buffer. This stage processes the binary input signal sampled at the system frequency, incrementing the accumulator for each sampled logic 1 and decrementing it when no logic 1 is present in the sliding window.

[0027] The second stage of the filter uses a moving average (which can be implemented as a three-point average) to further refine the signal. This stage helps to smooth out any residual glitches.

[0028] The final stage employs a hysteresis comparator with programmable high and low thresholds. These thresholds can be adjusted based on the relationship between the duty cycle of the input signal and the length of the moving average window, thus allowing for optimized glitch suppression across a variety of input conditions.

[0029] The output of this glitch suppression circuit provides a clean clock signal for the counter in the FSK demodulator. By removing glitches from the input signal, the system advantageously enables accurate frequency measurement, even at high bit rates and system clock frequencies.

[0030] This disclosure also includes techniques for setting filter parameters. The length of the first-stage moving average can be programmed based on the maximum glitch width to be suppressed. The hysteresis threshold can be set based on the peak value of the moving average output, which can depend on the relationship between the duty cycle of the input signal and the moving average length.

[0031] As used throughout this disclosure, the terms "averaging circuit" and "averaging" refer to any circuit or operation that processes a series of input samples to generate an output based on multiple samples, including but not limited to moving average implementations without division and true moving average implementations with division. The division operation in a true moving average implementation can be implemented by various means, including but not limited to using a bucket shifter, multiplying by a fixed-point number storing the reciprocal of the averaging length, or a dedicated division circuit. While specific embodiments may be described with reference to particular implementations (such as moving averages without division), the claims are not limited to such implementations unless explicitly stated otherwise.

[0032] The various embodiments disclosed offer advantages over traditional filtering methods, such as state-variable filters, particularly in high-bit-rate scenarios where the quality factor of analog filters becomes a limiting factor. The proposed system provides a digital solution that can be synthesized for high-frequency computation while maintaining flexibility through its programmable parameters. These and additional details are discussed further below.

[0033] Figure 1The illustration shows a block diagram of an embodiment of a wireless power system 100 (also referred to as a wireless charging system). The system includes a transmitting device 110 and a receiving device 120, which may (or may not) be arranged as shown. The transmitting device 110 generates and transmits a power signal 130 to the receiving device 120.

[0034] The transmitting device 110 may be a base station, such as a charging pad, that provides inductive power to the receiving device 120. The receiving device 120 may be, for example, a mobile device, tablet, cellular phone, wearable communication device (e.g., smartwatch), digital pen, wireless headset, toothbrush, sensor, Internet of Things (IoT) device, etc. The receiving device 120 is a consumer of inductive power.

[0035] Transmitting device 110 includes transmitter coil 112 (L TX The receiving device 120 includes a receiver coil 122 (L). RX Each coil, or winding, can be a loop or a magnetic antenna. The coil can have a physical core (e.g., a ferrite core) or an air core. The coil can be implemented as an antenna strip or using Litz wire. The resonant frequency of each coil is based on the shape and size of the loop wire or coil. In some embodiments, additional capacitance and inductance can be added to each coil to create a resonant structure at the desired resonant operating frequency.

[0036] In one embodiment, a power signal 130 is transmitted from the transmitting device 110 to the receiving device 120 using resonant inductive coupling between the transmitter coil 112 and the receiver coil 122. The receiving device 120 can use this power to charge a rechargeable battery or directly power its internal components.

[0037] In this embodiment, the wireless power system 100 employs Frequency Shift Keying (FSK) modulation for bidirectional communication between transmitting device 110 and receiving device 120. Transmitting device 110 can modulate the frequency of its power signal 130 to encode data, which is then demodulated by receiving device 120. Conversely, receiving device 120 can communicate back to transmitting device 110 using an ASK-modulated signal 140. This bidirectional ASK / FSK communication allows the exchange of information such as power delivery protocols, device identification, and charging status.

[0038] The receiving device 120 integrates glitch suppression circuitry within its FSK demodulator to ensure accurate demodulation and decoding of the power signal 130, even in the presence of noise and distortion that may be caused by the power transmission process. Glitch suppression technology enables reliable high-bit-rate communication, which is particularly beneficial for optimizing power transmission efficiency and supporting advanced features in compact electronic devices.

[0039] Figure 2 A block diagram of an embodiment of a receiving device 120 is shown. The receiving device 120 includes a receiver coil 122, a power charging circuit 200, a load 206, a comparator 208, a synchronization stage 210, and a demodulator 212, which may (or may not) be arranged as shown. The power charging circuit 200 includes a rectifier 202 and a regulator 204. The receiving device 120 may include... Figure 2 Additional components not shown include, for example, long-term storage devices (e.g., non-volatile memory), non-transitory computer-readable media, one or more antenna elements, drivers, demodulators, modulators, filter circuits, and impedance matching circuits.

[0040] Rectifier 202 converts the alternating current (AC) voltage at receiver coil 122 into a direct current (DC) voltage. It can be any type of rectifier, such as a low-impedance synchronous rectifier with full-wave or half-wave rectification, or an active rectifier. In this embodiment, rectifier 202 can be a bridge rectifier; however, other types of rectifiers are also conceivable.

[0041] Regulator 204 receives voltage (V) from rectifier 202 RECT Then adjust the voltage to maintain a constant output voltage (V) at load 206. OUT Regulator 204 can be any type of voltage regulator, such as a linear regulator (e.g., a low dropout (LDO) linear regulator). In some embodiments, rectifier 202 and regulator 204 can be part of a switch-mode power supply (SMPS) circuit.

[0042] As shown in the figure, load 206 is the primary beneficiary of the wireless power transmitted from transmitting device 110 to receiving device 120. Load 206 can be a charge storage device, such as a battery. For example, load 206 could be a cellular phone battery or a smartwatch. For example, transmitting device 110 could be a charging pad, and the smartwatch could be placed on the charging pad. The charging pad transmits wireless power to the smartwatch's battery without requiring a cable to connect the two devices.

[0043] Several interface standards have been developed to standardize wireless power transmission and related functions. One such interface standard is Qi, which is promoted by the Wireless Power Consortium (WPC). Qi and similar standardized protocols can be used to define the communication interface for controlling power transmission in wireless power system 100. For example, receiving device 120 can request changes (e.g., increase, decrease, pause, etc.) related to the wireless energy transmitted from transmitting device 110.

[0044] The mechanism of inductive power transfer can also be used for communication between transmitting device 110 and receiving device 120. For example, receiving device 120 can notify transmitting device 110 when the charging process is complete. This communication can be facilitated by a technique called backscatter modulation, as specified in the Qi standard for inductive wireless power transfer.

[0045] In practice, receiving device 120 can change its load impedance, for example, by changing the impedance of load 206. The change in impedance results in an observable change in the amplitude of the current or voltage in transmitter coil 112, thereby allowing information to be transmitted from receiving device 120 to transmitting device 110.

[0046] Comparator 208 is configured to compare the rectified voltage from rectifier 202 with a reference voltage (V). REF The comparison generates a digital signal representing the frequency variation of the incoming power signal, thus effectively converting the analog FSK-modulated signal into a digital form suitable for further processing.

[0047] Synchronization stage 210 is configured to synchronize the incoming signal from comparator 208 with the system clock (CLK). SYS Alignment is achieved to ensure proper timing of subsequent demodulation processes. Synchronization stage 210 may include circuitry for detecting and correcting the phase difference between the incoming signal and the system clock. This can be advantageous for accurate frequency measurement in counter-based FSK demodulation schemes.

[0048] Demodulator 212 includes glitches suppression circuitry 214, conditioning circuitry 216, and demodulation circuitry 218, which may (or may not) be arranged as shown. Demodulator 212 may include additional components, such as a filtering stage, not shown.

[0049] The glitch suppression circuit 214 can be arranged as a normalized low-pass filter. It is configured to filter out glitches from the binary input signal, thereby producing a clean output signal and overcoming the limitations of existing solutions.

[0050] In various embodiments, conditioning circuit 216 is configured to process the output from glitch suppression circuit 214, which receives a signal from an internal hysteresis comparator. Conditioning circuit 216 can provide multiple operating modes to further enhance signal quality. In one embodiment, conditioning circuit 216 can be bypassed, thereby effectively bypassing any additional processing. In another embodiment, conditioning circuit 216 functions as a blanking circuit or deglitcher, activated by the glitch suppression signal.

[0051] The blanking operation provided by the conditioning circuit 216 can implement a time masking mechanism based on the predictable glitch behavior pattern in the input signal received from the glitch suppression circuit 214.

[0052] For example, these patterns include a characteristic sequence at the beginning of the duty cycle, including a low-to-high transition, followed by a voltage drop before stabilizing at the duty cycle level. As another example, at the end of the duty cycle, a high-to-low transition is followed by a stray pulse.

[0053] In various embodiments, the blanking operation employs a counter-based scheme to address known patterns. Upon detecting a signal transition edge (either rising or falling), the conditioning circuit 216 updates its output and starts a counter. During the counting period, the output remains masked until the counter reaches a predetermined maximum value. This time masking effectively filters out predictable spurious signals following legitimate transitions. Upstream glitch suppression helps prevent false triggering of the blanking mechanism by filtering out random glitches before they reach the blanking stage.

[0054] In another embodiment, the conditioning circuit 216 can be configured as a bandpass filter with a low quality factor, thereby providing an alternative method of signal conditioning. This configuration flexibility allows for optimization based on specific signal characteristics and application requirements.

[0055] Demodulation circuit 218 implements a counter-based FSK demodulation technique. In this embodiment, it uses a synchronized signal from synchronization stage 210 and a system clock to measure the frequency of the incoming FSK signal. Demodulation circuit 218 can count the number of system clock cycles within each period of the FSK signal, thereby converting frequency changes into digital values ​​representing the transmitted data.

[0056] Figure 3 A block diagram of embodiment circuit 300 is shown, which can be implemented within demodulator 212. Circuit 300 includes a first counter 302, a filter 304, a second counter 306, a conditioning circuit 308, and a first-in-first-out (FIFO) logic circuit 310. These components may or may not be arranged as shown, and circuit 300 may include additional components not shown in the figure.

[0057] Circuit 300 is designed to be based on a known frequency signal (e.g., SYS). CLK ) Measuring unknown signals (e.g., FSK) IN The frequency of the FSK signal is determined by a counter. This scheme forms the basis of counter-based FSK demodulation, where the number of system clock ticks within one cycle of the incoming FSK signal determines the frequency of the FSK signal. This count is approximately equal to the ratio of the system clock frequency to the FSK signal frequency. ).

[0058] The first counter 302 receives the system clock signal (SYS). CLKAnd it increments its value at each rising edge of this known frequency signal. Concurrently, filter 304 receives the incoming FSK signal (FSK). IN It also removes potential glitches, thus effectively acting as a bandpass filter. A second counter 306, coupled to the output of the filter, increments its value at each rising edge of the filtered FSK signal.

[0059] The operation of these counters is synchronized, causing the first counter 302 to increment until the second counter 306 registers a single increment. This event triggers a reset of both counters, thus preparing them for the subsequent evaluation loop. This mechanism allows an unknown frequency signal to be converted into a digital sample, where the value in the first counter 302 corresponds to the frequency of the incoming FSK signal.

[0060] Typically, evaluation occurs over multiple carrier cycles to address the challenge of distinguishing between closely spaced FSK frequencies. This approach involves accumulating counts over several cycles (N increments of the second counter 306), thereby enhancing the system's ability to distinguish between small frequency differences, even in the presence of noise or signal distortion.

[0061] For example, consider a system with a system clock frequency of 48MHz and two FSK signal frequencies: 127.772kHz (FSK). IN1 ) and 126.984kHz (FSK) IN2 In this case, the first FSK signal (FSK) IN1 Each cycle will generate approximately 376±1 clock ticks, while the second FSK signal (FSK) IN2 Each cycle will generate approximately 378±1 clock beats.

[0062] As demonstrated in this example, the frequencies of the incoming FSK signals can be very close, resulting in small differences in the number of clock beats counted. In extreme cases, two signals could result in a count of 377 beats, making it impossible to distinguish between them within a single cycle. This small difference poses a challenge to reliable frequency change detection, especially in the presence of noise or signal distortion.

[0063] The conditioning circuit 308 further processes the digital samples by averaging, extracting baseline measurement results (mean), peak measurement results (peak value), and detecting the start of modulation. The FIFO logic circuit 310 stores the demodulated samples for subsequent processing or analysis.

[0064] This design allows for robust FSK demodulation, enabling accurate differentiation between closely spaced frequencies and effective operation even under the challenging signal conditions typical of wireless power transmission applications.

[0065] However, conventional FSK demodulation processes face challenges. The rectified voltage often contains glitches (i.e., unwanted short-duration pulses or transitions) that can occur near the boundaries of frequency transitions and are caused by various factors such as component selection, coil coupling, and load characteristics. These glitches can lead to errors in the frequency measurement process, potentially causing misinterpretations of the transmitted data.

[0066] Existing solutions for addressing glitches at the rectified voltage have various limitations. One approach involves using bandpass filters (BPFs), such as state-variable filters, in the input chain. While conventional methods are effective for reducing glitches, they encounter difficulties at high bit rates. The filter's quality factor cannot be set too high without the risk of cutting off the modulation itself, especially when dealing with bit rates around 120 kbps. Furthermore, synthesizing the circuitry for such filters at high frequencies can be challenging due to the long critical paths in their designs.

[0067] Another common solution uses a reset / set (RS) flip-flop to generate a clean frequency signal. However, this approach becomes problematic when the input signal contains glitches whose number changes over time. In such cases, the flip-flop output may produce large frequency steps, which could trigger a mismodulation detection interrupt, leading to communication errors.

[0068] As wireless power transmission systems evolve to support higher data rates and more complex communication protocols, these limitations become increasingly problematic, especially in compact electronic devices where signal integrity is often difficult to maintain.

[0069] Figure 4 A block diagram of a glitch suppression circuit 400 is shown, which can be implemented as a glitch suppression circuit 214 within the demodulator 212. The glitch suppression circuit 400 includes a first moving average (MA) stage 402, a second moving average (MA) stage 404, and a hysteresis comparator stage 406, which may (or may not) be arranged as shown. The glitch suppression circuit 400 may include additional components not shown in the figure. The glitch suppression circuit 400 is arranged as a normalized low-pass filter. It is configured to filter out glitches from the binary input signal, thereby producing a clean output signal and overcoming the limitations of existing solutions.

[0070] The circuit design integrates up to four adders in the critical path, resulting in minimal critical path length. Its efficient architecture allows the glitch suppression circuit 400 to operate effectively at high frequencies while maintaining low latency. It is particularly suitable for high-bit-rate FSK demodulation in wireless power transmission applications.

[0071] The first MA stage 402 implements a division-free recursive moving average. It consists of a FIFO buffer 412, a multiplexer 414, an adder circuit 416, and an accumulator 418, which may (or may not) be arranged as shown in the figure. The first MA stage 402 may include additional components not shown in the figure.

[0072] With system frequency (F SYS The sampled input binary signal is fed into FIFO buffer 412, which stores the last K input samples. Adder circuit 416 has three inputs: (1) the current input binary sample (NEW_IN_BIT), (2) the output of multiplexer 414 (MUX_OUT), and (3) the current value (CURR_ACC_VAL) stored in accumulator 418. Multiplexer 414 selects the bit (the bit pushed out of the window) in FIFO buffer 412 at the desired length (moving average length ≤ K).

[0073] Adder circuit 416 performs the following operation: NEW_ACC_VAL = CURR_ACC_VAL + NEW_IN_BIT - MUX_OUT. This operation essentially adds the new input bit (NEW_IN_BIT) to the sum (if the new input bit is "1"), subtracts the oldest bit in the window (if the oldest bit in the window is "1"), and otherwise maintains the current sum. The result is stored back in accumulator 418. This mechanism ensures that accumulator 418 always contains a count of "1"s in the current moving average length window, thus enabling moving sums of the window without requiring a complete recalculation at each step.

[0074] The output of accumulator 418 has a peak value that depends on the relationship between the duty cycle of the input binary signal and the moving average length of the first MA stage 402. If the moving average length is greater than the duty cycle length, then the peak value is equal to the duty cycle length. Conversely, if the moving average length is less than the duty cycle length, then the peak value is equal to the moving average length. This relationship sets the peak value to the minimum of the moving average length (MA_LENGTH) and the duty cycle length (DUTY_LENGTH) (i.e., PEAK = MIN(MA_LENGTH, DUTY_LENGTH)).

[0075] The size design of the FIFO buffer 412 determines the glitch suppression capability of the glitch suppression circuit 400. The maximum FIFO dimension (i.e., K points) is related to the maximum glitch width that can be effectively suppressed.

[0076] For example, at a system frequency of 288MHz (F SYSIn a system operating with a maximum FIFO dimension of 128 points, the glitch suppression circuit 400 can suppress glitch widths up to 0.22 microseconds (μs) (i.e., the maximum suppressable glitch width = ...). It is important to note that while this calculation provides a theoretical maximum value, the actual glitch width encountered in a real-world system may vary depending on external components and coupling conditions. Therefore, the size of the FIFO buffer 412 should be selected considering the specific application and the expected signal characteristics.

[0077] The second MA stage 404 is an n-point moving average (n is an integer), where in this embodiment, n equals three. This stage is designed to smooth the output from the first MA stage 402, thereby helping to prevent multiple threshold crossings that could lead to erroneous outputs. The second MA stage 404 includes a FIFO buffer 422, an adder circuit 424, and an accumulator circuit 426, which may (or may not) be arranged as shown. The second MA stage 404 may include additional components not shown.

[0078] The n-word FIFO buffer 422 stores n previous outputs from the first MA stage 402. In an embodiment, the FIFO buffer 422 is a 3-word FIFO buffer that stores three previous outputs from the first MA stage 402. This allows the second MA stage 404 to maintain a "memory" for recent values ​​used in moving average calculations.

[0079] The inputs to adder circuit 424 are the output from n-word FIFO buffer 422, the current output from first MA stage 402, and the current output from accumulator circuit 426. Adder circuit 424 efficiently updates the sum of the last three points by adding the new value and subtracting the oldest value. The output of adder circuit 424 is passed to accumulator circuit 426. The output of accumulator circuit 426 is fed back to adder circuit 424, thus forming a recursive structure. This feedback loop allows the circuit to maintain an operating average without explicitly storing all previous values.

[0080] Implementing an n-point moving average provides continuous smoothing of the signal, effectively reducing short-term fluctuations while maintaining responsiveness to changes in the real signal. The recursive nature of the circuit allows for efficient computation and seamless processing of continuous input streams.

[0081] In this embodiment, the 3-point moving average provides a good balance between additional smoothing and maintaining responsiveness to changes in the actual signal. It helps reduce the likelihood of false detections due to noise or short-duration glitches, while allowing the glitch suppression circuitry 400 to respond quickly to actual changes in the input signal.

[0082] The hysteresis comparator stage 406 includes a first multiplexer 432, a first comparator 434, a second comparator 436, and a second multiplexer 438, which may (or may not) be arranged as shown in the figure.

[0083] The outputs of the first MA stage 402 and the second MA stage 404 are fed as inputs to the first multiplexer 432. The first multiplexer 432 can forward one of these outputs to the first comparator 434 and the second comparator 436, thereby effectively enabling bypass or enable mode selection for the second MA stage 404. For example, when the first multiplexer forwards the output of the first MA stage 402, the second MA stage 404 can be bypassed. As another example, when the first multiplexer forwards the output of the second MA stage 404, the second MA stage 404 can be enabled. This multi-mode operation provides operational flexibility.

[0084] The output of the first multiplexer 432 is fed as input to the first comparator 434 and the second comparator 436. The first comparator 434 compares the output of the first multiplexer 432 with a first threshold (e.g., TH). HIGH The comparison is performed. In an embodiment, if the output of the first multiplexer 432 is greater than or equal to the first threshold, then the output of the first comparator 434 is logic "1"; otherwise, the output is logic "0".

[0085] In contrast, the second comparator 436 compares the output of the first multiplexer with a second threshold (e.g., TH). LOW The comparison is performed. In an embodiment, if the output of the first multiplexer 432 is less than the second threshold, then the output of the second comparator 436 is logic "1"; otherwise, the output is logic "0".

[0086] In the embodiment where the second MA stage 404 is not bypassed, the first and second thresholds are programmable and can be set based on peak values ​​determined in previous stages. Accordingly, the effective threshold for the first threshold can be calculated as follows: α can be set to a value between 0 and 0.5 (i.e., ), and PEAK equals the minimum of the moving average length (MA_LENGTH) and the duty cycle length (DUTY_LENGTH). In the embodiment, the effective threshold of the second threshold can be calculated as: .

[0087] In the embodiment of bypassing the second MA level, the effective threshold of the first threshold can be calculated as follows: And the effective threshold of the second threshold can be calculated as: .

[0088] This circuit also allows the confidence level to be adjusted based on the duty cycle of the input signal. For example, it is possible to use a lower confidence level (i.e., a higher α) with a higher duty cycle. A higher α value brings the first threshold and the second threshold closer together, making the glitch suppression circuit 400 more sensitive to changes in the input signal.

[0089] Furthermore, a higher duty cycle results in a wider signal pulse, which is more distinct from short glitches. Accordingly, the glitch suppression circuit 400 can more easily distinguish between legitimate signal changes and unwanted glitches. This allows the glitch suppression circuit 400 to be more responsive to actual signal changes when processing input signals with a higher proportion of on-time (i.e., a higher duty cycle), while maintaining effective glitch suppression. This represents a trade-off between sensitivity to actual signal changes and robustness against noise or glitches, which can be optimized based on the characteristics of the input signal.

[0090] The sampling clock frequency can also affect the glitch suppression capability of the glitch suppression circuit 400. A higher sampling clock frequency can provide higher resolution and more samples for glitch detection and suppression. Increasing the sampling frequency while maintaining the same duty cycle can generate additional samples for signal analysis, similar to the effect of increasing the duty cycle at a fixed sampling frequency. The relationship between sampling frequency and the number of samples can provide additional flexibility for optimizing glitch suppression performance.

[0091] The second multiplexer 438 determines the final output of the glitch suppression circuit 400. It has three input signals: a logic "1", a logic "0", and the previous output bit (BIT). The outputs of the first comparator 434 and the second comparator 436 provide selection signals for the second multiplexer 438. Accordingly, which input is selected as the output forwarding of the second multiplexer 438 is based on the outputs of the first comparator 434 and the second comparator 436.

[0092] When the input signal (from the first multiplexer 432) is greater than or equal to the first threshold (TH) HIGH When the input signal is less than the second threshold (TH), the second multiplexer 438 selects a logic "1" input. LOW When the threshold is reached, it selects a logic "0" input. In the region between these thresholds (called the hysteresis band), the second multiplexer 438 maintains the previous output state by selecting the bit output.

[0093] This operation creates a hysteresis effect, thus preventing rapid switching of the output due to small fluctuations in the input signal around a single threshold. The hysteresis behavior enhances noise immunity and stability when the input signal may contain residual glitches or noise from previous filtering stages.

[0094] Advantageously, the glitch suppression circuit 400 provides a robust method for cleaning binary input signals. Glitches can also be effectively removed using multi-stage moving averages and programmable hysteresis comparators while maintaining the integrity of the original signal, even in typical high-frequency applications in wireless power transmission systems.

[0095] Figure 5 A flowchart illustrating an embodiment of method 500 for glitch suppression in FSK demodulation is shown. Method 500 can be implemented in a wireless power transmission system (such as wireless power system 100). It should be noted that all steps outlined in the flowchart of method 500 are not required and may be optional. Furthermore, similar changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections can be contemplated.

[0096] At step 502, a binary input signal sampled at the system frequency is received. This input signal may contain glitches or unwanted short-duration pulses to be filtered out. These glitches can occur due to a variety of factors, such as component selection, coil coupling variations, load characteristics, and electromagnetic interference. For example, a sudden change in the load or coupling between the transmitter and receiver coils may cause voltage spikes or brief oscillations in the rectified signal. Furthermore, the switching nature of the power conversion circuit may also introduce high-frequency noise.

[0097] These glitches pose a challenge to accurate FSK demodulation, especially at high bit rates. If not removed, glitches can cause misfires in the demodulator's counters, leading to incorrect frequency measurements and data interpretation. This is particularly problematic in compact electronic devices where signal integrity is inherently difficult to maintain due to space constraints and the proximity of various components. Therefore, effective glitch removal ensures reliable communication and optimized performance in wireless power transmission systems. This enables accurate data exchange for power transmission protocols, device identification, and charging status updates.

[0098] At step 504, the signal is processed through a first moving average (MA) stage. This step involves storing the K most recent samples in a FIFO buffer, adding the new input bits to an accumulator, subtracting the oldest bit from the accumulator, and outputting the current accumulator value. The length K of this moving average can be programmable, allowing adjustment based on the maximum glitch width to be suppressed.

[0099] Step 506 represents an optional second MA level. If enabled, this step processes the output from the first MA level using an n-point (e.g., 3-point) moving average. The three most recent outputs from the first MA level are stored, their average is calculated, and the output is a smoothed signal. This additional averaging helps prevent multiple threshold crossings from causing erroneous outputs.

[0100] At step 508, the signal passes through a hysteresis comparator. This step involves comparing the signal with a high threshold and a low threshold. The output is determined based on these comparisons: if the signal is greater than or equal to the high threshold, the output is set to logic "1"; if the signal is less than the low threshold, the output is set to logic "0"; if the signal is between the two thresholds, the previous output state is maintained. After processing through the moving average stage and the hysteresis comparator, the output signal is free of short-duration glitches from the original input. A glitch-free clock signal can then be fed to the FSK demodulator counter.

[0101] A clean signal allows for accurate frequency measurements in counter-based FSK demodulation, even at high bit rates and system clock frequencies. Method 500 provides a robust glitch suppression scheme that utilizes a programmable moving average stage and hysteresis comparator to effectively remove unwanted signal artifacts while maintaining the integrity of the FSK-modulated data.

[0102] Figure 6 The diagram illustrates a block diagram of the first moving average (MA) level 600 in this embodiment, which is related to... Figure 4 The first MA stage 402 described herein shares functional similarities. The first MA stage 600 implements recursive shifting and averaging. It includes a flip-flop and multiplexer chain 602, a first multiplexer 604, a first adder circuit 606, a second multiplexer 607, an optional register 608, a second adder circuit 610, a third multiplexer 611, and an output register 612, which may (or may not) be arranged as shown. This implementation maintains the functionality described for the first MA stage 402 while optimizing timing through strategic placement of pipelined registers.

[0103] Input data signal (FSK) IN The data is fed into a chain 602 of flip-flops and multiplexers that forms the shift register. Each flip-flop stores one bit, and the chain extends along K flip-flops, effectively implementing the functionality of the FIFO buffer—K corresponding to the buffer size. The length of this chain is configurable. This configuration allows for flexible adjustment of the moving average window based on the maximum glitch width to be suppressed. Each multiplexer within the chain 602 includes a selection input coupled to an enable signal (DATA_VLD_IN). The enable signal, when asserted, enables the start / shift operation within the FIFO buffer.

[0104] A first multiplexer 604 with K inputs receives outputs from flip-flops and all flip-flops in the multiplexer chain 602. The first multiplexer 604 selects an appropriate delayed version of the input signal based on a programmed moving average (MA) length value, thereby effectively selecting the oldest bit within the moving average window. This operation is related to... Figure 4 It is similar to the multiplexer 414 in the example, but it achieves additional flexibility through programmable length selection.

[0105] The first MA stage 600 includes two adder stages. The first adder circuit 606 and the second adder circuit 610 perform recursive shift and averaging operations, adding the new input bits while subtracting the oldest bit from the current sum. An optional register 608 is arranged between the adders to break the critical path and facilitate easier synthesis at higher operating frequencies.

[0106] The output of output register 612 provides the moving average result to the subsequent processing stage. A second multiplexer 607 and a third multiplexer 611, which can be removed in some embodiments, may be employed to enable or disable the capture process by setting an enable signal, as discussed above.

[0107] Figure 7 The diagram illustrates a block diagram of the second moving average (MA) level 700 of this embodiment, which is related to... Figure 4 The second MA stage 404 described herein shares functional similarities. The second MA stage 700 implements a three-point moving average and includes a series of registers and multiplexers 702, 703, 704, 706, 707, 708, 710, 710, 711, 712, and 714, which may (or may not) be arranged as shown. This implementation maintains the core functionality of the second MA stage 404 while integrating additional features for improved timing performance and operational flexibility. The strategic placement of pipelined registers and the inclusion of bypass functionality make this design particularly suitable for high-frequency applications in FSK demodulation systems.

[0108] The input signal from the first MA stage 402 passes through a series of registers and a multiplexer 702 storing consecutive samples for three-point averaging. In this embodiment, the series of registers and multiplexer 702 includes two registers. The output of these samples is fed into a first adder circuit 706. The select input of the multiplexer in the series of registers and multiplexer 702 receives a synchronization signal (DATA_VLD_OUT_Q) to synchronize the operation of the first MA stage 402 with the operation of the second MA stage 404—in Figure 9Further details will be provided later.

[0109] The first adder circuit 706 and the second adder circuit 710 perform summation on three consecutive points, thereby realizing the three-point moving average calculation described in the second MA level 404.

[0110] The first optional register 704 and the second optional register 708 (located between the adder stages) break the critical path. This pipelined technique facilitates easier synthesis at higher operating frequencies while maintaining the functional requirements of the moving average operation. Adding optional registers provides the flexibility to meet timing constraints without affecting the basic averaging operation.

[0111] The output stage includes a bypass multiplexer 714 controlled by a bypass signal. The bypass multiplexer 714 allows the circuit to forward the three-point averaged output or perform a full bypass averaging operation. This bypass capability provides operational flexibility, allowing the system to adapt to different signal conditions or test requirements. The final output is provided at the output register 712.

[0112] As discussed above, a first multiplexer 703, a second multiplexer 707, and a third multiplexer 711, which can be removed in some embodiments, can be used to enable or disable the capture process by setting the synchronization signal (DATA_VLD1_OUT).

[0113] Figure 8 The diagram illustrates a block diagram of an embodiment of a hysteresis comparator stage 800, which is related to... Figure 4 The hysteresis comparator stage 406 described herein shares functional similarity. The hysteresis comparator stage 800 includes a first comparator 802, a second comparator 804, a first multiplexer 806, a second multiplexer 807, and a flip-flop 808, which may (or may not) be arranged as shown. This configuration maintains consistency with the functionality described in the hysteresis comparator stage 406.

[0114] First comparator 802 and second comparator 804 receive the input signal (MA_OUTPUT2) from the second MA stage 404 and compare it with the high threshold and low threshold, respectively. First comparator 802 compares the input signal with the first threshold (TH). HIGH The input signal is compared with a second threshold. In an embodiment, if the input signal is greater than or equal to a first threshold, the output of the first comparator 802 is logic "1"; otherwise, the output is logic "0". The second comparator 804 compares the input signal with a second threshold. LOW The input signal is compared with the second threshold. In the embodiment, if the input signal is less than the second threshold, the output of the second comparator 804 is logic "1"; otherwise, the output is logic "0".

[0115] The first multiplexer 806 determines the intermediate output based on the comparison result. It has three input signals: logic "1", logic "0", and the previous output (OUTPUT). The outputs of the first comparator 802 and the second comparator 804 provide selection signals for the first multiplexer 806. When the input signal is greater than or equal to a first threshold, the first multiplexer 806 selects the logic "1" input. When the input signal is less than a second threshold, it selects the logic "0" input. In the region between these thresholds (called the hysteresis band), the first multiplexer 806 maintains the previous output state by selecting the previous output.

[0116] Flip-flop 808 is coupled to the output of the first multiplexer 806 and clocked by the system clock signal. Flip-flop 808 synchronizes its output with the system clock, thus providing a clean, glitch-free output signal. This synchronization ensures proper timing of subsequent processing stages in the FSK demodulator.

[0117] In some embodiments, the second multiplexer 807 can be removed to enable or disable the capture process by properly setting the enable signal (DATA_VLD2_OUT).

[0118] Although Figure 8 Not shown, but it is understood that a bypass multiplexer (similar to) can be added at the input stage. Figure 4 The first multiplexer 432 in the middle provides the flexibility to bypass or enable the second MA level.

[0119] Figure 9 A block diagram of a first synchronization circuit 900 is shown, which provides synchronization between a first moving average stage and a second moving average stage of a glitch suppression circuit 400. The first synchronization circuit 900 includes a multiplexer 902, an adder circuit 904, a register 906, a comparator 908, a first AND gate 910, a second AND gate 912, an inverter 914, and an output flip-flop 916, which may (or may not) be arranged as shown.

[0120] The first synchronization circuit 900 includes a feedback loop in which adder circuit 904 receives two inputs: a constant value 'd1' and a feedback signal. The output of the adder is fed to a multiplexer 902 (a 2-to-1 multiplexer) that selects between the feedback and the adder output based on a moving average length control signal. The output of the multiplexer is registered by register 906, which returns the feedback signal to adder circuit 904.

[0121] Comparator 908 compares the moving average length value with the output of register 906. The output of comparator 908 is fed directly to second AND gate 912 and via inverter 914 to first AND gate 910. First AND gate 910 performs a logical AND operation between the inverted comparator output and the enable signal (DATA_VLD_IN). Second AND gate 912 performs a logical AND operation between the direct comparator output and the enable signal.

[0122] The output of the AND gate forms a synchronized output (DATA_VLD1_OUT). This output is further registered by output flip-flop 916 to generate a clean synchronization signal (DATA_VLD1_OUT_Q). The synchronized signal (DATA_VLD1_OUT_Q) is used as a synchronization signal to coordinate the operation between the first moving average stage and the second moving average stage.

[0123] Figure 10 A block diagram of a second synchronization circuit 1000 is shown, which provides synchronization between the second moving average stage and the hysteresis comparator stage of the glitch suppression circuit 400. The second synchronization circuit 1000 includes a multiplexer 1002, an adder circuit 1004, a register 1006, a comparator 1008, a first AND gate 1010, a second AND gate 1012, and an inverter 1014, which may (or may not) be arranged as shown.

[0124] The second synchronization circuit 1000 includes a feedback loop in which adder circuit 1004 receives two inputs: a constant value 'd1' and a feedback signal. The output of the adder is fed to a multiplexer 1002 (a 2-to-1 multiplexer) that selects between the feedback and the adder output based on a moving average length control signal. The output of the multiplexer is registered by register 1006, which returns the feedback signal to adder circuit 1004.

[0125] Comparator 1008 compares the output of register 1006 with value 2 (2). The output of comparator 1008 is fed directly into second AND gate 1012 and through inverter 1014 into first AND gate 1010. First AND gate 1010 performs a logical AND operation between the inverted comparator output and the enable signal (DATA_VLD1_OUT_Q) from first synchronization circuit 900. Second AND gate 1012 performs a logical AND operation between the direct comparator output and the enable signal (DATA_VLD1_OUT_Q).

[0126] The output of the AND gate forms a synchronized output (DATA_VLD2_OUT), which serves as a synchronization signal to coordinate the operation between the second moving average stage and the hysteresis comparator stage of the glitch suppression circuit.

[0127] Synchronization mechanisms are particularly advantageous for maintaining proper data flow and preventing timing misalignment between processing stages. A dual AND gate structure with comparator feedback provides precise control over synchronization timing based on a programmed moving average length value. By providing synchronized control signals, this circuit ensures that data is properly captured and processed as it moves from one stage to the next, thus contributing to the overall reliability of the glitch suppression process.

[0128] The first aspect relates to a circuit for glitch suppression in a frequency shift keying (FSK) demodulator, the circuit being configured to receive a binary input signal sampled at a system frequency, the circuit including a first-stage averaging circuit having a programmable length; a second-stage averaging circuit coupled to the output of the first-stage averaging circuit; and a hysteresis comparator coupled to the output of the second-stage averaging circuit, wherein the circuit is configured to output a glitch-free clock signal.

[0129] In a first implementation of the circuit, according to the first aspect itself, the first-stage averaging circuit includes: a first-in-first-out (FIFO) buffer configured to store input samples; a multiplexer configured to output the oldest bit from the FIFO buffer; an accumulator configured to maintain the sum of logic one in the input samples; and an adder circuit configured to update the accumulator by adding a new input bit and subtracting the output of the multiplexer, a divider circuit configured to divide the output of the accumulator by a programmable length, or a combination thereof.

[0130] In a second implementation of the circuit, depending on the first aspect itself or any of the aforementioned implementations of the first aspect, the second-level averaging circuit is a three-point moving average circuit.

[0131] In a third implementation of the circuit, depending on the first aspect itself or any of the aforementioned implementations of the first aspect, the hysteresis comparator includes a programmable high threshold and a programmable low threshold.

[0132] In a fourth implementation of the circuit, depending on the first aspect itself or any of the aforementioned implementations of the first aspect, the programmable high threshold and the programmable low threshold are set based on the peak value of the output of the first-stage averaging circuit.

[0133] In a fifth implementation of the circuit, depending on the first aspect itself or any of the aforementioned implementations of the first aspect, the circuit further includes a multiplexer configured to bypass the second-stage averaging circuit.

[0134] In a sixth implementation of the circuit, the programmable length is determined based on the maximum glitch width to be suppressed, depending on the first aspect itself or any of the aforementioned implementations of the first aspect.

[0135] The second aspect relates to a system for high bit rate frequency shift keying (FSK) demodulation, the system comprising: a glitch suppression circuit configured to receive an input signal from a zero-crossing comparator and generate a glitch-free output, the glitch suppression circuit including a first-stage averaging circuit having a programmable length, a second-stage averaging circuit coupled to the output of the first-stage averaging circuit, and a hysteresis comparator having programmable high and low thresholds; a conditioning circuit configured to perform blanking, filtering, or bypassing operations in response to an operating mode of the conditioning circuit; and an FSK demodulator counter circuit configured to receive the glitch-free output from the glitch suppression circuit.

[0136] In a first implementation of the system, according to the second aspect itself, the first-stage averaging circuit includes: a first-in-first-out (FIFO) buffer configured to store input samples; a multiplexer configured to output a selection bit from the FIFO buffer; an accumulator configured to maintain a sum of logic one in the input samples; and an adder circuit configured to update the accumulator by adding a new input bit and subtracting the output of the multiplexer, a divider circuit configured to divide the output of the accumulator by a programmable length, or a combination thereof.

[0137] In a second implementation of the system, depending on the second aspect itself or any of the aforementioned implementations of the second aspect, the glitch suppression circuit includes a second stage comprising a moving average circuit, wherein the second stage includes a three-point averaging circuit.

[0138] In a third implementation of the system, depending on the second aspect itself or any of the aforementioned implementations of the second aspect, the programmable high threshold and low threshold are set based on the peak value of the output of the first-stage averaging circuit.

[0139] In a fourth implementation of the system, according to the second aspect itself or any of the foregoing implementations of the second aspect, the glitch suppression circuit includes a second stage comprising a moving average circuit, and the system further includes a multiplexer configured to bypass the second stage averaging circuit.

[0140] In a fifth implementation of the system, the programmable length is determined based on the maximum glitch width to be suppressed, depending on the second aspect itself or any of the aforementioned implementations of the second aspect.

[0141] In a sixth implementation of the system, depending on the second aspect itself or any of the aforementioned implementations of the second aspect, the FSK demodulator counter circuit is configured to measure the frequency of the glitch-free output using a known system clock frequency.

[0142] The third aspect relates to a method for glitch suppression in a frequency shift keying (FSK) demodulator, the method comprising receiving a binary input signal sampled at a system frequency; processing the binary input signal through a first-stage averaging circuit having a programmable length; processing the output of the first-stage averaging circuit through a second-stage averaging circuit; applying a hysteresis comparator to the output of the second-stage averaging circuit; and outputting a glitch-free clock signal for use by a counter in the FSK demodulator.

[0143] In a first implementation of the method, according to the third aspect itself, processing the binary input signal by the first-stage averaging circuit includes: storing the input samples in a first-in-first-out (FIFO) buffer; using an accumulator to maintain the sum of logic one in the input samples; and updating the accumulator by adding a new input bit and subtracting the oldest bit from the FIFO buffer, dividing the output of the accumulator by a programmable length, or a combination thereof.

[0144] In a second implementation of the method, the second-level averaging circuit is a three-point averaging circuit, depending on the third aspect itself or any of the aforementioned implementations of the third aspect.

[0145] In a third implementation of the method, depending on the third aspect itself or any of the aforementioned implementations of the third aspect, the application of the hysteresis comparator includes using programmable high and low thresholds set based on the peak value of the output of the first-stage averaging circuit.

[0146] In a fourth implementation of the method, depending on the third aspect itself or any of the aforementioned implementations of the third aspect, the method further includes selectively bypassing the second-stage averaging circuit using a multiplexer.

[0147] In a fifth implementation of the method, depending on the third aspect itself or any of the aforementioned implementations of the third aspect, the method further includes determining a programmable length based on the maximum glitch width to be suppressed.

[0148] While this description has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure as defined in the appended claims. In the various figures, the same elements are designated by the same reference numerals. Furthermore, the scope of this disclosure is not limited to the specific embodiments described herein, as those skilled in the art will readily recognize from this disclosure that existing or future processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods, or steps within their scope.

[0149] Accordingly, the specification and drawings are to be regarded merely as a description of this disclosure as defined in the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A circuit for glitch suppression in a frequency shift keying (FSK) demodulator, the circuit being configured to receive a binary input signal sampled at a system frequency, the circuit comprising: The first-stage averaging circuit has a programmable length. The second-stage averaging circuit is coupled to the output of the first-stage averaging circuit. as well as A hysteresis comparator, coupled to the output of the second-stage averaging circuit, The circuit described therein is configured to output a glitch-free clock signal.

2. The circuit of claim 1, wherein the first-stage averaging circuit comprises: A first-in-first-out (FIFO) buffer, which is configured to store input samples; A multiplexer configured to output the oldest bit from a FIFO buffer; An accumulator configured to maintain a sum of logic one in the input samples; as well as An adder circuit configured to update the accumulator by adding a new input bit and subtracting the output of the multiplexer, a divider circuit configured to divide the output of the accumulator by a programmable length, or a combination thereof.

3. The circuit as described in claim 1, wherein the second-stage averaging circuit is a three-point moving average circuit.

4. The circuit of claim 1, wherein the hysteresis comparator includes a programmable high threshold and a programmable low threshold.

5. The circuit of claim 4, wherein the programmable high threshold and the programmable low threshold are set based on the peak value of the output of the first-stage averaging circuit.

6. The circuit of claim 1 further includes a multiplexer configured to bypass the second-stage averaging circuit.

7. The circuit of claim 1, wherein the programmable length is determined based on the maximum glitch width to be suppressed.

8. A system for high bit rate frequency shift keying (FSK) demodulation, the system comprising: A glitch suppression circuit, configured to receive an input signal from a zero-crossing comparator and generate a glitch-free output, the glitch suppression circuit comprising: The first-stage averaging circuit has a programmable length. The second-stage averaging circuit is coupled to the output of the first-stage averaging circuit, and... A hysteresis comparator having programmable high and low thresholds; A conditioning circuit, configured to perform blanking, filtering, or bypassing operations in response to an operating mode of the conditioning circuit; and The FSK demodulator circuit is configured to receive a glitch-free output from a glitch suppression circuit.

9. The system of claim 8, wherein the first-stage averaging circuit comprises: A first-in-first-out (FIFO) buffer, which is configured to store input samples; A multiplexer configured to output a selection bit from a FIFO buffer; An accumulator configured to maintain a sum of logic one in the input samples; as well as An adder circuit configured to update the accumulator by adding a new input bit and subtracting the output of the multiplexer, a divider circuit configured to divide the output of the accumulator by a programmable length, or a combination thereof.

10. The system of claim 8, wherein the second-stage averaging circuit comprises a three-point averaging circuit.

11. The system of claim 8, wherein the programmable high threshold and low threshold are set based on the peak value of the output of the first-stage averaging circuit.

12. The system of claim 8 further includes a multiplexer configured to bypass the second-stage averaging circuit.

13. The system of claim 8, wherein the programmable length is determined based on the maximum burr width to be suppressed.

14. The system of claim 8, wherein the FSK demodulator circuit is configured to measure the frequency of the glitch-free output using a known system clock frequency.

15. A method for glitch suppression in a frequency shift keying (FSK) demodulator, the method comprising: Receives binary input signals sampled at the system frequency; The binary input signal is processed by a first-stage averaging circuit with a programmable length. The output of the first-stage averaging circuit is processed by the second-stage averaging circuit. Apply the hysteresis comparator to the output of the second-stage averaging circuit; as well as Output a glitch-free clock signal for use by the counter in the FSK demodulator.

16. The method of claim 15, wherein processing the binary input signal through the first-stage averaging circuit comprises: The input samples are stored in a first-in-first-out (FIFO) buffer; Use an accumulator to maintain the sum of logic 1s in the input samples; as well as The accumulator can be updated by adding a new input bit and subtracting the oldest bit from the FIFO buffer, by dividing the accumulator output by a programmable length, or a combination thereof.

17. The method of claim 15, wherein the second-stage averaging circuit is a three-point averaging circuit.

18. The method of claim 15, wherein applying the hysteresis comparator includes using programmable high and low thresholds set based on the peak value of the output of the first-stage averaging circuit.

19. The method of claim 15, further comprising using a multiplexer to selectively bypass the second-stage averaging circuit.

20. The method of claim 15, further comprising determining a programmable length based on the maximum burr width to be suppressed.

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