Downlink power adjustment method and device

Abstract

This application provides a downlink power adjustment method and apparatus, which can be applied in the field of communications. The method includes: receiving a frequency-domain complex signal in real time in response to an open distributed unit transmitting such a signal; wherein the frequency-domain complex signal includes a frequency-domain baseband signal, and the frequency-domain baseband signal includes a secondary synchronization signal; learning the digital power of the secondary synchronization signal using a counting analysis strategy based on the frequency-domain baseband signal to obtain a learned power; calculating a downlink power scaling factor based on the learned power and the target power of the secondary synchronization signal; and adjusting the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes either the frequency-domain complex signal or a time-domain complex signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, and more particularly to a downlink power adjustment method and device. BACKGROUND

[0002] In the 5G communication scenario, the current open radio access network (O-RAN) downlink signal processing flow is as follows: the open distributed unit (O-DU) sends the baseband frequency domain data to the open radio unit (O-RU) through the open fronthaul interface, the O-RU converts the time domain signal through the fast inverse Fourier transform, and then optimizes the peak-to-average power ratio characteristics of the orthogonal frequency division multiplexing through peak clipping and digital pre-distortion, and then converts the signal to analog through digital-to-analog conversion, up-converts the frequency, amplifies and filters the radio frequency, and then transmits the signal through the antenna. The cell coverage is determined by the fixed transmission power of the broadcast signals such as synchronization signal block (SSB) and system information block (SIB), and the peak clipping and digital pre-distortion modules require stable time domain average power input.

[0003] However, under the O-RAN open architecture, different manufacturers' O-DU and O-RU have different signal processing methods for the baseband, which makes the digital power of the frequency domain signal output by the O-DU of different manufacturers inconsistent, and the power scaling strategies of the O-RU for converting the frequency domain to digital signal are different, resulting in significant differences in the time domain signal power input to the peak clipping / digital pre-distortion module during integration, so that the subsequent modules cannot work in the best state, and the radio frequency signal output to the antenna is not the required power, resulting in substandard radio frequency output power, which requires long-term power debugging, even code modification, low compatibility and integration efficiency, and significantly increased integration cost. SUMMARY

[0004] In view of the above problems, the present application provides a downlink power adjustment method and device to improve compatibility.

[0005] According to a first aspect of this application, a downlink power adjustment method is provided, comprising: applying to an open radio frequency unit, the method comprising: receiving a frequency domain complex signal in real time in response to the open distributed unit transmitting a frequency domain complex signal; wherein the frequency domain complex signal includes a frequency domain baseband signal, the frequency domain baseband signal including a secondary synchronization signal; learning the digital power of the secondary synchronization signal using a counting analysis strategy based on the frequency domain baseband signal to obtain a learned power; calculating a downlink power scaling factor based on the learned power and the target power of the secondary synchronization signal; and adjusting the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes the frequency domain complex signal or a time domain complex signal.

[0006] According to an embodiment of this application, the step of learning the digital power of the auxiliary synchronization signal based on the frequency domain baseband signal using a counting analysis strategy to obtain the learned power includes: initializing a real number counter, an all-zero counter, and an auxiliary synchronization sample register; extracting in-phase quadrature samples of the frequency domain baseband signal in real time; continuously detecting the unique real part and all-zero continuity of the in-phase quadrature samples to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register; and reading the auxiliary synchronization sample data of the auxiliary synchronization sample register, calculating the digital power of the auxiliary synchronization signal based on the auxiliary synchronization sample data, and obtaining the learned power.

[0007] According to an embodiment of this application, the step of continuously detecting the unique existence of the real part and the continuity of all zeros of the in-phase quadrature samples to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register includes: continuously detecting the unique existence of the real part of the in-phase quadrature samples to update the real number counter; in response to the updated real number counter satisfying a first preset value, storing the in-phase quadrature sample corresponding to satisfying the first preset value into the auxiliary synchronization sample register, and continuously detecting the continuity of all zeros of the in-phase quadrature samples to update the all-zero counter; and in response to the updated all-zero counter satisfying a second preset value, determining whether the next in-phase quadrature sample corresponding to satisfying the second preset value is zero; if yes, resetting the real number counter, the all-zero counter, and the auxiliary synchronization sample register; if no, storing the in-phase quadrature samples in the auxiliary synchronization sample register as the auxiliary synchronization sample data.

[0008] According to an embodiment of this application, continuously detecting the uniqueness of the real part of the in-phase quadrature sample value to update the real number counter includes: detecting whether the current in-phase quadrature sample value satisfies the condition of having real parts and no virtual parts; if it satisfies the condition, the real number counter increments by 1; and if it does not satisfy the condition, the real number counter is reset.

[0009] According to an embodiment of this application, the step of continuously detecting the all-zero continuity of the in-phase quadrature sample values ​​to update the all-zero counter includes: detecting whether the current in-phase quadrature sample value is an all-zero sample value; if yes, then the all-zero counter increments by 1; and if no, then the all-zero counter is reset.

[0010] According to an embodiment of this application, calculating the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal includes: calculating the power difference between the learning power and the target power of the auxiliary synchronization signal; and performing a linear conversion on the power difference to obtain the downlink power scaling factor.

[0011] According to an embodiment of this application, adjusting the power of the downlink digital baseband signal based on the downlink power scaling factor includes: multiplying the downlink power scaling factor as a scaling factor with the downlink digital baseband signal to obtain the power-adjusted downlink digital baseband signal.

[0012] According to an embodiment of this application, the method further includes: performing power conversion processing on the power-adjusted downlink digital baseband signal to obtain a digital signal; performing radio frequency conversion processing on the digital signal to obtain an analog signal; performing radio frequency amplification and filtering processing on the analog signal to obtain an electrical signal; and transmitting the electrical signal to an antenna so that the antenna receives and transmits the electrical signal.

[0013] According to an embodiment of this application, the power-adjusted downlink digital baseband signal includes a power-adjusted frequency-domain complex signal or a power-adjusted time-domain complex signal; the step of performing power conversion processing on the power-adjusted downlink digital baseband signal to obtain a digital signal includes: performing a fast inverse Fourier transform on the power-adjusted frequency-domain complex signal to obtain a time-domain baseband signal, and performing radio frequency power linearization processing on the time-domain baseband signal to obtain the digital signal; or performing radio frequency power linearization processing on the power-adjusted time-domain complex signal to obtain the digital signal.

[0014] A second aspect of this application provides a downlink power adjustment device, comprising: a signal receiving module, configured to receive a frequency-domain complex signal in real time in response to an open distributed unit transmitting such a signal; wherein the frequency-domain complex signal includes a frequency-domain baseband signal, and the frequency-domain baseband signal includes a secondary synchronization signal; a counting analysis module, configured to learn the digital power of the secondary synchronization signal based on the frequency-domain baseband signal using a counting analysis strategy to obtain a learned power; a scaling factor calculation module, configured to calculate a downlink power scaling factor based on the learned power and the target power of the secondary synchronization signal; and a power adjustment module, configured to adjust the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes the frequency-domain complex signal or a time-domain complex signal.

[0015] In the embodiments of this application, the Open RF Unit (O-RU) receives the frequency domain complex signal and uses the auxiliary synchronization signal as a power reference. Through a counting analysis strategy, it learns the digital power of the auxiliary synchronization signal in real time and calculates a precise power scaling factor based on the target power. This uniformly adjusts the downlink digital baseband signal power, eliminating power differences between Open Distributed Units (O-DUs) and O-RUs from different manufacturers. This ensures that subsequent transmission modules, such as peak clipping and digital predistortion modules, receive stable time-domain power input, allowing them to operate at their optimal state. Simultaneously, it ensures that the antenna transmits RF signal power meets specifications, significantly reducing power debugging time and code modification costs during integration, and improving O-RAN compatibility and integration efficiency. Attached Figure Description

[0016] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 This schematically illustrates a traditional downlink signal processing flowchart;

[0018] Figure 2 This illustration schematically depicts an application scenario of the downlink power adjustment method and apparatus according to embodiments of this application;

[0019] Figure 3 A flowchart illustrating a downlink power adjustment method according to an embodiment of this application is shown schematically.

[0020] Figure 4 A schematic diagram of a synchronization block diagram of a downlink power adjustment method according to an embodiment of this application is shown;

[0021] Figure 5 An O-RU connection diagram of a downlink power adjustment method according to an embodiment of this application is schematically shown;

[0022] Figure 6Another connection diagram of the O-RU for the downlink power adjustment method according to an embodiment of this application is schematically shown;

[0023] Figure 7 A flowchart illustrating the counting analysis strategy of the downlink power adjustment method according to an embodiment of this application is shown.

[0024] Figure 8 A schematic diagram illustrating the structure of a downlink power adjustment device according to an embodiment of this application is shown.

[0025] Figure 9 A block diagram schematically illustrates an electronic device suitable for implementing a downlink power adjustment method according to an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0029] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0030] Figure 1 A schematic diagram of a traditional downlink signal processing flowchart is shown, such as Figure 1As shown, in a typical O-RAN downlink signal processing flow, the O-DU transmits the downlink baseband frequency domain data to the O-RU via an open fronthaul interface. The O-RU then transforms the frequency domain data to the time domain using an Inverse Fast Fourier Transform (iFFT). Due to the peak-to-average power ratio (PAPR) characteristic of Orthogonal Frequency Division Multiplexing (OFDM), to fully utilize the power amplifier's capabilities, peak clipping (CFR) and digital pre-distortion (DPD) are typically performed on the time-domain digital signal in the baseband. Then, an analog signal is generated via a digital-to-analog converter, and the baseband signal is up-converted to the corresponding carrier frequency RF signal. Finally, after amplification and filtering at the RF front-end, the RF signal is transmitted through the antenna via a feeder.

[0031] The coverage area of ​​a cell depends on the transmit power of downlink broadcast signals (SSB and SIB, etc.), so the system requires these signals to be transmitted at a fixed power. For a specific type of equipment, the gain provided by the RF front-end is fixed. At the same time, in order for the CFR, DPD, and digital-to-analog converter to operate at their optimal levels, the average power of the input time-domain signal is generally required to be relatively stable.

[0032] The original design intention of O-RAN was to open the fronthaul interface so that O-DU and O-RU from different manufacturers could be freely combined. However, since the signal processing methods of the baseband are not completely consistent among different manufacturers, the main manifestations are: (1) the digital average power of the baseband frequency domain signal output from the O-DU is inconsistent, and (2) the scaling of power is inconsistent during the conversion of the frequency domain signal to the digital signal of the O-RU.

[0033] These two inconsistencies will result in a significant difference in the average power of the time-domain signal output to the CFR / DPD during initial integration. This will cause subsequent modules to not operate optimally, and the RF signal output to the antenna will not be at the required power. Therefore, the following problems often occur when integrating O-DUs and O-RUs from different manufacturers:

[0034] (1) It takes a long time to align and debug the power of O-DU and O-RU to obtain the final output power to the antenna as required.

[0035] (2) If the O-DU and O-RU do not support configurable downlink power scaling, one of them may even need to modify its code to finally obtain the required power. This adds a lot of extra testing and debugging time to the integration.

[0036] This application provides a downlink power adjustment method applied to an open-source radio unit (O-RU). The method includes: receiving a frequency-domain complex signal in real time in response to the O-RU transmitting a frequency-domain complex signal; wherein the frequency-domain complex signal includes a frequency-domain baseband signal, and the frequency-domain baseband signal includes a secondary synchronization signal; learning the digital power of the secondary synchronization signal based on the frequency-domain baseband signal using a counting analysis strategy to obtain a learned power; calculating a downlink power scaling factor based on the learned power and the target power of the secondary synchronization signal; and adjusting the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes a frequency-domain complex signal or a time-domain complex signal. In the embodiments of this application, the O-RU receives the frequency-domain complex signal and uses the secondary synchronization signal as a power reference. It learns the digital power of the secondary synchronization signal in real time using a counting analysis strategy, and calculates a precise power scaling factor based on the target power to uniformly adjust the power of the downlink digital baseband signal. This eliminates the power differences between O-DUs and O-RUs from different manufacturers, ensuring that subsequent transmission modules such as peak clipping and digital predistortion receive stable time-domain power input, allowing them to operate in optimal condition. At the same time, it ensures that the power of the antenna's transmitted radio frequency signal meets the standard, greatly reducing the power debugging time and code modification cost during integration, and improving O-RAN compatibility and integration efficiency.

[0037] It is worth noting that the PSS (Primary Synchronization Signal) and SSS (Secondary Synchronization Signal) of the 4G mobile communication technology standard LTE (Long Term Evolution) are ZC sequences, which are complex signals. In contrast, the PSS in the Synchronization Signal Block (SSB) of the 5G mobile communication air interface technology standard 5G NR (5th Generation New Radio) is a frequency-domain m-sequence, and the SSS in the SSB is a frequency-domain Gold sequence. The PSS / SSS sequence designs of 5G NR and LTE differ, and the SSS power intelligent learning method of this application is only adapted to the sequence characteristics of 5G and cannot be directly used in LTE systems. Therefore, the application scope of the downlink power adjustment method of this application is limited to 5G scenarios.

[0038] Figure 2 The diagram illustrates an application scenario of the downlink power adjustment method and apparatus according to embodiments of this application.

[0039] like Figure 2 As shown, application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0040] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0041] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0042] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0043] It should be noted that the downlink power adjustment method provided in this application embodiment can generally be executed by an open radio frequency unit in network 104. Accordingly, the downlink power adjustment device provided in this application embodiment can generally be disposed in an open radio frequency unit in network 104.

[0044] It should be understood that Figure 2 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0045] The following will be based on Figure 2 The described scene, through Figures 3-7 The downlink power adjustment method according to the embodiments of this application will be described in detail.

[0046] Figure 3 A flowchart illustrating a downlink power adjustment method according to an embodiment of this application is shown schematically.

[0047] like Figure 3 As shown, the downlink power adjustment method of this embodiment includes operations S310 to S340, and the downlink power adjustment method is applied to an open radio frequency unit.

[0048] In operation S310, in response to the open distributed unit sending a frequency domain complex signal, the frequency domain complex signal is received in real time; wherein, the frequency domain complex signal includes a frequency domain baseband signal, and the frequency domain baseband signal includes an auxiliary synchronization signal.

[0049] When the Open Distributed Unit (O-DU) sends out a frequency domain complex signal, the Open Radio Unit (O-RU) receiver starts receiving the frequency domain complex signal in real time.

[0050] Frequency domain complex signals are the frequency domain transmission carriers sent by the O-DU, including various downlink frequency IQ data (the frequency domain digital representation obtained by orthogonal sampling of downlink signals, which is the core carrier of digital baseband signals). Downlink frequency IQ data are frequency domain complex signals output by the O-DU and mapped on different subcarriers (In-phase is the in-phase component I, Quadrature is the quadrature component Q), which is the core data transmitted by the fronthaul interface.

[0051] The secondary synchronization signal is the core physical signal for downlink synchronization. Together with the primary synchronization signal (PSS), it carries information related to the physical cell identifier and is used by the terminal to complete frame synchronization and cell search.

[0052] When operating the S320, the digital power of the auxiliary synchronization signal is learned by using a counting analysis strategy based on the frequency domain baseband signal, and the learned power is obtained.

[0053] In the 3GPP protocol, the power of the secondary synchronization signal is kept consistent across all synchronization blocks (SSBs), and the power of other downlink physical channels is based on the power of the secondary synchronization signal. The power offset of other physical channels relative to the secondary synchronization signal is sent down from higher layers. Therefore, it is possible to synchronize the power of other baseband signals by learning the power of the secondary synchronization signal.

[0054] According to the 3GPP protocol, PSS and SSS are modulated using BPSK, while other channels and signals are modulated using at least QPSK or higher order modulation. All manufacturers implement BPSK as IQ data with only real parts and no imaginary parts. This allows for easy identification of PSS and SSS signals by checking if the imaginary part is zero. Figure 4A schematic diagram illustrating a synchronization block diagram of a downlink power adjustment method according to an embodiment of this application is shown. Figure 4 As shown, in the 3GPP-defined SSB block, there are 57 REs (Real Estate Names) with all zeros to the right of the PSS (Primary Synchronization Signal) and 9 REs with all zeros to the right of the SSS (Secondary Synchronization Signal). Horizontally, there are Orthogonal Frequency Division Multiplexing (OFDM) symbols, and vertically, there are 240 subcarriers. The PSS (Primary Synchronization Signal) is located at subcarrier indices 56-182 (127 subcarriers) of OFDM symbol 0. The SSS (Secondary Synchronization Signal) is located at subcarrier indices 56-182 (127 subcarriers) of OFDM symbol 2. The PBCH (Physical Broadcast Channel) is distributed across the remaining subcarriers of the four OFDM symbols (including part of symbol 2 and the entire area of ​​symbol 1 / 3). The zero-marked area is a protection / idle resource within the SSB, used to avoid signal interference. Based on these characteristics, the SSS can be identified using a counting analysis strategy. The core idea of ​​this strategy is to identify 127 consecutive IQ data points with only real parts and no imaginary parts, where the right side of these 127 data points contains only 9 IQ data points with all zeros.

[0055] When operating S330, the downlink power scaling factor is calculated based on the learning power and the target power of the auxiliary synchronization signal.

[0056] The downlink power scaling factor is calculated based on the learned auxiliary synchronization signal power (learned power) and the auxiliary synchronization signal power required by the system (target power).

[0057] According to an embodiment of this application, in operation S330, calculating the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal includes: calculating the power difference between the learning power and the target power of the auxiliary synchronization signal; and performing a linear conversion on the power difference to obtain the downlink power scaling factor.

[0058] Based on target power P t and learning power P r Calculate the downlink power scaling factor A p The formula is as follows:

[0059] A p = 10 (Pt-Pr) / 20 ;

[0060] In operation S340, the power of the downlink digital baseband signal is adjusted based on the downlink power scaling factor; wherein, the downlink digital baseband signal includes a frequency domain complex signal or a time domain complex signal.

[0061] The power of all downlink digital baseband signals can be adjusted proportionally according to the downlink power scaling factor. Downlink digital baseband signals can be either frequency-domain complex signals or time-domain complex signals. Time-domain complex signals refer to the time-domain complex signals (time-domain IQ signals) after iFFT conversion of the O-RU, which serve as the direct input signals for the CFR and DPD modules.

[0062] According to an embodiment of this application, the operation S340, which adjusts the power of the downlink digital baseband signal based on the downlink power scaling factor, includes: multiplying the downlink power scaling factor as a scaling factor with the downlink digital baseband signal to obtain the downlink digital baseband signal with adjusted power.

[0063] The downlink IQ data is adjusted based on the downlink power scaling factor, assuming the downlink power adjustment is from signal S. n The process takes effect immediately upon finding the SSS sequence and updating the power scaling factor. The IQ data output to CFR / DPD starting from Sn is then... .

[0064] In the embodiments of this application, the Open RF Unit (O-RU) receives the frequency domain complex signal and uses the auxiliary synchronization signal as a power reference. Through a counting analysis strategy, it learns the digital power of the auxiliary synchronization signal in real time and calculates a precise power scaling factor based on the target power. This uniformly adjusts the downlink digital baseband signal power, eliminating power differences between Open Distributed Units (O-DUs) and O-RUs from different manufacturers. This ensures that subsequent transmission modules, such as peak clipping and digital predistortion modules, receive stable time-domain power input, allowing them to operate at their optimal state. Simultaneously, it ensures that the antenna transmits RF signal power meets specifications, significantly reducing power debugging time and code modification costs during integration, and improving O-RAN compatibility and integration efficiency.

[0065] According to an embodiment of this application, after obtaining the downlink digital baseband signal with adjusted power, the downlink power adjustment method further includes: performing power conversion processing on the downlink digital baseband signal with adjusted power to obtain a digital signal; performing radio frequency conversion processing on the digital signal to obtain an analog signal; performing radio frequency amplification and filtering processing on the analog signal to obtain an electrical signal; and transmitting the electrical signal to an antenna so that the antenna receives and transmits the electrical signal.

[0066] After adjusting the downlink digital baseband signal, further conversion and transmission are required. First, power conversion is performed using inverse fast Fourier transform and / or RF power linearization techniques to obtain a digital signal, achieving iFFT, CFR, and DPD. Second, RF conversion (such as digital-to-analog conversion and up-conversion) is used to obtain an analog signal from the digital signal. Third, the analog signal is transmitted to the RF front-end, where RF amplification and filtering convert the analog signal into an electrical signal. RF amplification is achieved through a built-in power amplifier in the RF front-end, linearly amplifying the weak analog signal to increase its strength and meet the antenna's power threshold requirements, avoiding signal attenuation and distortion during transmission. Filtering uses a bandpass filter to remove clutter, harmonics, and interference noise from the signal, retaining the effective signal within the target frequency band and ensuring the purity and frequency accuracy of the transmitted electrical signal. Finally, the amplified and filtered RF analog electrical signal is sent to the antenna, which converts the signal into an electromagnetic wave, radiating it into space according to the specified frequency band, completing the entire transmission process.

[0067] According to embodiments of this application, the power-adjusted downlink digital baseband signal includes a power-adjusted frequency-domain complex signal or a power-adjusted time-domain complex signal; the power conversion processing of the power-adjusted downlink digital baseband signal to obtain a digital signal includes: performing a fast inverse Fourier transform on the power-adjusted frequency-domain complex signal to obtain a time-domain baseband signal, and performing radio frequency power linearization processing on the time-domain baseband signal to obtain a digital signal; or performing radio frequency power linearization processing on the power-adjusted time-domain complex signal to obtain a digital signal.

[0068] In some embodiments, Figure 5 The diagram schematically illustrates the O-RU connection of the downlink power adjustment method according to an embodiment of this application. Figure 6 This schematically illustrates another connection diagram of the O-RU for the downlink power adjustment method according to an embodiment of this application. Power adjustment can be performed in the frequency domain (before iFFT) or in the time domain (after iFFT), as shown below. Figure 5 As shown, a smart power adjustment module (to implement power adjustment) is inserted before iFFT to complete the intelligent adjustment of downlink digital power, as follows. Figure 6As shown, depending on the different implementations of iFFT in the O-RU, the power adjustment process can also be placed after the time domain is completed. This is because iFFT is a linear transformation, so placing linear power scaling before or after iFFT is essentially the same. In practice, whether the power adjustment process is placed before or after depends on the system implementation, especially the design of iFFT. iFFT transforms the frequency domain data to the time domain. CFR and DPD processing are performed on the time domain signal in the baseband. An analog signal is then generated by a digital-to-analog converter, and the baseband signal is up-converted to the corresponding carrier frequency. Finally, after amplification and filtering by the RF front-end, the electrical signal is transmitted through the antenna via a feeder.

[0069] like Figure 5 , 6 As shown, an intelligent power adjustment module is added to the O-RU to achieve downlink power adjustment. The SSS power intelligent learning module intelligently learns the digital power of the SSS from the frequency domain baseband signal; the automatic power scaling factor calculation module calculates the automatic power scaling factor based on the learned SSS digital power and the desired SSS power; and the digital power adjustment module adjusts the power of the digital baseband signal proportionally according to the calculated automatic power scaling factor. This digital power adjustment module can be placed in the frequency domain (before iFFT) or the time domain (after iFFT). By intelligently learning the power of the auxiliary synchronization signal within the O-RU and automatically scaling all downlink baseband signals based on this power, the problem of digital power mismatch between O-DUs and O-RDUs from different manufacturers is intelligently solved, significantly shortening the integration time.

[0070] For example, the frequency domain baseband signals transmitted from the O-DU to the O-RU are S0, S1, S2, ..., S n S n+1 ... During initialization, the power scaling factor is 1 (no power adjustment), and the set SSS desired power (target power) is P. t Since the initial power scaling factor is 1, no power adjustment is performed on the baseband signal at this time, and the IQ data output to CFR / DPD is still S0, S1, S2, ....

[0071] The parallel SSS power intelligent learning module obtains the SSS power (learning power) of the frequency domain data sent from the O-DU from the input baseband IQ data, which is P. r dBFS, and P r Send to the automatic power scaling factor calculation module.

[0072] The automatic power scaling factor calculation module calculates power through P t and P r Calculate scaling factor A p=10 (Pt-Pr) / 20 And set the new amplitude scaling factor register to A. p .

[0073] The digital power adjustment module adjusts the downlink IQ data according to the amplitude scaling factor, from S n Start adjusting, from S n The initial IQ data output to CFR / DPD is .

[0074] The IQ data output by the intelligent power adjustment module to the CFR / DPD is With an initial power of P r dBFS, after intelligent power adjustment takes effect (sample point S) n (Start) The output power is the desired P t dBFS, based on intelligent learning, automatically completes power matching and outputs the desired digital power to the subsequent modules of O-RU.

[0075] It is worth noting that S0-S n Before SSS power learning, the power of the IQ sample values ​​before this point does not meet the requirements, but it has no impact on the entire system. This is because, according to the 3GPP definition, the period of the SS / PBCH block can be configured as 5ms, 10ms, 20ms, 40ms, 80ms, or 160ms. The longest time interval between the next SSS occurrence is 160ms. Considering that this only occurs during system initialization, the impact of 160ms is negligible.

[0076] According to an embodiment of this application, in operation S320, which learns the digital power of the auxiliary synchronization signal based on the frequency domain baseband signal using a counting analysis strategy to obtain the learned power, the process includes: initializing a real number counter, an all-zero counter, and an auxiliary synchronization sample register; extracting in-phase quadrature samples of the frequency domain baseband signal in real time; continuously detecting the unique real part and all-zero continuity of the in-phase quadrature samples to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register; and reading the auxiliary synchronization sample data from the auxiliary synchronization sample register, calculating the digital power of the auxiliary synchronization signal based on the auxiliary synchronization sample data, and obtaining the learned power.

[0077] The counting analysis strategy identifies the SSS sequence (secondary synchronization signal) by detecting the characteristics of IQ sample values ​​(in-phase quadrature sample values) (real part stored independently, continuous all zeros). A real number counter, an all-zero counter, and a secondary synchronization sample register are introduced to perform counting discrimination and secondary synchronization sample storage.

[0078] During initial reset, the real number counter, the all-zero counter, and the SSS sample register are all reset to 0 to prepare for detection. Detecting continuous IQ samples stored only in the real part can identify PSS / SSS candidates, and detecting continuous all-zero samples can further distinguish between PSS and SSS. During detection, the values ​​of the real number counter, the all-zero counter, and the auxiliary synchronization sample register are updated in real time. Finally, the stored IQ samples are read from the SSS sample register, and the learned SSS power P is calculated. r For example, to calculate the instantaneous digital power P by storing only a single IQ sample. r for:

[0079] P r =I 2

[0080] Where I represents the real part of the IQ sample value, and the imaginary part Q of the IQ sample value is 0.

[0081] According to an embodiment of this application, continuously detecting the unique real part of the in-phase quadrature sample values ​​and the continuity of all zeros to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register includes: continuously detecting the unique real part of the in-phase quadrature sample values ​​to update the real number counter; in response to the updated real number counter satisfying a first preset value, storing the in-phase quadrature sample value corresponding to the first preset value into the auxiliary synchronization sample register, and continuously detecting the continuity of all zeros of the in-phase quadrature sample values ​​to update the all-zero counter; and in response to the updated all-zero counter satisfying a second preset value, determining whether the next in-phase quadrature sample value corresponding to the second preset value is zero; if yes, resetting the real number counter, the all-zero counter, and the auxiliary synchronization sample register; if no, storing the in-phase quadrature sample values ​​in the auxiliary synchronization sample register as auxiliary synchronization sample data.

[0082] Real part uniqueness detection: Continuously detect the next IQ sample value. If it is not "only real part, no imaginary part", reset the real number counter to 0 and start detection again; if it is "only real part, no imaginary part", increment the real number counter by 1, and check if the counter has reached 127. If the counter has not reached the first preset value (e.g., 127), continue detecting the next IQ sample value; if the counter reaches the first preset value, it means that a candidate PSS / SSS has been found. Store the current IQ sample value in the SSS sample value register and proceed to the next step to distinguish between PSS and SSS, and perform all-zero continuity detection.

[0083] Detecting all-zero continuity: Check if the next IQ sample is all zeros. If it is not all zeros, return to the initial reset stage and start again. If it is all zeros, increment the all-zero counter by 1 and check if it has reached the second preset value (e.g., 9). If the all-zero counter has not reached 9, continue to detect the next all-zero sample. If the all-zero counter reaches 9, continue to check the next IQ sample. If the IQ sample is all zeros, return to the initial reset stage. If the IQ sample is not all zeros, it is confirmed to be an SSS sequence, and proceed to the power calculation stage.

[0084] According to an embodiment of this application, continuously detecting the real-part exclusivity of in-phase quadrature samples to update the real counter includes: detecting whether the current in-phase quadrature samples satisfy the condition of having real parts and no virtual parts; if satisfied, incrementing the real counter by 1; and if not satisfied, resetting the real counter.

[0085] The condition of "real part only, no imaginary part" means that the IQ sample value has only a real part and no imaginary part. The next IQ sample value is continuously tested. If it is not "real part only, no imaginary part" (the condition of "real part only, no imaginary part" is not met), the real number counter is reset to 0. If it is "real part only, no imaginary part" (the condition of "real part only, no imaginary part" is met), the real number counter is incremented by 1.

[0086] According to an embodiment of this application, continuously detecting the all-zero continuity of in-phase quadrature samples to update the all-zero counter includes: detecting whether the current in-phase quadrature sample is an all-zero sample; if yes, incrementing the all-zero counter by 1; and if no, resetting the all-zero counter.

[0087] After satisfying the real part of the IQ sample is uniquely stored, continue to check the continuity of all zeros. Check if the next IQ sample is all zeros. If it is not all zeros, return to the initial reset stage, reset the all-zero counter, and start again; if it is all zeros, the all-zero counter is incremented by 1.

[0088] For example, Figure 7 A flowchart illustrating the counting analysis strategy of the downlink power adjustment method according to an embodiment of this application is shown, as follows: Figure 7 As shown, the process of intelligently learning the digital power of an SSS sequence through a counting analysis strategy is as follows:

[0089] (1) System initialization, reset the real number counter, the all-zero counter, and the SSS sample register (auxiliary synchronous sample register).

[0090] (2) Check whether the next IQ sample (in-phase orthogonal sample) has only real part and no imaginary part.

[0091] (3) If the IQ sample value does not have only real part and no imaginary part, then reset the real number counter = 0 and return to step (2).

[0092] (4) If the IQ sample value has only a real part and no imaginary part, then the real number counter is incremented by 1, and then the real number counter is checked to see if it is equal to 127.

[0093] (5) If the real number counter is not equal to 127, return to step two to continue detecting the next IQ sample value.

[0094] (6) If the real counter equals 127, it means that PSS or SSS has been detected. Save the current IQ sample value to the SSS sample register for power estimation. The next step is to further distinguish between PSS and SSS by detecting the nine REs with all zeros on the right.

[0095] (7) Check whether the next IQ sample is a sample of all zeros.

[0096] (8) If the IQ sample value is not 0, return to the initial state and return to step (1).

[0097] (9) If the IQ sample value is 0, then increment the all-zero counter by 1, and then check if the all-zero counter is equal to 9.

[0098] (10) If the all-zero counter is not equal to 9, then return to step (7).

[0099] (11) If the all-zero counter is equal to 9, then further check whether the next IQ sample is an all-zero sample.

[0100] (12) If the IQ sample value is 0, return to the initial state and return to step (1).

[0101] (13) If the IQ sample value is not 0, the SSS sequence detection is successful. Read the IQ data from the SSS sample register and calculate the SSS power P. r .

[0102] Based on the aforementioned downlink power adjustment method, this application also provides a downlink power adjustment device applied to an open RF unit, the device executing the aforementioned downlink power adjustment method. The following will be combined with... Figure 8 The device is described in detail.

[0103] Figure 8 A schematic block diagram of a downlink power adjustment device according to an embodiment of this application is shown.

[0104] like Figure 8 As shown, the downlink power adjustment device 800 in this embodiment includes a signal receiving module 810, a counting analysis module 820, a scaling factor calculation module 830, and a power adjustment module 840.

[0105] The signal receiving module 810 is used to receive frequency-domain complex signals in real time in response to the open distributed unit transmitting such signals; wherein the frequency-domain complex signals include frequency-domain baseband signals, and the frequency-domain baseband signals include auxiliary synchronization signals. In one embodiment, the signal receiving module 810 can be used to perform the operation S210 described above, which will not be repeated here.

[0106] The counting analysis module 820 is used to learn the digital power of the auxiliary synchronization signal based on the frequency domain baseband signal using a counting analysis strategy, thereby obtaining the learned power. In one embodiment, the counting analysis module 820 can be used to perform the operation S220 described above, which will not be repeated here.

[0107] The scaling factor calculation module 830 is used to calculate the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal. In one embodiment, the scaling factor calculation module 830 can be used to perform the operation S230 described above, which will not be repeated here.

[0108] The power adjustment module 840 is used to adjust the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes a frequency domain complex signal or a time domain complex signal. In one embodiment, the power adjustment module 840 can be used to perform the operation S240 described above, which will not be repeated here.

[0109] According to embodiments of this application, any plurality of modules among the signal receiving module 810, the counting analysis module 820, the scaling factor calculation module 830, and the power adjustment module 840 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this application, at least one of the signal receiving module 810, the counting analysis module 820, the scaling factor calculation module 830, and the power adjustment module 840 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the signal receiving module 810, the counting analysis module 820, the scaling factor calculation module 830, and the power adjustment module 840 may be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0110] Figure 9A block diagram schematically illustrates an electronic device suitable for implementing a downlink power adjustment method according to an embodiment of this application.

[0111] like Figure 9 As shown, an electronic device 900 according to an embodiment of this application includes a processor 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage portion 908 into a random access memory (RAM) 903. The processor 901 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 901 may also include onboard memory for caching purposes. The processor 901 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this application.

[0112] RAM 903 stores various programs and data required for the operation of electronic device 900. Processor 901, ROM 902, and RAM 903 are interconnected via bus 904. Processor 901 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 902 and / or RAM 903. It should be noted that programs may also be stored in one or more memories other than ROM 902 and RAM 903. Processor 901 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in one or more memories.

[0113] According to embodiments of this application, the electronic device 900 may further include an input / output (I / O) interface 905, which is also connected to a bus 904. The electronic device 900 may also include one or more of the following components connected to the input / output (I / O) interface 905: an input section 906 including a keyboard, mouse, etc.; an output section 907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN card, modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the input / output (I / O) interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 910 as needed so that computer programs read from it can be installed into the storage section 908 as needed.

[0114] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0115] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include ROM 902 and / or RAM 903 and / or one or more memories other than ROM 902 and RAM 903 described above.

[0116] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the downlink power adjustment method provided in the embodiments of this application.

[0117] When the computer program is executed by the processor 901, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0118] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 909, and / or installed from a removable medium 911. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0119] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 909, and / or installed from the removable medium 911. When the computer program is executed by the processor 901, it performs the functions defined in the system of this application embodiment. According to the embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0120] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0122] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. A method for adjusting downlink power, characterized in that, Applied to open-type radio frequency units, the method includes: In response to the open distributed unit sending a frequency domain complex signal, the frequency domain complex signal is received in real time; wherein, the frequency domain complex signal includes a frequency domain baseband signal, and the frequency domain baseband signal includes an auxiliary synchronization signal; Based on the frequency domain baseband signal, the digital power of the auxiliary synchronization signal is learned using a counting analysis strategy to obtain the learned power. Calculate the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal; and The power of the downlink digital baseband signal is adjusted based on the downlink power scaling factor; wherein the downlink digital baseband signal includes the frequency domain complex signal or the time domain complex signal.

2. The method according to claim 1, characterized in that, The step of learning the digital power of the auxiliary synchronization signal based on the frequency domain baseband signal using a counting analysis strategy to obtain the learned power includes: Initialize the real number counter, the all-zero counter, and the auxiliary synchronization sample register; Real-time extraction of in-phase quadrature samples of the frequency domain baseband signal; The real part of the in-phase quadrature samples is continuously monitored for independence and all-zero continuity to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register; and Read the auxiliary synchronization sample data from the auxiliary synchronization sample register, calculate the digital power of the auxiliary synchronization signal based on the auxiliary synchronization sample data, and obtain the learning power.

3. The method according to claim 2, characterized in that, The continuous detection of the real part uniqueness and all-zero continuity of the in-phase quadrature samples to update the real number counter, the all-zero counter, and the auxiliary synchronization sample register includes: The real part of the in-phase orthogonal sample is continuously detected to update the real number counter; In response to the updated real counter satisfying a first preset value, the in-phase quadrature sample value corresponding to the first preset value is stored in the auxiliary synchronization sample register, and the continuity of all zeros of the in-phase quadrature sample value is continuously detected to update the all-zero counter; and In response to the updated all-zero counter satisfying the second preset value, it is determined whether the next in-phase quadrature sample corresponding to satisfying the second preset value is zero. If yes, the real number counter, the all-zero counter, and the auxiliary synchronization sample register are reset; if no, the in-phase quadrature sample in the auxiliary synchronization sample register is stored as the auxiliary synchronization sample data.

4. The method according to claim 3, characterized in that, The step of continuously detecting the uniqueness of the real part of the in-phase quadrature samples to update the real number counter includes: Check whether the current in-phase orthogonal sample values ​​satisfy the condition that there are real samples and no imaginary samples; If satisfied, the real number counter increments by 1; and If the condition is not met, then the real number counter is reset.

5. The method according to claim 3, characterized in that, The step of continuously detecting the all-zero continuity of the in-phase quadrature samples to update the all-zero counter includes: Detect whether the current in-phase orthogonal sample values ​​are all zero samples; If so, the all-zero counter increments by 1; and If not, then reset the all-zero counter.

6. The method according to claim 1, characterized in that, The step of calculating the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal includes: Calculate the power difference between the learning power and the target power of the auxiliary synchronization signal; and The downlink power scaling factor is obtained by performing a linear conversion on the power difference.

7. The method according to claim 1, characterized in that, Adjusting the power of the downlink digital baseband signal based on the downlink power scaling factor includes: The downlink power scaling factor is used as a scaling factor and multiplied by the downlink digital baseband signal to obtain the power-adjusted downlink digital baseband signal.

8. The method according to claim 7, characterized in that, The method further includes: The power-adjusted downlink digital baseband signal is subjected to power conversion processing to obtain a digital signal; The digital signal is subjected to radio frequency conversion processing to obtain an analog signal; The analog signal is amplified and filtered by radio frequency to obtain an electrical signal; and The electrical signal is transmitted to the antenna so that the antenna receives and transmits the electrical signal.

9. The method according to claim 8, characterized in that, The power-adjusted downlink digital baseband signal includes a power-adjusted frequency-domain complex signal or a power-adjusted time-domain complex signal; the step of performing power conversion processing on the power-adjusted downlink digital baseband signal to obtain a digital signal includes: The frequency-domain complex signal with adjusted power is subjected to a fast inverse Fourier transform to obtain a time-domain baseband signal, and the time-domain baseband signal is then subjected to radio frequency power linearization processing to obtain the digital signal; or The power-adjusted time-domain complex signal is subjected to radio frequency power linearization processing to obtain the digital signal.

10. A downlink power adjustment device, characterized in that, The device includes: A signal receiving module is used to receive a frequency-domain complex signal in real time in response to the open distributed unit sending the frequency-domain complex signal; wherein the frequency-domain complex signal includes a frequency-domain baseband signal, and the frequency-domain baseband signal includes an auxiliary synchronization signal; The counting analysis module is used to learn the digital power of the auxiliary synchronization signal based on the frequency domain baseband signal using a counting analysis strategy, and obtain the learned power. The scaling factor calculation module is used to calculate the downlink power scaling factor based on the learning power and the target power of the auxiliary synchronization signal; and A power adjustment module is used to adjust the power of the downlink digital baseband signal based on the downlink power scaling factor; wherein the downlink digital baseband signal includes the frequency domain complex signal or the time domain complex signal.

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