Chip packaging structure, circuit boards and servers

Abstract

This application provides a chip packaging structure, a circuit board, and a server. The chip packaging structure includes: a carrier substrate and at least two interposer substrate modules packaged on the carrier substrate. Each interposer substrate module includes M computing cores, N high-bandwidth storage units, and an interposer substrate, where N is an integer multiple of M. The first interposer substrate of the first interposer substrate module and the second interposer substrate module are both fixedly disposed on the carrier substrate. Each computing core is connected to at least two high-bandwidth storage units through each interposer substrate. The interposer substrate modules are bidirectionally interconnected through traces on the carrier substrate to improve the yield and processing efficiency of the chip corresponding to the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a chip packaging structure, board, and server. Background Technology

[0002] As a typical parallel processor in the computer field, the general-purpose graphics processing unit (GPU) occupies a core position in large-scale parallel computing scenarios such as large model training and inference.

[0003] To improve chip data processing efficiency, the industry generally adopts 2.5D packaging solutions, stacking high-bandwidth memory (HBM) near the GPU chip. However, existing 2.5D packaging solutions have significant limitations. On the one hand, next-generation memory such as HBM3 has extremely high parallel port trace density, requiring silicon substrates for packaging. The size of silicon substrates is limited by physical characteristics, making it difficult to integrate many HBM chips around the GPU chip, directly restricting the potential for bandwidth improvement. On the other hand, stacking excessive HBM chips around a single GPU chip significantly increases packaging complexity, leading to a decrease in chip yield. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a chip packaging structure, board, and server to solve the practical problem of the limitations of chip packaging in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a chip packaging structure, including: a carrier substrate and at least two interposer substrate modules packaged on the carrier substrate, wherein each interposer substrate module includes M computing cores, N high-bandwidth storage units and an interposer substrate, wherein N is an integer multiple of M; The first interposer substrate of the first interposer substrate module and the second interposer substrate of the second interposer substrate module are both fixedly disposed on the carrier substrate. Each of the aforementioned computing cores is connected to at least two high-bandwidth storage units via each intermediary substrate; The intermediate layer substrate modules are bidirectionally interconnected through carrier substrate traces.

[0006] As an optional implementation, the interposer substrate module includes a silicon substrate packaging module, the interposer substrate includes a silicon substrate, the high bandwidth storage unit includes HBM particles, and a first computing core, a first HBM particle and a second HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle respectively through silicon substrate traces. Alternatively, a first computing core, a second computing core, a first HBM particle, a second HBM particle, a third HBM particle, and a fourth HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle respectively through silicon substrate traces. The second computing core is connected to the third HBM particle and the fourth HBM particle respectively through silicon substrate traces. The first computing core and the second core are connected to each other through silicon substrate traces. The silicon substrate packaging modules are bidirectionally interconnected through the traces on the carrier substrate.

[0007] As an optional implementation, the number of silicon substrate packaging modules is two, the carrier substrate includes an ABF substrate, and the chip corresponding to the chip packaging structure is a dual-core chip.

[0008] As an optional implementation, the number of silicon substrate packaging modules is 6, each silicon substrate packaging module is provided with 2 computing cores, the carrier substrate includes a glass substrate, and the chip corresponding to the chip packaging structure is a 12-core chip.

[0009] Secondly, embodiments of this application provide a board, the board including at least one chip packaging structure as described in the first aspect.

[0010] As an optional implementation, the board includes multiple chip package structures, which are interconnected in a ring, and the computing cores in each chip package structure are interconnected in a ring.

[0011] As an optional implementation, the board is a single-chip dual-core board, and the chip package structure of the board includes a dual-core chip. The dual-core chip includes an ABF substrate and two silicon substrate package modules packaged on the ABF substrate. Each silicon substrate package module is packaged with a computing core and two HBM particles. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The silicon substrate packaging modules are interconnected bidirectionally via ABF substrate traces and ring-shaped via PCB traces.

[0012] As an optional implementation, the board is a single-chip 12-core board. The chip package structure of the board includes a 12-core chip. The 12-core chip includes a glass substrate and six silicon substrate package modules packaged on the glass substrate. Each silicon substrate package module has two computing cores and four HBM particles packaged on it. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The computing cores of each adjacent silicon substrate package module are bidirectionally interconnected through glass substrate traces, and the computing cores within each silicon substrate package module are bidirectionally interconnected through silicon substrate traces. The first target computing core and the second target computing core are bidirectionally interconnected through the glass substrate traces, and the third target computing core and the fourth target computing core are ring-connected through PCB traces. Wherein, the first target computing core is the computing core in the first row and first column of the 12-core chip, the second target computing core is the computing core in the last row and first column of the 12-core chip, the third target computing core is the computing core in the first row and last column of the 12-core chip, and the fourth target computing core is the computing core in the last row and last column of the 12-core chip.

[0013] As an optional implementation, the board is a dual-chip 24-core board. The chip packaging structure of the board includes a first 12-core chip and a second 12-core chip. Each 12-core chip includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module packages two computing cores and four HBM particles. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The computing cores of adjacent silicon substrate packaging modules within each chip packaging structure are bidirectionally interconnected via glass substrate traces, and the computing cores within each silicon substrate packaging module are bidirectionally interconnected via silicon substrate traces. The fifth target computing core and the sixth target computing core are bidirectionally interconnected through the glass substrate traces of the first 12-core chip, and the seventh target computing core and the eighth target computing core are bidirectionally interconnected through the glass substrate traces of the second 12-core chip. The fifth target computing core is the computing core in the first row and first column of the first 12-core chip, the sixth target computing core is the computing core in the last row and first column of the first 12-core chip, the seventh target computing core is the computing core in the first row and last column of the second 12-core chip, and the eighth target computing core is the computing core in the last row and last column of the second 12-core chip. The ninth and tenth target computing cores are interconnected in a ring via PCB traces, and the eleventh and twelfth target computing cores are interconnected in a ring via PCB traces. The ninth target computing core is the computing core in the first row and last column of the first 12-core chip, the tenth target computing core is the computing core in the first row and first column of the second 12-core chip, the eleventh target computing core is the computing core in the last row and last column of the first 12-core chip, and the twelfth target computing core is the computing core in the last row and first column of the second 12-core chip.

[0014] Thirdly, embodiments of this application provide a server, including: at least one switching chip, multiple computing systems, and at least one CPU, wherein the computing system includes at least one board as described in the second aspect; The switching chip, each of the computing systems, and the CPU are connected via a subnet; The switching chip is connected to a CPU and multiple computing systems respectively; The switching chip includes at least two computing system connection interfaces, and each computing system connection interface corresponds to at least one interconnection channel; Each of the computing systems is interconnected via the switching chip.

[0015] The beneficial effects of this application include at least the following: This application provides a chip packaging structure, a circuit board, and a server. The chip packaging structure includes a carrier substrate and at least two interposer substrate modules packaged on the carrier substrate. Each interposer substrate module includes M computing cores, N high-bandwidth memory cells, and an interposer substrate. Each computing core is connected to at least two high-bandwidth memory cells through an interposer substrate, and the interposer substrate modules are bidirectionally interconnected through traces on the carrier substrate. The interconnects on the interposer substrate enable the connection between the computing cores within each interposer substrate module and the at least two high-bandwidth memory cells, and the high-speed, bidirectional interconnection between the interposer substrate modules is achieved through the traces on the carrier substrate. This improves chip packaging yield and reliability while maintaining low packaging costs, and enhances chip processing efficiency through the at least two high-bandwidth memory cells connected to each computing core. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 1 ; Figure 2 A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a silicon substrate packaging module provided in an embodiment of this application; Figure 4 A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 3 ; Figure 5 This is a schematic diagram of another silicon substrate packaging module provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a dual-core chip provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a 12-core chip provided in an embodiment of this application; Figure 8 This is a schematic diagram of the ring interconnection of a single-chip dual-core board provided in an embodiment of this application; Figure 9 This is a schematic diagram of the ring interconnect of a single-chip 12-core board provided in an embodiment of this application; Figure 10 This is a schematic diagram of the ring interconnection of a dual-chip 24-core board provided in an embodiment of this application; Figure 11 This is a schematic diagram of the server structure provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] The modules and units mentioned in this application may include one or more hardware circuits, including but not limited to: application-specific integrated circuits, digital signal processors, field-programmable gate arrays, discrete logic circuits, state machines, and any combination of the foregoing circuits; these circuits are specifically designed, configured and interconnected to perform one or more specific functions disclosed in this application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0022] Currently, the 2.5D packaging solution is widely used, stacking HBM chips near the GPU chip. However, existing 2.5D packaging solutions have significant limitations. On the one hand, the parallel port trace density of next-generation memory such as HBM3 is extremely high, requiring packaging on a silicon substrate. The size of the silicon substrate is limited by its physical properties, making it difficult to significantly expand, thus hindering the integration of a large number of HBM chips around the GPU chip and directly restricting the potential for bandwidth improvement. On the other hand, stacking excessive HBM chips around a single GPU chip significantly increases packaging complexity, leading to a decrease in chip yield.

[0023] Based on the above-mentioned problems, this application provides a chip packaging structure that improves the yield and processing efficiency of the chip corresponding to the chip packaging structure by packaging at least two interposer substrate modules on a carrier substrate, while ensuring low packaging cost.

[0024] Figure 1 A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 1 ,like Figure 1 As shown, the chip packaging structure includes: a carrier substrate and at least two interposer substrate modules packaged on the carrier substrate, wherein each interposer substrate module includes M computing cores, N high-bandwidth storage units and an interposer substrate, where N is an integer multiple of M.

[0025] Optionally, in the chip packaging structure, at least two interposer substrate modules are packaged on the carrier substrate to... Figure 1For example, two interposer substrate modules are packaged on a carrier substrate. Each interposer substrate module includes one interposer substrate, M computing cores, and N high-bandwidth storage units, where N is an integer multiple of M. The computing cores may include several computing units.

[0026] Reference Figure 1 Each computing core is connected to N high-bandwidth storage units, and the two intermediary substrate modules are packaged together on the carrier substrate to form a complete chip.

[0027] The first interposer substrate of the first interposer substrate module and the second interposer substrate of the second interposer substrate module are both fixedly mounted on the carrier substrate; each computing core is connected to at least two high-bandwidth storage units through each interposer substrate; and each interposer substrate module is bidirectionally interconnected through traces on the carrier substrate.

[0028] Optionally, continue to refer to Figure 1 A first interposer substrate module and a second interposer substrate module are fixedly disposed on the carrier substrate. The computing core on the first interposer substrate of the first interposer substrate module is connected to at least two high-bandwidth storage units through the wiring of the first interposer substrate.

[0029] Accordingly, the computing core on the second interposer substrate of the second interposer substrate module is connected to at least two high-bandwidth memory cells through the traces on the second interposer substrate. Furthermore, the interposer substrate modules are bidirectionally interconnected through the traces on the carrier substrate, meaning that the interposer substrate modules are interconnected at high speed on the carrier substrate.

[0030] In other words, multiple independent interposer substrate modules are set at the carrier substrate level. The computing cores within each interposer substrate module are connected to at least two high-bandwidth memory cells through the wiring on the interposer substrate, and high-speed, bidirectional interconnection between the interposer substrate modules is achieved through the wiring on the carrier substrate. In this way, chip packaging yield and reliability can be improved while ensuring low packaging costs, and the chip's processing efficiency can be improved by connecting at least two high-bandwidth memory cells to each computing core.

[0031] In this embodiment, the chip packaging structure includes a carrier substrate and at least two interposer substrate modules packaged on the carrier substrate. Each interposer substrate module includes M computing cores, N high-bandwidth memory cells, and an interposer substrate. Each computing core is connected to at least two high-bandwidth memory cells through an interposer substrate, and the interposer substrate modules are bidirectionally interconnected through carrier substrate traces. The interconnects on the interposer substrates enable the connection between the computing cores within each interposer substrate module and the at least two high-bandwidth memory cells, and the high-speed, bidirectional interconnection between the interposer substrate modules is achieved through the carrier substrate traces. This improves chip packaging yield and reliability while maintaining low packaging costs, and enhances chip processing efficiency through the at least two high-bandwidth memory cells connected to each computing core.

[0032] In some embodiments, two computing cores and four high-bandwidth storage units can be provided on an interposer substrate. The chip packaging structure can also include more interposer substrate modules. While keeping the area of ​​the interposer substrate modules from being too large, the performance of the chip packaging structure is improved, which facilitates the formation of a larger-scale interconnect after overall packaging and is more suitable for high-performance computing applications.

[0033] Figure 2 A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 2 ,like Figure 2 As shown, the interposer substrate module includes a silicon substrate packaging module, the interposer substrate includes a silicon substrate, and the high bandwidth memory cell includes HBM particles.

[0034] Optionally, refer to Figure 2 The interposer substrate module is a silicon substrate packaging module, the interposer substrate is a silicon substrate, and the high bandwidth memory cell is an HBM chip, which can be an HBM3 chip, for example.

[0035] Continue to refer to Figure 2 Since the first silicon substrate in the first silicon substrate packaging module and the second silicon substrate in the second silicon substrate packaging module are packaged independently, the area of ​​the silicon substrate is reduced, which can improve the yield. Furthermore, the wafers can be screened separately, thereby improving the reliability of the chip packaging structure and the packaging yield.

[0036] Figure 3 This is a schematic diagram of the structure of a silicon substrate packaging module provided in an embodiment of this application, as shown below. Figure 3 As shown, a first computing core, a first HBM particle, and a second HBM particle are packaged on a silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle via silicon substrate traces. The silicon substrate packaged modules are bidirectionally interconnected via carrier substrate traces.

[0037] Optionally, refer to Figure 2 and Figure 3 One computing core and two HBM particles are packaged on a silicon substrate, and two silicon substrate packaging modules are packaged on a carrier substrate. Figure 3 The black traces represent traces on the silicon substrate. The computing core 1 in the first silicon substrate packaging module is bidirectionally interconnected with the first HBM particle HBM1 and the second HBM particle HBM2 through the traces on the first silicon substrate. The computing core 2 in the second silicon substrate packaging module is bidirectionally interconnected with the third HBM particle HBM3 and the fourth HBM particle HBM4 through the traces on the second silicon substrate, so as to improve the chip's storage capacity.

[0038] Continue to refer to Figure 3 ,by Figure 3 Taking the packaging of two silicon substrate packaging modules on a carrier substrate as an example, the red traces represent the traces at the carrier substrate level. The computing core 1 in the first silicon substrate packaging module and the computing core 2 in the second silicon substrate packaging module are interconnected at high speed and bidirectionally through the carrier substrate traces to improve the interconnection bandwidth and computing power of the chip.

[0039] N can be twice M, meaning that each computing core in the silicon substrate packaging module is connected to two HBM3 particles. This allows for a smaller silicon substrate size, reduces packaging process risks, improves packaging yield, and enables flexible fulfillment of the chip's required storage capacity, interconnect bandwidth, and computing power by packaging multiple silicon substrate packaging modules on the carrier substrate.

[0040] Specifically, with Figure 2 and Figure 3 Taking the example of two silicon substrate packaging modules encapsulated on a carrier substrate, with each module containing one computing core and two HBM3 chips, the yield of this packaging structure is explained. Factors affecting chip packaging yield include the yield of the computing core. HBM3 particle yield Silicon substrate yield , Packaging yield as well as Packaging yield .in, This describes the process of packaging the computing core and HBM3 particles onto a silicon substrate. This describes the process of packaging a silicon substrate packaging module onto a carrier substrate.

[0041] Figure 2 If each independent silicon substrate packages one computing core and two HBM3 chips, then the chip packaging yield is [missing information]. The reduction in silicon substrate size has led to a decrease in silicon substrate packaging yield. and the yield of packaging computing cores and HBM particles onto silicon substrates. All are significantly improved, making packaging easier, and multiple silicon substrate packaging modules can be packaged together onto a carrier substrate according to application needs, improving product yield while meeting chip processing performance requirements.

[0042] Figure 4 A schematic diagram of the chip packaging structure provided in the embodiments of this application. Figure 3 , Figure 5 This is a schematic diagram of another silicon substrate packaging module provided in an embodiment of this application, as shown below. Figure 4 and Figure 5 As shown, a first computing core, a second computing core, a first HBM particle, a second HBM particle, a third HBM particle, and a fourth HBM particle are packaged on a silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle via silicon substrate traces, and the second computing core is connected to the third HBM particle and the fourth HBM particle via silicon substrate traces. The first computing core and the second computing core are bidirectionally interconnected via carrier substrate traces. The silicon substrate packaged modules are bidirectionally interconnected via carrier substrate traces.

[0043] Optionally, refer to Figure 4 and Figure 5 Two computing cores and four HBM particles are packaged on a silicon substrate, and two silicon substrate packaging modules are packaged on a carrier substrate. Figure 5 The black traces represent traces on the silicon substrate layer. The computing core 1 in the first silicon substrate packaging module is bidirectionally interconnected with the first HBM particle HBM1 and the second HBM particle HBM2 through the traces on the first silicon substrate. The computing core 2 in the first silicon substrate packaging module is bidirectionally interconnected with the third HBM particle HBM3 and the fourth HBM particle HBM4 through the traces on the first silicon substrate. Furthermore, the computing core 1 and the computing core 2 in the first silicon substrate packaging module are bidirectionally interconnected at high speed through the traces on the first silicon substrate.

[0044] Reference Figure 4 and Figure 5 The computing core 3 in the second silicon substrate packaging module is bidirectionally interconnected with the fifth HBM particle HBM5 and the sixth HBM particle HBM6 through the traces of the second silicon substrate. The computing core 4 in the second silicon substrate packaging module is bidirectionally interconnected with the seventh HBM particle HBM7 and the eighth HBM particle HBM8 through the traces of the second silicon substrate. Furthermore, the computing core 3 and the computing core 4 in the second silicon substrate packaging module are bidirectionally interconnected at high speed through the traces of the second silicon substrate.

[0045] Continue to refer to Figure 5 ,by Figure 5Taking the packaging of two silicon substrate packaging modules on a carrier substrate as an example, the red traces represent the traces at the carrier substrate level. The computing core 2 in the first silicon substrate packaging module and the computing core 3 in the second silicon substrate packaging module are interconnected at high speed and bidirectionally through the carrier substrate traces to improve the interconnection bandwidth and computing power of the chip.

[0046] Figure 4 Each independent silicon substrate encapsulates two computing cores and four HBM3 chips, in order to Figure 4 For example, the chip packaging yield of this packaging structure is... .

[0047] In this embodiment, the interposer substrate module includes a silicon substrate packaging module. The interposer substrate includes a silicon substrate, and the high-bandwidth memory unit includes HBM particles. A first computing core, a first HBM particle, and a second HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle respectively through silicon substrate traces. Alternatively, a first computing core, a second computing core, a first HBM particle, a second HBM particle, a third HBM particle, and a fourth HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle respectively through silicon substrate traces, and the second computing core is connected to the third HBM particle and the fourth HBM particle respectively through silicon substrate traces. The first computing core and the second core are connected to each other through silicon substrate traces. The silicon substrate packaging modules are bidirectionally interconnected through carrier substrate traces. By using a 1:2 ratio of computing cores to HBM particles, the chip packaging process risk can be reduced, the packaging yield can be improved, and the bidirectional interconnection between silicon substrate packaging modules can be achieved through carrier substrate traces, thereby increasing the chip's storage capacity, interconnect bandwidth, and computing power, and thus improving the chip's processing efficiency in large-scale model computing scenarios.

[0048] Figure 6 This is a schematic diagram of the structure of the dual-core chip provided in the embodiments of this application, such as... Figure 6 As shown, there are two silicon substrate packaging modules, and the carrier substrate includes an ABF substrate.

[0049] Optionally, the carrier substrate includes an Ajinomoto Build-up Film (ABF) substrate or a glass substrate, wherein the insulating layer of the ABF substrate is an ABF thin film, and the insulating layer of the glass substrate is glass, ABF material, and resin. When the number of silicon substrate packaged modules is two, the carrier substrate is an ABF substrate.

[0050] Reference Figure 6The chip integrates two computing cores and four HBM particles into a single silicon substrate package module at the silicon substrate level, and further integrates two silicon substrate package modules into a dual-core chip at the ABF substrate level. Multiple silicon substrate package modules can be flexibly combined according to actual computing power and storage requirements, allowing for flexible expansion of the number of modules based on application needs. For example, one silicon substrate package module achieves dual-core computing power, while six modules achieve 12-core computing power. A 12-core chip, combining multiple silicon substrate package modules, can meet the high computing power demands of large-scale model computation and acquisition, handling complex multitasking and significantly improving the chip's scenario adaptability. Furthermore, multiple silicon substrate package modules can be combined / packaged using a glass substrate. This 12-core chip achieves high performance while facilitating layout and routing on a single printed circuit board (PCB), avoiding excessively large PCB dimensions.

[0051] Continue to refer to Figure 3 and Figure 6 In the dual-core chip, the two computing cores are connected to two HBM particles respectively through black silicon substrate traces, and the computing cores in the two silicon substrate package modules are interconnected at high speed and bidirectionally through red ABF substrate traces.

[0052] A total of 2 computing cores and 4 HBM3 chips are packaged in two silicon substrate packaging modules. If the memory capacity of each HBM3 chip is... The memory bandwidth of each HBM3 chip is Therefore, each computing core has The memory bandwidth is [not specified]. The two computing cores are bidirectionally interconnected on the ABF substrate, with an interconnect bandwidth of [not specified] for each direction. The peak computing power of a single computing core is In a dual-core chip, the number of computing cores is 2, the number of HBM3 chips is 4, and the memory capacity is... Memory bandwidth is Peak computing power is The internal interconnect bandwidth is bidirectional. External interconnect bandwidth is It can adapt to the needs of chips with medium to low computing power.

[0053] In this embodiment, there are two silicon substrate packaging modules, the carrier substrate includes an ABF substrate, and the chip corresponding to the chip packaging structure is a dual-core chip. This improves the packaging yield of the dual-core chip, as well as its storage capacity, interconnect bandwidth, and computing power, thereby enhancing its processing efficiency.

[0054] Figure 7 This is a schematic diagram of the structure of the 12-core chip provided in the embodiments of this application, as shown below. Figure 7As shown, there are 6 silicon substrate packaging modules, each with 2 computing cores. The carrier substrate includes a glass substrate, and the chip packaging structure corresponds to a 12-core chip.

[0055] Optionally, refer to Figure 7 At the silicon substrate level, 12 computing cores and 24 HBM particles are packaged into 6 silicon substrate package modules, with each silicon substrate package module containing 2 computing cores and 4 HBM particles. At the glass substrate level, the 6 silicon substrate package modules are packaged into a complete 12-core chip.

[0056] The reason for using a glass substrate to encapsulate six silicon substrate modules is that the package size would be too large and the package warpage would be too significant when encapsulating six silicon substrate modules on an ABF substrate. Using a glass substrate to encapsulate the six silicon substrate modules reduces package warpage. It is worth noting that encapsulating a total of six silicon substrate modules on a glass substrate, i.e., 12 computing cores and 24 HBM3 chips, results in relatively high overall power consumption; liquid cooling can be used to improve stability.

[0057] Continue to refer to Figure 5 and Figure 7 In the 12-core chip, each computing core is connected to two HBM chips via silicon substrate traces. The silicon substrate packaging modules are interconnected at high speed and bidirectionally via red glass substrate traces. The computing cores within each silicon substrate packaging module are interconnected via silicon substrate traces. Figure 5 Computing core 1 and computing core 2 are bidirectionally interconnected via black silicon substrate traces, computing core 3 and computing core 4 are bidirectionally interconnected via black silicon substrate traces, and computing core 2 and computing core 3 are bidirectionally interconnected via red glass substrate traces.

[0058] It is worth noting that six silicon substrate packaging modules can be packaged on the glass substrate using the Flip Chip Ball Grid Array (FCBGA) packaging method, and interconnection between the six silicon substrate packaging modules can be achieved through the glass substrate.

[0059] Specifically, continue to refer to Figure 7 The six silicon substrate packaging modules are arranged in a 2×3 (i.e., 2 rows and 3 columns) manner. The silicon substrate packaging modules in the bottom row are rotated 180 degrees and placed. The adjacent silicon substrate packaging modules in each row are interconnected through glass substrate traces. At the same time, the computing cores on one side of the upper and lower rows are interconnected through the glass substrate, and the other side is fanned out through the glass substrate.

[0060] In a 12-core chip, the number of computing cores is 12, the number of HBM3 chips is 24, and the memory capacity is [missing information]. Memory bandwidth is Peak computing power is The internal interconnect bandwidth is bidirectional. External interconnect bandwidth is It can be adapted to major mainstream large models, thereby enabling consumer-level applications of large models.

[0061] In this embodiment, there are six silicon substrate packaging modules, each with two computing cores. The carrier substrate includes a glass substrate, and the chip packaging structure corresponds to a 12-core chip. This improves the packaging yield of the 12-core chip, as well as its storage capacity, interconnect bandwidth, and computing power, thereby enhancing its processing efficiency to adapt to major mainstream large-scale models.

[0062] This application also provides a board, which includes at least one chip packaging structure as described in the foregoing embodiments.

[0063] Optionally, the board includes at least one chip package structure, which can realize multi-chip interconnection and board-level expansion interconnection at the PCB level.

[0064] Among them, the chip packaging structure corresponds to a dual-core chip or a 12-core chip, and the board packaging form can be a single-chip dual-core board, a single-chip 12-core board, or a dual-chip 24-core board.

[0065] In this embodiment, the board includes at least one chip package structure, which realizes multi-chip interconnection and board-level expansion interconnection at the PCB level, thereby improving the board's storage capacity, interconnect bandwidth and computing power.

[0066] As an optional implementation, the board includes multiple chip package structures, which are interconnected in a ring, and the computing cores within each chip package structure are interconnected in a ring.

[0067] Optionally, the chip packages in the board are interconnected in a ring via PCB traces, forming a complete ring in the interconnection topology.

[0068] In this embodiment, the board includes multiple chip package structures, which are interconnected in a ring. The computing cores in each chip package structure are also interconnected in a ring, thereby achieving multi-chip interconnection and board-level expansion interconnection.

[0069] Figure 8 This is a schematic diagram of the ring interconnection of a single-chip dual-core board provided in an embodiment of this application, as shown below. Figure 8As shown, the board is a single-chip dual-core board. The chip package structure of the board corresponds to a dual-core chip. The dual-core chip includes an ABF substrate and two silicon substrate package modules packaged on the ABF substrate. Each silicon substrate package module packages one computing core and two HBM particles. Each computing core is connected to the two HBM particles through silicon substrate traces. The silicon substrate package modules are bidirectionally interconnected through ABF substrate traces and ring-shaped interconnected through PCB traces.

[0070] Optionally, refer to Figure 8 In a single-chip dual-core board, the chip packaging structure corresponds to a dual-core chip. The dual-core chip includes an ABF substrate and two silicon substrate packaging modules packaged on the ABF substrate. A total of two computing cores and four HBM particles are packaged on the two silicon substrate packaging modules.

[0071] The two silicon substrate packaging modules encapsulate a total of two computing cores and four HBM chips. The two computing cores are connected via... Figure 8 The black silicon substrate traces connect the two HBM particles respectively. The two computing cores are interconnected at high speed and bidirectionally through the red ABF substrate traces, and the two computing cores are interconnected in a ring through the green PCB traces.

[0072] Due to the strong insulation and anti-interference capabilities of the ABF substrate, and its extremely small trace spacing, high-precision wiring can be achieved. This effectively suppresses signal crosstalk between computing cores, avoids signal distortion and packet loss during high-frequency data transmission, ensures the stability of high-speed bidirectional interconnection between two computing cores, and guarantees the reliability of computing power collaboration. The flexible PCB routing allows for ring interconnection between two computing cores, enabling flexible expansion of chip computing power as needed.

[0073] In this embodiment, the board is a single-chip dual-core board. The chip package structure of the board corresponds to a dual-core chip, which includes an ABF substrate and two silicon substrate package modules packaged on the ABF substrate. Each silicon substrate package module packages one computing core and two HBM particles. Each computing core is connected to the two HBM particles through silicon substrate traces. The silicon substrate package modules are bidirectionally interconnected through ABF substrate traces and ring-shaped interconnected through PCB traces. The ring-shaped interconnection between the silicon substrate package modules realizes the interconnection topology of the single-chip dual-core board.

[0074] Figure 9 This is a schematic diagram of the ring interconnection of a single-chip 12-core board provided in an embodiment of this application, as shown below. Figure 9As shown, the board is a single-chip 12-core board. The chip package structure of the board corresponds to a 12-core chip. The 12-core chip includes a glass substrate and 6 silicon substrate package modules packaged on the glass substrate. Each silicon substrate package module has two computing cores and four HBM particles packaged on it. Each computing core is connected to two HBM particles through silicon substrate traces.

[0075] Optionally, refer to Figure 9 In a single-chip 12-core board, the chip packaging structure corresponds to a 12-core chip, which includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module packages two computing cores and four HBM particles. Each computing core connects via... Figure 9 The black silicon substrate traces connect to two HBM particles respectively.

[0076] The computing cores between adjacent silicon substrate packaging modules are bidirectionally interconnected via glass substrate traces, and the computing cores within each silicon substrate packaging module are bidirectionally interconnected via silicon substrate traces. The first target computing core and the second target computing core are bidirectionally interconnected via glass substrate traces, and the third target computing core and the fourth target computing core are ring-connected via PCB traces. The first target computing core is the computing core in the first row and first column of the 12-core chip, the second target computing core is the computing core in the last row and first column of the 12-core chip, the third target computing core is the computing core in the first row and last column of the 12-core chip, and the fourth target computing core is the computing core in the last row and last column of the 12-core chip.

[0077] Optionally, continue to refer to Figure 9 The two computing cores within each silicon substrate packaging module are bidirectionally interconnected via black silicon substrate traces. The computing cores within adjacent silicon substrate packaging modules are bidirectionally interconnected via red glass substrate traces. The first target computing core and the second target computing core are bidirectionally interconnected via red glass substrate traces, and the third target computing core and the fourth target computing core are ring-connected via green PCB traces.

[0078] The first target computing core is the computing core in the first row and first column of the 12-core chip, that is, the first target computing core is... Figure 9 The first target computing core is the computing core in the last row and first column of a 12-core chip. Figure 9 The third target computing core is the computing core in the first row and last column of a 12-core chip, that is, the third target computing core is... Figure 9 The fourth target computing core is the last row and last column of the 12-core chip, that is, the fourth target computing core is... Figure 9 The core of the computing system is 12.

[0079] In this embodiment, the board is a single-chip 12-core board. The chip package structure of the board corresponds to a 12-core chip. The 12-core chip includes a glass substrate and six silicon substrate package modules packaged on the glass substrate. Each silicon substrate package module packages two computing cores and four HBM particles. Each computing core is connected to two HBM particles through silicon substrate traces. The computing cores of adjacent silicon substrate package modules are bidirectionally interconnected through glass substrate traces, and the computing cores within each silicon substrate package module are bidirectionally interconnected through silicon substrate traces. The first target computing core and the second target computing core are bidirectionally interconnected through glass substrate traces, and the third target computing core and the fourth target computing core are ring-connected through PCB traces. The interconnection topology of the single-chip 12-core board is realized through the ring interconnection of the computing cores.

[0080] Figure 10 This is a schematic diagram of the ring interconnection of a dual-chip 24-core board provided in an embodiment of this application, as shown below. Figure 10 As shown, the board is a dual-chip 24-core board. The chip packaging structure of the board includes a first 12-core chip and a second 12-core chip. Each 12-core chip includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module packages two computing cores and four HBM particles. Each computing core is connected to two HBM particles through silicon substrate traces.

[0081] Optionally, refer to Figure 10 In the dual-chip 24-core board, the chip package structure corresponds to a 12-core chip. The board includes a first 12-core chip and a second 12-core chip. Each 12-core chip includes a glass substrate and six silicon substrate package modules packaged on the glass substrate. Each silicon substrate package module packages two computing cores and four HBM particles. Each computing core connects via... Figure 10 The black silicon substrate traces connect to two HBM particles respectively.

[0082] The computing cores within adjacent silicon substrate packaging modules of each chip packaging structure are bidirectionally interconnected via glass substrate traces, and the computing cores within each silicon substrate packaging module are bidirectionally interconnected via silicon substrate traces; the fifth target computing core and the sixth target computing core are bidirectionally interconnected via glass substrate traces of the first 12-core chip, and the seventh target computing core and the eighth target computing core are bidirectionally interconnected via glass substrate traces of the second 12-core chip; wherein, the fifth target computing core is the computing core in the first row and first column of the first 12-core chip, the sixth target computing core is the computing core in the last row and first column of the first 12-core chip, the seventh target computing core is the computing core in the first row and last column of the second 12-core chip, and the eighth target computing core is the computing core in the last row and last column of the second 12-core chip.

[0083] Optionally, continue to refer to Figure 10 Within the silicon substrate packaging module, each computing core is interconnected at high speed and bidirectionally via black silicon substrate traces. Within each chip packaging structure, the computing cores of adjacent silicon substrate packaging modules are interconnected via red glass substrate traces. Furthermore, the fifth target computing core and the sixth target computing core are bidirectionally interconnected via red glass substrate traces of the first 12-core chip, and the seventh target computing core and the eighth target computing core are bidirectionally interconnected via red glass substrate traces of the second 12-core chip.

[0084] The fifth target computing core is the computing core in the first row and first column of the first 12-core chip, that is, the fifth target computing core is... Figure 10 The sixth target computing core is the computing core in the last row and first column of the first 12-core chip, that is, the sixth target computing core is... Figure 10 The seventh target computing core is the computing core in the first row and last column of the second 12-core chip, that is, the seventh target computing core is... Figure 10 The eighth target computing core is the last row and last column of the second 12-core chip, that is, the eighth target computing core is... Figure 10 The core of the computing system is 24.

[0085] The ninth and tenth target computing cores are interconnected via a ring of PCB traces, and the eleventh and twelfth target computing cores are interconnected via a ring of PCB traces. The ninth target computing core is the computing core in the first row and last column of the first 12-core chip, the tenth target computing core is the computing core in the first row and first column of the second 12-core chip, the eleventh target computing core is the computing core in the last row and last column of the first 12-core chip, and the twelfth target computing core is the computing core in the last row and first column of the second 12-core chip.

[0086] Optionally, continue to refer to Figure 10 The ninth and tenth target computing cores are interconnected in a ring via green PCB traces, and the eleventh and twelfth target computing cores are interconnected in a ring via green PCB traces.

[0087] Among them, the ninth target computing core is the computing core in the first row and last column of the first 12-core chip, that is, the ninth target computing core is... Figure 10 The tenth target computing core is the computing core in the first row and first column of the second 12-core chip, that is, the tenth target computing core is... Figure 10 The eleventh target computing core is the computing core in the last row and last column of the first 12-core chip, that is, the eleventh target computing core is... Figure 10The twelfth target computing core is the computing core in the last row and first column of the second 12-core chip, that is, the twelfth target computing core is... Figure 10 Core 19 of the Chinese Computing System.

[0088] In this embodiment, the board is a dual-chip 24-core board. The chip packaging structure of the board includes a first 12-core chip and a second 12-core chip. Each 12-core chip includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module packages two computing cores and four HBM particles. Each computing core is connected to two HBM particles through silicon substrate traces. The computing cores of adjacent silicon substrate packaging modules within each chip packaging structure are bidirectionally interconnected through glass substrate traces, and the computing cores within each silicon substrate packaging module are bidirectionally interconnected through silicon substrate traces. The fifth target computing core and the sixth target computing core are bidirectionally interconnected through the glass substrate traces of the first 12-core chip, and the seventh target computing core and the eighth target computing core are bidirectionally interconnected through the glass substrate traces of the second 12-core chip. The ninth target computing core and the tenth target computing core are interconnected in a ring through PCB traces, and the eleventh target computing core and the twelfth target computing core are interconnected in a ring through PCB traces. The interconnection topology of the dual-chip 24-core board is realized through the ring interconnection of each computing core.

[0089] Figure 11 This is a schematic diagram of the server structure provided in the embodiments of this application, such as... Figure 11 As shown, the server includes: at least one switching chip, multiple computing systems, and at least one CPU, wherein the computing system includes at least one board as described in the foregoing embodiments.

[0090] Optionally, the server includes at least one switching chip, one CPU, and multiple computing systems, as shown in the reference. Figure 11 The server may include a switching chip, a CPU, and two computing systems, namely computing system 1 and computing system 2. Each computing system includes at least one board as described in the preceding embodiments.

[0091] The switching chip, each computing system, and the CPU are connected via a subnet; the switching chip is connected to one CPU and multiple computing systems respectively; the switching chip includes at least two computing system connection interfaces, and each computing system connection interface corresponds to at least one interconnection channel; the computing systems are interconnected through the switching chip.

[0092] Optionally, continue to refer to Figure 11The switching chip includes multiple computing system connection interfaces, each of which corresponds to at least one interconnection channel. The first two computing system connection interfaces of the switching chip can be connected to computing system 1, and the last two computing system connection interfaces of the switching chip can be connected to computing system 2, so that computing system 1 and computing system 2 are interconnected through the switching chip, and there are two interconnection channels between computing system 1 and computing system 2.

[0093] The switching chip is also connected to a CPU, which is indirectly interconnected with computing system 1 and computing system 2 through the switching chip. In other words, the switching chip, computing system 1, computing system 2, and CPU are connected via a converged subnet. This allows the connection between computing system 1 or computing system 2 and the CPU, as well as the interconnection between computing system 1 and computing system 2, to be achieved through the switching chip, eliminating the need for dedicated interconnection channels. This subnet convergence reduces the complexity of the server's interconnection topology and ensures high compatibility.

[0094] In this embodiment, the server includes at least one switching chip, multiple computing systems, and at least one CPU. Each computing system includes at least one board. The switching chip, each computing system, and the CPU are connected via a subnet. The switching chip is connected to one CPU and multiple computing systems respectively. The switching chip includes at least two computing system connection interfaces, each corresponding to at least one interconnect channel. The computing systems are interconnected via the switching chip. The switching chip, each computing system, and the CPU are connected via a converged subnet, enabling connections between each computing system and the CPU, as well as interconnections between computing systems, to be achieved through the switching chip, eliminating the need for dedicated interconnect channels. This subnet convergence reduces the complexity of the interconnect topology, provides high compatibility, and improves server processing efficiency through the at least one board included in each computing system. Furthermore, multiple interconnect channels allow for low-cost, high-bandwidth connections between computing systems.

[0095] In one embodiment, the switching chip includes a PCIe Switch. The computing core includes a packaging unit for repackaging access requests (whether read, write, etc.) from itself (as the source computing core) that point to a storage unit other than its own as a write request. This repackaging is then mapped via the PCIe Switch's Bar to a designated address of the depackaging unit of the computing core containing the destination storage unit. The depackaging unit receives the write request and depackages it into an access request pointing to the destination storage unit. If the access request is a read request, after the computing core containing the destination storage unit obtains the target data, it repackages the obtained data return request into a write request via its own packaging unit. This repackaging is then mapped via the PCIe Switch's Bar to a designated address of the depackaging unit of the source computing core. The depackaging unit of the source computing core depackages the write request returned by the computing core containing the destination storage unit and obtains the target data.

[0096] For large-scale computing core interconnect systems, in order to expand the video memory capacity, the total video memory of a single computing system is often greater than the capacity of a single bar in a PCIe switch. Directly mapping video memory addresses through bars will result in insufficient space, making stable access to the target node's computing core impossible.

[0097] The PCIe switch maps domain addresses to depackaging units via its Bar instead of directly mapping to memory addresses, significantly reducing the required address space and enabling smooth, flexible, and stable access to computing cores in large memory chip interconnect systems. This improves the smoothness of cross-computing core access without needing to expand the PCIe switch's Bar space, facilitating the interconnection of larger memory chips.

[0098] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A chip packaging structure, characterized in that, include: The carrier substrate and at least two interposer substrate modules packaged on the carrier substrate, wherein each interposer substrate module includes M computing cores, N high-bandwidth storage units and an interposer substrate, wherein N is an integer multiple of M. The first interposer substrate of the first interposer substrate module and the second interposer substrate of the second interposer substrate module are both fixedly disposed on the carrier substrate. Each of the aforementioned computing cores is connected to at least two high-bandwidth storage units via each intermediary substrate; The intermediate layer substrate modules are bidirectionally interconnected through carrier substrate traces.

2. The chip packaging structure according to claim 1, characterized in that, The interposer substrate module includes a silicon substrate packaging module. The interposer substrate includes a silicon substrate. The high bandwidth storage unit includes HBM particles. A first computing core, a first HBM particle, and a second HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle through silicon substrate traces. Alternatively, a first computing core, a second computing core, a first HBM particle, a second HBM particle, a third HBM particle, and a fourth HBM particle are packaged on the silicon substrate. The first computing core is connected to the first HBM particle and the second HBM particle respectively through silicon substrate traces. The second computing core is connected to the third HBM particle and the fourth HBM particle respectively through silicon substrate traces. The first computing core and the second core are connected to each other through silicon substrate traces. The silicon substrate packaging modules are bidirectionally interconnected through the traces on the carrier substrate.

3. The chip packaging structure according to claim 2, characterized in that, The number of silicon substrate packaging modules is two, the carrier substrate includes an ABF substrate, and the chip corresponding to the chip packaging structure is a dual-core chip.

4. The chip packaging structure according to claim 2, characterized in that, The number of silicon substrate packaging modules is 6, and each silicon substrate packaging module is provided with 2 computing cores. The carrier substrate includes a glass substrate, and the chip corresponding to the chip packaging structure is a 12-core chip.

5. A circuit board, characterized in that, The board includes at least one chip packaging structure as described in any one of claims 1-4.

6. The board according to claim 5, characterized in that, The board includes multiple chip package structures, which are interconnected in a ring, and the computing cores in each chip package structure are interconnected in a ring.

7. The board according to claim 5, characterized in that, The board is a single-chip dual-core board. The chip package structure of the board includes a dual-core chip. The dual-core chip includes an ABF substrate and two silicon substrate packaging modules packaged on the ABF substrate. Each silicon substrate packaging module is packaged with a computing core and two HBM particles. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The silicon substrate packaging modules are interconnected bidirectionally via ABF substrate traces and ring-shaped via PCB traces.

8. The board according to claim 5, characterized in that, The board is a single-chip 12-core board. The chip package structure of the board includes a 12-core chip. The 12-core chip includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module has two computing cores and four HBM particles packaged on it. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The computing cores of each adjacent silicon substrate package module are bidirectionally interconnected through glass substrate traces, and the computing cores within each silicon substrate package module are bidirectionally interconnected through silicon substrate traces. The first target computing core and the second target computing core are bidirectionally interconnected through the glass substrate traces, and the third target computing core and the fourth target computing core are ring-connected through PCB traces. Wherein, the first target computing core is the computing core in the first row and first column of the 12-core chip, the second target computing core is the computing core in the last row and first column of the 12-core chip, the third target computing core is the computing core in the first row and last column of the 12-core chip, and the fourth target computing core is the computing core in the last row and last column of the 12-core chip.

9. The board according to claim 5, characterized in that, The board is a dual-chip 24-core board. The chip packaging structure of the board includes a first 12-core chip and a second 12-core chip. Each 12-core chip includes a glass substrate and six silicon substrate packaging modules packaged on the glass substrate. Each silicon substrate packaging module has two computing cores and four HBM particles packaged on it. Each of the aforementioned computing cores is connected to two HBM particles via silicon substrate traces. The computing cores of adjacent silicon substrate packaging modules within each chip packaging structure are bidirectionally interconnected via glass substrate traces, and the computing cores within each silicon substrate packaging module are bidirectionally interconnected via silicon substrate traces. The fifth target computing core and the sixth target computing core are bidirectionally interconnected through the glass substrate traces of the first 12-core chip, and the seventh target computing core and the eighth target computing core are bidirectionally interconnected through the glass substrate traces of the second 12-core chip. The fifth target computing core is the computing core in the first row and first column of the first 12-core chip, the sixth target computing core is the computing core in the last row and first column of the first 12-core chip, the seventh target computing core is the computing core in the first row and last column of the second 12-core chip, and the eighth target computing core is the computing core in the last row and last column of the second 12-core chip. The ninth and tenth target computing cores are interconnected in a ring via PCB traces, and the eleventh and twelfth target computing cores are interconnected in a ring via PCB traces. The ninth target computing core is the computing core in the first row and last column of the first 12-core chip, the tenth target computing core is the computing core in the first row and first column of the second 12-core chip, the eleventh target computing core is the computing core in the last row and last column of the first 12-core chip, and the twelfth target computing core is the computing core in the last row and first column of the second 12-core chip.

10. A server, characterized in that, include: The system comprises at least one switching chip, multiple computing systems, and at least one CPU, wherein the computing system includes at least one board according to any one of claims 5-9; The switching chip, each of the computing systems, and the CPU are connected via a subnet; The switching chip is connected to a CPU and multiple computing systems respectively; The switching chip includes at least two computing system connection interfaces, and each computing system connection interface corresponds to at least one interconnection channel; Each of the computing systems is interconnected via the switching chip.

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