Display devices and display panels

Abstract

Embodiments of this disclosure may provide a display device and a display panel. The display device includes: a display panel including a display area having a plurality of sub-pixels; and a driving circuit configured to drive the display panel, wherein the display area includes a first embankment defining an emission area of ​​the plurality of sub-pixels and a second embankment on the first embankment, the second embankment including multi-pattern areas of different heights.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0176738, filed on December 2, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to display devices and display panels, and more specifically, to display devices and display panels capable of improving the packaging function of light-emitting elements. Background Technology

[0004] As examples of display devices that use digital data to display images, there are liquid crystal displays (LCDs) that use liquid crystals and organic light-emitting displays (OLEDs) that use organic light-emitting diodes.

[0005] In display devices, organic light-emitting display devices utilize self-emissive light-emitting diodes (LEDs), which offer fast response times and advantages in contrast, luminous efficiency, brightness, and viewing angle. In this case, the LEDs can be implemented using either inorganic or organic materials.

[0006] An organic light-emitting display device may include an organic light-emitting diode in each of a plurality of sub-pixels disposed on a display panel, and the brightness of each sub-pixel may be controlled by controlling the voltage flowing to the organic light-emitting diode to emit light, thereby displaying an image.

[0007] In this case, an encapsulation layer can be placed on the top of the display panel to prevent external moisture or oxygen from penetrating into the light-emitting elements.

[0008] However, as display panels become thinner, the encapsulation layer also becomes thinner, and therefore, there is a possibility that the encapsulation layer may not be properly formed on the surface of the light-emitting element. Summary of the Invention

[0009] Therefore, the inventors of this disclosure have invented a display device and display panel that can form an encapsulation layer to seal the surface of the light-emitting element even when the thickness of the encapsulation layer is reduced.

[0010] Embodiments of this disclosure may provide a display device and a display panel, wherein the encapsulation layer is formed as a multi-pattern structure, such that the encapsulation layer can be effectively applied to the surface of the light-emitting element.

[0011] Embodiments of this disclosure may provide a display device and a display panel in which a valley pattern is formed in some areas of the embankment, such that the encapsulation layer can be easily extended to the surface of the light-emitting element.

[0012] Embodiments of this disclosure may provide a display device and a display panel in which a protrusion is formed at the location where a recessed portion of a dam overlaps, thereby allowing the encapsulation layer to easily extend to the surface of the light-emitting element.

[0013] Embodiments of this disclosure may provide a display device comprising: a display panel including a display area having a plurality of sub-pixels disposed therein; and a driving circuit configured to drive the display panel, wherein the display area includes a first embankment defining an emission area of ​​the plurality of sub-pixels and a second embankment on the first embankment, the second embankment including a multi-patterned area of ​​different thicknesses.

[0014] Embodiments of this disclosure may provide a display panel including a plurality of subpixels, a first dike defining emission regions of the plurality of subpixels, and a second dike on the first dike including multi-patterned regions of different thicknesses.

[0015] According to embodiments of this disclosure, even when the thickness of the encapsulation layer is reduced, a lightweight display device can still be manufactured by forming an encapsulation layer to seal the surface of the light-emitting element.

[0016] According to embodiments of this disclosure, it is possible to provide the effect of effectively applying an encapsulation layer to the surface of a light-emitting element by forming the embankment into a multi-pattern structure.

[0017] According to embodiments of this disclosure, it is possible to provide the effect of forming valley patterns in some areas of the dike, allowing the encapsulation layer to be easily extended to the surface of the light-emitting element.

[0018] According to embodiments of this disclosure, it is possible to provide the effect of forming protrusions at the locations where the valley patterns of the embankment overlap, thereby allowing the encapsulation layer to easily extend onto the surface of the light-emitting element. Attached Figure Description

[0019] Figure 1 A display device according to an embodiment of the present disclosure is shown schematically.

[0020] Figure 2 An equivalent circuit of a subpixel in a display panel according to an embodiment of the present disclosure is shown as an example.

[0021] Figure 3 A cross-section of a display area in a display panel according to an embodiment of the present disclosure is shown.

[0022] Figure 4 This is a cross-sectional photograph of the encapsulation layer formed on the upper part of the dam in the display device.

[0023] Figure 5 This is a plan view of a display device in which a dam surrounding the emission area is formed with a dual-pattern structure, according to an embodiment of the present disclosure.

[0024] Figure 6 This is a cross-sectional view taken along the A-A' direction of a display device including a sub-pixel with a dam having a dual-pattern structure, according to an embodiment of the present disclosure.

[0025] Figure 7 This is a plan view showing a dam structure including a valley pattern between sub-pixels in a display device according to an embodiment of the present disclosure.

[0026] Figure 8 It is a cross-sectional view taken along the B-B' direction of a dam structure including a valley pattern in a display device according to an embodiment of the present disclosure.

[0027] Figure 9 It is a cross-sectional view taken along the C-C' direction of a dam structure including a valley pattern in a display device according to an embodiment of the present disclosure.

[0028] Figure 10 This is a plan view showing a case where the valley pattern of the second embankment in a display device according to an embodiment of the present disclosure extends only to a portion of the area between sub-pixels.

[0029] Figure 11 This is a plan view illustrating a dam structure in a display device according to an embodiment of the present disclosure, including a double pattern and a valley pattern between sub-pixels positioned around the emission area.

[0030] Figure 12 This is a plan view showing a dam structure including protrusions between sub-pixels in a display device according to an embodiment of the present disclosure.

[0031] Figure 13 This is a cross-sectional view taken along the D-D' direction of a dam structure including a protruding portion in a display device according to an embodiment of the present disclosure.

[0032] Figure 14 This is a cross-sectional view taken along the E-E' direction of a dam structure including a protruding portion in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. Reference will be made to the accompanying drawings in which specific examples or embodiments of the invention are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even when these components are shown in different drawings. Furthermore, in the following description of the examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such detailed descriptions might make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0035] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted as meaning that the first element can not only be "directly connected or coupled to" the second element or "directly in contact with or overlapping" a second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact with," or "overlapped" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapped" with each other.

[0036] When time-relative terms such as “after,” “follow,” “next,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “directly” or “immediately after” are used together.

[0037] Furthermore, when referring to any size, relative dimensions, etc., the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0038] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 A display device according to an embodiment of the present disclosure is shown schematically.

[0040] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110 and a display driving circuit for driving the display panel 110.

[0041] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The non-display area NDA may also be referred to as the border area.

[0042] Display panel 110 may include a plurality of subpixels SP for displaying images. For example, the plurality of subpixels SP may be arranged in display area DA. In some cases, at least one subpixel SP may be arranged in non-display area NDA. At least one subpixel SP arranged in non-display area NDA may also be referred to as a dummy subpixel.

[0043] The display panel 110 may include multiple signal lines for driving multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL and multiple gate lines GL. Depending on the structure of the sub-pixel SP, the signal lines may also include multiple data lines DL and multiple gate lines GL, as well as other signal lines. For example, other signal lines may include drive voltage lines and reference voltage lines.

[0044] Multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may be arranged to extend in a first direction. Each of the multiple gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. In this disclosure, the column direction and the row direction are relative. For example, the column direction may be a vertical direction, and the row direction may be a horizontal direction. As another example, the column direction may be a horizontal direction, and the row direction may be a vertical direction.

[0045] The driving circuit may include a data driving circuit 130 for driving multiple data lines DL and a gate driving circuit 120 for driving multiple gate lines GL. The driving circuit may also include a timing controller 140 for controlling the data driving circuit 130 and the gate driving circuit 120.

[0046] The data driving circuit 130 is used to drive multiple data lines DL and can output data signals (also referred to as data voltages) corresponding to the image signals to the multiple data lines DL. The gate driving circuit 120 is used to drive multiple gate lines GL and can generate gate signals and output the gate signals to the multiple gate lines GL. The gate signals may include one or more scan signals and light emission signals.

[0047] The timing controller 140 can begin scanning according to the timing implemented in each frame, and control the data drive at appropriate times according to the scan. The timing controller 140 can convert input image data from external sources into a data signal format used by the data drive circuit 130, and supply the converted image data (Data) to the data drive circuit 130.

[0048] The timing controller 140 can receive display drive control signals and input image data from the external host system 200. For example, the display drive control signals may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal.

[0049] The timing controller 140 can generate a data drive control signal DCS and a gate drive control signal GCS based on the display drive control signal input from the host system 200. The timing controller 140 can control the drive operation and timing of the data drive circuit 130 by supplying the data drive control signal DCS to the data drive circuit 130. The timing controller 140 can control the drive operation and timing of the gate drive circuit 120 by supplying the gate drive control signal GCS to the gate drive circuit 120.

[0050] The data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit may include a shift register, latch circuit, digital-to-analog converter (DAC), output buffer, etc. Depending on the circumstances, each source driver integrated circuit may also include an analog-to-digital converter (ADC).

[0051] For example, each source driver integrated circuit can be connected to the display panel 110 via tape auto-bonding (TAB), connected to the bonding pads of the display panel 110 via chip on glass (COG) or chip on panel (COP), or implemented and connected to the display panel 110 via chip on film (COF).

[0052] The gate drive circuit 120 can output a gate signal with an on-level voltage or a gate signal with an off-level voltage under the control of the timing controller 140. The gate drive circuit 120 can sequentially drive multiple gate lines GL by sequentially supplying the gate signal with an on-level voltage to multiple gate lines GL.

[0053] The gate drive circuit 120 may include one or more gate drive integrated circuits (GDICs).

[0054] The gate driving circuit 120 can be connected to the display panel 110 via tap-on-buck (TAB), to the bonding pads of the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP), or to the display panel 110 via chip-on-film (COF). Alternatively, the gate driving circuit 120 can be formed in the non-display area NDA of the display panel 110 as a gate-in-panel (GIP) type. The gate driving circuit 120 can be disposed on or connected to the substrate. That is, in the case of the gate-in-panel (GIP) type, the gate driving circuit 120 can be disposed in the non-display area NDA of the substrate. If the gate driving circuit 120 is of the chip-on-glass (COG) type or the chip-on-film (COF) type, it can be connected to the substrate.

[0055] Meanwhile, at least one of the data driving circuit 130 and the gate driving circuit 120 can be disposed in the display area DA. For example, at least one of the data driving circuit 130 and the gate driving circuit 120 can be configured not to overlap with the sub-pixel SP, or can be configured to partially or completely overlap with the sub-pixel SP.

[0056] The data driving circuit 130 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 130 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 110.

[0057] The gate driving circuit 120 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gate driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 110.

[0058] The timing controller 140 can be implemented as a component separate from the data drive circuitry 130, or it can be implemented as an integrated circuit by integrating it with the data drive circuitry 130. The timing controller 140 can be a controller used in typical display technologies, or it can be a control device capable of performing other control functions, including the timing controller 140, or it can be circuitry within a control device. The timing controller 140 can be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0059] The timing controller 140 can be mounted on a printed circuit board or flexible printed circuit board and can be electrically connected to the data drive circuit 130 and the gate drive circuit 120 via the printed circuit board or flexible printed circuit board. The timing controller 140 can send and receive signals with the data drive circuit 130 according to one or more predefined interfaces. Here, for example, the interface may include a low-voltage differential signaling (LVDS) interface, an EPI interface, or a serial peripheral (SP) interface, etc.

[0060] The display device 100 according to embodiments of the present disclosure may be a self-emissive display device in which the display panel 110 emits its own light. If the display device 100 according to embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element. For example, the display device 100 according to embodiments of the present disclosure may be an organic light-emitting display device, wherein the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to embodiments of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting element is implemented as an inorganic light-emitting diode. As yet another example, the display device 100 according to embodiments of the present disclosure may be a quantum dot display device, wherein the light-emitting element is implemented as a quantum dot, which is a semiconductor crystal that emits its own light.

[0061] The display device 100 may include: at least one source printed circuit board (SPCB) for circuit connection between multiple source driver integrated circuits (SDICs) and other devices; and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0062] In this case, the other side of the source film SF on which the source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB.

[0063] The timing controller 140 and power management circuitry (not shown) can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuitry 130 and the gate drive circuitry 120. The power management circuitry can supply drive voltage or current to the display panel 110, the data drive circuitry 130, and the gate drive circuitry 120, and can control the supplied voltage or current.

[0064] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be electrically connected to each other via at least one connecting member, which can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. Furthermore, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0065] In this case, each sub-pixel SP on the display panel 110 arranged in the display device 100 may consist of a light-emitting element and circuit elements such as driving transistors for driving the light-emitting element.

[0066] The type and number of circuit elements constituting each sub-pixel SP can be determined in various ways based on the provided functions and design methods.

[0067] Figure 2 An example of a sub-pixel circuit of a display device according to an embodiment of the present disclosure is shown.

[0068] Reference Figure 2 According to embodiments of the present disclosure, the sub-pixel SP of the display device 100 may include a first switching transistor T1 to a seventh switching transistor T7, a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0069] Here, for example, the light-emitting element ED can be a self-emitting element capable of emitting light itself, such as an organic light-emitting diode (OLED).

[0070] In the sub-pixel SP according to the embodiments of this disclosure, the second switching transistors T2 to T4, the sixth switching transistor T6, and the seventh switching transistor T7 can be P-type transistors. Furthermore, the first switching transistor T1 and the fifth switching transistor T5 can be N-type transistors.

[0071] Oxide transistors have a relatively low leakage current compared to silicon transistors. Therefore, at least some of the switching transistors or driving transistors DRT that constitute the sub-pixel SP can be configured as oxide transistors.

[0072] For example, the driving transistor DRT and the first switching transistor T1 and the fifth switching transistor T5 connected to the gate electrode of the driving transistor DRT can be configured as oxide transistors.

[0073] In addition, the remaining switching transistors T2, T3, T4, T6 and T7 can be configured as low-temperature polysilicon transistors.

[0074] In this configuration, the sub-pixel SP of the display device 100 can be configured as a driving transistor DRT formed by an oxide transistor and a first set of switching transistors T1 and T5, and a second set of switching transistors T2, T3, T4, T6 and T7 formed by a low-temperature polysilicon transistor.

[0075] A first scan signal SCAN1 can be supplied to the gate electrode of the first switching transistor T1. The second electrode (e.g., the drain electrode) of the first switching transistor T1 can be connected to the gate electrode N2 of the driving transistor DRT. Furthermore, the first electrode (e.g., the source electrode) of the first switching transistor T1 can be connected to the second electrode (e.g., the drain electrode) N3 of the driving transistor DRT.

[0076] The first switching transistor T1 can be turned on by the first scan signal SCAN1, and a current path is formed between the gate electrode N2 of the driving transistor DRT and the second electrode (e.g., the drain electrode) N3 through the storage capacitor Cst connected on one side to the high potential driving voltage VDD.

[0077] A second scan signal SCAN2 can be supplied to the gate electrode of the second switching transistor T2. A data voltage Vdata can be supplied to the first electrode (e.g., the source electrode) of the second switching transistor T2. The second electrode (e.g., the drain electrode) of the second switching transistor T2 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT. The second switching transistor T2 can be turned on by the second scan signal SCAN2 and supply the data voltage Vdata to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0078] If the first switching transistor T1 is turned on, the data voltage Vdata can be supplied to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT through the second switching transistor T2. Furthermore, the difference (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DRT can be sampled and supplied to the gate electrode N2 of the driving transistor DRT. Therefore, the first switching transistor T1 can be referred to as the sampling transistor, and the first scan signal SCAN1 can be referred to as the sampling scan signal.

[0079] A transmit signal EM can be supplied to the gate electrode of the third switching transistor T3. A high-potential drive voltage VDD can be supplied to the first electrode (e.g., the source electrode) of the third switching transistor T3. The second electrode (e.g., the drain electrode) of the third switching transistor T3 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT. The third switching transistor T3 can be turned on by transmitting the transmit signal EM and supplying a high-potential drive voltage VDD to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0080] A transmit signal EM can be supplied to the gate electrode of the fourth switching transistor T4. The first electrode (e.g., the source electrode) of the fourth switching transistor T4 can be connected to the second electrode (e.g., the drain electrode) N3 of the driving transistor DRT. The second electrode (e.g., the drain electrode) of the fourth switching transistor T4 can be connected to the anode electrode N4 of the light-emitting element ED. The fourth switching transistor T4 can be turned on by the transmit signal EM and supply a drive current Id to the anode electrode N4 of the light-emitting element ED.

[0081] The gate electrode of the fifth switching transistor T5 can receive a third scan signal SCAN3. Here, the third scan signal SCAN3 can be a signal with a different phase than the first scan signal SCAN1 supplied to the sub-pixel SP at different locations. For example, if the first scan signal SCAN1 is applied to the nth gate line, the third scan signal SCAN3 can use the first scan signal SCAN1[n-1] applied to the (n-1)th gate line. That is, the third scan signal SCAN3 can use the first scan signal SCAN1, which changes the gate line GL according to the phase driving the display panel 110.

[0082] An initialization voltage Vini can be supplied to the second electrode (e.g., the drain electrode) of the fifth switching transistor T5. The first electrode (e.g., the source electrode) of the fifth switching transistor T5 can be connected to the gate electrode N2 of the driving transistor DRT and the storage capacitor Cst. The fifth switching transistor T5 can be turned on by the third scan signal SCAN3, and the initialization voltage Vini can be supplied to the gate electrode N2 of the driving transistor DRT. Therefore, the fifth switching transistor T5 can be referred to as the initialization transistor, and the third scan signal SCAN3 can be referred to as the initialization scan signal.

[0083] A fourth scan signal SCAN4 can be supplied to the gate electrode of the sixth switching transistor T6. A reset voltage VAR can be supplied to the first electrode (e.g., the source electrode) of the sixth switching transistor T6. The second electrode (e.g., the drain electrode) of the sixth switching transistor T6 can be connected to the anode electrode N4 of the light-emitting element ED. The sixth switching transistor T6 can be turned on by the fourth scan signal SCAN4 and supply the reset voltage VAR to the anode electrode N4 of the light-emitting element ED.

[0084] A fifth scan signal SCAN5 can be supplied to the gate electrode of the seventh switching transistor T7. A bias voltage VOBS can be supplied to the first electrode (e.g., the source electrode) of the seventh switching transistor T7. The second electrode (e.g., the drain electrode) of the seventh switching transistor T7 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0085] Here, the fifth scan signal SCAN5 can be a signal with a different phase than the third scan signal SCAN3 supplied to the sub-pixel SP at different locations. For example, if the third scan signal SCAN3 is applied to the nth gate line, then the fifth scan signal SCAN5 can be the third scan signal SCAN3 applied to the (n-1)th gate line. That is, the fifth scan signal SCAN5 can utilize the third scan signal SCAN3, which changes the gate line GL according to the phase driving the display panel 110.

[0086] Meanwhile, since the fifth scan signal SCAN5 is used to apply the bias voltage VOBS to the driving transistor DRT, it is desirable to distinguish the fifth scan signal SCAN5 from the second scan signal SCAN2 used to apply the data voltage Vdata.

[0087] The gate electrode N2 of the driving transistor DRT can be connected to the second electrode (e.g., the drain electrode) of the first switching transistor T1. The first electrode (e.g., the source electrode) N1 of the driving transistor DRT can be connected to the second electrode (e.g., the drain electrode) of the second switching transistor T2. The second electrode (e.g., the drain electrode) N3 of the driving transistor DRT can be connected to the first electrode (e.g., the source electrode) of the first switching transistor T1.

[0088] The driving transistor DRT can be turned on by the voltage difference between the gate electrode N2 and the first electrode (e.g., the source electrode) N1, and the driving current Id can be applied to the light-emitting element ED.

[0089] The first electrode (e.g., source electrode) and the second electrode (e.g., drain electrode) of the first switching transistor T1 can be connected to the second electrode (e.g., drain electrode) N3 and the gate electrode N2 of the driving transistor DRT, respectively. Furthermore, if the first switching transistor T1 is turned on, the operation of sampling and compensating the threshold voltage of the driving transistor DRT by applying the data voltage Vdata to the first electrode (e.g., source electrode) N1 of the driving transistor DRT can be performed.

[0090] A high-potential drive voltage VDD can be supplied to one side of the storage capacitor Cst, and the other side of the storage capacitor Cst can be connected to the gate electrode N2 of the driving transistor DRT. The storage capacitor Cst can store the voltage of the gate electrode N2 of the driving transistor DRT.

[0091] The anode N4 of the light-emitting element ED can be connected to the second electrode (e.g., drain electrode) of the fourth switching transistor T4 and the second electrode (e.g., drain electrode) of the sixth switching transistor T6. A low potential base voltage VSS can be applied to the cathode electrode of the light-emitting element ED.

[0092] The light-emitting element ED can emit light at a predetermined brightness by the drive current Id flowing through the driving transistor DRT.

[0093] In this case, an initialization voltage Vini can be supplied to stabilize the change in capacitance formed at the gate electrode N2 of the driving transistor DRT, and a reset voltage VAR can be supplied to reset the anode electrode N4 of the light-emitting element ED.

[0094] If the fourth switching transistor T4, which is located between the anode electrode N4 of the light-emitting element ED and the second electrode (e.g., the drain electrode) N3 of the driving transistor DRT, is turned off and the reset voltage VAR is supplied to the anode electrode N4 of the light-emitting element ED, then the anode electrode N4 of the light-emitting element ED can be reset.

[0095] The sixth switching transistor T6, which supplies the reset voltage VAR, can be connected to the anode N4 of the light-emitting element ED.

[0096] In this way, the sub-pixel SP, consisting of eight transistors DRT, T1, T2, T3, T4, T5, T6 and T7 and a storage capacitor Cst, can be called an 8T1C structure.

[0097] Here, the 8T1C structure is shown as an example of various structures for a subpixel SP circuit, and the structure and number of transistors and capacitors constituting the subpixel SP can vary in various ways. Furthermore, each of the multiple subpixel SPs can have the same structure, and some subpixels in the multiple subpixel SPs can have different structures.

[0098] Figure 3 An example of a cross-section of a display area in a display panel according to an embodiment of the present disclosure is shown.

[0099] Reference Figure 3 The display panel 110 according to the embodiments of the present disclosure may include a substrate SUB, a driving transistor DRT, a planarization layer PLN, a light-emitting element ED, an encapsulation layer ENCAP, and a touch layer.

[0100] The substrate SUB may include a first substrate SUB1, a substrate insulating film IPD, and a second substrate SUB2. The substrate insulating film IPD may be located between the first substrate SUB1 and the second substrate SUB2.

[0101] Moisture penetration can be prevented by configuring the substrate SUB with a first substrate SUB1, a substrate insulating film IPD, and a second substrate SUB2.

[0102] For example, the first substrate SUB1 and the second substrate SUB2 can be polyimide (PI) substrates. The first substrate SUB1 can be referred to as the primary PI substrate, and the second substrate SUB2 can be referred to as the secondary PI substrate.

[0103] Various patterns (e.g., ACT, SD1, and GATE) for forming transistors such as driving transistors DRT, various insulating films (e.g., MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, and PAS0), and various metal patterns (e.g., TM, GM, ML1, and ML2) can be disposed on the substrate SUB.

[0104] For example, a multi-buffer layer MBUF can be disposed on a second substrate SUB2, and a first active buffer layer ABUF1 can be disposed on the multi-buffer layer MBUF.

[0105] The first metal layer ML1 and the second metal layer ML2 can be disposed on the first active buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 can be light-shielding layers LS for blocking light.

[0106] The second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. An active layer ACT, on which a driving transistor DRT is disposed, can be disposed on the second active buffer layer ABUF2.

[0107] A gate insulating film GI can be set to cover the active layer ACT.

[0108] The gate electrode GATE of the driving transistor DRT can be disposed on the gate insulating film GI. In this case, at a location different from where the driving transistor DRT is formed, the gate material layer GM can be disposed on the gate insulating film GI together with the gate electrode GATE of the driving transistor DRT.

[0109] A first interlayer insulating film (ILD1) can be provided to cover the gate electrode (GATE) and the gate material layer (GM). A metal pattern (TM) can be provided on the first interlayer insulating film (ILD1). The metal pattern (TM) can be located at a location different from the formation location of the driving transistor (DRT).

[0110] A second interlayer insulating film ILD2 can be formed on the first interlayer insulating film ILD1 to cover the metal pattern TM.

[0111] Two first source-drain electrode patterns SD1 can be formed on the second interlayer insulating film ILD2. One of the two first source-drain electrode patterns SD1 is the source node of the driving transistor DRT, and the other is the drain node of the driving transistor DRT.

[0112] The two first source-drain electrode patterns SD1 can be electrically connected to one side and the other side of the active layer ACT through the contact holes of the second interlayer insulating film ILD2, the first interlayer insulating film ILD1 and the gate insulating film GI, respectively.

[0113] Simultaneously, the second interlayer insulating film ILD2 may include a second-first interlayer insulating film ILD2-1 and a second-second interlayer insulating film ILD2-2. The second-first interlayer insulating film ILD2-1 may be configured to cover a metallic pattern TM. The second-second interlayer insulating film ILD2-2 may be positioned on the second-first interlayer insulating film ILD2-1.

[0114] The portion of the active layer ACT that overlaps with the gate electrode GATE can be a channel region. One of the two first source-drain electrode patterns SD1 can be connected to one side of the channel region in the active layer ACT, and the other of the two first source-drain electrode patterns SD1 can be connected to the other side of the channel region in the active layer ACT.

[0115] A passivation layer PAS0 can be set to cover the two first source-drain electrode patterns SD1. A planarization layer PLN can be set on the passivation layer PAS0.

[0116] The planarization layer PL may include a first planarization layer PLN1 and a second planarization layer PLN2. The planarization layer PLN may be formed from an organic insulating material such as acrylic resin.

[0117] A first planarization layer PLN1 can be set on the passivation layer PAS0.

[0118] A second source-drain electrode pattern SD2 can be formed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 (corresponding to) through the contact holes of the first planarization layer PLN1. Figure 2 The second drain electrode N3 of the driving transistor DRT in the sub-pixel SP.

[0119] The second planarization layer PLN2 can be configured to cover the second source-drain electrode pattern SD2. The light-emitting element ED can be disposed on the second planarization layer PLN2.

[0120] A light-emitting element (ED) may include an anode electrode (AE), an emission layer (EL), and a cathode electrode (CE).

[0121] The anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source-drain electrode pattern SD2 through the contact holes of the second planarization layer PLN2.

[0122] A dam can be set to cover a portion of the anode electrode AE. The portion of the dam corresponding to the emission area EA of the sub-pixel SP can be opened or removed.

[0123] A portion of the anode electrode AE ​​may be exposed to an opening in the dam bank (e.g., an opening portion).

[0124] The emitter layer (EL) can be located on one side of the dam bank and on the opening (opening portion) of the dam bank. All or part of the emitter layer (EL) can be located between adjacent dam banks. The emitter layer (EL) can include an organic membrane.

[0125] In the opening of the dam bank, the emitter layer EL can contact the anode electrode AE. A cathode electrode CE can be placed on the emitter layer EL.

[0126] The encapsulation layer ENCAP can be set on the light-emitting element ED.

[0127] The encapsulation layer ENCAP can have a single-layer or multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0128] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic films, and the second encapsulation layer PCL can be an organic film. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL can be the thickest. Therefore, the second encapsulation layer PCL can be used as a planarization layer.

[0129] The first encapsulation layer PAS1 can also be called the first inorganic encapsulation layer, the second encapsulation layer PCL can also be called the organic encapsulation layer, and the third encapsulation layer PAS2 can also be called the second inorganic encapsulation layer.

[0130] The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and can be positioned closest to the light-emitting element ED. The first encapsulation layer PAS1 can be formed from an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer PAS1 can be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), or aluminum oxide (Al2O3). Because the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere, it can prevent damage to the emitter layer EL, which includes organic materials susceptible to high-temperature atmospheres, during the deposition process.

[0131] The second encapsulation layer PCL can be formed with a smaller area than the first encapsulation layer PAS1. In this case, the second encapsulation layer PCL can be formed to expose both ends of the first encapsulation layer PAS1. The organic encapsulation layer PCL can act as a buffer to reduce the stress between each layer caused by the bending of the display device 100, and can also be used to enhance planarization performance.

[0132] For example, the second encapsulation layer PCL can be formed from acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC), and can also be formed from organic insulating materials. For example, the second encapsulation layer PCL can be formed by inkjet printing.

[0133] A third encapsulation layer, PAS2, may be formed on the second encapsulation layer, PCL, to cover the top and side surfaces of each of the second encapsulation layer, PCL, and the first encapsulation layer, PAS1. The third encapsulation layer, PAS2, may minimize or prevent external moisture or oxygen from penetrating into the first encapsulation layer, PAS1, and the second encapsulation layer, PCL.

[0134] For example, the third encapsulation layer PAS2 can be formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3).

[0135] Meanwhile, the display device 100 of this disclosure may have a touch sensor TS formed on the encapsulation layer ENCAP to detect the touch of a user's finger or pen.

[0136] If the touch sensor TS is the type that is built into the display panel 110, the touch sensor TS can be disposed on the encapsulation layer ENCAP. The touch sensor structure will be described in detail below.

[0137] A touch buffer membrane (T-BUF) can be set on the encapsulation layer ENCAP.

[0138] The touch sensor TS can be set on the touch buffer membrane T-BUF.

[0139] The touch sensor TS may include a touch sensor metal TSM and a bridging metal BRG positioned in different layers.

[0140] The touch sensor metal TSM and bridging metal BRG can be formed from a Ti / Al / Ti triple structure.

[0141] A touch interlayer insulating film (T-ILD) can be placed between the touch sensor metal TSM and the bridging metal BRG.

[0142] The touch interlayer insulating film (T-ILD) can be formed from inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the T-ILD can be formed from inorganic materials such as silicon oxide (SiOx) to improve touch performance.

[0143] For example, a touch sensor TS may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal positioned adjacent to each other.

[0144] If a third touch sensor metal exists between the first touch sensor metal and the second touch sensor metal, and the first touch sensor metal and the second touch sensor metal are to be electrically connected to each other, the first touch sensor metal and the second touch sensor metal can be electrically connected to each other through a bridging metal BRG in different layers.

[0145] The bridging metal BRG can be insulated from the third touch sensor metal via the interlayer insulating film T-ILD.

[0146] When the touch sensor TS is formed on the display panel 110, chemical solutions (e.g., developer solutions or etchants) used in the process may be generated from the outside or moisture may be generated.

[0147] Because the touch sensor TS is mounted on the touch buffer film T-BUF, chemical solutions or moisture can be prevented from penetrating into the emitter layer EL, which contains organic matter, during the manufacturing process of the touch sensor TS.

[0148] Therefore, the touch buffer film T-BUF can prevent damage to the emitter layer EL, which is susceptible to liquids or moisture.

[0149] Touch buffer films (T-BUFs) can be formed at low temperatures (e.g., 100°C) or lower and can be formed from organic insulating materials with low dielectric constants to prevent damage to the emitter layer (EL), which includes organic materials susceptible to high temperatures. For example, touch buffer films (T-BUFs) can be formed from acrylic, epoxy, or siloxane-based materials.

[0150] When the display device 100 is bent, the encapsulation layer ENCAP may be damaged due to bending, and the touch sensor metal TSM located on the touch buffer film T-BUF may be broken. Even if the display device 100 is bent, the encapsulation layer ENCAP can be prevented from being damaged, or the touch sensor metal TSM or bridging metal BRG can be prevented from being damaged, by using the touch buffer film T-BUF with planarization properties made of organic insulating material.

[0151] A protective layer PAC can be provided to cover the touch sensor TS. The protective layer PAC can be an organic insulating film.

[0152] Meanwhile, during the process of forming the display panel 110 into a thin film, if the thickness of the second encapsulation layer PCL corresponding to the organic encapsulation layer becomes less than the reference thickness, the second encapsulation layer PCL may not be properly applied to the upper part of the light-emitting element ED, which may cause the light-emitting element ED to be exposed to the outside or moisture to enter the display panel.

[0153] Figure 4 This is an example of a cross-sectional photograph of the encapsulation layer formed on the upper part of the embankment in a display device.

[0154] Reference Figure 4 The display device 100 can open a portion of the dam BANK located on the upper part of the planarization layers PLN1 and PLN2, and form the emission area EA where the light-emitting element ED is located.

[0155] With the emitter region EA formed, an encapsulation layer can be formed to cover the emitter region EA and the BANK. The encapsulation layer can be formed as a stacked structure in which an organic encapsulation layer is disposed between inorganic encapsulation layers. Here, only the organic encapsulation layer PCL is shown.

[0156] The organic encapsulation layer (PCL) can be formed with various thicknesses. In this case, if the PCL is formed with a thickness lower than the reference thickness, the emitter region (EA) may not be properly covered.

[0157] In this situation, the light-emitting element located in the emission area EA may be exposed to the outside or external moisture may enter, resulting in defects.

[0158] Therefore, even if the thickness of the organic encapsulation layer PCL is reduced, it is still necessary to form a structure in which the organic encapsulation layer PCL is appropriately applied to the light-emitting element ED.

[0159] This problem primarily occurs in the case of an organic encapsulation layer (PCL), but it can also occur during the formation of an inorganic encapsulation layer (PAS). Therefore, the following description focuses on structures in which an organic encapsulation layer (PCL) is applied, but it can also be applied to cases where the inorganic encapsulation layer (PAS) is not properly applied to the emitter region (EA).

[0160] The display device 100 of this disclosure can form a dam with a dual-pattern structure located below the encapsulation layer ENCAP, such that the encapsulation layer ENCAP (especially the organic encapsulation layer PCL) can be properly applied along the emission region EA.

[0161] Figure 5 This is a plan view of a display device according to an embodiment of the present disclosure, showing a case where a double-pattern structure is formed around the emission area. Furthermore, Figure 6 It is a cross-sectional view taken along the A-A' direction of the sub-pixels of the dike with a double pattern structure.

[0162] Reference Figure 5 and Figure 6 In the display device 100 according to the embodiments of the present disclosure, the display area DA of the display panel 110 may have sub-pixels that emit multiple colors.

[0163] For example, the display area DA of the display panel 110 may include a red sub-pixel SPr that emits red, a green sub-pixel SPg that emits green, and a blue sub-pixel SPb that emits blue.

[0164] Each subpixel SP can emit a color specified by the light-emitting element ED formed in the emission region EA, and can form a dam BANK around the emission region EA to define the emission region EA.

[0165] In this case, the display device 100 of this disclosure can form a dam BANK with a structure in which a first dam BANK1 and a second dam BANK2 are stacked to define a transmission area EA.

[0166] The first dam BANK1 can be formed on the planarization layer PLN with a first dam thickness TB1 to define the emission region EA.

[0167] The first bank BANK1 may include black pigment and may be made of organic or inorganic materials.

[0168] The second dam BANK2 can be formed on the first dam BANK1 with a second dam thickness TB2. The second dam thickness TB2 can be less than the first dam thickness TB1. For example, the second dam thickness TB2 of the second dam BANK2 can be 1 μm or less, and the first dam thickness TB1 of the first dam BANK1 can be 1 μm to 2 μm.

[0169] The second dam, BANK2, can be configured to be separated from the launch area EA by a dam separation distance DB. The dam separation distance DB can be from 1 μm to 5 μm.

[0170] The second dam BANK2 may include a first patterned area PA1 and a second patterned area PA2 formed on the first dam BANK1 with different thicknesses.

[0171] The first pattern area PA1 of the second dam BANK2 can be the area of ​​the second dam thickness TB2 that forms the second dam BANK2, and the second pattern area PA2 can be formed to be lower than the second dam thickness TB2 and positioned adjacent to the emission area EA.

[0172] A second pattern area PA2 can be set in a circular shape along the shape of the emission area EA at the outer edge of the emission area EA.

[0173] During the process of forming the emission region EA using a full-tone mask, a second pattern region PA2 can be formed using a half-tone mask.

[0174] Therefore, the second embankment BANK2 can be described as a stepped structure having a first patterned area PA1 and a second patterned area PA2.

[0175] The second dam BANK2 can be formed of a transparent material, and the transparent material forming the second dam BANK2 can be one of polyimide, acrylic acid, and benzocyclobutene (BCB).

[0176] In the second dam BANK2, the second pattern region PA2 can be formed between the emission region EA and the first pattern region PA1.

[0177] In the second dam BANK2, the thickness of the second pattern region PA2 can be less than the thickness of the first pattern region PA1.

[0178] Therefore, the encapsulation layer ENCAP, especially the organic encapsulation layer PCL, formed on the second dam BANK2 can be easily shaped to cover the emission region EA, because the material used for the encapsulation layer can easily flow down from the first patterned region PA1 to the second patterned region PA2 at a lower position.

[0179] In this case, even if the organic encapsulation layer PCL is formed to be 10 μm or smaller, the encapsulation layer ENCAP or the organic encapsulation layer PCL can be formed to cover the emission region EA.

[0180] Meanwhile, the display device 100 of this disclosure can form the second BANK2 as including a third pattern region PA3 formed as a valley pattern between sub-pixels SP, so as to improve the flow of the encapsulation layer ENCAP between sub-pixels SP.

[0181] Figure 7 This is a plan view of a dam structure including a valley pattern between sub-pixels in a display device according to an embodiment of the present disclosure. Furthermore, Figure 8 It is a cross-sectional view of a levee structure including a valley pattern, cut along the B-B' direction, and Figure 9 This is a cross-sectional view of a dike structure with a valley pattern cut along the C-C' direction.

[0182] Reference Figures 7 to 9 In the display device 100 according to the embodiments of the present disclosure, sub-pixels emitting multiple colors can be arranged in the display area DA of the display panel 110.

[0183] Each subpixel SP can emit a color specified by the light-emitting element ED formed in the emission region EA, and can form a dam BANK around the emission region EA to define the emission region EA.

[0184] In this case, the display device 100 of the present disclosure may include a first dam BANK1 for defining the transmission area EA and a second dam BANK2 formed on the first dam BANK1 around the first dam BANK1.

[0185] The first dam BANK1 can be formed on the upper portion of the planarization layer PLN with a first dam thickness TB1 to define the emission region EA.

[0186] The first bank BANK1 may include black pigment and may be made of organic or inorganic materials.

[0187] The second dam BANK2 can be formed on the first dam BANK1 with a second dam thickness TB2. The second dam thickness TB2 can be less than the first dam thickness TB1. For example, the second dam thickness TB2 of the second dam BANK2 can be 1 μm or less, and the first dam thickness TB1 of the first dam BANK1 can be 1 μm to 2 μm.

[0188] The second dam BANK2 may include a first patterned area PA1 and a third patterned area PA3 formed on the first dam BANK1 with different thicknesses.

[0189] The first pattern area PA1 of the second dam BANK2 can be the area of ​​the second dam thickness TB2 that forms the second dam BANK2, and the third pattern area PA3 can be formed as a valley pattern between sub-pixels SP.

[0190] The third pattern region PA3 can extend in a straight line structure between sub-pixels SP and can be formed as a valley pattern lower than the second dam thickness TB2, so that the upper encapsulation layer ENCAP, especially the organic encapsulation layer PCL, can be easily extended and applied.

[0191] However, it is effective to form a third pattern area PA3 so that the lower first embankment BANK1 is not exposed.

[0192] During the process of forming the emission region EA using a full-tone mask, a third pattern region PA3 can be formed using a half-tone mask.

[0193] Therefore, the second dam BANK2 can be formed with a structure including a first pattern region PA1 and a third pattern region PA3.

[0194] The second dam BANK2 can be formed of a transparent material, and the transparent material forming the second dam BANK2 can be one of polyimide, acrylic acid, and benzocyclobutene (BCB).

[0195] Since the third patterned region PA3 in the second dam BANK2 is formed to have a smaller thickness than the first patterned region PA1, the encapsulation layer ENCAP, especially the organic encapsulation layer PCL, formed on the second dam BANK2 can flow downward from the first patterned region PA1 along the lower position of the third patterned region PA3 to effectively cover the emission region EA.

[0196] Therefore, even if the organic encapsulation layer PCL is formed on the bank with a thickness of 10 μm or less, the encapsulation layer ENCAP or the organic encapsulation layer PCL can be formed to cover the emission region EA.

[0197] In this case, the third pattern region PA3 of the second dam BANK2 extending between sub-pixels SP can extend to connect the emission region EA of the sub-pixels SP, or it can extend only to a portion of the outer region of the sub-pixels SP.

[0198] Figure 10 This is a plan view showing a case in a display device according to an embodiment of the present disclosure where the valley pattern of the second embankment extends only to a portion of the outer region between sub-pixels.

[0199] Reference Figure 10 In the display device 100 according to an embodiment of the present disclosure, the third pattern region PA3 of the second dam BANK2 extending between sub-pixels SP may extend only to a portion of the outer region of the sub-pixels SP. In this case, the third pattern region PA3 of the second dam BANK2 may be formed as a structure in which the sub-pixels SP are disconnected.

[0200] Furthermore, the dam BANK of the display device 100 of this disclosure can be formed as a first pattern area PA1 and a second pattern area PA2 surrounding the emission area EA, and a third pattern area PA3 consisting of valley patterns between sub-pixels SP.

[0201] Figure 11 This is a plan view of a dam structure in a display device according to an embodiment of the present disclosure, including a double pattern located around the emission area and a valley pattern between sub-pixels.

[0202] Reference Figure 11 According to the embodiments of the present disclosure, the display device 100 can form the BANK below the encapsulation layer ENCAP as a stacked structure of a first BANK1 and a second BANK2, and can form the second BANK2 around the emission region EA as a dual-pattern structure of a first pattern region PA1 and a second pattern region PA2.

[0203] Therefore, the encapsulation layer ENCAP, especially the organic encapsulation layer PCL formed on the second dam BANK2, can easily flow down from the first patterned region PA1 to the second patterned region PA2 at a lower position, making it easy to apply the emission region EA.

[0204] Furthermore, the display device 100 of this disclosure can easily apply an encapsulation layer ENCAP between sub-pixels SP by including a third pattern region PA3 formed as a valley pattern between sub-pixels SP, thereby improving the flowability of the encapsulation layer ENCAP between sub-pixels SP.

[0205] Furthermore, the display device 100 of this disclosure can form a protrusion at the position where the third pattern region PA3 of the valley pattern overlaps, thereby enabling the encapsulation layer ENCAP, and in particular the organic encapsulation layer PCL, to flow more effectively along the third pattern region PA3.

[0206] Figure 12 This is a plan view of a dam structure including protrusions between sub-pixels in a display device according to an embodiment of the present disclosure. Furthermore, Figure 13 It is a cross-sectional view of the embankment structure, including the protruding portion, cut along the D-D' direction, and Figure 14 This is a cross-sectional view of the embankment structure, including the protruding portion, cut along the E-E' direction.

[0207] Reference Figures 12 to 14 In the display device 100 according to the embodiments of the present disclosure, the display area DA of the display panel 110 may have sub-pixels that emit multiple colors.

[0208] Each subpixel SP can emit a color specified by the light-emitting element ED formed in the emission region EA, and can form a dam BANK around the emission region EA to define the emission region EA.

[0209] In this case, the display device 100 of the present disclosure may include a first dam BANK1 for defining the transmission area EA and a second dam BANK2 formed on the first dam BANK1 around the first dam BANK1.

[0210] The first dam BANK1 can be formed on the planarization layer PLN with a first dam thickness TB1 to define the emission region EA.

[0211] The first group BANK1 may include black pigment and may be made of organic or inorganic materials.

[0212] The second dam BANK2 can be formed of a transparent material, and the transparent material forming the second dam BANK2 can be one of polyimide, acrylic acid, and benzocyclobutene (BCB).

[0213] The second dam BANK2 may include a transparent material formed on the first dam BANK1 with a second dam thickness TB2. The second dam thickness TB2 may be less than the first dam thickness TB1. For example, the second dam thickness TB2 of the second dam BANK2 may be 1 μm or less, and the first dam thickness TB1 of the first dam BANK1 may be 1 μm to 2 μm.

[0214] The second dam BANK2 may include a first pattern area PA1 and a third pattern area PA3.

[0215] The first pattern area PA1 of the second dam BANK2 can be the area that forms the thickness TB2 of the second dam, and the third pattern area PA3 can be formed as a valley pattern between sub-pixels SP.

[0216] The third pattern area PA3 can extend in a straight line structure between sub-pixels SP, allowing the upper encapsulation layer ENCAP, especially the organic encapsulation layer PCL, to be easily extended and applied.

[0217] During the process of forming the emission region EA using a full-tone mask, a third pattern region PA3 can be formed using a half-tone mask.

[0218] In this case, since the third pattern region PA3 extends between sub-pixels SP, areas where the third pattern regions PA3 overlap with each other can be formed.

[0219] The display device 100 of this disclosure can form a fourth pattern region PA4 including a protrusion at the position where the third pattern region PA3 overlaps, thereby allowing the encapsulation layer ENCAP to extend well along the third pattern region PA3.

[0220] The fourth pattern region PA4 may include a protruding structure that extends beyond the second embankment thickness TB2. Furthermore, the fourth pattern region PA4 may include a recessed portion that is partially recessed at the top of the protruding structure.

[0221] In this case, the bottom of the recessed portion can be formed at a position higher than the thickness TB2 of the second dike.

[0222] Simultaneously, spacers can be formed in some areas between sub-pixels SP. Therefore, the fourth pattern area PA4, including the protruding portion, can be located in areas where spacers are not formed.

[0223] In this case, the spacer can be formed above the fourth pattern area PA4. Therefore, during the deposition of a protective film, such as an outer coating, on the upper portion, the contact between the mask and the display panel 110 can be minimized, and the fourth pattern area PA4 can be prevented from contacting the mask.

[0224] In this way, in the display device 100 of this disclosure, the fourth patterned region PA4 constituting the second dam BANK2 can be formed at a higher position than the first patterned region PA1, and the third patterned region PA3 can be formed at a lower position than the first patterned region PA1. Therefore, the encapsulation layer ENCAP, particularly the organic encapsulation layer PCL, formed on the second dam BANK2 can easily flow downward from the fourth patterned region PA4 along the first patterned region PA1 and the third patterned region PA3 to effectively cover the emission region EA.

[0225] Therefore, even if the organic encapsulation layer PCL is formed on the bank as 10 μm or smaller, the encapsulation layer ENCAP or the organic encapsulation layer PCL can be formed to cover the emission region EA.

[0226] The implementation methods of the present disclosure described above are summarized below.

[0227] A display device according to embodiments of the present disclosure may include: a display panel including a display area having a plurality of sub-pixels disposed therein; and a driving circuit configured to drive the display panel. The display area may include: a first dam defining an emission area of ​​the plurality of sub-pixels; and a second dam on the first dam, the second dam including a multi-patterned area of ​​different thicknesses.

[0228] The first dike may include black pigment formed to the thickness of the first dike.

[0229] The second dike can be a transparent dike with a thickness less than that of the first dike.

[0230] The thickness of the first dike can be from 1 μm to 2 μm, and the thickness of the second dike can be 1 μm or less.

[0231] The multi-pattern region may include a first pattern region having a second dam thickness, and a second pattern region having a thickness less than the second dam thickness between the first pattern region and the emission region.

[0232] The second pattern area can be located between the first pattern area and the emission area.

[0233] The second pattern area can be formed along the outside of the emitting area in the same shape as the emitting area.

[0234] The separation distance between the emission region and the second pattern region can be from 1 μm to 5 μm.

[0235] The multi-pattern region may also include a third pattern region formed as a valley pattern between multiple sub-pixels.

[0236] The multi-pattern region may include a first pattern region having a second embankment thickness and a third pattern region having a valley pattern formed between multiple sub-pixels.

[0237] The third pattern area can be extended to connect multiple sub-pixels.

[0238] The depth of the third pattern area can be less than the thickness of the second dike.

[0239] The third pattern region can be located in at least some regions between adjacent sub-pixels.

[0240] The multi-pattern area may also include a fourth pattern area, which includes a protrusion at the location where the third pattern area overlaps.

[0241] The fourth pattern area can be formed in the area where the spacers are not located.

[0242] The fourth pattern area can be formed below the spacers.

[0243] The fourth pattern area may include an upwardly projecting protrusion and a recessed portion that is partially recessed at the top of the protrusion.

[0244] The recessed portion may include a bottom formed at a location above the thickness of the second dike.

[0245] The display panel may also include an encapsulation layer formed on the second layer. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer having a thickness of 10 μm or less formed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer formed on the organic encapsulation layer.

[0246] A display panel according to an embodiment of the present disclosure may include a plurality of sub-pixels, a first dike defining an emission region of the plurality of sub-pixels, and a second dike on the first dike including a multi-patterned region of different thicknesses.

[0247] The display panel according to embodiments of this disclosure may further include an encapsulation layer formed on a second layer. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer having a thickness of 10 μm or less formed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer formed on the organic encapsulation layer.

[0248] The foregoing description has been presented to enable any person skilled in the art to implement and use the technical concepts of this disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and figures provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention.

Claims

1. A display device, comprising: The display panel includes a display area with multiple sub-pixels; as well as A driving circuit, configured to drive the display panel, The display area includes a first dike defining the emission area of ​​the plurality of sub-pixels and a second dike formed on the first dike. The second embankment includes a first pattern area and a second pattern area. The thickness of the second pattern region is less than the thickness of the first pattern region.

2. The display device according to claim 1, wherein, The first dike comprises black pigment having a first dike thickness.

3. The display device according to claim 2, wherein, The second dike is a transparent dike with a thickness less than that of the first dike.

4. The display device according to claim 3, wherein, The thickness of the first dike is 1 μm to 2 μm, and the thickness of the second dike is 1 μm or less.

5. The display device according to claim 1, wherein, The second pattern area is located between the first pattern area and the emission area.

6. The display device according to claim 5, wherein, The second patterned area is formed along the outside of the emission area in the same shape as the emission area.

7. The display device according to claim 6, wherein, The second patterned area is formed with a separation distance between it and the emission area.

8. The display device according to claim 7, wherein, The separation distance between the emission area and the second pattern area is 1 μm to 5 μm.

9. The display device according to claim 3, wherein, The second embankment also includes a third pattern region, which includes at least one valley pattern between the plurality of sub-pixels.

10. The display device according to claim 9, wherein, The third pattern region extends to connect the plurality of sub-pixels.

11. The display device according to claim 10, wherein, The depth of the third pattern region is less than the thickness of the second dike.

12. The display device according to claim 9, wherein, The third pattern region is located in at least some regions between adjacent sub-pixels.

13. The display device according to claim 9, wherein, The second embankment also includes a fourth patterned area, which includes a protrusion at the location where the third patterned area overlaps.

14. The display device according to claim 13, wherein, The fourth pattern area is formed in the area where the spacers are not located.

15. The display device according to claim 14, wherein, The fourth patterned area is formed below the spacer.

16. The display device according to claim 13, wherein, The fourth patterned area includes a recessed portion that is partially recessed at the top of the protruding portion.

17. The display device according to claim 16, wherein, The recessed portion includes a bottom formed at a position higher than the thickness of the second dike.

18. The display device according to claim 1, wherein, The display panel also includes an encapsulation layer formed on the second embankment. The encapsulation layer includes: First inorganic encapsulation layer; An organic encapsulation layer with a thickness of 10 μm or less is formed on the first inorganic encapsulation layer; and A second inorganic encapsulation layer is formed on the organic encapsulation layer.

19. A display panel, comprising: Multiple sub-pixels; A first dike defines the emission area of ​​the plurality of sub-pixels; as well as The second dike is formed on top of the first dike. The second embankment includes a first pattern area and a second pattern area. The thickness of the second pattern region is less than the thickness of the first pattern region.

20. The display panel of claim 19, further comprising an encapsulation layer formed on the second diaphragm, in, The encapsulation layer includes: First inorganic encapsulation layer; An organic encapsulation layer with a thickness of 10 μm or less is formed on the first inorganic encapsulation layer; and A second inorganic encapsulation layer is formed on the organic encapsulation layer.

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