Display panel and display device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2024-09-30
- Publication Date
- 2026-06-02
Smart Images
Figure CN122139472A_ABST
Abstract
Description
Display panel and display device TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND
[0002] In the related art, a periodic brightness burr problem occurs in a display panel, thereby affecting the display effect.
[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.
[0004] SUMMARY
[0005] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel comprises a pixel driving circuit and a light emitting unit, the pixel driving circuit comprises a driving transistor and a sixth transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit, and the display panel further comprises:
[0006] a substrate substrate;
[0007] a first gate layer located on one side of the substrate substrate, the first gate layer comprising an enable signal line, a projection of the enable signal line on the substrate substrate extending in a first direction, and part of a structure of the enable signal line being used to form a gate of the sixth transistor;
[0008] a first source-drain layer located on a side of the first gate layer away from the substrate substrate, the first source-drain layer comprising a first bridge portion connected between the second electrode of the sixth transistor and the first electrode of the light emitting unit;
[0009] wherein a projection of the first bridge portion on the substrate substrate and a projection of the enable signal line on the substrate substrate do not overlap.
[0010] In an exemplary embodiment of the present disclosure, the first source-drain layer further comprises a second bridge portion, and the display panel further comprises:
[0011] a second source-drain layer, the second source-drain layer comprising a third bridge portion and a first conductive portion, the third bridge portion being connected to the first bridge portion through a first via, and the first conductive portion being connected to the second bridge portion through a second via;
[0012] An area of a projection of the opening of the first via facing the second source-drain layer on the substrate substrate is less than an area of a projection of the opening of the second via facing the second source-drain layer on the substrate substrate.
[0013] In an example embodiment of the present disclosure, a ratio of the area of the projection of the opening of the first via facing the second source-drain layer on the substrate substrate and the area of the projection of the opening of the second via facing the second source-drain layer on the substrate substrate is greater than or equal to 5 / 6 and less than or equal to 1.
[0014] In an example embodiment of the present disclosure, the first conductive part is a data line, and the data line is configured to provide a data line to the pixel driving circuit.
[0015] In an example embodiment of the present disclosure, the display panel further comprises:
[0016] The second source-drain layer comprises a third bridge part, and the third bridge part is connected to the first bridge part through a first via.
[0017] The third bridge part comprises a first via connection part and a second via connection part, the first via connection part is connected to the first bridge part through a first via, and the second via connection part is connected to the first electrode of the light emitting unit through a third via.
[0018] The projection of the second via connection part on the substrate substrate is located on a side of the projection of the first via connection part on the substrate substrate away from the projection of the enable signal line on the substrate substrate.
[0019] In an example embodiment of the present disclosure, the display panel further comprises:
[0020] The second source-drain layer comprises a third bridge part, and the third bridge part is connected to the first bridge part through a first via.
[0021] The projection of the third bridge part on the substrate substrate and the projection of the enable signal line on the substrate substrate do not overlap.
[0022] In an example embodiment of the present disclosure, the display panel further comprises:
[0023] The second source-drain layer comprises a third bridge part, and the third bridge part comprises a first via connection part, a second via connection part, and a connection part connected between the first via connection part and the second via connection part, the first via connection part is connected to the first bridge part through a first via, and the second via connection part is connected to the first electrode of the light emitting unit through a third via.
[0024] The first via connection portion is located on one side of the substrate away from the enable signal line.
[0025] In an example embodiment of the present disclosure, the second via connection portion is at least partially overlapped with the enable signal line on the substrate.
[0026] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel comprises a pixel driving circuit and a light emitting unit, the pixel driving circuit comprises a driving transistor and a sixth transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light emitting unit, and the display panel further comprises:
[0027] a substrate;
[0028] a first gate layer located on one side of the substrate, the first gate layer comprises an enable signal line, the enable signal line is extended along a first direction on the substrate, and part of the structure of the enable signal line is used to form a gate of the sixth transistor;
[0029] a first source-drain layer located on a side of the first gate layer away from the substrate, the first source-drain layer comprises a first bridge portion, and the first bridge portion is connected between the second electrode of the sixth transistor and the first electrode of the light emitting unit;
[0030] The first bridge portion is partially overlapped with the enable signal line on the substrate.
[0031] a conductive block, the conductive layer where the conductive block is located is between the first gate layer and the first source-drain layer, the conductive block is used to receive a direct current voltage signal, and the overlapped part of the first bridge portion and the enable signal line on the substrate and the conductive block on the substrate are at least partially overlapped.
[0032] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a storage capacitor, the first electrode of the storage capacitor is connected to the gate of the driving transistor, the second electrode of the storage capacitor is connected to a first power supply line, the first gate layer further comprises a second conductive portion, and the second conductive portion is used to form the first electrode of the storage capacitor.
[0033] The display panel further comprises:
[0034] a second gate layer between the first gate layer and the first source-drain layer, the second gate layer comprising a third conductive part, a footprint of the third conductive part on the substrate and a footprint of the second conductive part on the substrate overlap, the third conductive part being configured to form a second electrode of the storage capacitor;
[0035] The second gate layer comprises the conductive block, and the conductive block is connected to the third conductive part.
[0036] In an example embodiment of the present disclosure, the display panel further comprises an initial signal line configured to provide an initial signal to the pixel driving circuit, and the conductive block is connected to the initial signal line.
[0037] In an example embodiment of the present disclosure, the display panel comprises a plurality of initial signal lines, and the plurality of initial signal lines comprises a second initial signal line.
[0038] The pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit, and the conductive block is connected to the second initial signal line.
[0039] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel comprises a pixel driving circuit and a light emitting unit, the pixel driving circuit comprises a driving transistor, a sixth transistor, and a storage capacitor.
[0040] A first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit.
[0041] A first electrode of the storage capacitor is connected to a gate of the driving transistor, and a second electrode of the storage capacitor is connected to a first power supply line.
[0042] The display panel further comprises:
[0043] a substrate;
[0044] a first gate layer on one side of the substrate, the first gate layer comprising an enable signal line, a footprint of the enable signal line on the substrate extends in a first direction, and part of a structure of the enable signal line is configured to form a gate of the sixth transistor;
[0045] a first source-drain layer on a side of the first gate layer away from the substrate, the first source-drain layer comprising a first bridging part, the first bridging part being connected between a second electrode of the sixth transistor and the first electrode of the light emitting unit.
[0046] The ratio of the parasitic capacitance between the first bridge portion and the enable signal line and the capacitance of the storage capacitor is less than or equal to 1 / 70.
[0047] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected to the second initial signal line, a second electrode of the seventh transistor being connected to the first electrode of the light emitting unit, and a gate electrode of the seventh transistor being connected to a second reset signal line.
[0048] The enable signal line is used to change from low level to high level at a first time point, and the second reset signal line is used to change from high level to low level at a second time point, wherein the time difference between the first time point and the second time point is less than or equal to 4H, and H is the time length of the data writing stage of the pixel driving circuit.
[0049] According to an aspect of the present disclosure, a display device is provided, comprising the display panel as described above.
[0050] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0051] The drawings incorporated into the specification and forming part of the specification, show embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.
[0052] FIG. 1 is a display panel whose brightness change is detected by a photosensitive sensor;
[0053] FIG. 2 is a structure diagram of a pixel driving circuit in an example embodiment of the display panel detected by the photosensitive sensor;
[0054] FIG. 3 is a structure diagram of an example embodiment of the display panel detected by the photosensitive sensor;
[0055] FIG. 4 is a partial structure layout of an example embodiment of the display panel of the present disclosure;
[0056] FIG. 5 is a structure layout of a second source-drain layer in FIG. 4;
[0057] FIG. 6 is a structure layout of a first active layer and a first gate layer in FIG. 4;
[0058] FIG. 7 is a structure layout of a first active layer, a first gate layer and a first source-drain layer in FIG. 4;
[0059] FIG. 8 is a partial structure layout of an example embodiment of the display panel of the present disclosure;
[0060] Fig. 9 is a structure layout of the second source-drain layer in Fig. 8;
[0061] Fig. 10 is a structure layout of the first active layer, the first gate layer in Fig. 8;
[0062] Fig. 11 is a structure layout of the first active layer, the first gate layer, the first source-drain layer in Fig. 8;
[0063] Fig. 12 is a structure layout of the first active layer, the first gate layer, the first source-drain layer, the second source-drain layer in Fig. 8;
[0064] Fig. 13 is a partial structure layout in an exemplary embodiment of the display panel of the present disclosure;
[0065] Fig. 14 is a structure layout of the second gate layer in Fig. 13;
[0066] Fig. 15 is a structure layout of the first active layer, the first gate layer in Fig. 13;
[0067] Fig. 16 is a structure layout of the first active layer, the first gate layer, the second gate layer in Fig. 13;
[0068] Fig. 17 is a structure layout of the first active layer, the first gate layer, the second gate layer, the first source-drain layer in Fig. 13;
[0069] Fig. 18 is a structure schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure;
[0070] Fig. 19 is a timing diagram of each node in an exemplary driving method of the pixel driving circuit shown in Fig. 18;
[0071] Fig. 20 is a luminance variation diagram of the display panel shown in Figs. 4-17;
[0072] Fig. 21 is a partial cross-sectional view of the display panel shown in Fig. 13 along the dotted line AA. DETAILED DESCRIPTION
[0073] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be simplified or omitted.
[0074] The terms "one", "an", "said" are intended to replace one or more elements / components / etc.; the terms "include" and "have" are intended to mean open-ended inclusion and refer to additional elements / components / etc. in addition to the listed elements / components / etc.
[0075] As shown in FIG. 1, a display panel brightness change detected by a photosensitive sensor. As can be seen from FIG. 1, the display panel will periodically occur brightness glitches (the dotted circle position in the figure).
[0076] As shown in FIG. 2, a pixel driving circuit structure diagram in an exemplary embodiment of the display panel detected by the photosensitive sensor. The pixel driving circuit includes a driving transistor T3, a sixth transistor T6, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode of the light emitting unit L.
[0077] As shown in FIG. 3, a structure diagram of an exemplary embodiment of the display panel detected by the photosensitive sensor. The display panel further includes: a substrate, a first gate layer, a first source-drain layer, the first gate layer is located on one side of the substrate, the first gate layer includes an enable signal line EM, the orthogonal projection of the enable signal line EM on the substrate extends along the first direction X, and part of the structure of the enable signal line EM is used to form the gate of the sixth transistor T6; the first source-drain layer is located on the side of the first gate layer away from the substrate, and the first source-drain layer includes a first bridge portion 41 connected between the second electrode of the sixth transistor T6 and the first electrode D1 of the light emitting unit; wherein the orthogonal projection of the first bridge portion 41 on the substrate and the orthogonal projection of the enable signal line EM on the substrate at least partially overlap.
[0078] As shown in FIGS. 2 and 3, a parasitic capacitor is formed between the enable signal line EM and the first bridge portion 41. In the scanning stage, the enable signal line EM changes from low to high, and under the coupling effect of the parasitic capacitor, the first bridge portion 41 is pulled high, so that the first electrode D1 of the light emitting unit is pulled high, and the light emitting unit will appear brightness glitches.
[0079] Based on this, the present exemplary embodiment provides a display panel, which includes a substrate, a first active layer, a first gate layer, a first source-drain layer, a second source-drain layer, and an electrode layer which are sequentially stacked. The above-mentioned structure layers have an insulating layer therebetween. As shown in FIGS. 4-7, FIG. 4 is a partial structure layout in an exemplary embodiment of the display panel of the present disclosure, FIG. 5 is a structure layout of the second source-drain layer in FIG. 4, FIG. 6 is a structure layout of the first active layer and the first gate layer in FIG. 4, and FIG. 7 is a structure layout of the first active layer, the first gate layer, and the first source-drain layer in FIG. 4.
[0080] The display panel further includes: a substrate substrate, a first gate layer, a first source-drain layer, the first gate layer is located on one side of the substrate substrate, the first gate layer includes an enable signal line EM, the orthogonal projection of the enable signal line EM on the substrate substrate extends along a first direction X, the first direction X can be a row direction, and part of the structure of the enable signal line EM is used to form a gate of the sixth transistor T6; the first source-drain layer is located on the side of the first gate layer away from the substrate substrate, and the first source-drain layer includes a first bridge portion 41, and the first bridge portion 41 is connected between the second electrode of the sixth transistor T6 and the first electrode D1 of the light-emitting unit; wherein the orthogonal projection of the first bridge portion 41 on the substrate substrate and the orthogonal projection of the enable signal line EM on the substrate substrate do not overlap.
[0081] The present exemplary embodiment can reduce the parasitic capacitance between the first bridge portion 41 and the enable signal line EM, thereby reducing the coupling effect of the enable signal line EM on the first bridge portion 41, and further improving the technical problem of brightness burr of the display panel.
[0082] In the present exemplary embodiment, as shown in FIGS. 4-7, part of the structure of the first active layer is used to form a channel region of a transistor in the pixel driving circuit, wherein the display panel can use the first gate layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first gate layer can form a channel region of a transistor, the region of the first active layer not covered by the first gate layer forms a conductor structure, and the part of the structure of the first gate layer covering the first active layer is used to form a gate of a transistor.
[0083] In the present exemplary embodiment, as shown in FIGS. 4-7, the first source-drain layer further includes a second bridge portion 42, and the display panel further includes: a second source-drain layer, the second source-drain layer includes a third bridge portion 53 and a first conductive portion Da, the third bridge portion 53 connects the first bridge portion 41 through a first via hole H1, and the first conductive portion Da connects the second bridge portion 42 through a second via hole H2; the area of the opening of the first via hole H1 facing the orthogonal projection of the second source-drain layer on the substrate substrate is smaller than the area of the opening of the second via hole H2 facing the orthogonal projection of the second source-drain layer on the substrate substrate. That is, the present exemplary embodiment can reduce the third via connection portion 413 in the first bridge portion 41 for connecting the first via hole H1 by reducing the size of the first via hole H1, so that the setting can avoid the orthogonal projection of the first bridge portion 41 on the substrate substrate and the orthogonal projection of the enable signal line EM on the substrate substrate from overlapping.
[0084] It should be understood that in other example embodiments, the display panel can also reduce all vias between the second source-drain layer and the first source-drain layer, and accordingly, the area of the normal projection of the opening of the first via H1 facing the second source-drain layer on the substrate substrate can also be equal to or approximately equal to the area of the normal projection of the opening of the second via H2 facing the second source-drain layer on the substrate substrate. The area of the normal projection A is approximately equal to the area of the normal projection B, which can be understood as the ratio of the difference between the area of the normal projection A and the area of the normal projection B to the area of the normal projection B being less than or equal to 5%.
[0085] In the example embodiment, the ratio of the area of the normal projection of the opening of the first via H1 facing the second source-drain layer on the substrate substrate to the area of the normal projection of the opening of the second via H2 facing the second source-drain layer on the substrate substrate is greater than or equal to 5 / 6 and less than or equal to 1. For example, the ratio can be equal to 5 / 6, 6 / 7, 7 / 8, 1, etc.
[0086] In the example embodiment, as shown in FIGS. 4-7, the first conductive part Da can be a data line for providing a data line to the pixel driving circuit, and the second bridge part 42 can be used for via connection of the pixel driving circuit. It should be understood that in other example embodiments, the display panel can also include a third source-drain layer located on the side of the second source-drain layer away from the substrate substrate, and the data line can be located on the third source-drain layer, and the first conductive part can be bridged between the data line and the second bridge part through the via.
[0087] In the example embodiment, as shown in FIGS. 4-7, the third bridge part 53 includes a first via connection part 531 and a second via connection part 532, the first via connection part 531 is connected to the first bridge part 41 through the first via H1, and the second via connection part 532 is connected to the first electrode D1 of the light emitting unit through the third via H3; wherein the normal projection of the second via connection part 532 on the substrate substrate is located on the side of the normal projection of the first via connection part 431 on the substrate substrate away from the normal projection of the enable signal line EM on the substrate substrate.
[0088] In the example embodiment, as shown in FIGS. 4-7, the normal projection of the third bridge part 53 on the substrate substrate and the normal projection of the enable signal line EM on the substrate substrate do not overlap. This arrangement can reduce the parasitic capacitance between the enable signal line EM and the third bridge part 43, thereby reducing the coupling effect of the enable signal line EM on the first electrode D1 of the light emitting unit through the third bridge part 53, and further reducing the brightness burr problem of the display panel.
[0089] The present example embodiment also provides another display panel, as shown in FIGS. 8-12, FIG. 8 is a partial structure layout in an example embodiment of the display panel of the present disclosure, FIG. 9 is a structure layout of a second source-drain layer in FIG. 8, FIG. 10 is a structure layout of a first active layer and a first gate layer in FIG. 8, FIG. 11 is a structure layout of the first active layer, the first gate layer, and a first source-drain layer in FIG. 8, and FIG. 12 is a structure layout of the first active layer, the first gate layer, the first source-drain layer, and a second source-drain layer in FIG. 8.
[0090] In the present example embodiment, as shown in FIGS. 8-12, the third bridge portion 53 also includes a first via connection portion 531, a second via connection portion 532, and a connection portion 533 connected between the first via connection portion 531 and the second via connection portion 532, the first via connection portion 531 is used to connect the first bridge portion 41 through a first via H1, and the second via connection portion 532 is used to connect a first electrode D1 of the light-emitting unit through a third via H3; wherein the orthographic projection of the first via connection portion 531 on the substrate is located on the side of the orthographic projection of the connection portion 533 on the substrate away from the orthographic projection of the enable signal line EM on the substrate. That is, in the present example embodiment, the first bridge portion 41 and the third bridge portion 53 are inverted in the second direction Y, so that the orthographic projection of the first bridge portion 41 on the substrate and the orthographic projection of the enable signal line EM1 on the substrate do not overlap. The second direction can be the column direction.
[0091] In the present example embodiment, as shown in FIGS. 8-12, unlike the display panel shown in FIG. 4, the present example embodiment does not need to reduce the first via H1, so that the area of the orthographic projection of the opening of the first via H1 facing the second source-drain layer on the substrate can be equal to or approximately equal to the area of the orthographic projection of the opening of the second via H2 facing the second source-drain layer on the substrate.
[0092] In the present example embodiment, as shown in FIGS. 8-12, the orthographic projection of the second via connection portion 532 on the substrate and the orthographic projection of the enable signal line EM on the substrate at least partially overlap. Wherein, since the distance between the second via connection portion 532 and the enable signal line EM in the direction perpendicular to the substrate is far, even if the orthographic projection of the second via connection portion 532 on the substrate and the orthographic projection of the enable signal line EM on the substrate at least partially overlap, this arrangement can also improve the problem of brightness burr of the display panel.
[0093] In addition, in other example embodiments, the orthographic projection of the second via connection portion 532 on the substrate and the orthographic projection of the enable signal line EM on the substrate can also not overlap.
[0094] The present example embodiment also provides another display panel, which further comprises a second gate layer between the first gate layer and the first source-drain layer. As shown in FIGS. 13-17, FIG. 13 is a partial structure layout in an example embodiment of the display panel of the present disclosure, FIG. 14 is a structure layout of the second gate layer in FIG. 13, FIG. 15 is a structure layout of the first active layer and the first gate layer in FIG. 13, FIG. 16 is a structure layout of the first active layer, the first gate layer and the second gate layer in FIG. 13, and FIG. 17 is a structure layout of the first active layer, the first gate layer, the second gate layer and the first source-drain layer in FIG. 13.
[0095] In the example embodiment, the display panel also comprises: a substrate, a first gate layer, and a first source-drain layer. The first gate layer is located on one side of the substrate, and the first gate layer comprises an enable signal line EM, a projection of the enable signal line EM on the substrate extends along a first direction X, and part of the structure of the enable signal line EM is used to form a gate of the sixth transistor T6. The first source-drain layer is located on a side of the first gate layer away from the substrate, and the first source-drain layer comprises a first bridge portion 41 connected between a second electrode of the sixth transistor T6 and a first electrode D1 of the light-emitting unit.
[0096] Different from the above-mentioned embodiments, in the example embodiment, a projection of the first bridge portion on the substrate and a projection of the enable signal line EM on the substrate partially overlap. The display panel further comprises a conductive block 24, the conductive layer where the conductive block 24 is located is between the first gate layer and the first source-drain layer, and the conductive block 24 is used to receive a direct current voltage signal, i.e., the voltage on the conductive block 24 is stable when the display panel is working. The overlapping part of the projection of the first bridge portion 41 on the substrate and the projection of the enable signal line EM on the substrate and the projection of the conductive block 24 on the substrate at least partially overlap.
[0097] In the example embodiment, the conductive block 24 with stable voltage can shield the first bridge portion 41 and the enable signal line EM, so as to reduce the coupling effect of the enable signal line EM on the first bridge portion 41, and thus improve the problem of brightness burr of the display panel.
[0098] As shown in FIG. 18, a structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure is shown. In the exemplary embodiment, the display panel can include the pixel driving circuit shown in FIG. 18. As shown in FIGS. 13-18, the pixel driving circuit can further include a storage capacitor C, a first electrode of the storage capacitor C is connected to a gate of the driving transistor T3, a second electrode of the storage capacitor C is connected to a first power supply line VDD, and the first gate layer can further include a second conductive part 12 for forming the first electrode of the storage capacitor C. The display panel further includes a second gate layer between the first gate layer and the first source-drain layer, the second gate layer includes a third conductive part 23, a projection of the third conductive part 23 on the substrate overlaps a projection of the second conductive part 12 on the substrate, and the third conductive part 23 is used for forming a second electrode of the storage capacitor C; wherein the second gate layer includes the conductive block 24 connected to the third conductive part 23. The conductive block 24 can be connected to the first power supply line VDD through the third conductive part 23, so that the conductive block 24 can have a stable voltage.
[0099] As shown in FIG. 18, the display panel can further include a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3, and the initial signal lines have a stable voltage. The conductive block 24 can be connected to any one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3.
[0100] In the display panel shown in FIGS. 4-17, a ratio of a parasitic capacitance between the first bridge part 41 and the enable signal line EM and a capacitance value of the storage capacitor C can be less than or equal to 1 / 70. For example, the ratio of the parasitic capacitance between the first bridge part 41 and the enable signal line EM and the capacitance value of the storage capacitor C can be equal to 1 / 70, 1 / 75, 1 / 80, 1 / 85, 1 / 90, 1 / 95, 1 / 100, etc.
[0101] As shown in Fig. 18, the pixel driving circuit can further include a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, and an eighth transistor T8. The first electrode of the fourth transistor T4 is connected to a data line Da, the second electrode of the fourth transistor T4 is connected to the first electrode of a driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to a second gate driving signal terminal GT2. The first electrode of the fifth transistor T5 is connected to a first power supply line VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fifth transistor T5 is connected to an enable signal line EM. The gate electrode of the driving transistor T3 is connected to a node N. The first electrode of the second transistor T2 is connected to the node N, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, the gate electrode of the second transistor T2 is connected to a first gate driving signal terminal GT1, the first electrode of the seventh transistor T7 is connected to a second initial signal line Vinit2, and the gate electrode of the seventh transistor T7 is connected to a second reset signal line Re2. The first electrode of the first transistor T1 is connected to a first initial signal line Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate electrode of the first transistor T1 is connected to a first reset signal line Re1. The first electrode of the eighth transistor T8 is connected to a third initial signal line Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate electrode of the eighth transistor T8 is connected to the second reset signal line Re2. The pixel driving circuit can be used to drive a light emitting unit L. The first electrode of the light emitting unit L can be connected to the second electrode of a sixth transistor T6, the second electrode of the light emitting unit L can be connected to a second power supply terminal VSS, the first electrode of the light emitting unit L can be an anode of the light emitting unit L, and the second electrode of the light emitting unit L can be a cathode of the light emitting unit L. The second transistor T2 can be an N-type transistor, for example, the second transistor T2 can be an N-type metal oxide transistor. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low temperature poly-silicon transistors.
[0102] As shown in Fig. 19, a timing diagram of each node in a driving method of the pixel driving circuit shown in Fig. 18 is shown. GT1 represents the timing of the first gate driving signal terminal GT1, GT2 represents the timing of the second gate driving signal terminal GT2, Re2 represents the timing of the second reset signal line Re2, Re1 represents the timing of the first reset signal line Re1, and EM represents the timing of the enable signal line EM. One driving period of the pixel driving circuit can include a first reset stage t1, a second reset stage t2, a data writing stage t3, a third reset stage t5, and a light emitting stage t6.
[0103] In the first reset stage t1: the second reset signal line Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal line Vinit2 inputs a second initial signal to the first electrode of the light emitting unit L, and the third initial signal line Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3, so as to improve the hysteresis problem of the driving transistor T3. In the second reset stage t2: the first gate drive signal end GT1 outputs a high level, the first reset signal line Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal line Vinit1 inputs a first initial signal to the node N through the first transistor T1 and the second transistor T2. In the data writing stage t3: the second gate drive signal end GT2 outputs a low level signal, the first gate drive signal end GT1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data line Da writes a compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, wherein Vdata is the voltage of the data signal on the data line, and Vth is the threshold voltage of the driving transistor T3. In the third reset stage t5: the second reset signal line RE2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal line Vinit2 inputs a second initial signal to the first electrode of the light emitting unit L, and the third initial signal line Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the light emitting stage t6: the enable signal line EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the storage capacitor C. The driving transistor output current formula is as follows: I=(μWCox / 2L)(Vgs-Vth) 2
[0104] Wherein I is the output current of the driving transistor; μ is the carrier mobility; Cox is the unit area gate storage capacitance, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the driving transistor threshold voltage. The output current I of the driving transistor in the above pixel driving circuit=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
[0105] The display panel shown in FIGS. 4-17 can also improve the brightness burr described above by timing adjustment. For example, as shown in FIG. 19, the enable signal line EM is used to start changing from low to high at a first time K1, and the second reset signal line Re2 is used to change from high to low at a second time K2, wherein the time difference between the first time and the second time is less than or equal to 4H, and H is the time length of the pixel driving circuit in the data writing stage. The time difference between the first time and the second time can be equal to 1H, 2H, 3H, 4H, etc. This setting can reduce the time difference between the first time and the second time, so that the second reset signal line Re2 can reset the first electrode of the light emitting unit in time, thereby improving the problem that the first electrode part is pulled up by the enable signal line EM.
[0106] As shown in FIG. 20, it is a brightness change diagram of the display panel shown in FIGS. 4-17, and from FIG. 20 it can be seen that the display panel shown in FIGS. 4-17 can significantly improve the problem of brightness burr.
[0107] As shown in FIG. 21, it is a partial cross-sectional view of the display panel shown in FIG. 13 along the dashed line AA. The display panel can further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planar layer 108, and a second planar layer 109. Among them, the substrate 100, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the fifth insulating layer 105, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planar layer 108, the second source-drain layer, the second planar layer 109, and the electrode layer are sequentially stacked. Among them, the display panel can further include a second active layer between the fourth insulating layer 104 and the fifth insulating layer 105, and a third gate layer between the fifth insulating layer 105 and the first dielectric layer 106. Among them, the second active layer can be used to form the channel region of the oxide transistor (for example, T2 in FIG. 18) in the pixel driving circuit, and the third gate layer can be used to form the top gate of the oxide transistor in the pixel driving circuit. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planar layer 108 and the second planar layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), and the like. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer and the second source-drain layer can include metal materials, for example, one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer. The sheet resistance of any one of the first source-drain layer and the second source-drain layer can be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.
[0108] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel can also have other structures, for example, the pixel driving circuit can have a 7T1C, 9T1C, or the like structure.
[0109] It should be noted that, as shown in FIG. 3-17, the black square drawn on the side of the first source-drain layer away from the substrate substrate represents the via of the first source-drain layer connecting the other levels facing the substrate substrate side; the black rectangle drawn on the side of the second source-drain layer away from the substrate substrate represents the via of the second source-drain layer connecting the other levels facing the substrate substrate side, and the black circle drawn on the side of the electrode layer away from the substrate substrate represents the via of the electrode layer connecting the other levels facing the substrate substrate side. The vias at different positions can penetrate different insulating layers.
[0110] In addition, it should be noted that the proportions of the drawings in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of the structure. In addition, the adjectives first, second, etc. are only used to define different structure names, and do not have the meaning of a specific order. The same structure layer can be formed by the same patterning process. In the present exemplary embodiment, the orthographic projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as that the orthographic projection of the structure on the substrate substrate extends linearly or bends in the direction.
[0111] The present exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, a tablet computer, a television, or the like.
[0112] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure that follow, in general, the principles of the present disclosure and include specific designs, uses or adaptations of the present disclosure that are disclosed in the specification and examples. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the claims.
[0113] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure that follow, in general, the principles of the present disclosure and include specific designs, uses or adaptations of the present disclosure that are disclosed in the specification and examples. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the claims.
[0114] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.
Claims
1. A display panel, wherein, The display panel comprises a pixel driving circuit and a light emitting unit, the pixel driving circuit comprises a driving transistor and a sixth transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit, and the display panel further comprises: a substrate substrate; a first gate layer located on one side of the substrate substrate, the first gate layer comprising an enable signal line, a projection of the enable signal line on the substrate substrate extending in a first direction, and part of the structure of the enable signal line being used to form a gate of the sixth transistor; a first source-drain layer located on a side of the first gate layer away from the substrate substrate, the first source-drain layer comprising a first bridge portion connected between the second electrode of the sixth transistor and the first electrode of the light emitting unit; wherein the projection of the first bridge portion on the substrate substrate and the projection of the enable signal line on the substrate substrate do not overlap.
2. The display panel of claim 1, wherein, The first source-drain layer further comprises a second bridge portion, and the display panel further comprises: a second source-drain layer, the second source-drain layer comprising a third bridge portion and a first conductive portion, the third bridge portion being connected to the first bridge portion through a first via, and the first conductive portion being connected to the second bridge portion through a second via; an area of a projection of an opening of the first via facing the second source-drain layer on the substrate substrate is smaller than an area of a projection of an opening of the second via facing the second source-drain layer on the substrate substrate.
3. The display panel of claim 2, wherein, The ratio of the area of the projection of the opening of the first via facing the second source-drain layer on the substrate substrate to the area of the projection of the opening of the second via facing the second source-drain layer on the substrate substrate is greater than or equal to 5 / 6 and less than or equal to 1.
4. The display panel of claim 2, wherein, The first conductive portion is a data line, and the data line is used to provide a data line to the pixel driving circuit.
5. The display panel of claim 1, wherein, The display panel further comprises: a second source-drain layer, the second source-drain layer comprising a third bridge portion, the third bridge portion being connected to the first bridge portion through a first via; The third bridge portion comprises a first via connection portion and a second via connection portion, the first via connection portion being connected to the first bridge portion through a first via, and the second via connection portion being connected to the first electrode of the light emitting unit through a third via; wherein the projection of the second via connection portion on the substrate substrate is located on a side of the projection of the first via connection portion on the substrate substrate away from the projection of the enable signal line on the substrate substrate. The display panel further comprises:
6. The display panel of claim 1, wherein, a second source-drain layer, the second source-drain layer comprising a third bridge portion, the third bridge portion being connected to the first bridge portion through a first via; The projection of the third bridge portion on the substrate substrate and the projection of the enable signal line on the substrate substrate do not overlap. The display panel further comprises:
7. The display panel of claim 1, wherein, The second source-drain layer includes a third bridge portion, the third bridge portion includes a first via connection portion, a second via connection portion, and a connection portion connected between the first via connection portion and the second via connection portion, the first via connection portion connects the first bridge portion through a first via, and the second via connection portion connects a first electrode of the light emitting unit through a third via; The first via connection portion is located on one side of the connection portion away from the normal projection of the enable signal line on the substrate.
8. The display panel of claim 7, wherein, The normal projection of the second via connection portion on the substrate and the normal projection of the enable signal line on the substrate at least partially overlap.
9. A display panel, wherein, The display panel includes a pixel driving circuit and a light emitting unit, the pixel driving circuit includes a driving transistor and a sixth transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light emitting unit, and the display panel further includes: a substrate; a first gate layer located on one side of the substrate, the first gate layer includes an enable signal line, the normal projection of the enable signal line on the substrate extends in a first direction, and part of the structure of the enable signal line is used to form a gate of the sixth transistor; a first source-drain layer located on the side of the first gate layer away from the substrate, the first source-drain layer includes a first bridge portion, and the first bridge portion is connected between the second electrode of the sixth transistor and the first electrode of the light emitting unit; The normal projection of the first bridge portion on the substrate and the normal projection of the enable signal line on the substrate partially overlap; a conductive block, the conductive layer where the conductive block is located is between the first gate layer and the first source-drain layer, the conductive block is used to receive a direct current voltage signal, and the overlapping part of the normal projection of the first bridge portion on the substrate and the normal projection of the enable signal line on the substrate and the normal projection of the conductive block on the substrate at least partially overlap.
10. The display panel of claim 9, wherein, The pixel driving circuit further includes a storage capacitor, the first electrode of the storage capacitor is connected to the gate of the driving transistor, the second electrode of the storage capacitor is connected to a first power supply line, the first gate layer further includes a second conductive portion, and the second conductive portion is used to form the first electrode of the storage capacitor; The display panel further includes: a second gate layer located between the first gate layer and the first source-drain layer, the second gate layer includes a third conductive portion, the normal projection of the third conductive portion on the substrate and the normal projection of the second conductive portion on the substrate overlap, and the third conductive portion is used to form the second electrode of the storage capacitor; The second gate layer includes the conductive block, and the conductive block is connected to the third conductive portion.
11. The display panel of claim 9, wherein, The display panel further includes an initial signal line, the initial signal line is used to provide an initial signal to the pixel driving circuit, and the conductive block is connected to the initial signal line.
12. The display panel of claim 11, wherein, The display panel comprises a plurality of initial signal lines, and the plurality of initial signal lines comprises a second initial signal line; The pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit, and the conductive block is connected to the second initial signal line.
13. A display panel, wherein, The display panel comprises a pixel driving circuit and a light emitting unit, the pixel driving circuit comprises a driving transistor, a sixth transistor, and a storage capacitor; A first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit; A first electrode of the storage capacitor is connected to a gate electrode of the driving transistor, and a second electrode of the storage capacitor is connected to a first power supply line; The display panel further comprises: a substrate substrate; a first gate layer located on one side of the substrate substrate, the first gate layer comprising an enable signal line, a normal projection of the enable signal line on the substrate substrate extending in a first direction, and part of the structure of the enable signal line being used to form a gate electrode of the sixth transistor; a first source-drain layer located on a side of the first gate layer away from the substrate substrate, the first source-drain layer comprising a first bridge portion connected between a second electrode of the sixth transistor and a first electrode of the light emitting unit; A ratio of a parasitic capacitance between the first bridge portion and the enable signal line to a capacitance value of the storage capacitor is less than or equal to 1 / 70.
14. The display panel according to any one of claims 1-13, wherein, The pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit, and the conductive block is connected to the second initial signal line. The enable signal line is used to start changing from a low level to a high level at a first time, and the second reset signal line is used to change from a high level to a low level at a second time, wherein a time difference between the first time and the second time is less than or equal to 4H, and H is a time length of the pixel driving circuit in a data writing stage.
15. A display device, wherein, The display device comprises the display panel of any one of claims 1-14.