A radar signal processing method based on FPGA
By utilizing the collaborative processing of internal and external memories within the FPGA chip, the problems of long radar signal processing time and excessive storage resource consumption are solved, achieving efficient radar signal processing suitable for modern radar systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAHANG RADIO MEASUREMENT & RES INST
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-05
AI Technical Summary
Existing radar signal processing methods are time-consuming and consume excessive storage resources, affecting system stability and performance.
Using dual-port RAM within the FPGA chip and external memory of the DDR3 chip, radar echo signals are periodically acquired and preprocessed. The internal memory is used for accumulation and averaging calculations, while the external memory is used for transposition and subtraction to remove the azimuth DC component and perform coherent accumulation processing.
It effectively removes the azimuth DC component, improves computational efficiency, saves storage resources and computation time, and is suitable for modern radar signal processing.
Smart Images
Figure CN122151016A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radar signal processing technology, and in particular to a radar signal processing method based on FPGA. Background Technology
[0002] With the rapid development of modern radar systems and technologies, range resolution and azimuth resolution are key performance indicators for radar systems. Depending on the application scenario, radars with higher range resolution have a wider detection range for distance and are more accurate in direct ranging; radars with higher azimuth resolution have a wider detection range for direction and are more accurate in direct velocity measurement. Therefore, precise signal processing of radar signals is necessary to adapt to the needs of different application scenarios.
[0003] Currently, radar signals typically only consider removing the range-direction DC component. When the target speed is relatively high, if the azimuth DC component of the high-resolution radar echo signal is not removed, a large energy roll-off will occur near the zero frequency of the spectrum, affecting the identification of near-end targets.
[0004] In addition, in radar signal processing scenarios, the amount of data is usually large. Existing signal processing requires additional computing time, resulting in large processing delays. Furthermore, it consumes a large amount of FPGA storage resources to cache intermediate data, affecting the stability and performance of the system. Summary of the Invention
[0005] Based on the above analysis, the present invention aims to provide an FPGA-based radar signal processing method to solve the problems of long processing time and excessive storage resource consumption in existing radar signal processing methods.
[0006] This invention provides an FPGA-based radar signal processing method, comprising the following steps:
[0007] The radar echo signal is periodically acquired and preprocessed, and the range sequence data of each azimuth direction is simultaneously written into the internal memory and the external memory.
[0008] The range sequences of each azimuth direction in the internal memory are accumulated and averaged to obtain the mean values of each range sequence; the range sequence data of each azimuth direction written in the external memory are transposed, and the output sequence after transposition is subtracted from the corresponding mean value in the internal memory to obtain the azimuth data after removing the DC component.
[0009] The azimuth data after removing the DC component is subjected to coherent accumulation processing to obtain the processed radar echo signal.
[0010] Based on the further improvement of the above method, the preprocessing of radar echo signals includes: firstly, converting the high-frequency radar echo signal of each cycle to a baseband signal through digital downconversion; then, filtering, downsampling, and pulse compression of the baseband signal to obtain the radar echo signal of each azimuth direction; and finally, performing a fast Fourier transform on the radar echo signal of each azimuth direction to obtain the range sequence of each azimuth direction.
[0011] Based on a further improvement of the above method, the number of storage addresses occupied when writing to internal memory is the number of range points contained in the azimuth range sequence.
[0012] A further improvement to the above method involves accumulating the distance sequences in each direction in the internal memory by first reading the values already written to each memory address sequentially from the internal memory, then accumulating them with the corresponding values in the current distance sequence to be written, and finally overwriting the accumulated values with the corresponding memory addresses.
[0013] A further improvement to the above method involves averaging the values after accumulation by reading the accumulated values from the internal memory, dividing them by the number of azimuth points to obtain the average values in the range sequence, and then overwriting them back into the corresponding memory addresses.
[0014] Based on a further improvement of the above method, the internal memory is a dual-port RAM integrated inside the FPGA chip.
[0015] Based on a further improvement of the above method, the number of storage addresses occupied when writing to external memory is the product of the number of azimuth points and the number of range points contained in the range sequence.
[0016] A further improvement to the above method involves subtracting the mean from the corresponding mean in the internal memory of the transposed output sequence. This is done sequentially by subtracting the first mean from all azimuth data of the first range direction of the transposed output, then subtracting the second mean from all azimuth data of the second range direction of the transposed output, and so on, until the last mean is subtracted from all azimuth data of the last range direction of the transposed output.
[0017] Based on further improvements to the above method, the number of range points is obtained by multiplying the sampling frequency and the pulse duration; the number of azimuth points is determined based on the coherent processing time and pulse processing capability.
[0018] Based on further improvements to the above method, the external memory uses a DDR3 chip.
[0019] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0020] 1. Emphasizing the importance of removing the azimuth DC component, the system uses internal and external memory in conjunction with synchronous processing, eliminating the need for additional Fast Fourier Transform, thus minimizing memory and logic resource consumption and improving computational efficiency. Furthermore, the azimuth data with DC component removed is seamlessly integrated with the azimuth coherent accumulation processing, making it suitable for modern radar signal processing and facilitating the design and implementation of overall radar functions.
[0021] 2. The internal memory accumulation and average calculation are performed in parallel during the external memory transposition, which does not introduce additional operation delay, effectively ensuring operation efficiency and saving operation time.
[0022] 3. The internal memory uses a pipelining method to accumulate large amounts of data, thereby optimizing performance indicators such as computing speed and hardware resource consumption.
[0023] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0024] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0025] Figure 1 This is a flowchart of a radar signal processing method based on FPGA in an embodiment of the present invention. Detailed Implementation
[0026] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0027] A specific embodiment of the present invention discloses a radar signal processing method based on FPGA, such as... Figure 1 As shown, it includes the following steps:
[0028] S1. Periodically acquire and preprocess radar echo signals, and simultaneously write the obtained range sequence data for each azimuth direction into the internal memory and external memory.
[0029] It should be noted that when a radar emits a pulse signal, this signal propagates in all directions. When it encounters a target, part of the signal is reflected back. The original radar echo signal is periodically acquired using an AD chip and preprocessed, including:
[0030] First, the high-frequency radar echo signal of each cycle is converted to a baseband signal through digital downconversion, reducing the signal bandwidth and the complexity of subsequent processing. Then, the baseband signal is filtered to remove unnecessary frequency components and noise, the amount of data is reduced by downsampling, and the range resolution is improved by pulse compression, thereby obtaining the radar echo signal in each azimuth direction. Finally, a fast Fourier transform is performed on the radar echo signal in each azimuth direction to obtain the range sequence (i.e., range spectrum) in each azimuth direction.
[0031] It should be noted that range refers to a range in which radar signals are continuously sampled over time, and each sampling point within this range represents a different range. Because radar antennas receive signals in different azimuths, azimuth refers to the set of sampling points at the same location in multiple periodically sampled ranges, and these sampling points represent signals in different azimuths.
[0032] After preprocessing, the range sequence for each azimuth direction is output sequentially, where the range direction is continuous while the azimuth direction is discontinuous. This sequence is written to both internal and external memory simultaneously. The internal memory is a dual-port RAM integrated within the FPGA chip, which can be read and written simultaneously. The external memory uses a DDR3 (Double Data Rate 3 Synchronous Dynamic Random-Access Memory) chip.
[0033] S2. Accumulate and average the range sequences of each direction in the internal memory to obtain the mean values of each range sequence; transpose the range sequence data of each direction written in the external memory, and subtract the corresponding mean value in the internal memory from the transposed output sequence to obtain the azimuth data with the DC component removed.
[0034] It should be noted that the range sequence for each directional position has the same length, and the number of range points contained in the range sequence is obtained by multiplying the sampling frequency and the pulse duration; the number of azimuth points is determined based on the coherent processing time and pulse processing capability.
[0035] Let i represent the total number of points in the range direction, and q represent the total number of points in the azimuth direction. The range sequence data for the q azimuth directions are represented as follows: D 11 D 12 D 13 ,......,D 1i D 21 D 22 D 23 ,……,D 2i , ..., D q1 D q2D q3 ,……,D qi There is a certain time interval between two adjacent distance sequences.
[0036] (1) Write to internal memory
[0037] To save space, memory addresses start from 0, and each memory address is written with a single value. When writing to internal memory, the distance sequence in each direction is accumulated by reading data out and writing the accumulated result back to internal memory simultaneously.
[0038] Specifically, to accumulate the distance sequence in each direction in the internal memory, the process involves first reading the values already written to each memory address sequentially from the internal memory, then accumulating these values with the corresponding values in the current distance sequence to be written, and finally overwriting the accumulated values with the corresponding memory addresses.
[0039] In other words, write the first azimuth distance sequence D. 11 D 12 D 13 ,......,D 1i At this time, each memory address has no value, and the data is written to the internal memory in the order of memory addresses from 0 to i-1; the distance sequence D in the second directional direction is then written. 21 D 22 D 23 ,......,D 2i At that time, read D from memory address 0 to i-1. 11 D 12 D 13 ,......,D 1i Then, the two sequences are summed bit by bit, i.e., D 11 and D 21 Add, ..., D 1i and D 2i The two numbers are added together, and the result is then written to internal memory at addresses 0 to i-1, directly overwriting the first written D. 11 D 12 D 13 ,……,D 1i This reduces the consumption of storage resources; following the above method, the distance sequence D up to the q-th azimuth direction is obtained. q1 D q2 D q3 ,......,D qi Write, completing the accumulation of the entire sequence. The accumulated values written sequentially from memory address 0 to i-1 are:
[0040] It should be noted that when performing numerical accumulation, if the value is a fixed-point number, it is added directly, and the sign bit is extended for the maximum bit overflow; if the value is a floating-point number, it is added through the floating-point addition IP core in the FPGA design software.
[0041] Furthermore, the averaging process involves reading the accumulated value from internal memory after the accumulation is complete, dividing it by the number of points in the azimuth direction to obtain the mean value in the range sequence, and then writing it back to the corresponding memory address. That is, the mean values are written sequentially from memory address 0 to i-1.
[0042] It should be noted that when calculating the average, if q is 2 n If n is an integer, then division is performed by shifting the data, which saves logic resources and minimizes computational latency. When the accumulated value is a fixed-point number, division is performed directly by shifting. When the accumulated value is a floating-point number, division is performed by shifting the exponent. If q is 2... n However, if n is not an integer, the division operation is performed using the division IP core in the FPGA design software. By rationally selecting memory and arithmetic methods based on the data type and characteristics, the use of adders, subtractors, dividers, and registers is effectively reduced, thus lowering hardware resource consumption.
[0043] As can be seen from the above, the number of storage addresses occupied when writing to internal memory is equal to the number of range points contained in the azimuth range sequence, which greatly saves the storage resources of internal memory, as well as the computational resources of adders and dividers, and reduces the computation time.
[0044] (2) Write to external memory
[0045] While writing to internal memory, the range sequence for each direction bit is sequentially written to external memory, with each value written to a separate memory address. Therefore, the number of memory addresses occupied when writing to external memory is the product of the number of azimuth points and the number of range points contained in the range sequence. After writing all q azimuth range sequences, the sequence is transposed and output, resulting in the sequence: D 11 D 21 D 31 ,......,D q1 D 12 D 22 D 32 ,......,D q2 , ..., D 1i D 2i D 3i ,......,D qi .
[0046] Furthermore, subtracting the corresponding mean from the transposed output sequence is done sequentially by subtracting the first mean from all azimuth data in the first range direction of the transposed output, then subtracting the second mean from all azimuth data in the second range direction of the transposed output, and so on, until the last mean is subtracted from all azimuth data in the last range direction of the transposed output.
[0047] It should be noted that because the transpose operation in external memory takes longer than the calculation of the sum and mean in internal memory, after the mean is calculated and written sequentially into internal memory, the subtraction operation can begin as soon as the first sequence is output from external memory. This method of calculating the mean simultaneously with the transpose operation does not introduce any additional computational delay.
[0048] Specifically, when outputting the first range-direction azimuth sequence D 11 D 21 D 31 ,……,D q1 At this time, the first mean value is read from the internal memory (corresponding to memory address 0), and the first mean value is subtracted from each of the q values in the azimuth sequence. This process is repeated until the azimuth sequence D of the i-th range direction is finally output. 1i D 2i D 3i ,……,D qi At that time, the last mean value (corresponding to storage address i-1) is read from the internal memory, and the last mean value is subtracted from each of the q values in the azimuth sequence to obtain the azimuth data with the DC component removed.
[0049] S3. Perform coherent accumulation processing on the azimuth data after removing the DC component to obtain the processed radar echo signal.
[0050] It should be noted that this step further processes the azimuth data after removing the DC component to obtain the radar echo signal used for target identification and velocity acquisition. Coherent accumulation processing enhances signal strength by aligning and accumulating multiple signals, thereby improving the signal-to-noise ratio and obtaining the processed radar echo signal.
[0051] For example, constant false alarm rate (CFAR) processing of the processed radar echo information can detect targets and then extract information such as the target's speed and azimuth.
[0052] Compared with existing technologies, the FPGA-based radar signal processing method provided in this embodiment focuses on the importance of removing the azimuth DC component. It uses internal and external memory for synchronous processing, eliminating the need for additional Fast Fourier Transform, thus minimizing memory and logic resource consumption and improving computational efficiency. Furthermore, the azimuth data with DC component removal is seamlessly integrated with the azimuth coherent accumulation processing, making it suitable for modern radar signal processing and facilitating the design and implementation of the overall radar function. The parallel calculation of accumulation and mean value in the internal memory during external memory transposition avoids introducing additional computational delays, effectively ensuring computational efficiency and saving computation time. The internal memory employs a pipelining approach to accumulate large amounts of data, optimizing performance indicators such as computation speed and hardware resource consumption.
[0053] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0054] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A radar signal processing method based on FPGA, characterized in that, Includes the following steps: The radar echo signal is periodically acquired and preprocessed, and the range sequence data of each azimuth direction is simultaneously written into the internal memory and the external memory. The range sequences of each azimuth direction in the internal memory are accumulated and averaged to obtain the mean values of each range sequence; the range sequence data of each azimuth direction written in the external memory are transposed, and the output sequence after transposition is subtracted from the corresponding mean value in the internal memory to obtain the azimuth data after removing the DC component. The azimuth data after removing the DC component is subjected to coherent accumulation processing to obtain the processed radar echo signal.
2. The FPGA-based radar signal processing method according to claim 1, characterized in that, The preprocessing of the radar echo signal includes: first, converting the high-frequency radar echo signal of each cycle to a baseband signal through digital downconversion; then, filtering, downsampling, and pulse compression of the baseband signal to obtain the radar echo signal in each azimuth direction; and finally, performing a fast Fourier transform on the radar echo signal in each azimuth direction to obtain the range sequence in each azimuth direction.
3. The FPGA-based radar signal processing method according to claim 1, characterized in that, The number of memory addresses occupied when writing to internal memory is the number of range points contained in the azimuth range sequence.
4. The FPGA-based radar signal processing method according to claim 3, characterized in that, The process of accumulating the distance sequences in each direction in the internal memory involves first reading the values already written to each memory address sequentially from the internal memory, then accumulating them with the corresponding values in the current distance sequence to be written, and finally overwriting the accumulated values with the corresponding memory addresses.
5. The FPGA-based radar signal processing method according to claim 4, characterized in that, The averaging process involves reading the accumulated value from each memory address after the accumulation is complete, dividing it by the number of azimuth points to obtain the average value in the range sequence, and then overwriting it back into the corresponding memory address.
6. The FPGA-based radar signal processing method according to claim 1 or 3, characterized in that, The internal memory is a dual-port RAM integrated inside the FPGA chip.
7. The FPGA-based radar signal processing method according to claim 5, characterized in that, The number of memory addresses occupied when writing to external memory is the product of the number of azimuth points and the number of range points contained in the range sequence.
8. The FPGA-based radar signal processing method according to claim 5, characterized in that, The step of subtracting the mean from the transposed output sequence and the corresponding mean in the internal memory is to sequentially subtract the first mean from all azimuth data of the first range direction of the transposed output, then subtract the second mean from all azimuth data of the second range direction of the transposed output, and so on, until the last mean is subtracted from all azimuth data of the last range direction of the transposed output.
9. The FPGA-based radar signal processing method according to claim 5, characterized in that, The number of distance points is obtained by multiplying the sampling frequency and the pulse duration; the number of azimuth points is determined based on the coherent processing time and pulse processing capability.
10. The FPGA-based radar signal processing method according to claim 1, characterized in that, The external memory uses a DDR3 chip.