A fast mirror control system and method based on an FPGA platform

Abstract

The application discloses a fast reflecting mirror control system and method based on an FPGA platform and belongs to the technical field of optical control. The system comprises a host computer, external ADC and DAC, a fast reflecting mirror driving module, a fast reflecting mirror assembly and an FPGA. The FPGA is integrated with a fast feedback position processing assembly and a host computer communication, ADC data acquisition and preprocessing and DAC control and instruction output module. The communication module is bidirectionally interacted with the host computer. The ADC data acquisition and preprocessing module receives a position signal output by the external ADC and pre-processes the position signal. The fast feedback position processing assembly combines a control instruction with an actual position, generates a digital control instruction through path generation, interpolation operation and PID control, and the DAC control and instruction output module converts the instruction into an analog signal through the external DAC, drives the fast reflecting mirror assembly to move. The application solves the problems of high signal transfer delay and poor multi-task coordination in the traditional signal transfer through a highly integrated hardware control architecture in the FPGA, and realizes high-precision, low-delay response and reliable control of the fast reflecting mirror.

Description

Technical Field

[0001] This invention belongs to the field of optical control technology, specifically relating to a fast-reflecting mirror control system and method based on an FPGA (Field Programmable Gate Array) platform. Background Technology

[0002] A fast-steering mirror (FSM) is a reflective device used for high-precision, high-speed beam control, widely applied in laser communication, astronomical observation, remote sensing imaging, and laser processing. Current FSM control systems primarily employ DSPs or industrial controllers as the processing core, but these methods suffer from the following problems in practical applications:

[0003] First, while the DSP solution can perform the basic operations of the control algorithm, its inherent serial processing architecture leads to timing conflicts and computational delays when performing multiple tasks such as path planning, backscan compensation, and real-time position control. Especially in complex trajectory control processes, path calculation tasks are prone to resource contention with high-frequency position feedback processing, resulting in decreased system real-time performance and making it difficult to meet the control requirements of highly dynamic scenarios.

[0004] Secondly, industrial controller solutions, due to their fixed hardware architecture and non-reconfigurable underlying logic circuits, are difficult to customize for the high dynamic and multi-mode control requirements unique to fast-reflecting mirrors. For example, real-time correction of position deviation is required during backscanning, or millisecond-level response is needed when controlling a specified position; these requirements are difficult to fully meet under a fixed hardware architecture.

[0005] In addition, existing control systems are fragmented in the “position signal reception-algorithm processing-drive control” link: position signals usually need to be relayed through an external chip before they can be transmitted to the controller, resulting in signal transmission delay; at the same time, various functional algorithms (such as path planning and backscan) are scattered in different processing units, resulting in low coordination efficiency. For example, in the backscan process, the pre-calculation of path planning can easily interfere with the response speed of real-time position correction, affecting the overall control performance of the system.

[0006] Therefore, there is an urgent need for a fast-reflecting mirror control scheme that can effectively solve the above problems, so as to optimize the signal link and improve the efficiency of algorithm coordination, thereby meeting the stringent requirements of modern optical systems for fast-reflecting mirror control accuracy and response speed.

[0007] In view of this, the present invention is hereby proposed. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a fast reverse mirror control system and method based on an FPGA platform. It is mainly used to solve the problems of high signal transmission delay, weak multi-task coordination, insufficient control accuracy and limited response speed caused by the fixed hardware architecture in the prior art. The control accuracy of this invention is ≤ ±0.0001° and the closed-loop delay is ≤20ns, which fully meets the requirements of high-frequency reverse scanning and other scenarios.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] On the one hand, the present invention provides a fast-reflecting mirror control system based on an FPGA platform, including a host computer, an FPGA, an external ADC, an external DAC, a fast-reflecting mirror drive module and a fast-reflecting mirror component. The FPGA integrates a host computer communication module, a fast feedback position processing component, an ADC data acquisition and preprocessing module and a DAC control and command output module. Moreover, the modules within the FPGA interact with each other through a data bus and a synchronization signal to form a fully closed-loop control link.

[0011] The host computer communication module is bidirectionally connected to the host computer and is used to receive control commands issued by the host computer and to feed back status information to the host computer.

[0012] The fast feedback position processing component is connected to the host computer communication module and the ADC data acquisition and preprocessing module, respectively. It is used to generate the target position according to the control command, and combine the actual position output by the ADC data acquisition and preprocessing module to realize closed-loop control logic and generate digital control commands.

[0013] The ADC data acquisition and preprocessing module is connected to the fast feedback position processing component, and is used to receive and preprocess the real-time position feedback digital signal of the fast mirror component output by the external ADC, and send the preprocessed actual position to the fast feedback position processing component.

[0014] The DAC control and command output module is connected to the fast feedback position processing component and is used to receive the digital control command and convert it into a timing signal for output to an external DAC.

[0015] The external DAC is used to convert the timing signal into an analog drive signal and output it to the fast-reflection mirror drive module;

[0016] The fast-reflecting mirror drive module is used to drive the fast-reflecting mirror assembly to move according to the analog drive signal.

[0017] Furthermore, the ADC data acquisition and preprocessing module performs validity verification preprocessing (firstly removing abnormal data to avoid invalid data contaminating subsequent processing), moving average filtering (then filtering out noise and improving accuracy based on valid data), and format conversion (adapting to the internal calculation format) on the position feedback digital signal.

[0018] Furthermore, during the data validity verification preprocessing, the difference between the currently received location data and the previous original location is compared. If the absolute value of the difference exceeds a preset threshold of the full-scale range of the external ADC, preferably 5%, the current data is determined to be abnormal, and a re-acquisition process is triggered.

[0019] During the moving average filtering preprocessing, the window length ranges from 8 to 32 sampling points;

[0020] During the format conversion preprocessing, the binary two's complement output of the external ADC is converted into a unified fixed-point number format within the FPGA.

[0021] Furthermore, the fast feedback position processing component includes:

[0022] The parameter parsing and path point generation module is used to parse the control commands issued by the host computer and generate discrete path points.

[0023] The backscan path interpolation calculation module is connected to the parameter parsing and path point generation module and is used to interpolate the discrete path points to generate continuous, smooth and real-time target positions.

[0024] The closed-loop error calculation and PID control module is connected to the backscan path interpolation calculation module and the ADC data acquisition and preprocessing module, respectively. It is used to calculate the position error based on the target position and the actual position, and to generate the digital control command using an incremental PID algorithm.

[0025] Furthermore, the calculation formula for the incremental PID algorithm is as follows:

[0026]

[0027] in, To control the increment, Kp, Ki, and Kd are the proportional, integral, and derivative coefficients configured by the host computer, respectively, and e(k) is the current error. This represents the error increment.

[0028] Furthermore, the FPGA also integrates a clock and timing synchronization module, which generates multiple synchronous clocks through the FPGA's internal PLL and provides synchronous reset signals for the host computer communication module, fast feedback position processing component, ADC data acquisition and preprocessing module, and DAC control and command output module.

[0029] Furthermore, the FPGA also integrates a status monitoring and alarm module, which is used to monitor the operating status of each module in the system in real time. When an abnormality is detected, an alarm is triggered and the DAC control and command output module is controlled to output a zero voltage command.

[0030] On the other hand, the present invention also provides a fast-reflecting mirror control method based on an FPGA platform. This control method adopts the fast-reflecting mirror control system described above and includes the following steps:

[0031] Step 1, System Initialization and Parameter Configuration: After system initialization is completed, the host computer sends control commands to the FPGA through the host computer communication module;

[0032] Step 2, Discrete Path Point Generation: The parameter parsing and path point generation module in the fast feedback position processing component within the FPGA parses the parameters in the control command and generates discrete path points.

[0033] Step 3, Real-time target position interpolation: The discrete path points are read by the back-scan path interpolation calculation module in the fast feedback position processing component of the FPGA, and interpolation is performed according to the selected interpolation calculation mode to generate a continuous, smooth, and real-time target position.

[0034] Step 4, Position Feedback Acquisition and Preprocessing: The real-time position feedback digital signal from the fast-reflecting mirror component output by the external ADC is received through the FPGA's ADC data acquisition and preprocessing module, and the actual position is obtained after preprocessing the position feedback digital signal.

[0035] Step 5, Closed-loop error calculation and PID control: The closed-loop error calculation and PID control module in the fast feedback position processing component of the FPGA is used to calculate the position error between the target position and the preprocessed actual position, and an incremental PID algorithm is used to generate digital control commands.

[0036] Step 6, Drive Output: The digital control command is output to an external DAC through the FPGA's internal DAC control and command output module. After conversion, an analog drive signal is obtained to drive the fast-reflecting mirror assembly to move.

[0037] Step 7: Repeat steps 3 to 6 until the preset task is completed, and then the host computer issues a stop command.

[0038] Furthermore, in step 3, the interpolation operation mode includes linear interpolation mode and S-curve interpolation mode;

[0039] When linear interpolation mode is selected, the following formula is used for calculation:

[0040] Current position = Previous path point + (Current time - Previous time) × (Next path point - Previous path point) / (Next time - Previous time)

[0041] When the S-curve interpolation mode is selected, the positions of the acceleration and deceleration segments are calculated using the following cubic polynomial:

[0042]

[0043] The uniform velocity segment is calculated linearly using the following formula:

[0044]

[0045] in, , , , The coefficients are those of a cubic polynomial. For the uniform speed segment, The initial position of the uniform velocity segment. For time.

[0046] Furthermore, in step 5, the incremental PID algorithm is performed using a fixed-point number format and completes a single calculation within one clock cycle.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] 1. This invention utilizes the parallel processing capabilities and programmability of FPGAs to integrate the entire control chain into a single chip by constructing a direct data path between the ADC data acquisition and preprocessing module, the fast feedback position processing component, and the DAC control and command output module within the FPGA. This forms a fully closed-loop control process of "parameter input - path generation - position feedback - error control - command output", solving the problems of high signal transmission delay, weak multi-task coordination, and rigid hardware architecture caused by the use of DSPs or industrial controllers in existing fast mirror control schemes. It realizes a highly coordinated, extremely low-latency closed-loop control system.

[0049] 2. Based on the reconfigurable characteristics of FPGAs, this invention adopts a modular design (such as a parameter parsing and path point generation module, a backscan path interpolation calculation module, etc.). It allows for dynamic configuration of motion parameters, interpolation modes (S-curve / linear), and PID coefficients via a host computer, without requiring modification of the underlying hardware circuitry. This enables the same platform to adapt to different fast-reflection mirrors and application scenarios, significantly reducing development and subsequent maintenance costs.

[0050] 3. This invention achieves a reasonable allocation of hardware resources by mapping core algorithms (such as PID calculation and interpolation operations) to the FPGA's built-in DSP unit and storing discrete path points in BlockRAM. This allocation ensures high performance while maintaining a low logic resource occupancy rate, reserving sufficient hardware resources and expansion space for the subsequent integration of more complex control algorithms or additional functions into the system. Attached Figure Description

[0051] The accompanying drawings are incorporated in and form part of this specification, and together with the description serve to explain the principles of the invention.

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a block diagram showing the structure and connection of the fast-reflecting mirror control system based on the FPGA platform of the present invention.

[0054] Figure 2 This is a block diagram illustrating the overall closed-loop control principle of the fast-reflecting mirror control system based on the FPGA platform of this invention. Detailed Implementation

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses consistent with some aspects of the invention as detailed in the appended claims.

[0056] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0057] Please see Figure 1 and Figure 2This invention provides a fast-reflecting mirror control system based on an FPGA platform, comprising a host computer, an FPGA, an external ADC (not shown in the figure), an external DAC (not shown in the figure), a fast-reflecting mirror drive module, and a fast-reflecting mirror assembly. The host computer is primarily responsible for parameter configuration and status monitoring; the FPGA, as the core control unit of the entire system, integrates all digital logic functions, including a host computer communication module, a fast feedback position processing component, an ADC data acquisition and preprocessing module, and a DAC control and command output module; the external ADC outputs real-time position feedback digital signals from the fast-reflecting mirror assembly; the external DAC converts the FPGA's digital control commands into analog drive signals; the fast-reflecting mirror drive module drives the fast-reflecting mirror based on the analog signals; and the fast-reflecting mirror assembly is the final physical actuator. The core of this invention is to utilize the parallel processing capabilities and programmable features of FPGAs to integrate the complete control link onto a single chip, constructing a fully closed-loop control process of "parameter input - path generation - position feedback - error control - command output", forming a highly coordinated, ultra-low latency closed-loop control system. This solves the technical problems of link fragmentation, high latency, and weak coordination in traditional fast-reflecting mirror control schemes, thereby meeting the "high dynamic and multi-mode" control requirements of fast-reflecting mirrors in application scenarios such as laser tracking, astronomical observation, and remote sensing imaging.

[0058] It should be noted that the FPGA (such as the Xilinx Artix-77A35T) serves as the core of the control system of this invention. It achieves full-process closed-loop control through eight internally integrated functional modules, including "five core functional modules (ADC data acquisition and preprocessing module, DAC control and command output module, parameter parsing and path point generation module, reverse scan path interpolation calculation module, closed-loop error calculation and PID control module) + three auxiliary support modules (host computer communication module, clock and timing synchronization module, status monitoring and alarm module)". Each module interacts with the synchronization signal through the internal data bus, forming the overall closed-loop process as follows: host computer sends parameters → FPGA parses parameters and generates path → interpolation generates continuous target position → acquires the actual position of the fast reflector → calculates error and executes PID control → outputs drive command → fast reflector moves → real-time status monitoring and abnormal protection, thereby achieving precise control of the fast reflector.

[0059] Specifically, the host computer communication module undertakes the bidirectional data interaction between the FPGA and the host computer, supporting parameter configuration, data upload, and remote debugging. It has the following three functions: First, it adopts a custom frame structure (frame header 0x55 + frame type + data length + data + checksum), where the checksum is the lower eight bits of the XOR sum of the first N-1 (N is the frame length) bytes, ensuring data transmission integrity; second, the communication interface supports UART (baud rate 115200bps~1Mbps) to meet the communication needs of different host computers; third, after receiving parameters from the host computer, it first stores them in the "parameter buffer register" in the FPGA. After receiving the "parameter effective" command, it synchronizes the parameters to the corresponding functional modules (such as the parameter parsing and path point generation module, the closed-loop error calculation and PID control module), avoiding control disorder caused by parameter updates. The entire buffering and synchronization process is completed inside the FPGA.

[0060] The ADC data acquisition and preprocessing module receives the real-time position feedback digital signal from the fast-reflecting mirror component output by an external ADC (such as a 16-bit AD7606), and performs the following preprocessing: moving average filtering (the window length can be configured to 8-32 points via the host computer to effectively filter out sampling noise); data validity verification (comparing the difference between the current position data and the previous original position data; if the difference exceeds 5% of the full scale of the external ADC, the data is judged to be abnormal and a re-acquisition is triggered); format conversion (converting the binary two's complement to the fixed-point number format unified within the FPGA, such as the Q10.6 format, for easier subsequent calculations), and outputs accurate actual position data to the closed-loop error calculation and PID control module after processing.

[0061] The fast feedback position processing component in this invention comprises three core modules: a parameter parsing and path point generation module, a backscan path interpolation calculation module, and a closed-loop error calculation and PID control module. The parameter parsing and path point generation module receives backscan parameters (including motion mode, scan range, step size, maximum speed, interpolation mode, and PID parameters) synchronized from the host computer communication module, parses them, and stores them in the FPGA's BlockRAM. Based on the scan range and step size, it generates discrete path points with timestamps (e.g., 101 path points are generated when the scan start point is 0°, the end point is 1°, and the step size is 0.01°), and outputs a path enable signal. Because the generated discrete path points contain position information and timestamps, the consistency of the time base for subsequent interpolation calculations is ensured. This invention supports dynamic adaptation of the discrete path point buffer capacity (supporting a maximum of 1024 discrete path points).

[0062] Furthermore, the backscan path interpolation module is used to read discrete path points and generate continuous, smooth, and real-time target positions according to the interpolation operation mode configured by the host computer. In this invention, the interpolation operation modes include linear interpolation mode and S-curve interpolation mode. The linear interpolation mode is suitable for low-precision (control accuracy (angular displacement) ≤ ±0.01°, 485μrad) and high-speed scenarios; the S-curve interpolation mode is suitable for high-precision scenarios (control accuracy (angular displacement) ≤ ±0.0001°, ±4.85μrad), which can divide the path into acceleration, constant speed, and deceleration segments, ensuring the continuity of position, speed, and acceleration between adjacent segments and avoiding vibration.

[0063] Specifically, when linear interpolation mode is selected, the following formula is used for calculation:

[0064] Current position = Previous path point + (Current time - Previous time) × (Next path point - Previous path point) / (Next time - Previous time)

[0065] When the S-curve interpolation mode is selected, the positions of the acceleration and deceleration segments are calculated using the following cubic polynomial:

[0066]

[0067] The uniform velocity segment is calculated linearly using the following formula:

[0068]

[0069] in, , , , The coefficients are those of a cubic polynomial. For the uniform speed segment, The initial position of the uniform velocity segment. For time.

[0070] Furthermore, the closed-loop error calculation and PID control module is mainly used to compare the interpolated target position with the preprocessed actual position, calculating the position error when the valid signals of both are synchronized; it generates digital control commands through an incremental PID algorithm, the algorithm formula of which is as follows:

[0071]

[0072] in, To control the increment, Kp, Ki, and Kd are the proportional, integral, and derivative coefficients configured by the host computer, respectively, and e(k) is the current error. The increment is the error increment; this incremental PID algorithm has the advantages of low computational load and fast response speed, and can avoid integral saturation.

[0073] To further ensure control accuracy, this module incorporates an anti-integral saturation processing mechanism: when the digital control command reaches the upper limit of the external DAC output (e.g., the quantization value corresponding to ±5V), the integral operation is immediately paused, retaining only the proportional and derivative terms, effectively preventing control deviations caused by command overshoot. Simultaneously, the module employs an optimized computational design: it uses Q10.6 format fixed-point numbers for data computation, utilizes the FPGA's built-in DSP unit for efficient multiplication, and completes addition through a pipelined structure, ensuring that a single complete calculation can be completed within one clock cycle, meeting the low-latency requirements of the control system. Here, one clock cycle refers to the 50MHz clock cycle (20ns) of the PID control module. This invention decomposes the addition operation into "multi-level serial steps," buffering intermediate results in registers to allow different computational steps to be executed in parallel within the same clock cycle, ultimately achieving "one computational result output per clock cycle." The total delay for a single addition operation remains 3 clock cycles, but starting from the 4th cycle, a complete PID addition result can be output every 1 clock cycle, achieving "single-cycle output after the pipeline is fully loaded"; each stage of the pipeline uses an adder, which is directly connected to the output of the DSP multiplication unit, with no data waiting delay.

[0074] After receiving the digital control commands from the PID output, the DAC control and command output module converts them into timing signals (SPI interface signals) required by the external DAC (such as a 16-bit DAC) to drive the external DAC to output an analog voltage (±5V) and control the fast-reflecting mirror drive circuit. Specifically, it performs the following three tasks: First, command format conversion: converting the Q10.6 format PID command into a binary / two's complement format supported by the external DAC; second, timing generation: designing a dedicated control timing sequence based on the external DAC model (such as "chip select low → data output → latch signal pulse → chip select high") to ensure stable data writing; and third, command buffering: using a 256-bit deep FIFO to buffer data and avoid data loss due to the PID output rate exceeding the DAC update rate.

[0075] The clock and timing synchronization module uses the FPGA's internal PLL (phase-locked loop) to multiply / divide the external crystal oscillator clock (e.g., 50MHz) into multiple synchronous clocks (100MHz for the ADC data acquisition and preprocessing module to ensure sampling stability; 200MHz for the backscan path interpolation module to ensure trajectory smoothness; and 50MHz for the closed-loop error calculation and PID control module and the DAC control and instruction output module to ensure the accuracy of control instructions), and generates synchronous reset signals for each module. It employs a "two-stage register synchronization" approach for control signals to avoid metastability, and an "asynchronous FIFO" approach for data signals (e.g., position data) to achieve buffering and synchronization, ensuring reliable data transmission.

[0076] The status monitoring and alarm module samples the operating status signals of each module in real time, such as data anomalies in the ADC position acquisition and preprocessing module, error over-threshold errors in the closed-loop error calculation and PID control module, and output anomalies in the DAC control and command output module. It identifies anomalies and performs multi-level processing: anomaly detection (if the above-mentioned anomaly signals are detected and persist for 3 clock cycles, a fault is determined); multi-level alarms (triggering a hardware alarm, with the FPGA pin outputting a high level to drive an LED; triggering a host computer alarm, with the alarm code uploaded via the host computer communication module); and emergency protection (when a fault occurs, the DAC control and command output module outputs a zero command to reset the fast-reflecting mirror assembly to its initial position, preventing hardware damage), significantly improving system fault tolerance.

[0077] Combination Figure 1 It can be seen that the various modules inside the FPGA form signal links with the external hardware: the host computer interacts with the FPGA through the host computer communication module; the FPGA receives the position feedback from the external ADC through the ADC data acquisition and preprocessing module; after processing by the fast feedback position processing component, it drives the external DAC through the DAC control and command output module; then the fast reflector drive module controls the movement of the fast reflector component; finally, the position signal of the fast reflector component is fed back to the external ADC, forming a closed loop. Combined with... Figure 2 It can be seen that the internal modules of the FPGA work together in the logical order of "parameter parsing - path interpolation - error calculation - PID control - instruction output". The clock and timing synchronization module provides timing support, and the status monitoring and alarm module provides full protection. Together, they realize the high-precision and fast-response control of the fast-reflecting mirror. Compared with the traditional DSP solution (serial operation, high latency) and the industrial controller solution (fixed hardware, poor adaptability), the closed-loop control latency of this system is ≤20ns. Moreover, the modular and reconfigurable design supports dynamic parameter configuration, has excellent hardware resource utilization, and reserves space for subsequent functional expansion.

[0078] In this invention, the host computer serves as the parameter configuration and status monitoring terminal for the control system. It achieves bidirectional communication with the host computer communication module inside the FPGA via an RS422 interface. Its main functions include: sending backscan parameters (including motion mode, scan range, step size, maximum speed, interpolation mode, PID parameters, etc.) and scan trigger and stop commands; receiving real-time position data of the fast-reflecting mirror component, operating status information of each module of the system, and fault alarm codes (such as external ADC abnormality, PID error overshoot, external DAC abnormality) fed back by the FPGA.

[0079] Based on the above-mentioned control system, this invention also provides a fast-reflecting mirror control method based on an FPGA platform, which specifically includes the following steps:

[0080] Step 1, System Initialization and Parameter Configuration: After power-on, the clock and timing synchronization module generates multiple synchronous clocks through the FPGA's internal PLL and provides synchronous reset signals for each functional module. After completion, the host computer sends back-scan control commands to the FPGA's host computer communication module through the RS422 interface. These commands include motion mode, scan range, step size, maximum speed, interpolation mode (linear / S-curve), PID parameters (Kp, Ki, Kd), etc.

[0081] Step 2, Discrete Path Point Generation: The parameter parsing and path point generation module receives and parses the parameters in the above control instructions, generates discrete target path points with timestamps, and stores them in the BlockRAM of the FPGA.

[0082] Step 3: Real-time target position interpolation: The backscan path interpolation module reads the discrete path points mentioned above and generates a continuous, smooth, and real-time target position according to the set interpolation operation mode.

[0083] Step 4, Position Feedback Acquisition and Preprocessing: The real-time position feedback digital signal from the fast-reflecting mirror component output by the external ADC is received through the ADC data acquisition and preprocessing module, and the actual position is obtained after preprocessing the position feedback digital signal.

[0084] Step 5: Closed-Loop Error Calculation and PID Control: The closed-loop error calculation and PID control module calculates the position error between the target position and the actual position data when they are synchronized. It then uses an incremental PID algorithm to generate digital control commands. This algorithm also integrates an anti-integral saturation mechanism, automatically pausing the integral term when the control quantity reaches the DAC output limit. Through the FPGA's built-in DSP unit and pipeline design, fixed-point arithmetic is completed within a single clock cycle, achieving microsecond-level response.

[0085] Step 6, Drive Output: The DAC control and command output module converts the Q10.6 format digital command output by the PID into a binary format supported by the DAC, and buffers the data through a 256-bit deep FIFO. The module drives the external DAC according to a dedicated timing sequence (chip select pull-low → data output → latch pulse → chip select pull-high), outputting ±5V analog voltage to the fast-reflecting mirror drive module to control the movement of the fast-reflecting mirror actuator.

[0086] Step 7: Loop Execution: Repeat steps 3 to 6 to form a hard real-time closed-loop control of "position acquisition - interpolation calculation - error adjustment - drive output". When the preset scanning task is completed, the host computer issues a stop command. During this period, the host computer can dynamically adjust the control commands and switch them through a parameter caching mechanism.

[0087] It should be noted that this invention uses an FPGA-internal status monitoring and alarm module to monitor and protect the operating status of each module throughout the entire process. When an abnormality is detected and continues for 3 clock cycles, three levels of protection are immediately triggered: the FPGA pin outputs a high level to drive the hardware alarm indicator; an alarm code is sent to the host computer via UART; and at the same time, the DAC outputs a zero command to safely reset the fast mirror.

[0088] The above description is merely a specific embodiment of the present invention, intended to enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments without creative effort will be readily apparent to those skilled in the art; the basic principles defined herein can be applied to other embodiments without departing from the spirit and scope of the present invention.

[0089] It should be understood that this invention is not limited to the specific content described above, and various equivalent modifications or substitutions can be made without departing from its scope of protection. The scope of protection of this invention is defined only by the appended claims.

Claims

1. A fast-reflecting mirror control system based on an FPGA platform, characterized in that, It includes a host computer, FPGA, external ADC, external DAC, fast mirror drive module and fast mirror component. The FPGA integrates a host computer communication module, fast feedback position processing component, ADC data acquisition and preprocessing module and DAC control and command output module. The modules in the FPGA interact with each other through data bus and synchronization signal to form a closed-loop control link. The host computer communication module is bidirectionally connected to the host computer and is used to receive control commands issued by the host computer and to feed back status information to the host computer. The fast feedback position processing component is connected to the host computer communication module and the ADC data acquisition and preprocessing module, respectively. It is used to generate the target position according to the control command, and combine the actual position output by the ADC data acquisition and preprocessing module to realize closed-loop control logic and generate digital control commands. The ADC data acquisition and preprocessing module is connected to the fast feedback position processing component, and is used to receive and preprocess the real-time position feedback digital signal of the fast mirror component output by the external ADC, and send the preprocessed actual position to the fast feedback position processing component. The DAC control and command output module is connected to the fast feedback position processing component and is used to receive the digital control command and convert it into a timing signal for output to an external DAC. The external DAC is used to convert the timing signal into an analog drive signal and output it to the fast-reflection mirror drive module; The fast-reflecting mirror drive module is used to drive the fast-reflecting mirror assembly to move according to the analog drive signal.

2. The fast-reflecting mirror control system according to claim 1, characterized in that, The ADC data acquisition and preprocessing module performs validity verification preprocessing, moving average filtering, and format conversion on the position feedback digital signal.

3. The fast-reflecting mirror control system according to claim 2, characterized in that, During the data validity verification preprocessing, the difference between the currently received location data and the previous original location is compared. If the absolute value of the difference exceeds the preset threshold of the full-scale range of the external ADC, the current data is determined to be abnormal, and a re-acquisition process is triggered. During the moving average filtering preprocessing, the window length ranges from 8 to 32 sampling points; During the format conversion preprocessing, the binary two's complement output of the external ADC is converted into a unified fixed-point number format within the FPGA.

4. The fast-reflecting mirror control system according to claim 1, characterized in that, The fast feedback position processing component includes: The parameter parsing and path point generation module is used to parse the control commands issued by the host computer and generate discrete path points. The backscan path interpolation calculation module is connected to the parameter parsing and path point generation module and is used to interpolate the discrete path points to generate continuous, smooth and real-time target positions. The closed-loop error calculation and PID control module is connected to the backscan path interpolation calculation module and the ADC data acquisition and preprocessing module, respectively. It is used to calculate the position error based on the target position and the actual position, and to generate the digital control command using an incremental PID algorithm.

5. The fast-reflecting mirror control system according to claim 4, characterized in that, The calculation formula for the incremental PID algorithm is as follows: in, To control the increment, Kp, Ki, and Kd are the proportional, integral, and derivative coefficients configured by the host computer, respectively, and e(k) is the current error. This represents the error increment.

6. The fast-reflecting mirror control system according to claim 1, characterized in that, The FPGA also integrates a clock and timing synchronization module, which generates multiple synchronous clocks through the FPGA's internal PLL and provides synchronous reset signals for the host computer communication module, fast feedback position processing component, ADC data acquisition and preprocessing module, and DAC control and command output module.

7. The fast-reflecting mirror control system according to claim 1, characterized in that, The FPGA also integrates a status monitoring and alarm module, which is used to monitor the operating status of each module in the system in real time. When an abnormality is detected, an alarm is triggered and the DAC control and command output module is controlled to output a zero voltage command.

8. A fast-reflecting mirror control method based on an FPGA platform, characterized in that, The fast-reflective mirror control system as described in any one of claims 1 to 7 includes the following steps: Step 1, System Initialization and Parameter Configuration: After system initialization is completed, the host computer sends control commands to the FPGA through the host computer communication module; Step 2, Discrete Path Point Generation: The parameter parsing and path point generation module in the fast feedback position processing component within the FPGA parses the parameters in the control command and generates discrete path points. Step 3, Real-time target position interpolation: The discrete path points are read by the back-scan path interpolation calculation module in the fast feedback position processing component of the FPGA, and interpolation is performed according to the selected interpolation calculation mode to generate a continuous, smooth, and real-time target position. Step 4, Position Feedback Acquisition and Preprocessing: The real-time position feedback digital signal from the fast-reflecting mirror component output by the external ADC is received through the FPGA's ADC data acquisition and preprocessing module, and the actual position is obtained after preprocessing the position feedback digital signal. Step 5, Closed-loop error calculation and PID control: The closed-loop error calculation and PID control module in the fast feedback position processing component of the FPGA is used to calculate the position error between the target position and the preprocessed actual position, and an incremental PID algorithm is used to generate digital control commands. Step 6, Drive Output: The digital control command is output to an external DAC through the FPGA's internal DAC control and command output module. After conversion, an analog drive signal is obtained to drive the fast-reflecting mirror assembly to move. Step 7: Repeat steps 3 to 6 until the preset task is completed, and then the host computer issues a stop command.

9. The fast-reflection mirror control method according to claim 8, characterized in that, In step 3, the interpolation operation mode includes linear interpolation mode and S-curve interpolation mode; When linear interpolation mode is selected, the following formula is used for calculation: Current position = Previous path point + (Current time - Previous time) × (Next path point - Previous path point) / (Next time - Previous time) When the S-curve interpolation mode is selected, the positions of the acceleration and deceleration segments are calculated using the following cubic polynomial: The uniform velocity segment is calculated linearly using the following formula: in, , , , The coefficients are those of a cubic polynomial. For the uniform speed segment, The initial position of the uniform velocity segment. For time.

10. The fast-reflection mirror control method according to claim 8, characterized in that, In step 5, the incremental PID algorithm uses a fixed-point number format for calculation and completes a single calculation within one clock cycle.

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