Data migration method, storage control chip and flash memory device

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a data moving method, a storage control chip and a flash memory device, wherein storage units in each physical block are grouped based on positions of the storage units to obtain a plurality of storage unit groups, each storage unit group is divided into a plurality of logical page groups based on types of logical pages, each physical block is subjected to data scanning to determine a logical page group to be moved, and data moving is performed on each logical page in the logical page group to be moved, so that the grouping of the physical block can be refined, fine management is realized, data moving is performed only on the logical pages in the logical page group, the whole physical block does not need to be moved as a whole, the data moving amount is reduced, the write amplification effect is reduced, and the actual service life of the flash memory device is prolonged.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a data transfer method, a storage control chip, and a flash memory device. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Because NAND flash memory is susceptible to errors such as retention failure and read / write interference, bit shifts can easily occur in the stored data, affecting data integrity.

[0003] To improve the accuracy of data after power-on, the firmware of flash memory devices typically performs a background scan of the stored data during power-on, and moves data that is prone to errors or exceeds the error correction capability in advance.

[0004] In the process of developing this application, the inventors discovered that the prior art has at least the following problems: scanning and moving are performed on a physical block basis. When any sampled page in a physical block exceeds the error correction capability range, it will trigger the moving of the entire physical block, resulting in a large amount of data that needs to be moved in the background, increasing the write amplification effect and shortening the lifespan of the flash memory device. Summary of the Invention

[0005] This application provides a data transfer method, a storage control chip, and a flash memory device to reduce the amount of data transfer, reduce write amplification effect, and improve the actual service life of the flash memory device.

[0006] The embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a data migration method applied to a flash memory device. The flash memory device includes physical blocks, each physical block includes storage units, and each storage unit corresponds to at least one logical page. The data migration method includes:

[0008] Based on the location of the storage cells, the storage cells in each physical block are grouped to obtain several storage cell groups;

[0009] Based on the type of logical page, each storage unit group is divided into several logical page groups, where each logical page group includes several logical pages.

[0010] Perform a data scan on each physical block to determine the logical page group to be moved;

[0011] Data migration is performed on each logical page in the logical page group to be migrated.

[0012] In some embodiments, storage cells in each physical block are grouped based on their location to obtain several storage cell groups, including:

[0013] Obtain the first number of bits corresponding to each storage unit within each physical block, where the first number of bits is the average number of error bits of the same storage unit obtained through multiple tests;

[0014] Based on the address order of the storage cells in the physical block, several storage cells with consecutive addresses within the same physical block are divided into the same storage cell group to obtain several storage cell groups.

[0015] In each storage cell group, the difference in the number of first bits between any two storage cells is less than a first preset number.

[0016] In some embodiments, each storage unit group is divided into several logical page groups based on the type of logical page, including:

[0017] The type of logical page is determined based on the type of storage unit;

[0018] Each storage unit group is divided into several logical pages according to their type into corresponding logical page groups. In each logical page group, several logical pages are of the same type, and the number of logical page groups is the same as the number of logical page categories.

[0019] In some embodiments, the plurality of logical pages corresponding to each storage unit group are divided into corresponding logical page groups according to the type of the logical page, including:

[0020] Based on the number range of the storage units contained in each storage unit group and the mapping relationship between the storage units and the logical pages of each type, the page number range of each type of logical page group is calculated, where the page number range is the number range of the logical pages contained in the logical page group.

[0021] The number of any logical page in any type of logical page group is calculated using the following formula:

[0022] P = a * n + k

[0023] Where P represents the number of any logical page in the logical page group, a represents the number of logical page categories, n represents the number of any storage cell in the storage cell group, and k represents the page offset.

[0024] In some embodiments, the method further includes:

[0025] Obtain the second bit count for each logical page, where the second bit count is the average of the number of error bits for the same logical page obtained through multiple tests;

[0026] From each logical page group, select a predetermined number of logical pages as feature pages in descending order of the second bit number of the logical pages.

[0027] In some embodiments, a data scan is performed on each physical block to determine the logical page group to be moved, including:

[0028] Determine the physical blocks to be scanned, and select a group of storage cells that have not yet been scanned from the physical blocks;

[0029] Within the storage cell group, select a logical page group that has not yet undergone data scanning;

[0030] Perform a data scan on the logical page group to determine if it is the logical page group to be moved;

[0031] Select the next logical page group that has not been scanned in the storage cell group, and scan the data in that logical page group until every logical page group in the storage cell group has been scanned.

[0032] Select the next group of storage cells in the physical block that has not yet been scanned, and scan that group of storage cells until every group of storage cells in the physical block has been scanned.

[0033] The data is scanned for the next physical block until all physical blocks of the flash memory device have been scanned.

[0034] In some embodiments, a data scan of the logical page group is performed to determine whether the logical page group is the logical page group to be moved, including:

[0035] If valid data exists in the logical page group, select a feature page in the logical page group that has not been scanned for data.

[0036] Read the feature page and count the number of error bits in each allocation unit of the feature page;

[0037] When the number of error bits in any allocation unit is less than or equal to the second preset number, select a feature page in the logical page group that has not been scanned, read and count the number of error bits in each allocation unit of the feature page, until the number of error bits in each allocation unit of any feature page is greater than the second preset number, or, scan each feature page in the logical page group.

[0038] If the number of error bits in each allocation unit of any feature page is greater than the second preset number, the logical page group is determined to be a logical page group to be moved.

[0039] In some embodiments, performing a data scan on each physical block to determine the logical page group to be moved further includes:

[0040] If no valid data exists in any logical page group, or if the number of error bits in the allocation unit of each feature page in any logical page group is less than or equal to the second preset number, the logical page group is determined to be a logical page group not to be moved.

[0041] In some embodiments, the method further includes:

[0042] When any logical page group is determined to be a logical page group to be moved, all logical pages in the logical page group are added to the data move list. The data move list is used to record logical pages that are waiting to be moved.

[0043] Secondly, embodiments of this application provide a storage control chip, comprising:

[0044] At least one processor; and,

[0045] A memory that is communicatively connected to at least one processor; wherein,

[0046] The memory stores instructions that can be executed by at least one processor, such that the at least one processor is able to perform the data transfer method as described in the first aspect.

[0047] Thirdly, embodiments of this application provide a flash memory device, including:

[0048] Such as the storage control chip in the second aspect;

[0049] At least one flash memory medium is communicatively connected to the storage controller chip.

[0050] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions for enabling a flash memory device to perform the data transfer method as described in the first aspect.

[0051] The beneficial effects of the embodiments of this application are as follows: Unlike the prior art, the embodiments of this application provide a data migration method applied to a flash memory device. The flash memory device includes physical blocks, each physical block includes storage units, and each storage unit corresponds to at least one logical page. The data migration method includes: grouping the storage units in each physical block based on the location of the storage units to obtain several storage unit groups; dividing each storage unit group into several logical page groups based on the type of logical page, wherein each logical page group includes several logical pages; performing data scanning on each physical block to determine the logical page groups to be migrated; and migrating data from each logical page in the logical page groups to be migrated.

[0052] By grouping storage cells in each physical block based on their location to obtain several storage cell groups, and then dividing each storage cell group into several logical page groups based on the type of logical page, this application performs data scanning on each physical block to determine the logical page groups to be moved. Data is then moved to each logical page in the logical page groups to be moved. This application can refine the grouping of physical blocks, achieve fine-grained management, and move data only to the logical pages in the logical page groups, without having to move the entire physical block, thereby reducing the amount of data moved, reducing write amplification effect, and improving the actual lifespan of flash memory devices. Attached Figure Description

[0053] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0054] Figure 1 This is a schematic diagram illustrating the change in threshold voltage distribution of a storage cell before and after data retention, provided in an embodiment of this application.

[0055] Figure 2 This is a schematic diagram illustrating the background scanning process of stored data by firmware according to an embodiment of this application;

[0056] Figure 3 yes Figure 2 A detailed flowchart of step S205;

[0057] Figure 4 This is a flowchart illustrating a data transfer method provided in an embodiment of this application;

[0058] Figure 5 This is a schematic diagram of the structure of a stacked flash memory chip cell provided in an embodiment of this application;

[0059] Figure 6 This is a schematic diagram of the physical block structure of a stacked flash memory provided in an embodiment of this application;

[0060] Figure 7 This is a schematic diagram illustrating the relationship between a storage unit and the average number of error bits provided in an embodiment of this application;

[0061] Figure 8 This is a schematic diagram illustrating the grouping of storage units according to an embodiment of this application;

[0062] Figure 9 yes Figure 4 Detailed flowchart of step S403;

[0063] Figure 10 yes Figure 9 A detailed flowchart of step S434;

[0064] Figure 11 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0065] Figure 12 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0067] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0068] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0069] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Flash memory media consists of floating gate transistors (FN transistors), which achieve data storage through the Fowler-Nordheim (FN) tunneling effect. This means that data is written to or erased by injecting or removing charge into the floating gate, thereby changing its potential.

[0070] Due to design flaws, flash memory is prone to data errors and cannot retain data for long periods (e.g., more than 10 years). Causes of data errors include data retention failure and read disturbances.

[0071] Data retention capability refers to the ability of a flash memory device to continuously retain data when it is powered off or inactive. Data retention failure refers to the phenomenon where, when powered off or inactive, the charge on the floating gate in the memory cell gradually decreases or even disappears completely due to charge leakage, material aging, or environmental factors, making it impossible to read data correctly.

[0072] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating the change in threshold voltage distribution of a storage cell before and after data retention, provided in an embodiment of this application.

[0073] In flash memory devices, each storage cell stores electrons in a floating gate through charging. Over time, the number of electrons in the floating gate gradually decreases, or even disappears completely, causing the stored data to change abruptly. For example... Figure 1 As shown, the threshold voltage distribution of the storage cell changes after the data retention time. Therefore, if the data stored in the storage cell is not updated for a long period of time, electron leakage will inevitably lead to errors in the stored data.

[0074] Read interference refers to the phenomenon where, when reading data from a memory cell, the charge state of nearby cells is disturbed, leading to errors in the data of non-target cells. Flash memory media consists of many memory cells arranged in rows and columns. When reading and writing to different word lines, capacitive coupling affects adjacent memory cells. Therefore, read and write operations on different logical pages can cause bit transitions in adjacent logical pages.

[0075] Typically, each physical block of a flash memory medium is only sequentially written once after being erased. This effect is considered in the design of flash memory media and mitigated through strategies. In contrast, read interference has a greater impact. When upper-layer software repeatedly reads data from a storage unit, data errors will inevitably occur after the number of reads reaches a certain level.

[0076] Therefore, to improve the accuracy of data after power-on, the firmware of the flash memory device typically performs a background scan of the stored data during power-on, and migrates data that is prone to errors or exceeds the error correction capability in advance. Data migration refers to reading the original data from its current physical storage location and rewriting it to a new physical storage location.

[0077] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating the background scanning process of stored data by firmware according to an embodiment of this application;

[0078] like Figure 2As shown, the firmware's background scanning process for stored data includes:

[0079] Step S201: Trigger background scanning task;

[0080] Specifically, background scan tasks are triggered by data retention failure or read interference. Background scan tasks are used to scan the physical blocks of the flash memory device to relocate data that is prone to errors or exceeds the error correction capability.

[0081] Step S202: Identify the range of the physical blocks to be scanned;

[0082] Step S203: Select an unscanned physical block for scanning;

[0083] Step S204: Determine whether there is valid data in the physical block;

[0084] Specifically, if there is valid data in the physical block, proceed to step S205; if there is no valid data in the physical block, proceed to step S206.

[0085] Step S205: Initiate the scanning process for a single physical block;

[0086] For details, please refer to Figure 3 , Figure 3 yes Figure 2 A detailed flowchart of step S205;

[0087] like Figure 3 As shown, step S205 includes:

[0088] Step S251: Select the sampling page of the physical block;

[0089] Specifically, the sampling page is the logical page in the physical block where data is scanned, and the sampling page is selected based on the triggering condition of the background scan task. For example, for Triple Level Cell Flash (TLC Flash), if the triggering condition of the background scan task is data retention failure, then all the most significant bit pages (MSBpages) in the current physical block are selected as sampling pages; if the triggering condition of the background scan task is read interference, then all the least significant bit pages (LSBpages) in the current physical block are selected as sampling pages.

[0090] Step S252: Select an unscanned sampling page and perform a data scan on that sampling page;

[0091] Specifically, select an unscanned sampling page, read the sampling page, and count the number of error bits in each Allocation Unit (AU) of the feature page.

[0092] Step S253: Determine whether the number of error bits in each allocation unit of the sampling page is greater than the preset number of bits;

[0093] Specifically, if the number of error bits in each allocation unit of the sampling page is greater than the preset number of bits, then proceed to step S255; if the number of error bits in any allocation unit of the sampling page is less than or equal to the preset number of bits, then proceed to step S254. The preset number of bits is the maximum allowed number of error bits in an allocation unit.

[0094] Step S254: Determine whether all sampling pages have been scanned;

[0095] Specifically, if all sampling pages have been scanned, the process ends; if not all sampling pages have been scanned, the process returns to step S252.

[0096] Step S255: Determine to move all logical pages of the physical block.

[0097] Specifically, the process involves determining which logical pages of the physical block will be migrated, adding all logical pages of the physical block to the migration list to await data migration, thereby ending the scanning process for a single physical block.

[0098] Step S206: Determine whether all physical blocks that need to be scanned have been scanned;

[0099] Specifically, if all the physical blocks that need to be scanned have been scanned, the process ends; if not, the process returns to step S203.

[0100] As can be seen, existing solutions perform scanning and migration on a physical block basis. When any sampled page in a physical block exceeds the error correction capability, the entire physical block is migrated, resulting in a large amount of data needing to be migrated in the background. Data migration continuously writes existing data to new locations, which brings additional write operations and exacerbates the write amplification effect (WAF). In scenarios with a large amount of cold data, the large amount of data migrated exacerbates the write amplification effect, thereby shortening the lifespan of flash memory devices. Write amplification refers to the phenomenon in flash memory storage devices where, in order to complete a certain amount of actual data writing, the device needs to perform additional data writing operations, resulting in the amount of data written being much larger than the amount of data actually required by the host.

[0101] Based on this, this application proposes a data migration method that, by refining the grouping of physical blocks, performs data migration only on logical pages within logical page groups, without having to migrate the entire physical block, thereby reducing the amount of data migration, reducing write amplification effect, and improving the actual lifespan of flash memory devices.

[0102] Please see Figure 4 , Figure 4 This is a flowchart illustrating a data transfer method provided in an embodiment of this application;

[0103] This data transfer method is applied to a flash memory device, specifically, to at least one processor within the flash memory device. In this embodiment, the flash memory device includes a solid-state drive or other storage device using flash memory media. For example, the flash memory device may be a storage device using stacked flash memory, which includes, but is not limited to, 3D NAND flash memory.

[0104] The following describes the specific implementation of this data transfer method using a flash memory device employing stacked flash memory as an example. The specific implementation of this data transfer method on other types of flash memory devices is similar and will not be repeated here.

[0105] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a stacked flash memory chip cell provided in an embodiment of this application;

[0106] like Figure 5 As shown, a single die in 3D NAND Flash consists of multiple physical blocks, and each die consists of multiple planes, with each plane corresponding to a separate cache. A physical block is the smallest unit for erasing in the flash memory medium, and each physical block within a plane can simultaneously undergo erase / programming / read operations. It is understandable that... Figure 5 The numbers in the table represent the plane or physical block number. For example, the Nth physical block of the 0th plane is numbered 4*N+0, the Nth physical block of the 1st plane is numbered 4*N+1, and so on.

[0107] Please see Figure 6 , Figure 6 This is a schematic diagram of the physical block structure of a stacked flash memory provided in an embodiment of this application;

[0108] Among them, layer is a concept introduced by stacked flash memory, indicating the number of stacked layers; word line is a control line within a physical block that can select multiple memory cells; string is used to select a word line or a single memory cell within a layer; memory cell (also called physical cell) is the smallest physical unit for storing electrons on the flash memory medium, and also the smallest unit for programming operations; logical page is a logical concept based on different state encoding methods, and is the smallest unit for reading data.

[0109] like Figure 6 As shown, a physical block is an array of multiple storage units. Figure 6 The numbers in the code represent the numbering. For example, the storage unit of the 0th cluster on the Mth layer is numbered 5*M+0, and the logical page numbering range corresponding to this storage unit is [3*(5M)+0]~[3*(5M)+2].

[0110] Each storage cell can be divided into multiple logical pages depending on the type of NAND Flash. For example, for a single-level cell (SLC Flash), storing 1 bit of data in one storage cell corresponds to an LSB page.

[0111] For Multiple Level Cell Flash (MLC Flash), each memory cell stores 2 bits of data, and each memory cell can be divided into two logical pages: an LSB page and a MSB page. For Triple Level Cell Flash (TLC Flash), each memory cell stores 3 bits of data, and each memory cell can be divided into three logical pages: an LSB page, an MSB page, and a Central Significance Bit page (CSB page).

[0112] For a Quad-Level Cell Flash (QLC Flash), 4 bits of data are stored in one storage cell. Each storage cell can be divided into 4 logical pages, namely LSB page, MSB page, CSB page and extended Significance Bit Page (XSB Page).

[0113] Please see Figure 7 , Figure 7This is a schematic diagram illustrating the relationship between a storage unit and the average number of error bits provided in an embodiment of this application;

[0114] Figure 7 This describes the distribution of the average number of error bits per memory cell within a physical block of a 3D TLC NAND flash memory after multiple data retention tests. The average number of error bits is the average of the number of error bits in the same logical page or memory cell obtained from multiple tests; the number of error bits represents the number of bits that could not be correctly stored or read.

[0115] like Figure 7 As shown, the average number of error bits varies considerably between different memory cells, and there are also significant differences in the average number of error bits among the three types of logical pages (LSB, CSB, MSB) within the same memory cell.

[0116] The difference in average error bits between different memory cells is due to the varying reliability performance of memory cells in different locations caused by the 3D NAND Flash stacking process. This difference is particularly noticeable under data retention and read interference conditions. The difference in average error bits among the three types of logical pages within the same memory cell is closely related to the operating principle of NAND Flash.

[0117] It can be seen that due to the influence of the manufacturing process, stacked flash memory (such as 3D NAND Flash) has different numbers of error bits between different storage cells, and also different numbers of error bits between different logical pages within the same storage cell.

[0118] Existing data migration schemes that move data in physical blocks trigger the migration of the entire physical block when any sampled page in the block exceeds its error correction capability. This approach is suitable for situations where the number of error bits is relatively uniform across all logical pages or memory cells within a physical block, but it is not suitable for stacked flash memory. The data migration method proposed in this application, however, takes into account the characteristics of flash memory devices and the differences in data retention and read interference capabilities of different memory cell locations and logical pages. It groups physical blocks more precisely, enabling data migration only for logical pages within a logical page group. On one hand, it eliminates the need to migrate the entire flash memory block, reducing the amount of data migration, mitigating write amplification, and increasing the actual lifespan of the flash memory device. On the other hand, compared to physical block-based data migration schemes, this application is more suitable for stacked flash memory.

[0119] In this embodiment, the flash memory device includes physical blocks, and each physical block includes storage cells, with each storage cell corresponding to at least one logical page. The storage cells include, but are not limited to, stacked storage cells, such as 3D NAND Flash. The specific implementation of this data transfer method is described below using stacked storage cells as an example.

[0120] like Figure 4 As shown, the data migration method includes:

[0121] Step S401: Based on the location of the storage cells, group the storage cells in each physical block to obtain several storage cell groups;

[0122] Specifically, for each physical block in a flash memory device, the memory cells within that physical block are grouped based on their location, with memory cells having similar numbers of error bits grouped into the same memory cell group. A physical block comprises several memory cell groups, and each memory cell group comprises several memory cells.

[0123] In this embodiment of the application, step S401 specifically includes steps S411-S412:

[0124] Step S411: Obtain the first number of bits corresponding to each storage unit within each physical block;

[0125] The first bit count is the average number of error bits in the same storage unit obtained through multiple tests.

[0126] In some embodiments, the first number of bits corresponding to each storage cell within each physical block of the flash memory device is obtained by conducting large-sample tests in the laboratory in advance, and then uploaded to the flash memory device by relevant personnel.

[0127] In some embodiments, all storage cells within the same physical block are subjected to the same data retention time and number of read interferences during each test. Specifically, for the same type of flash memory device, under the same data retention time and number of read interferences, each storage cell within each physical block of the flash memory device is read, the number of error bits in each storage cell is counted, and the average number of error bits in the same storage cell obtained from multiple tests is calculated to obtain the first number of bits corresponding to each storage cell.

[0128] It is understood that other factors affecting the number of error bits in a storage cell can be considered during testing to ensure that all storage cells within the same physical block are under the same influencing conditions during each test. Test conditions can be set by those skilled in the art based on the factors affecting the number of error bits in a storage cell, and are not limited in the embodiments of this application.

[0129] Step S412: Based on the address order of the storage cells in the physical block, divide several consecutive storage cells in the same physical block into the same storage cell group to obtain several storage cell groups.

[0130] In each storage cell group, the difference in the number of first bits between any two storage cells is less than a first preset number. The first preset number is the maximum number of error bits allowed for a storage cell under the default read offset voltage. The first preset number is determined by the decoding capability of the flash memory device's controller and is not limited in this embodiment.

[0131] Specifically, for each physical block, several memory cells within the physical block whose addresses are consecutive and whose difference in the number of first bits is less than a first preset number are divided into the same memory cell group.

[0132] Please see Figure 8 , Figure 8 This is a schematic diagram illustrating the grouping of storage units according to an embodiment of this application;

[0133] Figure 8 Yes Figure 7 The diagram illustrates the grouping of storage cells. (See attached diagram.) Figure 8 As shown, several memory cells within a physical block with consecutive addresses and a difference in the number of first bits less than a first preset number are grouped into the same memory cell group, resulting in 8 memory cell groups (i.e., Figure 8 Group 0, Group 1, ..., Group 7). It is understandable that... Figure 7 and Figure 8 In this context, the average number of error bits per storage unit is the same as the first number of bits mentioned above.

[0134] In this embodiment of the application, by grouping the storage cells in each physical block based on the location of the storage cells, this application can group storage cells with similar numbers of error bits into the same storage cell group.

[0135] Step S402: Based on the type of logical page, divide each storage unit group into several logical page groups;

[0136] Each storage unit group comprises several logical page groups, and each logical page group comprises several logical pages.

[0137] In this embodiment of the application, step S402 specifically includes steps S421-S422:

[0138] Step S421: Determine the type of logical page based on the type of storage unit;

[0139] Specifically, the types of storage units include SLC Flash, MLC Flash, TLC Flash, or QLC Flash, and the types of logical pages include LSB pages, MSB pages, CSB pages, or XSB pages.

[0140] When the storage cell type is SLC Flash, there is only one type of logical page, which is an LSB page; when the storage cell type is MLC Flash, there are two types of logical pages, which include either an LSB page or an MSB page; when the storage cell type is TLC Flash, there are three types of logical pages, which include either an LSB page, an MSB page, or a CSB page; when the storage cell type is QLC Flash, there are four types of logical pages, which include either an LSB page, an MSB page, a CSB page, or an XSB page.

[0141] Step S422: Divide the logical pages corresponding to each storage unit group into the corresponding logical page groups according to the type of the logical pages.

[0142] In each logical page group, several logical pages are of the same type, and the number of logical page groups is the same as the number of logical page categories.

[0143] Specifically, the logical pages corresponding to the storage units contained in each storage unit group are divided into corresponding logical page groups according to the type of the logical page. For example, for SLC Flash, the type of logical page is LSB page, and a storage unit group includes only one logical page group, which includes all the LSB pages in the storage unit group.

[0144] For MLC Flash, logical pages can be either LSB pages or MSB pages. A storage cell group consists of two logical page groups: one logical page group contains all the LSB pages in the storage cell group, and the other logical page group contains all the MSB pages in the storage cell group.

[0145] For TLC Flash, logical pages include LSB pages, MSB pages, or CSB pages. A memory cell group consists of three logical page groups. A logical page group includes all LSB pages in the memory cell group, all MSB pages in the memory cell group, and all CSB pages in the memory cell group.

[0146] For QLC Flash, logical page types include LSB pages, MSB pages, CSB pages, or XSB pages. A memory cell group consists of four logical page groups. A logical page group includes all LSB pages in the memory cell group, all MSB pages in the memory cell group, all CSB pages in the memory cell group, and all XSB pages in the memory cell group.

[0147] In this embodiment of the application, step S422 specifically includes: calculating the page number range of each type of logical page group based on the number range of the storage units contained in each storage unit group and the mapping relationship between the storage units and each type of logical page.

[0148] The page number range is the range of logical page numbers contained in the logical page group. The mapping relationship between storage units and logical pages of each type includes the mapping relationship between the storage unit number and the logical page number of each type. The type of the logical page group is the type of logical pages contained in the logical page group.

[0149] Specifically, based on the numbering range of storage units and the mapping relationship between the storage unit numbers and the numbers of logical pages of each type, the page numbering range of each type of logical page group is calculated. The page numbering range of each type of logical page group is composed of the numbers of several logical pages in the logical page group.

[0150] The mapping relationship between the memory cell number and the logical page number of each type is expressed by the following formula, which can be used to calculate the number of any logical page in any logical page group of any type:

[0151] P = a * n + k

[0152] Where P represents the number of any logical page in the logical page group, a represents the number of logical page types, n represents the number of any storage unit in the storage unit group, and k represents the page offset. The page offset is the offset of a logical page of a certain type relative to the storage unit. The page offset can be determined by those skilled in the art based on the type of logical page, and is not limited here.

[0153] For example, for 3D TLC NAND Flash, there are three types of logical pages: a is 3, k is 0 for a logical page group containing LSB pages, k is 1 for a logical page group containing CSB pages, and k is 2 for a logical page group containing MSB pages.

[0154] Please refer to Table 1, which is a schematic table of the number range of storage units included in a storage unit group provided in the embodiments of this application;

[0155] Table 1

[0156]

[0157] Please refer to Table 2, which is a schematic table of page number ranges for a logical page group provided in an embodiment of this application;

[0158] Table 2

[0159]

[0160] In Table 2, LSB logical page group is a logical page group containing LSB pages, CSB logical page group is a logical page group containing CSB pages, and MSB logical page group is a logical page group containing MSB pages.

[0161] In this embodiment, the storage cells in each physical block are grouped based on their location to obtain several storage cell groups. Based on the type of logical page, each storage cell group is divided into several logical page groups. This application can perform more refined grouping of physical blocks based on the different storage cell locations and the differences in the data retention and read interference capabilities of logical pages. This facilitates subsequent data migration only for logical pages within logical page groups, without having to migrate the entire flash memory block, thus reducing the amount of data migration.

[0162] In this embodiment of the application, the method further includes: selecting a feature page from the logical page group. The feature page is a logical page in the logical page group used for data scanning, that is, the logical page used in step S403 to obtain the number of error bits.

[0163] Specifically, the steps for selecting a feature page from a logical page group include steps S1-S2:

[0164] Step S1: Obtain the second number of bits corresponding to each logical page;

[0165] The second bit count is the average number of error bits for the same logical page obtained through multiple tests.

[0166] In some embodiments, the second number of bits corresponding to each logical page is obtained by conducting large-sample tests in the laboratory in advance, and then uploaded to the flash memory device by relevant personnel.

[0167] In some embodiments, all logical pages within the same physical block are subjected to the same data retention time and number of read interferences during each test. For example, as described above, by obtaining the first bit count for each storage unit through multiple tests under the same data retention time and number of read interferences, the number of error bits for each logical page is counted, and the average number of error bits for the same logical page obtained from multiple tests is calculated to obtain the second bit count for each logical page.

[0168] It is understood that other factors affecting the number of error bits in a storage cell can be considered during testing to ensure that all storage cells within the same physical block are under the same influencing conditions during each test. Test conditions can be set by those skilled in the art based on the factors affecting the number of error bits in a storage cell, and are not limited in the embodiments of this application.

[0169] Step S2: From each logical page group, select a preset number of logical pages as feature pages in descending order of the second bit number of the logical pages.

[0170] Specifically, the second bit count of the logical pages in each logical page group is sorted in descending order, and a preset number of logical pages are selected as feature pages according to the order of the second bit count of the logical pages from largest to smallest.

[0171] The preset number refers to the number of feature pages selected in a logical page group. This preset number can be set by those skilled in the art based on the impact of the storage unit's location on the number of error bits. In this embodiment, no limitation is imposed. For example, considering the influence of individual locations, the preset number is greater than 3. For instance, the four logical pages with the largest second bit count are selected as four feature pages in a logical page group.

[0172] Step S403: Perform a data scan on each physical block to determine the logical page group to be moved;

[0173] Specifically, a background task scans each physical block to identify the logical page groups to be moved. Data scanning involves performing read operations to count the number of error bits, and the logical page groups to be moved are those that require data migration.

[0174] Please see Figure 9 , Figure 9 yes Figure 4 Detailed flowchart of step S403;

[0175] like Figure 9 As shown, step S403 includes:

[0176] Step S431: Determine the physical blocks to be scanned;

[0177] Specifically, data is scanned sequentially for each physical block.

[0178] Step S432: Select a group of storage cells that have not been scanned for data;

[0179] Specifically, the physical block to be scanned is determined, and a group of storage cells that has not yet been scanned is selected within that physical block.

[0180] Step S433: Select a logical page group that has not yet undergone data scanning;

[0181] Specifically, within this storage unit group, select a logical page group that has not yet undergone data scanning.

[0182] Step S434: Perform a data scan on the logical page group;

[0183] Specifically, a data scan is performed on the logical page group to determine whether it is the logical page group to be moved.

[0184] Please see Figure 10 , Figure 10 yes Figure 9 A detailed flowchart of step S434;

[0185] like Figure 10 As shown, step S434 includes:

[0186] Step S4341: Determine whether there is valid data in the logical page group;

[0187] Specifically, if there is valid data in the logical page group, proceed to step S4342; if there is no valid data in the logical page group, proceed to step S4347.

[0188] Step S4342: Select a feature page that has not undergone data scanning;

[0189] Specifically, when valid data exists in a logical page group, a feature page that has not been scanned is selected from the logical page group.

[0190] Step S4343: Read the feature page and count the number of error bits in each allocation unit;

[0191] Specifically, the feature page is scanned, that is, the feature page is read and the number of error bits in each allocation unit of the feature page is counted.

[0192] Step S4344: Determine whether the number of error bits in each allocation unit is greater than the second preset number;

[0193] The second preset quantity is the maximum number of error bits allowed by an allocation unit under the default read offset voltage. The second preset quantity is determined by the decoding capability of the flash memory device's controller and is not limited in this embodiment.

[0194] Specifically, if the number of error bits in each allocation unit is greater than the second preset number, proceed to step S4345; if the number of error bits in any allocation unit is less than or equal to the second preset number, proceed to step S4346.

[0195] Step S4345: Determine that the logical page group is the logical page group to be moved;

[0196] Specifically, when the number of error bits in each allocation unit of any feature page is greater than the second preset number, the logical page group is determined to be the logical page group to be moved, and step S434 ends.

[0197] In this embodiment of the application, the method further includes: when any logical page group is determined to be a logical page group to be moved, adding all logical pages in that logical page group to a data migration list. The data migration list is used to record logical pages waiting to be migrated.

[0198] Step S4346: Determine whether each feature page in the logical page group has been scanned;

[0199] Specifically, if every feature page in the logical page group has been scanned, proceed to step S4347; if every feature page in the logical page group has not been scanned, return to step S4342 to scan the next feature page that has not yet been scanned.

[0200] That is, when the number of error bits in any allocation unit is less than or equal to the second preset number, a feature page that has not been scanned in the logical page group is selected, and the number of error bits in each allocation unit in the feature page is read and counted until the number of error bits in each allocation unit of any feature page is greater than the second preset number, or until the scanning of each feature page in the logical page group is completed.

[0201] Step S4347: Determine that the logical page group is not a logical page group to be moved;

[0202] Specifically, if there is no valid data in any logical page group, or if the number of error bits in the allocation unit of each feature page in any logical page group is less than or equal to the second preset number, the logical page group is determined to be a non-transferable logical page group, that is, the logical page group does not need to be transferred, and step S434 ends.

[0203] Step S435: Determine whether each logical page group in the memory cell group has been scanned;

[0204] Specifically, if every logical page group in the storage unit group has been scanned, the scanning of the storage unit group is considered complete, and the process proceeds to step S436; if every logical page group in the storage unit group has not been scanned, the process returns to step S433, selects the next logical page group that has not been scanned in the storage unit group, and performs a data scan on that logical page group until every logical page group in the storage unit group has been scanned, and then proceeds to step S436.

[0205] Step S436: Determine whether every group of memory cells in the physical block has been scanned;

[0206] Specifically, if every storage cell group in the physical block has been scanned, the physical block is considered scanned and the process proceeds to step S437; if every storage cell group in the physical block has not been scanned, the process returns to step S432, selects the next storage cell group in the physical block that has not been scanned, and performs a data scan on that storage cell group until every storage cell group in the physical block has been scanned, and then proceeds to step S437.

[0207] Step S437: Determine whether all physical blocks of the flash memory device have been scanned;

[0208] Specifically, if all physical blocks of the flash memory device have been scanned, the process ends; if not, the process returns to step S431 to redetermine the physical blocks to be scanned, and then scans the next physical block until all physical blocks of the flash memory device have been scanned.

[0209] Step S404: Perform data migration for each logical page in the logical page group to be migrated.

[0210] Specifically, based on each logical page recorded in the data migration list, data migration is performed on these logical pages in sequence, that is, the data of the logical pages is read and rewritten to the new physical storage location.

[0211] Understandably, although the data transfer operation is a background operation of the firmware and is theoretically invisible to the host user above the flash memory device, the bandwidth of the backend for NAND read and write operations is limited. When the amount of data to be transferred in the background is too large, the I / O pressure on the foreground is high, which will affect the I / O performance of the foreground, manifested as a decrease in bandwidth and an increase in latency.

[0212] Compared to existing solutions that move data in physical blocks, resulting in a large amount of data to be moved in the backend, this application addresses two main issues. First, by scanning characteristic pages within logical page groups instead of all logical pages, it reduces the number of backend scanning operations while ensuring the effectiveness of the backend scan, thereby reducing the impact on frontend I / O and improving frontend business performance. Second, by moving data only to logical pages within logical page groups instead of moving the entire physical block, this application reduces the amount of data moved, thereby reducing the impact on frontend I / O and improving frontend business performance.

[0213] In this embodiment, a data migration method is provided, which is applied to a flash memory device. The flash memory device includes physical blocks, and each physical block includes storage cells. Each storage cell corresponds to at least one logical page. The data migration method includes: grouping the storage cells in each physical block according to the location of the storage cells to obtain several storage cell groups; dividing each storage cell group into several logical page groups according to the type of logical page, wherein each logical page group includes several logical pages; performing data scanning on each physical block to determine the logical page groups to be migrated; and migrating data for each logical page in the logical page groups to be migrated.

[0214] By grouping storage cells in each physical block based on their location to obtain several storage cell groups, and then dividing each storage cell group into several logical page groups based on the type of logical page, this application performs data scanning on each physical block to determine the logical page groups to be moved. Data is then moved to each logical page in the logical page groups to be moved. This application can refine the grouping of physical blocks, achieve fine-grained management, and move data only to the logical pages in the logical page groups, without having to move the entire physical block, thereby reducing the amount of data moved, reducing write amplification effect, and improving the actual lifespan of flash memory devices.

[0215] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0216] like Figure 11 As shown, the storage control chip 110 includes one or more processors 111 and a memory 112. Wherein, Figure 11 Taking a processor 111 as an example, in this embodiment, the storage control chip includes a controller for a solid-state drive or other storage device using flash memory as the storage medium. The flash memory device includes physical blocks, each physical block includes storage cells, and each storage cell corresponds to at least one logical page.

[0217] Processor 111 and memory 112 can be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0218] Processor 111 is configured to provide computing and control capabilities to control flash memory device 120 to perform corresponding tasks, such as controlling flash memory device 120 to perform a data transfer method in any of the above method embodiments. The data transfer method includes: grouping storage cells in each physical block into several storage cell groups based on the location of the storage cells; dividing each storage cell group into several logical page groups based on the type of logical page, wherein the logical page group includes several logical pages; performing data scanning on each physical block to determine the logical page group to be transferred; and performing data transfer on each logical page in the logical page group to be transferred.

[0219] By grouping storage cells in each physical block based on their location to obtain several storage cell groups, and then dividing each storage cell group into several logical page groups based on the type of logical page, this application performs data scanning on each physical block to determine the logical page groups to be moved. Data is then moved to each logical page in the logical page groups to be moved. This application can refine the grouping of physical blocks, achieve fine-grained management, and move data only to the logical pages in the logical page groups, without having to move the entire physical block, thereby reducing the amount of data moved, reducing write amplification effect, and improving the actual lifespan of flash memory devices.

[0220] Processor 111 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0221] Memory 112, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data transfer method in the embodiments of this application. Processor 111 can implement the data transfer method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in memory 112. Specifically, memory 112 may include volatile memory (VM), such as random access memory (RAM); memory 112 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 112 may also include combinations of the above types of memory.

[0222] Memory 112 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 112 may optionally include memory remotely located relative to processor 111, and these remote memories may be connected to processor 111 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0223] One or more modules are stored in memory 112. When executed by one or more processors 111, they perform the data transfer method in any of the above method embodiments, for example, the method described above. Figure 4 The steps shown.

[0224] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0225] like Figure 12 As shown, the flash memory device 120 includes a storage control chip 110 and at least one flash memory medium 121. Figure 12 Taking a flash memory medium 121 as an example, the storage control chip 110 and the flash memory medium 121 are connected in communication.

[0226] The storage control chip 110 is used to execute the data migration method in any of the above embodiments. The data migration method includes: grouping the storage cells in each physical block into several storage cell groups based on the location of the storage cells; dividing each storage cell group into several logical page groups based on the type of logical page, wherein the logical page group includes several logical pages; scanning each physical block to determine the logical page group to be migrated; and migrating data for each logical page in the logical page group to be migrated.

[0227] At least one flash memory medium 121 is communicatively connected to the storage control chip 110 for storing data. The flash memory medium includes physical blocks, each physical block comprising storage cells, and each storage cell corresponding to at least one logical page.

[0228] The flash memory device includes a storage control chip and at least one flash memory medium. The storage control chip is used to execute the data transfer method in any of the above embodiments, and the flash memory medium is used to store data. This application can refine the grouping of physical blocks, realize fine management, and perform data transfer only on logical pages in logical page groups, without having to transfer the entire physical block, thereby reducing the amount of data transfer, reducing write amplification effect, and improving the actual service life of the flash memory device.

[0229] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data transfer method in any of the above method embodiments, such as executing the data transfer method in any of the above method embodiments, or executing the steps described above.

[0230] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0231] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0232] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data migration method, characterized in that, Applied to a flash memory device, the flash memory device comprising physical blocks, the physical blocks comprising storage cells, each storage cell corresponding to at least one logical page, the method comprising: Based on the location of the storage cells, the storage cells in each physical block are grouped to obtain several storage cell groups; Based on the type of logical page, each of the aforementioned storage unit groups is divided into several logical page groups, wherein each logical page group includes several logical pages; Each physical block is scanned to determine the logical page group to be moved; Data migration is performed on each logical page in the logical page group to be migrated.

2. The method according to claim 1, characterized in that, Based on the location of the storage cells, the storage cells in each physical block are grouped to obtain several storage cell groups, including: Obtain the first number of bits corresponding to each storage unit within each physical block, wherein the first number of bits is the average number of error bits of the same storage unit obtained through multiple tests; Based on the address order of the storage cells in the physical block, several storage cells with consecutive addresses within the same physical block are divided into the same storage cell group to obtain several storage cell groups. In each storage cell group, the difference in the number of first bits between any two storage cells is less than a first preset number.

3. The method according to claim 1, characterized in that, The method of dividing each storage unit group into several logical page groups based on the logical page type includes: The type of logical page is determined based on the type of storage unit; Each storage unit group is divided into several logical pages according to their type into corresponding logical page groups. In each logical page group, several logical pages are of the same type, and the number of logical page groups is the same as the number of logical page categories.

4. The method according to claim 3, characterized in that, The step of dividing the several logical pages corresponding to each storage unit group into corresponding logical page groups according to the type of the logical page includes: Based on the number range of the storage units contained in each storage unit group and the mapping relationship between the storage units and logical pages of each type, the page number range of each type of logical page group is calculated, wherein the page number range is the number range of the logical pages contained in the logical page group. The number of any logical page in any type of logical page group is calculated using the following formula: P = a * n + k Where P represents the number of any logical page in the logical page group, a represents the number of logical page categories, n represents the number of any storage cell in the storage cell group, and k represents the page offset.

5. The method according to claim 1, characterized in that, The method further includes: Obtain the second number of bits corresponding to each logical page, where the second number of bits is the average number of error bits of the same logical page obtained through multiple tests; From each logical page group, a predetermined number of logical pages are selected as feature pages in descending order of the second bit count of the logical pages.

6. The method according to claim 5, characterized in that, The step of scanning each physical block to determine the logical page group to be moved includes: Determine the physical blocks to be scanned, and select a group of storage units that have not yet been scanned from the physical blocks; In the group of storage cells, select a logical page group that has not been scanned for data; The logical page group is scanned to determine whether it is a logical page group to be moved. Select the next logical page group that has not been scanned in the storage unit group, and scan the logical page group until the scanning of each logical page group in the storage unit group is completed; Select the next storage cell group that has not been scanned in the physical block and scan the data in that storage cell group until the scanning of every storage cell group in the physical block is completed; The data is scanned for the next physical block until all physical blocks of the flash memory device have been scanned.

7. The method according to claim 6, characterized in that, The step of scanning the logical page group to determine whether the logical page group is a logical page group to be moved includes: When valid data exists in the logical page group, select a feature page in the logical page group that has not been scanned for data. Read the feature page and count the number of error bits in each allocation unit of the feature page; When the number of error bits in any allocation unit is less than or equal to the second preset number, select a feature page in the logical page group that has not been scanned, read and count the number of error bits in each allocation unit in the feature page, until the number of error bits in each allocation unit in any feature page is greater than the second preset number, or, scan each feature page in the logical page group. If the number of error bits in each allocation unit of any feature page is greater than the second preset number, the logical page group is determined to be a logical page group to be moved.

8. The method according to claim 7, characterized in that, The step of scanning each physical block to determine the logical page group to be moved also includes: If no valid data exists in any logical page group, or if the number of error bits in the allocation unit of each feature page in any logical page group is less than or equal to the second preset number, the logical page group is determined to be a logical page group not to be moved. The method further includes: When any logical page group is determined to be a logical page group to be moved, all logical pages in the logical page group are added to the data move list, wherein the data move list is used to record logical pages waiting to be moved.

9. A storage control chip, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the data transfer method as described in any one of claims 1-8.

10. A flash memory device, characterized in that, include: The storage control chip as described in claim 9; At least one flash memory medium is communicatively connected to the storage control chip.

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