Temperature throttling method for storage devices

Abstract

A method of temperature throttling of a storage device includes monitoring a current performance of a memory device responsive to input / output command operations respectively included in a plurality of streams, determining a reference performance and a reference latency value for each of the plurality of streams based on a current temperature of the storage device, determining a weight for each of the plurality of streams based on the current performance, determining a target latency value for each of the plurality of streams by reflecting the weight on the reference latency value, and applying the weight for which the reference performance is measured in each of the plurality of streams.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0177419, filed with the Korean Intellectual Property Office on December 3, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method for temperature throttling of storage devices. Background Technology

[0004] A storage device may include a memory controller and a storage device. The memory controller can receive or generate input / output commands from a host computer. The memory controller can also send input / output commands to the storage device, and the corresponding input / output operations can be performed within the storage device. For example, the storage device can perform input / output operations such as storing and / or erasing data and / or reading stored data and sending it to an external device. However, if the internal temperature of the storage device rises excessively, the storage device may be unable to stably perform input / output operations. Here, the memory controller can perform dynamic thermal throttling (DTT) operations, such as controlling the input / output throughput of the storage device, to reduce the internal temperature of the storage device. Summary of the Invention

[0005] One aspect of the present invention provides a method for monitoring the input / output throughput of each of a plurality of streams in a memory device and delaying the number of input / output commands sent by the memory controller in each of the plurality of streams per unit time differently, in order to control the input / output throughput of each of the plurality of streams in the memory device, thereby improving the temperature control efficiency of the memory device.

[0006] According to one aspect of the present invention, a temperature throttling method for a storage device includes: monitoring the current performance of the storage device, the storage device responding to input / output command operations included in a plurality of streams respectively; determining a reference performance and a reference latency value for each of the plurality of streams based on the current temperature of the storage device; determining a weight for each of the plurality of streams based on the current performance; determining a target latency value for each of the plurality of streams by reflecting the weights on the reference latency value; and applying the weights for their measured reference performance to each of the plurality of streams.

[0007] According to one aspect of the present invention, a temperature throttling method for an automotive storage device includes: determining a reference performance ratio for each of a plurality of streams based on the current temperature of the automotive storage device; determining a reference performance by multiplying the current performance corresponding to each of the plurality of streams by the reference performance ratio for each of the plurality of streams; determining a reference latency value for each of the plurality of streams based on the difference between the current performance and the reference performance; determining a weight for each of the plurality of streams based on the ratio of the current performance corresponding to each of the plurality of streams to the sum of the current performances of the plurality of streams; determining a target latency value for the corresponding stream among the plurality of streams by applying the weight to the reference latency value; and applying the target latency value to the corresponding stream for each of the plurality of streams.

[0008] According to one aspect of the present invention, a temperature throttling method for a storage device includes: initiating throttling of the storage device based on determining that the current temperature of the storage device is higher than a reference temperature; monitoring the input / output throughput of each of a plurality of streams; determining a delay time for an input / output transmission period applied to each of the plurality of streams by reflecting the current temperature of the storage device and the input / output throughput of each of the plurality of streams; applying the delay time in the delay time to the corresponding stream in the plurality of streams; and terminating throttling of the storage device based on determining that the current temperature of the storage device is lower than a reference temperature, wherein at least a portion of the delay time applied to the input / output transmission period of the plurality of streams is different from at least a portion of the remaining portion of the delay time of the input / output transmission period.

[0009] According to one aspect of the present invention, a storage device may include a memory device, a memory controller configured to control the memory device, and a temperature sensor configured to detect the current temperature of the memory device. The memory controller may be configured to control the operation of the memory device based on input / output commands included in a plurality of streams; monitor the current performance of the memory device in response to the input / output command operations; determine a reference performance and a reference latency value for each of the plurality of streams based on the current temperature of the memory device; determine a weight for each of the plurality of streams based on the current performance; determine a target latency value for each of the plurality of streams by reflecting the weights on the reference latency value; and apply a weight for its measured reference performance to each of the plurality of streams.

[0010] The memory controller can also be configured to delay the transmission period of at least one of the input / output commands by applying a target delay value to the corresponding stream in a plurality of streams.

[0011] Memory devices may include different types of memory cells; and the type of memory cell may include at least one of single-level cell, multi-level cell, three-level cell, or four-level cell. Attached Figure Description

[0012] The above and other aspects, features and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram schematically illustrating at least one example embodiment of a host-storage system according to the concept of the present invention;

[0014] Figure 2 This is a diagram illustrating the operation of controlling the temperature of a storage device according to at least one exemplary embodiment of the concept of the present invention;

[0015] Figure 3 This is a block diagram schematically illustrating at least one example embodiment of a memory block according to the concept of the present invention;

[0016] Figure 4 This is a diagram illustrating a 3D V-NAND structure applicable to a storage device, based on at least one exemplary embodiment of the concept according to the present invention;

[0017] Figure 5 It is a diagram illustrating the threshold voltage distribution of a memory cell according to at least one exemplary embodiment of the present invention;

[0018] Figure 6 This is a block diagram schematically illustrating at least one example embodiment of a throttling controller according to the present invention.

[0019] Figure 7 This is a flowchart illustrating the throttling operation of a throttling controller according to at least one example embodiment of the concept of the present invention;

[0020] Figure 8 It is a graph illustrating the performance ratio per flow of at least one example embodiment of the present invention according to the temperature range of the storage device;

[0021] Figure 9 This is a diagram illustrating the calculation of the target delay value per stream according to at least one example embodiment of the concept of the present invention; and

[0022] Figure 10 and Figure 11 This is a diagram illustrating the transmission period of input / output commands according to an embodiment of the present invention. Detailed Implementation

[0023] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0024] In the specification and drawings, unless otherwise stated, the functional elements configured to perform at least one function or operation can be implemented by processing circuitry (such as hardware, software, or a combination of hardware and software). For example, unless otherwise stated, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuitry may also include electrical components (such as at least one of transistors, resistors, capacitors, etc.), and / or electronic circuitry including said components. Furthermore, the operation of the processing circuitry can be based on non-transitory machine-readable instructions implemented by a computer.

[0025] Figure 1 This is a block diagram schematically illustrating at least one example embodiment of a host-storage system according to the concept of the present invention.

[0026] The host-storage system 10 may include a host 100 and a storage device 200. Furthermore, the storage device 200 may include a memory controller 210, a memory device 220, and a temperature sensor 230. In at least one example, the host-storage system 10 may be included in an automotive device; however, the examples are not limited thereto.

[0027] Host 100 may include one or more electronic devices, such as portable electronic devices like mobile phones, MP3 players, laptops, and electronic devices (such as desktop computers, game consoles, TVs, projectors, etc.). Host 100 may include at least one operating system (OS). The operating system can be configured to manage and control the overall functionality and operation of host 100. For example, in the case where host-storage system 10 is included in an automotive device, host 100 may be an automotive processor included in the automotive device.

[0028] Storage device 200 may include a storage medium configured to store data in response to a request from host 100. For example, in the case where host-storage system 10 is included in an automotive device, storage device 200 may be an automotive storage device included in the automotive device. Storage device 200 may include at least one of solid-state drive (SSD), embedded memory, and removable external memory. Storage device 200 may be configured to conform to a corresponding standard. For example, if storage device 200 includes an SSD, then storage device 200 may be a device conforming to the nonvolatile memory express (NVMe) standard; and if storage device 200 includes embedded memory or external memory, then storage device 200 may be a device conforming to the universal flash storage (UFS) or embedded multimedia card (eMMC) standard. Host 100 and storage device 200 may each be configured (e.g., according to the adopted standard protocol) to generate and send packets.

[0029] Even when power is not available, the memory device 220 can maintain the stored data. For example, the memory device 220 may include non-volatile memory. The memory device 220 can store data provided from the host 100 via write operations and can output the data stored in the memory device 220 via read operations. The memory device 220 includes multiple memory blocks, each of which includes multiple pages, and each page may include multiple memory cells connected to word lines. In at least one exemplary embodiment of the inventive concept, the memory device 220 may be flash memory, and data related to the operation of the automotive equipment may be stored in the memory device 220.

[0030] When the memory device 220 of the storage device 200 includes flash memory, the flash memory may include at least one of a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include a variety of other types of non-volatile memory. For example, the storage device 200 may include at least one of magnetic RAM (MRAM), spin-torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, or a variety of other types of memory.

[0031] The memory controller 210 can be configured to control the memory device 220 in response to a request from the host 100. For example, the memory controller 210 can provide data read from the memory device 220 to the host 100 and write (program) data provided by the host 100 to the memory device 220.

[0032] In at least one example embodiment, the memory controller 210 may include a host interface layer (HIL) 211, a flash translation layer (FTL) 212, a flash interface layer (FIL) 213, a buffer memory 214, a throttling controller 215, and an error correction code (ECC) engine 216. The host interface layer 211, the flash interface layer 213, and the buffer memory 214 may be controlled by the flash translation layer 212.

[0033] The host interface layer 211 can be configured to send packets to and receive packets from the host 100. When the host 100 sends a write request, the packet sent from the host 100 to the host interface layer 211 may include a command or data to be written to the memory device 220. When the host 100 sends a read request, the packet sent from the host interface layer 211 to the host 100 may include a response to the command or data read from the memory device 220. The host interface layer 211 can send requests received from the host 100 to the flash translation layer 212.

[0034] The flash translation layer 212 can be configured to perform various operations or generate commands and addresses to control the memory device 220. The flash translation layer 212 can generate various commands for programming operations, read operations, erase operations, data compression operations, copyback operations, programming progress status checks, etc., and generate addresses corresponding to the commands.

[0035] The flash memory translation layer 212 can be configured to control the programming operation of the memory device 220 according to a programming request received from the host interface layer 211. For example, the flash memory translation layer 212 can generate programming commands and programming addresses according to the host's programming request and send them to the flash memory interface layer 213.

[0036] The flash translation layer 212 can be configured to control the read operation of the memory device 220 based on a read request received from the host interface layer 211. The flash interface layer 213 can be configured to transmit data and information received from the memory device 220 to the flash translation layer 212.

[0037] The flash interface layer 213 can be configured to communicate with the memory device 220 using a communication protocol. For example, the flash interface layer 213 can be implemented to conform to standard protocols such as Toggle, Open NAND Flash Interface (ONFI), etc.

[0038] Flash interface layer 213 can be configured to send input / output commands to memory device 220. Memory device 220 can perform input / output operations corresponding to the input / output commands. Input / output commands may include command / address signals and / or data, instructing memory device 220 to perform the operation corresponding to the input / output command. Input / output commands can be sent to memory device 220 in the form of a stream (which is a set of input / output commands).

[0039] In at least one example embodiment, memory controller 210 can be configured to send multiple streams to memory device 220. Memory device 220, having received multiple streams, can process in parallel operations indicated by input / output commands included in each of the multiple streams. For example, each of the input / output commands may include different commands, addresses, and data.

[0040] Memory device 220 can be configured to perform input / output operations to store and / or erase data and / or read out stored data and send it to an external device. Flash interface layer 213 can store commands and addresses received from flash translation layer 212 and send the stored commands and addresses to memory device 220. Flash interface layer 213 can also send data and information read from memory device 220 to flash translation layer 212.

[0041] The buffer memory 214 can temporarily store data when the memory controller 210 controls the memory device 220. The buffer memory 214 can temporarily store data to be written to the memory device 220 or data to be read from the memory device 220. The buffer memory 214 can be a component located within the memory controller 210, or it can be located outside the memory controller 210.

[0042] ECC engine 216 can be configured to perform error detection and correction functions on read data read from memory device 220. More specifically, ECC engine 216 can generate parity bits for write data to be written to memory device 220, and the parity bits generated in this way can be stored in memory device 220 along with the write data. When reading data from memory device 220, ECC engine 216 can use the parity bits read from memory device 220 along with the read data to correct errors in the read data and output the error-corrected read data.

[0043] Temperature sensor 230 can be configured to measure the internal temperature of storage device 200 and send the measured temperature to memory controller 210. When the internal temperature of storage device 200 is higher than a reference temperature, memory controller 210 can perform throttling on storage device 200 by activating throttling controller 215. Therefore, due to throttling, the internal temperature of storage device 200 can be reduced below the reference temperature.

[0044] Throttling controller 215 can be configured to perform throttling based on the current performance of memory device 220. Input / output commands for each of the multiple streams can be executed independently, and memory device 220 can have different input / output throughputs (input / output per second, IOPS) for each of the multiple streams. Input / output throughput can be the number of input / output operations that memory device 220 can process per unit time for each of the multiple streams.

[0045] For example, a stream with high input / output throughput may have a greater impact on the increase in internal temperature of storage device 200. Conversely, a stream with low input / output throughput may have a smaller impact on the increase in internal temperature of storage device 200. Therefore, delaying the input / output commands of a stream with high input / output throughput relatively more significantly has a greater impact on internal temperature.

[0046] In at least one exemplary embodiment of the present invention, the throttling controller 215 can be configured to monitor the input / output throughput of each of the plurality of streams of the memory device 220 in real time. A typical throttling controller can uniformly delay the input / output commands of the plurality of streams, regardless of the different input / output throughputs of the streams.

[0047] Therefore, the throttling controller 215 according to at least one example embodiment of the present invention can delay input / output commands sent in each of the plurality of streams differently based on the monitored input / output throughput of each stream. Specifically, for streams with relatively high input / output throughput, input / output commands can be significantly delayed, and for streams with low input / output throughput, input / output commands can be undelayed or slightly delayed. Thus, the temperature of the storage device 200 can be efficiently reduced, thereby improving throttling efficiency.

[0048] Figure 2 This is a diagram illustrating the operation of controlling the temperature of a storage device according to at least one exemplary embodiment of the concept of the present invention.

[0049] The storage device may include a memory controller, a memory device, and a temperature sensor. The memory controller may include a throttling controller configured to perform throttling on the storage device. Specific example embodiments of the storage device may be referenced above. Figure 1 The descriptions are the same or substantially similar.

[0050] The memory controller can periodically detect the current temperature of the storage device using the output of a temperature sensor (S100). For example, in at least some embodiments, the memory controller can be configured to detect the current temperature based on at least one of a timer or a clock signal. The current temperature of the storage device can correspond to the current internal temperature of the storage device. The memory controller can compare the current temperature of the storage device with a reference temperature (S110). Here, the reference temperature can be a specific temperature used as a reference for triggering or terminating throttling of the storage device. For example, the reference temperature can be 100°C (on a Celsius scale), but is not limited thereto.

[0051] If the current temperature of the storage device is equal to or lower than the reference temperature (S110 No), throttling for the storage device is not performed, and the current temperature of the storage device can be continuously monitored (S110).

[0052] If the current temperature of the storage device is higher than the reference temperature (S110), the throttling controller can throttle the storage device (e.g., perform throttling on the storage device) (S120). According to at least one example embodiment of the invention, the throttling controller can differently delay input / output commands sent in each of the plurality of streams based on the monitored input / output throughput corresponding to each stream.

[0053] If the current temperature of the storage device is higher than the reference temperature (No in S130), the throttling controller may continue to throttle the storage device (S120). If the current temperature of the storage device is lower than the reference temperature (Yes in S130), the throttling controller may terminate the throttling of the storage device (S140).

[0054] In the following text, before specifically illustrating at least one example embodiment of the throttling controller according to the inventive concept, reference will be made to... Figures 3 to 5 Describe the memory device in detail.

[0055] Figure 3 This is a block diagram illustrating at least one example embodiment of a memory device according to a concept of the present invention.

[0056] refer to Figure 3 The memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. Although not explicitly stated... Figure 2As shown, however, memory device 300 may also include memory interface circuitry configured to receive commands CMD and addresses ADDR from an external source and exchange data DATA with the external source, and may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. Here, a single input / output command received from the memory controller in a single stream of the memory device may include commands CMD and addresses ADDR received from an external source and data DATA exchanged with the external source.

[0057] The control logic circuit 320 can be configured to generally control various operations within the memory device 300. The control logic circuit 320 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0058] The memory cell array 330 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 330 may be connected to the page buffer 340 via bit line BL, and may be connected to the line decoder 360 via word line WL, serial select line SSL, and ground select line GSL.

[0059] For example, memory cell array 330 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include multiple NAND strings. Each NAND string may include memory cells connected to word lines vertically stacked on a substrate. In at least one example embodiment, memory cell array 330 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include multiple NAND strings arranged in row and column directions.

[0060] Page buffer 340 may include multiple page buffers PB1 to PBn (n is an integer of 3 or greater), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL. Page buffer 340 may respond to column address Y-ADDR to select at least one bit line in the bit line BL. Page buffer 340 may operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer 340 may detect the data stored in the memory cell by detecting the current or voltage of the selected bit line.

[0061] Voltage generator 350 can be configured to generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, read voltage, programming verification voltage, erase voltage, etc., as word line voltage VWL.

[0062] The row decoder 360 can select one word line from multiple word lines (WL) and one string select line from multiple string select lines (SSL) in response to the row address X-ADDR. For example, during a programming operation, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the row decoder 360 can apply a read voltage to the selected word line.

[0063] Figure 4 This is a diagram illustrating a 3DV-NAND structure applicable to a storage device, based on at least one example embodiment of the concept according to the present invention.

[0064] refer to Figure 4 When the memory device of a storage device is implemented as 3D V-NAND flash memory, each of the multiple memory blocks constituting the memory device can be represented as follows: Figure 4 The equivalent circuit shown is shown in the figure.

[0065] refer to Figure 4 The memory block BLKi includes multiple NAND strings that can be formed in a direction perpendicular to the substrate. The memory block BLKi may include multiple NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Although Figure 4 Each of the multiple memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, ..., MC8, but is not necessarily limited to these.

[0066] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3, respectively. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL. Word lines of the same height (e.g., WL1) can be connected together, and the ground select lines GSL1, GSL2, and GSL3 and the serial select lines SSL1, SSL2, and SSL3 can be separate. Figure 4 In the diagram, the memory block BLKi is shown connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2 and BL3, but is not necessarily limited to this.

[0067] Figure 5 This is a diagram illustrating the threshold voltage distribution of a memory cell according to at least one example embodiment of the present invention.

[0068] refer to Figure 5 In each graph, the horizontal axis represents the magnitude of the threshold voltage, and the vertical axis represents the number of memory cells. Storage devices can include a variety of different memory types. For example, memory types can include one or more of single-level cell, multi-level cell, three-level cell, and four-level cell types.

[0069] When the memory cell is a single-level cell (SLC) storing 1 bit of data, the memory cell can have a threshold voltage corresponding to either a first programming state P1 or a second programming state P2. The read voltage Va1 can be used to distinguish between the first programming state P1 and the second programming state P2. A memory cell with the first programming state P1 can be read as an ON cell because it has a threshold voltage lower than the read voltage Va1. A memory cell with the second programming state P2 can be read as an OFF cell because it has a threshold voltage higher than the read voltage Va1.

[0070] When the memory cell is a multi-level cell (MLC) storing 2 bits of data, the memory cell can have a threshold voltage corresponding to one of the first programming states P1 to the fourth programming state P4. The first read voltage Vb1 to the third read voltage Vb3 can be read voltages used to distinguish between the first programming state P1 and the fourth programming state P4, respectively. The first read voltage Vb1 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2. The second read voltage Vb2 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3. The third read voltage Vb3 can be a read voltage used to distinguish between the third programming state P3 and the fourth programming state P4.

[0071] When the memory cell is a triple-level cell (TLC) storing 3 bits of data, the memory cell can have a threshold voltage corresponding to any one of the first programming states P1 to the eighth programming state P8. The first read voltage Vc1 to the seventh read voltage Vc7 can be read voltages used to distinguish between the first programming states P1 to the eighth programming states P8, respectively. The first read voltage Vc1 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2. The second read voltage Vc2 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3. Similarly, the seventh read voltage Vc7 can be a read voltage used to distinguish between the seventh programming state P7 and the eighth programming state P8.

[0072] When the memory cell is a quadruple level cell (QLC) storing 4 bits of data, the memory cell can have a threshold voltage corresponding to any one of the first programming states P1 to the sixteenth programming state P16. The first read voltage Vd1 to the fifteenth read voltage Vd15 can be read voltages used to distinguish between the first programming states P1 to the sixteenth programming state P16, respectively. The first read voltage Vd1 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2. The second read voltage Vd2 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3. Similarly, the fifteenth read voltage Vd15 can be a read voltage used to distinguish between the fifteenth programming state P15 and the sixteenth programming state P16.

[0073] However, these are just examples, and the types of memory cells are not limited to these.

[0074] A memory controller according to at least one exemplary embodiment of the present invention can independently control memory cells of the same type by separating memory cells of the same type into different regions. In the following, automotive storage devices included in automotive equipment will be described as at least one exemplary embodiment of the present invention.

[0075] For example, when a memory device comprises two or more memory cells selected from SLC, MLC, TLC, and QLC, the memory controller can independently control the SLC, MLC, TLC, and QLC memory cell regions by separating them. The memory controller can send input / output commands to each of the multiple memory cell regions via different streams.

[0076] In at least one exemplary embodiment of the present invention, the memory controller can monitor the input / output throughput of each of a plurality of memory cell regions in real time. Based on the monitored input / output throughput of each memory cell region, the memory controller can delay input / output commands sent to each of the plurality of memory cell regions via different streams.

[0077] For example, when the input / output throughput of an SLC memory cell region is relatively high, the input / output commands sent to the SLC memory cell region can be delayed relatively more. The temperature of the SLC memory cell region, which has a significant impact on the internal temperature of the storage device, can be reduced more significantly. As another example, when the input / output throughput of a QLC memory cell region is relatively low, the input / output commands sent to the QLC memory cell region can be delayed relatively less. The temperature of the QLC memory cell region, which has a relatively small impact on the internal temperature of the storage device, can be reduced relatively less. Therefore, the internal temperature of the storage device can be controlled efficiently.

[0078] Figure 6 This is a block diagram schematically illustrating at least one example embodiment of a throttling controller according to the concept of the present invention.

[0079] The storage device may include a memory controller, a memory device, and a temperature sensor. In this case, the storage device may be included in an automotive device. The memory controller may include a throttling controller 400 that performs throttling on the storage device. The memory controller may use the output of the temperature sensor to periodically detect the current temperature of the storage device. Specific embodiments of the storage device may be referenced above. Figures 1 to 5 The descriptions are the same or substantially similar.

[0080] If the current temperature of the storage device is higher than the reference temperature, the throttling controller 400 can perform throttling on the storage device. First, the reference... Figure 6 The throttling controller 400 may include a workload manager 410, a throttling manager 420, and a throttling table 430.

[0081] The workload manager 410 can periodically monitor the current performance CP of each of multiple flows. In this case, the current performance CP can include input / output throughput. The workload manager 410 can send the monitoring results to the throttling manager 420.

[0082] The throttling manager 420 can determine (e.g., calculate) a target delay value TD based on the current performance CP of each of the monitored multiple streams to delay input / output commands sent in each of the multiple streams. Here, the target delay value TD can be a value applied by the memory controller to delay the input / output commands sent through each of the multiple streams. The target delay value TD can correspond to a change in the waiting time between input / output commands or a change in the duration of input / output command transmission, but the type of target delay value TD may not be limited to these.

[0083] The target delay value TD determined by the throttling manager 420 can be sent to the throttling table 430 and stored in the throttling table 430.

[0084] In the following text, reference will be made to Figures 7 to 9 Describe in detail the process of calculating the target delay value TD.

[0085] Figure 7 This is a flowchart illustrating the throttling operation of a throttling controller according to at least one example embodiment of the concept of the present invention. Figure 8 This is a graph illustrating the performance ratio per flow of a storage device according to the temperature range of at least one example embodiment of the invention. Figure 9 This is a diagram illustrating the calculation of the target delay value per stream according to at least one example embodiment of the concept of the present invention.

[0086] First, refer to Figure 7 The workload manager can periodically monitor the current performance of each of the multiple streams (S200). For example, the workload manager can monitor the current performance based on at least one of a timer or a clock signal. Here, the workload manager can monitor the current performance after the throttling operation begins, or continuously regardless of the throttling operation. In at least one example embodiment, the workload manager can calculate the input / output throughput processed by each of the multiple streams within 1 second as the current performance of the corresponding stream. However, the type and time period of performance are not limited to this.

[0087] The throttling manager can receive the current temperature CT of the storage device, which is detected periodically. The throttling manager can determine (e.g., calculate) a reference performance ratio for each of the multiple streams based on the current temperature CT of the storage device (S210).

[0088] refer to Figure 8 , Figure 8 This can represent the performance ratio PR for each of the multiple streams S1 to Sn for a temperature section TR of the storage device. The performance ratio PR for the temperature section TR can be data predetermined during the design and / or testing phases of the storage device. The data for the temperature section TR and performance ratio PR of the storage device can be expressed as follows: Figure 8 The chart format shown is stored in the throttling controller or memory controller, but the data format and / or storage location are not limited to this.

[0089] The temperature range TR of the storage device can be larger than the reference temperature of the storage device. Each of the first temperature ranges TR1 to the x-th temperature range TRx can have the same value, or at least one of the first temperature ranges TR1 to the x-th temperature range TRx can have a different value. The first temperature range TR1 can represent the range with the lowest temperature, and the x-th temperature range TRx can represent the range with the highest temperature. Therefore, the temperature can increase from the first temperature range TR1 to the x-th temperature range TRx.

[0090] The performance ratio PR can represent the ratio to the maximum performance (referred to as "maximum performance" in this document), and the unit can be % (percentage). The performance ratio PR can represent the ratio of each of multiple flows S1 to Sn to the maximum performance. For example, the performance ratio PR can have a value less than or equal to one hundred (100). However, the size of the performance ratio PR is not limited to this.

[0091] For example, when the current temperature CT of the storage device corresponds to the first temperature range TR1, the performance ratio of the first stream S1 can be controlled to change to the eleventh performance ratio RP11, and the performance ratio of the nth stream Sn can be controlled to change to the (n+1)th performance ratio RPn1. The throttling manager can determine the range corresponding to the current temperature CT from the first temperature range TR1 to the xth temperature range TRx, and determine the performance ratio PR of the corresponding range as the reference performance ratio RPR for each stream.

[0092] refer to Figure 9The current performance of each of the multiple streams S1 to Sn can correspond to a first current performance CP1 to an nth current performance CPn. The first current performance CP1 can refer to the number of input / output commands processed by the memory device for the first stream within a predetermined time period. For example, the current performance CP can represent the number of input / output commands for the stream corresponding to the memory device in one (1) second. The first reference performance ratio RPR1 to the nth reference performance ratio RPRn of each of the multiple streams S1 to Sn can be the reference ratios mentioned above. Figure 8 A defined reference performance ratio.

[0093] refer to Figure 7 and Figure 9 The throttling manager can determine a reference performance RP and a reference delay value RD (S220) for each of multiple flows S1 to Sn. The reference performance RP for each of the multiple flows S1 to Sn can be determined (e.g., calculated) as or based on the product of the current performance CP and the reference performance ratio RPR. The reference performance RP can be equal to or greater than the minimum performance of flow S. The minimum performance can be the minimum number of input / output commands to be executed per unit time for each of the multiple flows S1 to Sn.

[0094] The reference delay value RD can correspond to the difference between the reference performance RP and the current performance CP. The current performance CP of each of the multiple flows S1 to Sn can be the maximum performance of each flow.

[0095] For example, the reference delay value RD can be a value added to the transmission period of the input / output command, and the transmission period of the input / output command sent by the memory controller to the memory device can be changed by the reference delay value RD. At least one of the first reference delay values ​​RD1 to nth reference delay values ​​RDn of the multiple streams S1 to Sn can be different.

[0096] The throttling manager can determine the weights W1 to Wn of each of a plurality of flows S1 to Sn (S230). Each of the weights W1 to Wn can be calculated using a first reference performance RP1 to an nth reference performance RPn. In at least one example embodiment of the inventive concept, the weights W1 to Wn of each of the plurality of flows S1 to Sn can represent the ratio of the current performance of the corresponding flow to the sum (e.g., and) of the current performances CP1 to CPn or the total reference performance (e.g., the sum of the first reference performances RP1 to the nth reference performances RPn). For example, in at least one example embodiment, if the first current performance CP1 accounts for 70% of the sum of the current performances CP1 to CPn, then the first weight W1 can be 0.7. The sum of the first weights W1 to the nth weight Wn can be 1.

[0097] The throttling manager can determine and apply a target delay value TD (S240) to each of a plurality of streams S1 to Sn by reflecting weights W1 to Wn on reference delay values ​​RD1 to RDn. In at least one example embodiment, the target delay value TD can be a value obtained by applying weights W to the reference delay value RD. In the example, if the first weight W1 is 0.7, then the first target delay value TD1 can be 0.7 times the first reference delay value RD1. Each of the first target delay values ​​TD1 to the nth target delay value TDn calculated by the throttling manager can be applied to the corresponding stream S such that the transmission period of input / output commands sent through the stream can be changed by the target delay value TD. Therefore, the target delay value TD can be the amount of change in the transmission period of input / output commands.

[0098] The throttling manager can send the calculated first target delay value TD1 to the nth target delay value TDn to the throttling table. The throttling table can store the first target delay value TD1 to the nth target delay value TDn (S250). For example, the first target delay value TD1 to the nth target delay value TDn corresponding to the first stream S1 to the nth stream Sn respectively can be stored in the throttling table in the form of a table. However, the storage format and / or location of the data are not limited to this.

[0099] Even after reflecting the target latency values ​​TD1 to TDn, the workload manager can periodically monitor the current performance CP of each of the multiple flows S1 to Sn and send it to the throttling manager. The throttling manager can determine whether a reference performance RP is measured in each of the multiple flows S1 to Sn (S260). Here, the reference performance RP1 to RPn can be the result determined in the previous operation S220.

[0100] If reference performance RP1 to RPn is measured in each of the multiple streams S1 to Sn (as in S260), the throttling manager can determine whether throttling of the storage device has terminated (S280). The throttling manager can apply first target latency values ​​TD1 to nth target latency values ​​TDn until throttling of the storage device terminates, and continue to determine whether reference performance RP is measured.

[0101] If reference performance RP1 to RPn is not measured in each of the multiple flows S1 to Sn (No in S260), the throttling manager can correct the individual weights W1 to Wn of the multiple flows S1 to Sn (S270). For example, when the current performance of each of the multiple flows does not fall within the tolerance range of the reference performance, the throttling manager can correct the weights corresponding to the multiple flows that fall outside the tolerance range. The sum of the first weights W1 to the nth weights Wn remains constant, and some of the first weights W1 to the nth weights Wn can be increased or decreased within a predetermined range. In at least one example embodiment, the first weight W1 can be increased by 5%, and the nth weight Wn can be decreased by 5%. However, the inventive concept is not limited to this.

[0102] The throttling manager can repeatedly perform the process of determining and applying the target delay value TD for each of the multiple flows S1 to Sn and determining whether the reference performance RP is measured by reflecting the corrected weights on the reference delay values ​​RD1 to RDn calculated in operation S220 (S240 to S260). The above process can be repeated until the reference performance RP is measured in each of the multiple flows S1 to Sn.

[0103] According to at least one example embodiment of the present invention, the delay time of an input / output transmission period (e.g., when a reference performance RP is determined in each of a plurality of streams S1 to Sn) can be determined (e.g., calculated) as a target delay value TD for each of the plurality of streams S1 to Sn. In determining the target delay value TD, the reference performance RP and a weight W can be reflected, and the reference performance RP can be equal to or greater than the minimum performance of each stream S. The minimum performance can be the minimum number of input / output commands that must be executed per unit time in the input / output commands of each of the plurality of streams S1 to Sn.

[0104] In other words, when throttling is applied to a storage device, the minimum performance of each of the multiple streams can be maintained. Furthermore, by weighting the current performance of each of the multiple streams, input / output commands sent through each of the multiple streams can be delayed differently. Therefore, the efficiency of reducing the storage device's temperature can be improved by relatively delaying the input / output commands of the streams that have a greater impact on the storage device's temperature rise.

[0105] Figure 10 and Figure 11 This is a diagram illustrating the transmission time of input / output commands according to an embodiment of the present invention.

[0106] The storage device may include a memory controller, a memory device, and a temperature sensor. The memory controller may include a throttling controller that performs throttling on the storage device. The memory controller may use the output of the temperature sensor to periodically detect the current temperature of the storage device. The throttling controller may include a workload manager, a throttling manager, and a throttling table. Specific embodiments of the storage device can be found in the above references. Figures 1 to 9 The descriptions are the same or substantially similar.

[0107] According to at least one example embodiment of the present invention, a throttling manager can calculate a target delay value for delaying the transmission period of input / output commands sent in each of the plurality of monitored streams, based on the current performance of the memory device for each of the plurality of monitored streams. Here, the target delay value may correspond to the amount of change in the transmission period of the input / output commands in each of the plurality of streams.

[0108] according to Figure 10 and Figure 11 In the illustrated embodiment, the memory device can receive input / output commands included in each of the first stream S1 and the second stream S2, and can process the operations indicated by the input / output commands in parallel. If the current temperature of the memory device is higher than a reference temperature and throttling is performed, the throttling controller can delay the transmission period of the input / output commands for each of the first stream S1 and the second stream S2. Each of the first stream S1 and the second stream S2 may include input / output commands sent to the memory device by the host and / or input / output commands generated by the flash conversion layer 212.

[0109] refer to Figure 10 and Figure 11 It can indicate the number of input / output commands sent per unit time for each of the first stream S1 and the second stream S2. Before throttling, five input / output commands can be sent per unit time for the first stream S1, and three input / output commands can be sent per unit time for the second stream S2. The throttling controller can delay the sending period of input / output commands for the first stream S1 and the second stream S2.

[0110] First, refer to Figure 10 The throttling controller can determine the target delay value for each of the first stream S1 and the second stream S2. According to... Figure 10 In the example shown, the target delay value for the first stream S1 can be 2, and the target delay value for the second stream S2 can be 1. In other words, the input / output command sending period of the first stream S1 can be delayed by 2, and the input / output command sending period of the second stream S2 can be delayed by 1.

[0111] refer to Figure 11The throttling controller can calculate the target delay value only for the first flow S1. According to... Figure 11 In the example shown, the target delay value TD1 of the first stream S1 can be 3, and the target delay value TD2 of the second stream S2 can be 0. Here, the current performance of the second stream S2 can be the minimum performance. The minimum performance can be the minimum number of input / output commands that must be executed per unit time in the input / output commands included in the second stream S2. Therefore, the throttling controller can avoid delaying the input / output command transmission period of the second stream S2.

[0112] According to at least one exemplary embodiment of the present invention, a temperature control operation of the storage device can be performed when the current temperature of the storage device is higher than a reference temperature. The memory controller can delay input / output commands sent in each of the multiple streams differently based on the current input / output throughput of each of the multiple streams. Therefore, the temperature control efficiency of the storage device can be improved.

[0113] While some exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A temperature throttling method for a storage device, the temperature throttling method comprising: Monitor the current performance of the memory device, which responds to input / output command operations included in multiple streams; Based on the current temperature of the storage device, a reference performance and a reference latency value are determined for each of the plurality of streams; The weight of each of the plurality of streams is determined based on the current performance. A target delay value is determined for each of the plurality of streams by reflecting the weights on the reference delay value; and The weights for measuring the reference performance are applied to each of the plurality of streams.

2. The temperature throttling method according to claim 1, wherein, Monitoring the current performance includes monitoring the input / output throughput of the memory device for each of the plurality of streams.

3. The temperature throttling method according to claim 1, wherein, Determining the reference performance and the reference delay value for each of the plurality of streams includes: For a given range corresponding to the current temperature of the storage device, a reference performance ratio is determined for each of the plurality of streams; and The reference performance is determined using the current performance and the reference performance ratio of each of the plurality of streams.

4. The temperature throttling method according to claim 3, wherein, The reference performance is based on the product of the current performance and the reference performance ratio, and is equal to or greater than the minimum performance.

5. The temperature throttling method according to claim 3, wherein, The reference delay value is based on the difference between the reference performance and the current performance.

6. The temperature throttling method according to claim 1, wherein, The weight of each of the plurality of streams is based on the ratio of the reference performance of each of the plurality of streams to the total reference performance.

7. The temperature throttling method according to claim 6, wherein, The overall reference performance is based on the sum of the weights of each of the plurality of streams.

8. The temperature throttling method according to claim 6, wherein, The sum of the weights of each of the plurality of streams is one.

9. The temperature throttling method according to claim 1, wherein, The target delay value is obtained by applying the weight to the reference delay value.

10. The temperature throttling method according to claim 1, wherein, The target delay value includes the amount of change in the transmission period of each of the input / output commands.

11. The temperature throttling method according to claim 1, further comprising: By applying the target delay value to the corresponding stream among the plurality of streams, the transmission period of at least one of the input / output commands is delayed.

12. The temperature throttling method according to claim 1, wherein, Applying the weights includes, for each of the plurality of streams: The current performance is monitored repeatedly by applying the target latency value; and The weights are adjusted when the current performance does not fall within a specific range of the reference performance.

13. The temperature throttling method according to claim 1, wherein, The multiple streams correspond to memory cell regions that include different types of memory cells.

14. The temperature throttling method according to claim 13, wherein, The different types of memory cells include two or more of single-level cells, multi-level cells, three-level cells, or four-level cells.

15. A temperature throttling method for an automotive storage device, the temperature throttling method comprising: Based on the current temperature of the automotive storage device, a reference performance ratio is determined for each of the multiple streams; The reference performance is determined by multiplying the current performance corresponding to each of the plurality of streams by the reference performance ratio of each of the plurality of streams; A reference delay value is determined for each of the plurality of streams based on the difference between the current performance and the reference performance; The weight of each of the plurality of flows is determined based on the ratio of the current performance corresponding to each of the plurality of flows to the sum of the current performances of the plurality of flows; By applying the weights to the reference delay value, the target delay value for the corresponding flow among the plurality of flows is determined; and For each of the plurality of streams, the target delay value is applied to the corresponding stream.

16. The temperature throttling method according to claim 15, wherein, The current performance includes the input / output throughput of each of the plurality of streams.

17. The temperature throttling method according to claim 15, further comprising: By applying the target delay value to the corresponding stream, the sending period of input / output commands is delayed.

18. The temperature throttling method according to claim 15, wherein, The multiple streams correspond to memory cell regions that include different types of memory cells.

19. The temperature throttling method according to claim 18, wherein, The different types of memory cells include at least one of single-level cells, multi-level cells, three-level cells, or four-level cells.

20. A temperature throttling method for a storage device, the temperature throttling method comprising: Based on the determination that the current temperature of the storage device is higher than the reference temperature, throttling of the storage device is initiated. Monitor the input / output throughput of each of multiple streams; The delay time for the input / output transmission period applied to each of the plurality of streams is determined by reflecting the current temperature of the storage device and the input / output throughput of each of the plurality of streams; The delay time in the delay time is applied to the corresponding stream in the plurality of streams; and Based on the determination that the current temperature of the storage device is lower than the reference temperature, the throttling of the storage device is terminated. Wherein, at least a portion of the delay time applied to the input / output transmission period of the plurality of streams is different from at least a portion of the remaining portion of the delay time of the input / output transmission period.

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