A gpu-accelerated gate-level timing concurrent simulation method and system

Abstract

The application provides a GPU accelerated gate-level timing parallel simulation method and system, which realizes double parallel acceleration of space and time by dividing the circuit into logical cones mapped to GPU thread blocks and dividing time into multi-cycle windows; when it is detected that the register prediction value is inconsistent with the actual value, local rollback for a specific logical cone and time window is triggered to minimize calculation waste, and the error register and its predecessor combination logic are automatically extracted to build a local error gate-level subnetwork, and a correction value is generated by using gate-level simulation to update the prediction state of the subsequent window; the self-optimization ability of this error correction, i.e., learning, effectively avoids the repeated occurrence of the same error source, significantly reduces the rollback frequency and range, thereby greatly improving the overall throughput efficiency of parallel simulation while ensuring gate-level timing accuracy.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design verification technology, and more specifically, to a GPU-accelerated gate-level timing parallel simulation method and system. Background Technology

[0002] With the continuous evolution of digital integrated circuit process nodes and the rapid expansion of design scale, the complexity of chip verification is increasing daily. Gate-level timing simulation, as a core step in verifying the correctness of chip physical implementation, involves simulating low-level logic gates (such as inverters and AND gates). Compared to the abstract functional statements in RTL simulation (such as adders), gate-level simulation requires the operation of hundreds or thousands of logic gates to simulate the same function, resulting in an order-of-magnitude increase in computational overhead. Furthermore, gate-level simulation requires loading a standard delay format (SDF) file extracted from the layout to accurately detect timing violations such as setup time, hold time, and signal integrity. This high-fidelity simulation leads to a significant decrease in simulation efficiency: a test case that takes only a few minutes in RTL simulation often takes several hours in gate-level netlist simulation, becoming a key performance bottleneck restricting the chip verification process.

[0003] In terms of simulation mechanisms, gate-level timing simulation typically employs an event-driven model. This model abstracts the circuit as a network of delayed logic gates, and the simulation kernel maintains a globally time-ordered event queue. Any change in the input signal triggers the recalculation of subsequent logic and generates new events added to the queue, thereby accurately simulating gate and interconnect delays and effectively capturing dynamic timing issues such as race conditions and glitches. However, the event-driven mechanism is inherently limited by the serial processing mechanism of the global event queue, making it computationally intensive and difficult to directly parallelize. When dealing with large-scale circuits, the processing of massive amounts of events leads to extremely low simulation efficiency.

[0004] To overcome performance limitations, the industry has explored various parallelization paths, but all have faced challenges. For example, while module-level parallel simulation divides the design, the dense signal interactions between sub-modules often result in communication and synchronization overhead exceeding computational gains, and load balancing is difficult, with parallel efficiency rapidly decreasing as the number of cores increases. Fine-grained parallelism (such as parallel processing of event or gate computation) suffers from the highly coupled dependencies within the circuit netlist, leading to frequent synchronization between threads, which can easily cause cache consistency conflicts and lock contention, resulting in limited actual speedup.

[0005] In recent years, leveraging GPUs for massively parallel acceleration has become a research hotspot. However, the irregular and dynamic nature of traditional event-driven simulations is incompatible with the GPU's strength in regular, large-scale data parallelism, resulting in inefficient direct mapping. In contrast, cycle-parallelism simulation methods divide the process into clock cycles, with each cycle primarily performing combinational logic evaluation, demonstrating greater data parallelism potential. Nevertheless, existing GPU-based cycle-parallelism schemes still fall short in balancing speed and accuracy. In particular, high-frequency rollbacks and large-scale state recovery due to inaccurate timing predictions severely offset the performance gains from parallel computing, and overall simulation efficiency still needs improvement. Summary of the Invention

[0006] The purpose of this application is to provide a GPU-accelerated gate-level time-parallel simulation method and system to address the shortcomings of existing technologies in balancing speed and accuracy. In particular, the high-frequency rollback and large-scale state recovery caused by inaccurate timing prediction severely offset the performance gains brought by parallel computing, and the overall simulation efficiency still needs to be improved.

[0007] This application provides a GPU-accelerated gate-level time-parallel simulation method, including: Based on the circuit partitioning information, the gate-level circuit netlist is divided into L logic cones; The simulation time is divided into M simulation windows, and each simulation window includes N consecutive clock cycles; Through RTL simulation, register state prediction values ​​for M×N clock cycles are generated; Launch L thread blocks of the GPU to perform simulation calculations based on the test stimulus. Each thread block is responsible for the calculation of a logic cone within N clock cycles, and obtains the actual values ​​of the register states corresponding to the L logic cones. The actual register status value is compared with the corresponding predicted register status value. If an inconsistency is detected, the first faulty register and the first faulty time window are located. Extract the first error register and all its predecessor combinational logic, and add them to the local error gate subnet; Perform gate-level simulation on the partially faulty gate-level subnet to generate the first fault time window and the first register state prediction correction value for the subsequent time windows; The register state prediction value is updated using the first register state prediction correction value; A partial rollback is triggered, and the logic cone related to the first error register is sent to the GPU for simulation tasks in the first error time window and subsequent time windows. The corresponding thread block of the GPU is then started to re-perform the simulation calculation.

[0008] In the above technical solution, by dividing the circuit into logic cones and mapping them to GPU thread blocks, and dividing the time into multiple cycle windows, dual parallel acceleration in space and time is achieved. When a discrepancy is detected between the predicted value and the actual value of the register, a local rollback is triggered for a specific logic cone and time window to minimize computational waste. Furthermore, the faulty register and its predecessor combinational logic are automatically extracted to construct a local fault gate-level subnet. The gate-level simulation is used to generate correction values ​​to update the prediction state of subsequent windows. This error correction and learning self-optimization capability effectively avoids the recurrence of the same error source, significantly reduces the rollback frequency and range, and thus greatly improves the overall throughput efficiency of parallel simulation while ensuring gate-level timing accuracy.

[0009] In some alternative implementations, prior to launching the L thread blocks of the GPU, the following is also included: Static timing and structural analysis are performed on the gate-level circuit netlist to identify high-risk registers; Extract high-risk registers and all their predecessor combinational logic to form a high-risk, suspicious gate-level subnet; Gate-level simulation was performed on high-risk, suspicious gate-level subnets to obtain reference values ​​for register state prediction. The register state prediction reference value is compared with the corresponding register state prediction value. If an inconsistency is detected, the second fault register and the second fault time window are located. Extract the second error register and all its predecessor combinational logic, and add them to the local error gate subnet; Perform gate-level simulation on the partially faulty gate-level subnet to generate the second fault time window and the second register state prediction correction value for the subsequent time window; The register state prediction value is updated using the second register state prediction correction value.

[0010] The above technical solution integrates static temporal pre-analysis and dynamic subnet learning mechanisms to construct a dual prediction optimization system of pre-emptive prevention and in-process correction, significantly reducing the rollback overhead during simulation. Building upon the original dynamic error capture and subnet expansion, the addition of pre-simulation static temporal analysis and high-risk subnet pre-correction can eliminate prediction errors caused by known temporal violation paths in advance, significantly reducing the rollback rate of the first simulation window and avoiding waste of initial GPU computing resources. This combination of static prior knowledge and dynamic adaptive capabilities not only compensates for the initial error cost of relying solely on runtime learning but also further refines the prediction model, ensuring higher prediction accuracy throughout the entire simulation cycle, thereby maximizing the effective utilization of GPU parallel computing and overall throughput efficiency.

[0011] In some optional implementations, the second error register and all its predecessor combinational logic are extracted and added to the local error gate-level subnet, including: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove subnets from high-risk, suspicious gate-level subnets.

[0012] In some alternative implementations, adding to the local error gate-level subnet includes: The newly extracted local error gate-level subnets are merged with the existing local error gate-level subnets in the netlist. During the merging process, identical logical parts are identified and eliminated.

[0013] In some alternative implementations, the simulation task for each logic gate of the logic cone is assigned to a separate thread bundle of the corresponding thread block; Multiple threads within a thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

[0014] The aforementioned technical solution employs a fine-grained parallel mapping model of "logic gate-thread bundle, simulation cycle-thread," which deeply aligns with the SIMD architecture characteristics of GPUs. By assigning the computational tasks of the same logic gate in different clock cycles to different threads within the same thread bundle, it ensures that all threads within the thread bundle execute the exact same logic gate evaluation instructions, completely eliminating branch divergence within the thread bundle and maximizing the processing efficiency of single instruction multiple data streams. Simultaneously, this mapping method further explores the potential of temporal parallelism based on logic cone space parallelism, significantly improving the utilization of GPU core resources and the throughput of large-scale gate-level evaluation, thus guaranteeing the efficiency and stability of parallel computing.

[0015] This application provides a GPU-accelerated gate-level time-parallel simulation system, comprising: a CPU side and a GPU side; The CPU side includes a task scheduling and communication module, a subnet management module, and a mixed-precision simulation predictor. The task scheduling and communication module is used to: divide the gate-level circuit netlist into L logic cones according to the circuit partitioning information; and divide the simulation time into M simulation windows, each simulation window including N consecutive clock cycles. A mixed-precision simulation predictor is used to generate M×N clock cycle predicted register state values ​​through RTL simulation. On the GPU side, it is used to: launch L thread blocks of the GPU, perform simulation calculations according to the test stimulus, each thread block is responsible for the calculation of a logic cone in N clock cycles, and obtain the actual values ​​of the register states corresponding to the L logic cones; compare the actual values ​​of the register states with the corresponding predicted values ​​of the register states, and if an inconsistency is detected, locate the first fault register and the first fault time window; The subnet management module is used to: extract the first error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; A mixed-precision simulation predictor is used to: perform gate-level simulation on a locally faulty gate-level subnet, generate first register state prediction correction values ​​for the first fault time window and subsequent time windows; and update register state prediction values ​​using the first register state prediction correction values. The task scheduling and communication module is also used to: trigger a partial rollback, send the logic cone related to the first error register to the GPU for simulation tasks in the first error time window and subsequent time windows, and start the corresponding thread block of the GPU to re-perform the simulation calculation.

[0016] In some alternative implementations, the subnet management module dynamically maintains and runs locally faulty gate-level subnets and high-risk, suspicious gate-level subnets.

[0017] In some optional implementations, the task scheduling and communication module is also used to: acquire high-risk registers; The subnet management module is also used to: extract high-risk registers and all their predecessor combinational logic to form high-risk suspicious gate-level subnets; The hybrid precision simulation predictor is also used for: performing gate-level simulation on high-risk suspicious gate-level subnets to obtain register state prediction reference values; comparing the register state prediction reference values ​​with the corresponding register state prediction values, and if an inconsistency is detected, locating the second fault register and the second fault time window; The subnet management module is also used to: extract the second error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; The hybrid precision simulation predictor is also used for: performing gate-level simulation on a locally faulty gate-level subnet, generating second error time windows and subsequent second register state prediction correction values; and using the second register state prediction correction values ​​to update the register state prediction values.

[0018] In some alternative implementations, the subnet management module is also used for: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove subnets from high-risk, suspicious gate-level subnets.

[0019] In some alternative implementations, the simulation task for each logic gate of the logic cone is assigned to a separate thread bundle of the corresponding thread block; Multiple threads within a thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

[0020] In some alternative implementations, the hybrid precision simulation predictor includes an RTL simulator and a gate-level simulation engine; An RTL simulator is used for RTL simulation. The gate-level simulation engine is used for gate-level simulation; Both the RTL simulator and the gate-level simulation engine support quaternary logic systems with 0, 1, unknown states, and high-impedance states.

[0021] In some alternative implementations, the data communication between the CPU and the GPU is pipelined to overlap with the computation process on the GPU. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating the steps of a GPU-accelerated gate-level temporal parallel simulation method provided in this application embodiment; Figure 2 A functional block diagram of a GPU-accelerated gate-level temporal parallel simulation system provided in this application embodiment; Figure 3 This is a schematic diagram of a GPU-side three-level mapping parallel computing model provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0025] Please refer to Figure 1 , Figure 1 A flowchart illustrating the steps of a GPU-accelerated gate-level temporal parallel simulation method provided in this application embodiment includes: Step 100: Based on the circuit partitioning information, divide the gate-level circuit netlist into L logic cones; Specifically, the RepCut algorithm combined with the hMetis hypergraph partitioner is used to partition the combinational logic netlist into multiple independent logic cones. Each logic cone maps to a GPU thread block. Since the combinational logic within a thread block has no cross-dependencies, inter-block parallelism can be achieved. The partitioning goal is to ensure load balancing (similar workloads across thread blocks) while reducing logic duplication (avoiding the same logic gate being repeatedly computed across multiple cones). Each thread block is responsible for an independent logic cone, and threads within a block can efficiently synchronize and communicate without cross-block synchronization. The number of logic cones (i.e., the number of thread blocks) is dynamically determined by the partitioning algorithm. The algorithm determines an appropriate number of logic cones based on the size and structure of the netlist, as well as GPU hardware resources (such as the number of SMs and the number of thread blocks each SM can hold). Typically, the number of logic cones is much larger than the number of SMs on the GPU to ensure sufficient thread blocks to fill all SMs, achieving high GPU utilization.

[0026] Step 200: Divide the simulation time into M simulation windows, each simulation window including N consecutive clock cycles; The entire simulation time is divided into M windows, each containing N consecutive clock cycles. To fully utilize the parallelism of the GPU, initial register state predictions are generated for all M such windows at once and submitted to the GPU for parallel computation. Adjacent windows overlap by one cycle to ensure the continuity of timing checks (such as setup / hold times) across window boundaries.

[0027] Step 300: Generate register state prediction values ​​for M×N clock cycles through RTL simulation; Among them, RTL simulation is a fast 0-delay functional level RTL simulation, which obtains the initial register value prediction sequence of M windows.

[0028] Step 400: Start the L thread blocks of the GPU and perform simulation calculations according to the test stimulus. Each thread block is responsible for the calculation of a logic cone in N clock cycles to obtain the actual values ​​of the register states corresponding to the L logic cones. Specifically, the GPU-side parallel computing process includes: receiving the pre-defined combinational logic cone netlist structure data, the initial register state of the current window, and the input stimuli from the CPU. Read-only data such as netlist connections and delay information are stored in constant memory for faster access. Using the delay information of the sequential logic (obtained from the SDF file), the 0-delay sequential logic output waveform is converted into a delayed waveform. For example, the output of a D flip-flop changes after a certain clock-to-Q delay following the rising edge of the clock. Therefore, in the 0-delay simulation, we record the output value at the active clock edge, but this value should actually appear at the output after a certain delay. Therefore, in the re-simulation stage, we need to add the clock delay and the clock-to-Q delay to the 0-delay waveform to form a delayed waveform, which serves as the input to the combinational logic of the logic cone.

[0029] Step 500: Compare the actual value of the register status with the corresponding predicted value of the register status. If an inconsistency is detected, locate the first fault register and the first fault time window. Specifically, after the GPU completes the parallel computation of all combinational logic within a window, it can obtain the waveform data of the registers for these N cycles. Based on the waveform data of the N cycles, it performs register setup time checks and hold time checks for the previous (N-1) cycles (since the hold time check needs to be performed across cycles, the results of the N cycles can only detect the timing of the N-1 cycles). According to the timing check results, it updates the state value of each register in the next cycle and compares the updated register value with the corresponding predicted value received from the CPU.

[0030] Step 600: Extract the first error register and all its predecessor combinational logic, and add them to the local error gate subnet; In this process, the CPU does not trigger a global rollback. Instead, it initiates a local error subnet extraction: starting from the error register, it traverses backwards through all its predecessor combinational logic (i.e., the logic cone with the error register as the fixed point) until it encounters a node that is an original input, register output, or already exists in the precise subnet, forming a local error gate-level subnet. This newly extracted subnet is then merged and deduplicated with the existing precise simulation subnet within the predictor, updating the predictor's simulation range. The current window and subsequent windows require rollback. Afterward, in the RTL simulation of subsequent windows, the predictor will synchronously perform precise simulation on this expanded subnet, thereby fundamentally correcting the error prediction source and preventing the same error from recurring in future windows.

[0031] Step 700: Perform gate-level simulation on the local error gate-level subnet to generate the first error time window and the first register state prediction correction value for subsequent time windows; For circuits included in the precise gate-level timing simulation subnet, precise gate-level timing simulation with delay information is performed. The input signals for this simulation are: for the original inputs, clock signals, and reset signals at the subnet boundaries, the input values ​​are consistent with the excitation sources used by the GPU for global gate-level timing simulation, where the clock and reset signals use waveforms with delay information required for gate-level timing simulation; for nodes at the subnet boundaries driven by RTL simulation units, the input value is the corresponding output value of the current period's RTL simulation. To simulate precise gate-level timing, the delay information of the timing logic (obtained from the SDF file) is used to convert the 0-delay register output waveform into a delayed waveform. For example, the output of a D flip-flop changes after a certain clock-to-Q delay after the rising edge of the clock. Therefore, in the 0-delay simulation, we record the output value when the clock edge is valid, but this value should actually appear at the output after a certain delay. Therefore, in the precise simulation phase of the gate-level subnet, we need to add the clock delay and the clock-to-Q delay to the 0-delay waveform to form a delayed waveform, which serves as the input to the combinational logic at the gate-level register. Since the inputs of the combinational logic (including the outputs from the sequential logic) now have precise delays, the precise delay waveform of the gate-level combinational logic can be accurately calculated.

[0032] Step 800: Update the register state prediction value using the first register state prediction correction value; Specifically, the results of the accurate subnet simulation are used to directly replace the corresponding register values ​​in the RTL (for example, by using the force statement, force top.dut_rtl.reg_a_0 = top.dut_gate.reg_a_0, replacing the register top.dut_gate.reg_a_0 of the gate-level netlist with the register dut_rtl.reg_a_0 of the RTL simulation). After the RTL simulation is performed, a corrected and more accurate initial register state for the window is naturally generated.

[0033] Step 900: Trigger a partial rollback, send the logic cone related to the first error register to the GPU for simulation tasks in the first error time window and subsequent time windows, and start the corresponding thread block of the GPU to re-perform the simulation calculation.

[0034] In the above technical solution, by dividing the circuit into logic cones and mapping them to GPU thread blocks, and dividing the time into multiple cycle windows, dual parallel acceleration in space and time is achieved. When a discrepancy is detected between the predicted value and the actual value of the register, a local rollback is triggered for a specific logic cone and time window to minimize computational waste. Furthermore, the faulty register and its predecessor combinational logic are automatically extracted to construct a local fault gate-level subnet. The gate-level simulation is used to generate correction values ​​to update the prediction state of subsequent windows. This error correction and learning self-optimization capability effectively avoids the recurrence of the same error source, significantly reduces the rollback frequency and range, and thus greatly improves the overall throughput efficiency of parallel simulation while ensuring gate-level timing accuracy.

[0035] In some alternative implementations, prior to launching the L thread blocks of the GPU, the following is also included: Step 310: Perform static timing and structural analysis on the gate-level circuit netlist to identify high-risk registers; Step 320: Extract high-risk registers and all their predecessor combinational logic to form a high-risk, suspicious gate-level subnet; Step 330: Perform gate-level simulation on the high-risk suspicious gate-level subnet to obtain the register state prediction reference value; Step 340: Compare the register state prediction reference value with the corresponding register state prediction value. If an inconsistency is detected, locate the second fault register and the second fault time window. Step 350: Extract the second error register and all its predecessor combinational logic, and add them to the local error gate subnet; Step 360: Perform gate-level simulation on the local error gate-level subnet to generate the second error time window and the second register state prediction correction value for the subsequent time window; Step 370: Update the register state prediction value using the second register state prediction correction value.

[0036] The above technical solution integrates static temporal pre-analysis and dynamic subnet learning mechanisms to construct a dual prediction optimization system of pre-emptive prevention and in-process correction, significantly reducing the rollback overhead during simulation. Building upon the original dynamic error capture and subnet expansion, the addition of pre-simulation static temporal analysis and high-risk subnet pre-correction can eliminate prediction errors caused by known temporal violation paths in advance, significantly reducing the rollback rate of the first simulation window and avoiding waste of initial GPU computing resources. This combination of static prior knowledge and dynamic adaptive capabilities not only compensates for the initial error cost of relying solely on runtime learning but also further refines the prediction model, ensuring higher prediction accuracy throughout the entire simulation cycle, thereby maximizing the effective utilization of GPU parallel computing and overall throughput efficiency.

[0037] Specifically, before the simulation begins, static timing analysis (STA) and structural analysis are used to identify potentially high-risk registers (e.g., registers with the highest risk of setup / hold time violations along the top K paths). These registers and their predecessor combinational logic are extracted, and an initial high-risk suspicious gate-level subnet is constructed and included in the predictor's precise simulation range to reduce the first rollback rate. During the prediction phase for the states of M windows over N cycles, the high-risk subnet is the focus of monitoring. It is necessary to ensure that the final state of the registers in the high-risk subnet is consistent with the RTL simulation results. If they are inconsistent, the prediction results need to be rolled back on the CPU side to avoid triggering a rollback on the GPU. High-risk subnets can be dynamically optimized: suspicious registers and their subnets that have been verified correctly multiple times by comparing with the RTL simulation results can be removed to reduce overhead; for suspicious registers that actually err, they are formally merged into the erroneous subnet, and the prediction results are rolled back. The current window and subsequent windows of the current window also need to be rolled back.

[0038] In some optional implementations, the second error register and all its predecessor combinational logic are extracted and added to the local error gate-level subnet, including: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove subnets from high-risk, suspicious gate-level subnets.

[0039] In some alternative implementations, adding to the local error gate-level subnet includes: The newly extracted local error gate-level subnets are merged with the existing local error gate-level subnets in the netlist. During the merging process, identical logical parts are identified and eliminated.

[0040] In some alternative implementations, the simulation task for each logic gate of the logic cone is assigned to a separate thread bundle of the corresponding thread block; Multiple threads within a thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

[0041] For details, please refer to Figure 3 , Figure 3 This is a schematic diagram of a GPU-side three-level mapping parallel computing model provided in an embodiment of this application.

[0042] In this model, logic cones are mapped to thread blocks: each independent combinational logic cone is assigned to a GPU thread block for simulation. Since there are no dependencies between logic cones, thread blocks can execute in any order, maximizing parallelism. The thread block size is set to the maximum allowed by CUDA (1024 threads) to further maximize parallelism.

[0043] Logic gates are mapped to warps: Within each warp block, the computational task of a single logic gate within a simulation cycle is assigned to a warp. A warp is the basic unit for GPU execution of SIMT (Single Instruction Multithreading).

[0044] Simulation cycles are mapped to threads: To break cycle dependencies, computation tasks for the same logic gate in N different simulation cycles are mapped to N different threads within the same thread bundle. This parallelism of threads within the thread bundle (wap) enables simultaneous computation across N cycles. This "batch cycle processing" mode conforms to the SIMT architecture, ensuring consistent instructions and regular memory access. Threads within the same warp access contiguous memory addresses (such as waveform data from adjacent cycles), achieving memory access merging and improving bandwidth utilization.

[0045] The GPU employs an active event skipping mechanism. At each timestamp (period), Warp checks whether the input of the logic gate it is responsible for has changed (e.g., via gateActiveFlag). Gate computation is only performed if the input has changed; otherwise, it is skipped to reduce redundant computation.

[0046] Intra-thread scheduling works as follows: with operands in place and execution resources available, the GPU's warp scheduler selects instructions from ready warps and issues them to the execution unit. Simulation within a thread block proceeds according to logical hierarchy. All logic gates (corresponding to multiple warps) at the same logical level can be computed in parallel. Synchronization is performed after each level is completed to ensure data dependencies. Threads within a warp execute the same instruction stream, greatly improving scheduling efficiency. The size of a thread block (i.e., the number of warps) is limited by the GPU architecture (e.g., a maximum of 1024 threads, or 32 warps per thread block). If the number of logic gates in a logic cone exceeds 32, then a single thread block's warps may not be sufficient to process all logic gates simultaneously. In such cases, a round-robin approach might be used to allow warps within the same thread block to process multiple logic gates in batches.

[0047] GPU hierarchical synchronous computation: Within a thread block, simulation is performed according to the hierarchical order of combinational logic. All gates (i.e., all corresponding thread bundles) within the same logic level can be computed in parallel. After all computations at that level are completed, synchronization is achieved through barriers within the thread block before proceeding to the next level, ensuring the correctness of signal propagation.

[0048] GPU Register Processing and Timing Checks: After the GPU completes the parallel computation of all combinational logic within a window, waveform data for the registers over N cycles is obtained. Based on this waveform data, register setup and hold times are checked for the previous (N-1) cycles (since hold time checks need to be performed across cycles, the results of N cycles can only detect the timing of N-1 cycles). According to the timing check results, the state values ​​of each register in the next cycle are updated, and the updated register values ​​are compared with the corresponding predicted values ​​received from the CPU. If an error is found during the comparison, the GPU thread sends a rollback event packet to the CPU containing the error window ID, register index, and error value. The comparison result is then sent back to the CPU. The CPU then extracts the register that caused the error and all its preceding combinational logic, forming a local error gate-level subnet. This subnet is merged into the mixed-precision predictor for accurate simulation of subsequent window predictions. Subsequently, only the logic cones affected by the error are re-issued simulation tasks to the GPU, and a partial rollback is performed.

[0049] The aforementioned technical solution employs a fine-grained parallel mapping model of "logic gate-thread bundle, simulation cycle-thread," which deeply aligns with the SIMD architecture characteristics of GPUs. By assigning the computational tasks of the same logic gate in different clock cycles to different threads within the same thread bundle, it ensures that all threads within the thread bundle execute the exact same logic gate evaluation instructions, completely eliminating branch divergence within the thread bundle and maximizing the processing efficiency of single instruction multiple data streams. Simultaneously, this mapping method further explores the potential of temporal parallelism based on logic cone space parallelism, significantly improving the utilization of GPU core resources and the throughput of large-scale gate-level evaluation, thus guaranteeing the efficiency and stability of parallel computing.

[0050] Please refer to Figure 2 , Figure 2 A functional block diagram of a GPU-accelerated gate-level temporal parallel simulation system provided for embodiments of this application includes: a CPU side and a GPU side; The CPU side includes a task scheduling and communication module, a subnet management module, and a mixed-precision simulation predictor. The task scheduling and communication module is used to: divide the gate-level circuit netlist into L logic cones according to the circuit partitioning information; and divide the simulation time into M simulation windows, each simulation window including N consecutive clock cycles. A mixed-precision simulation predictor is used to generate M×N clock cycle predicted register state values ​​through RTL simulation. On the GPU side, it is used to: launch L thread blocks of the GPU, perform simulation calculations according to the test stimulus, each thread block is responsible for the calculation of a logic cone in N clock cycles, and obtain the actual values ​​of the register states corresponding to the L logic cones; compare the actual values ​​of the register states with the corresponding predicted values ​​of the register states, and if an inconsistency is detected, locate the first fault register and the first fault time window; The subnet management module is used to: extract the first error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; A mixed-precision simulation predictor is used to: perform gate-level simulation on a locally faulty gate-level subnet, generate first register state prediction correction values ​​for the first fault time window and subsequent time windows; and update register state prediction values ​​using the first register state prediction correction values. The task scheduling and communication module is also used to: trigger a partial rollback, send the logic cone related to the first error register to the GPU for simulation tasks in the first error time window and subsequent time windows, and start the corresponding thread block of the GPU to re-perform the simulation calculation.

[0051] In some alternative implementations, the subnet management module dynamically maintains and runs locally faulty gate-level subnets and high-risk, suspicious gate-level subnets.

[0052] In some optional implementations, the task scheduling and communication module is also used to: acquire high-risk registers; The subnet management module is also used to: extract high-risk registers and all their predecessor combinational logic to form high-risk suspicious gate-level subnets; The hybrid precision simulation predictor is also used for: performing gate-level simulation on high-risk suspicious gate-level subnets to obtain register state prediction reference values; comparing the register state prediction reference values ​​with the corresponding register state prediction values, and if an inconsistency is detected, locating the second fault register and the second fault time window; The subnet management module is also used to: extract the second error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; The hybrid precision simulation predictor is also used for: performing gate-level simulation on a locally faulty gate-level subnet, generating second error time windows and subsequent second register state prediction correction values; and using the second register state prediction correction values ​​to update the register state prediction values.

[0053] In some alternative implementations, the subnet management module is also used for: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove subnets from high-risk, suspicious gate-level subnets.

[0054] In some alternative implementations, the simulation task for each logic gate of the logic cone is assigned to a separate thread bundle of the corresponding thread block; Multiple threads within a thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

[0055] In some alternative implementations, the hybrid precision simulation predictor includes an RTL simulator and a gate-level simulation engine; An RTL simulator is used for RTL simulation. The gate-level simulation engine is used for gate-level simulation; Both the RTL simulator and the gate-level simulation engine support quaternary logic systems with 0, 1, unknown states, and high-impedance states.

[0056] In some alternative implementations, the data communication between the CPU and the GPU is pipelined to overlap with the computation process on the GPU.

[0057] In summary, the GPU-accelerated gate-level temporal parallel simulation method and system of this embodiment have the following advantages: By dynamically learning and correcting error sources through a hybrid precision predictor, the traditional prediction-error-global rollback mode is transformed into a learning-correction-progressive precision mode, greatly reducing the frequency and scope of rollback operations. The proposed three-level mapping model of logic cone-thread block, logic gate-thread bundle, and cycle-thread fully conforms to the hardware architecture hierarchy of the GPU, achieving the ultimate utilization of computing resources and fully leveraging the massive parallel advantages of the GPU. The system has self-learning capabilities, continuously optimizing prediction accuracy and simulation subnet composition through static pre-analysis and dynamic runtime feedback. The further the simulation process progresses, the more accurate the prediction and the higher the efficiency. It supports four-valued logic (0,1,X,Z) and precise gate-level temporal simulation, ensuring the signature-level credibility of the verification results. Through optimization strategies such as data resident and overlapping computation and communication pipelines, the data transmission bottleneck between the CPU and GPU is effectively alleviated.

[0058] In one specific embodiment, a complex and realistic digital circuit—a 32-bit MCU processor core—is used as the design under test (DUT) to illustrate the specific implementation process of the present invention in detail. The 32-bit MCU contains a complete five-stage pipeline (IF, ID, EX, MEM, WB), register file, ALU, control unit, and bus interface. Its gate-level netlist is of moderate size (typically tens of thousands to hundreds of thousands of gates), and its timing paths are complex, making it an ideal object for verifying the effectiveness of the present invention.

[0059] 1. Example Circuit and Environment Setup Design under test (DUT): Gate-level netlist of a 32-bit MCU processor core (physically implemented, containing standard cells and timing information).

[0060] Simulation objective: Run a small test program (e.g., calculate the first 10 terms of the Fibonacci sequence) to complete a gate-level timing simulation of approximately 5000 clock cycles, verify functional correctness, and capture timing violations.

[0061] Stimulus: Includes clock CLK, reset signal RESETn, instruction memory read data INSTR, data memory read data MEM_RDATA, etc.

[0062] System configuration: CPU: Multi-core x86 server, running the predictive scheduling subsystem. GPU: NVIDIA H100, running the parallel computing subsystem. Simulation window parameters: N = 64 cycles / window, M = 8 windows in parallel. This configuration aims to fully utilize the massive parallelism of the GPU while balancing communication overhead and rollback granularity.

[0063] Accuracy: Supports 0, 1, X, Z four-value logic. Timing information is derived from the SDF file of this design at a specific process node.

[0064] 2. Specific Implementation Steps Step 1: Static pre-analysis and system initialization (CPU side) 1. The circuit netlist partitioning and storage module first partitions the combinational logic section of the 32-bit MCU. Using a hypergraph partitioning tool (such as hMetis), the entire netlist is divided into approximately 1000 independent logic cones. The partitioning goal is to minimize inter-cone dependencies while ensuring that the size (number of gates) of each cone is roughly balanced to facilitate load balancing among GPU thread blocks. The partitioning results (netlist structure and connection relationships of the cones) are encoded into a GPU-friendly data structure.

[0065] 2. The subnet management module performs static pre-analysis: Run a Static Time Series Analysis (STA) tool to analyze the gate-level netlist. Identify the paths with the highest risk of setup and hold violations. For example, the analysis report might indicate: The long combinational logic path from the EX-level pipeline register to the MEM-level pipeline register (involving multiplexing and bypass logic of ALU operation results) is extremely risky.

[0066] Based on the STA report and netlist structure analysis, the top 50 registers with the highest risk were selected (such as state machine registers like pcpi_mul_wait, mem_state, and cpu_state, as well as critical data path registers like mem_rdata).

[0067] Extract the complete logic cones from each of these 50 registers, merge and deduplicate them to form an initial high-risk, suspicious gate-level subnet covering the core control logic and critical parts of the data path of the 32-bit MCU. This subnet may contain approximately 15% of the total number of gates.

[0068] The local error subnet is initially empty.

[0069] 3. The entire gate-level netlist structure data, partitioning information, and SDF latency information are transmitted to the GPU memory in one go and remain resident there through the top-level task scheduling and communication module. Subsequent simulations only transmit state and stimulus data.

[0070] 4. The parallel simulation kernel and register processing and comparison kernel on the GPU side are compiled and loaded.

[0071] Step 2: Prediction and execution of the first batch processing window (Window 0-7); 2.1 CPU Side: Mixed Precision Prediction and Task Distribution 1. The task scheduling and communication module is planned to use the first 8 parallel windows (Window 0-7), with each window simulating 64 cycles, for a total of 512 cycles. Adjacent windows overlap by 1 cycle.

[0072] 2. RTL Simulation Engine Startup. Utilizing the 32-bit MCU's RTL reference model, a fast, zero-latency functional simulation is performed, generating a preliminary register value prediction sequence for 512 cycles across Windows 0-7. This includes predicted values ​​for all pipeline registers, general-purpose register files, control status registers, etc.

[0073] 3. The local precise timing simulation engine starts synchronously, performing precise gate-level timing simulation on the initial high-risk suspicious gate-level subnet, covering 512 cycles of Window 0-7.

[0074] Input drive: For signals at subnet boundaries: CLK, RESETn: Use waveforms with clock tree and reset tree delays consistent with GPU emulation.

[0075] RTL register outputs from outside the subnet (such as the Q input of some non-high-risk registers): Use the 0-delay value output by the RTL simulation engine, but waveform reconstruction is required, i.e., add the clock-to-Q delay (Tclk-q) of the register before using it as a combinational logic input.

[0076] Raw input (e.g., INSTR, MEM_RDATA): Use test vectors.

[0077] 4. Prediction Correction and Comparison: The register results (such as the precise value of mem_state) output by the accurate simulation subnet are extracted and compared in real time with the corresponding predicted values ​​generated by the RTL simulation.

[0078] Suppose that in window 2 cycle T (corresponding to a global cycle of approximately 128+T), it is found that the mem_state register's precise sampled value (e.g., MEM_STATE_READ) differs from the RTL predicted value (e.g., MEM_STATE_IDLE) due to combinational logic delays from accessing external memory. This indicates a timing issue that the RTL model has not captured.

[0079] At this point, the error is caught during the CPU-side prediction phase. The system determines that the error-predicted state of Windows 2 and later windows (Windows 2-7) is invalid.

[0080] 5. Dynamic Learning (First Time): The subnet management module immediately starts from the faulty mem_state register and reverses to extract its complete logical cone, forming a local error gate-level subnet.

[0081] The subnet management module synchronously removes subnets associated with the mem_state register from high-risk, suspicious subnets. This reduces the proportion of these subnets in the total number of gates to below 12%.

[0082] Update the module scope of the local precise timing simulation engine (Error Subnet + Suspicious Subnet) and the boundary drive for hybrid RTL simulation.

[0083] 6. Task Adjustment: Since the error was detected and corrected by the predictor before GPU computation, there is no need to trigger a GPU rollback. The system will regenerate the initial state for Windows 2-7 based on the corrected and more accurate register state (using the subnet's accurate simulation results to overwrite the RTL prediction values), and prepare to distribute the simulation tasks of these six windows (Windows 2-7) to the GPU along with the unaffected tasks of Windows 0-1. This demonstrates the predictor's advantage of "preventing problems before they arise."

[0084] 2.2 GPU-based: Large-scale parallel simulation 1. The GPU receives the initial register states and input stimuli from 8 windows (Window 0-7).

[0085] 2. The parallel simulation kernel starts approximately 1000 thread blocks (corresponding to the number of logic cones), with each block responsible for the computation of one logic cone over 64 cycles.

[0086] Three-level mapping: Thread block Block_i is responsible for logic cone Cone_i. The computation of each logic gate (such as an AND gate) within a cone in one cycle is assigned to a Warp (32 threads). Within this Warp, Thread 0 computes the output of the gate in cycle 0, Thread 1 computes the output in cycle 1, ..., Thread 63 computes the output in cycle 63 (here, a Warp has 32 threads; computed over 64 cycles, requiring 2 rounds or a special mapping. In practice, N can be adjusted to 32 or a more flexible thread organization can be used).

[0087] Hierarchical synchronization and event skipping: Each thread block proceeds strictly according to its logical hierarchy, with synchronization between levels. In each cycle, Warp checks for input changes, skipping calculations of many unchanged signals, greatly improving efficiency.

[0088] 3. Register processing and timing check: After all logic cones have been calculated, the register processing and comparison kernel is activated to perform setup / hold time checks on all sequential logic.

[0089] Suppose that during a certain cycle of Windows 5, a hold time violation occurs on a certain write port of the general-purpose register file reg_file, causing the written data to be unstable, and the actual sampled value Actual_Val does not match the expected value Predicted_Val (from CPU prediction).

[0090] 4. Comparison and feedback: The GPU packages this error information (window ID=5, register=reg_file[3], error period, actual value) and sends it back to the CPU.

[0091] Step 3: Error Handling and Incremental Learning (CPU Side) 1. The subnet management module received an error report from the GPU regarding a hold-up time violation on the reg_file write port.

[0092] 2. Start the extraction of the local error subnet. This time, starting from the write data input port of the error register reg_file[3], we traverse in reverse the path of all the preceding logic that may affect the stability of the port after the clock edge. This includes: the multiplexer from which the write data comes (which may come from ALU results, memory data, etc.), the logic for generating the write enable signal, and the path from the clock network to the clock end of the register (which may involve clock skew). The extracted subnet may partially overlap with the existing Error Subnet, or it may contain entirely new logic.

[0093] 3. Merge the newly extracted subnet with the existing Error Subnet and remove duplicates. The Error Subnet will be further expanded, and the coverage may be increased to 5% of the total number of gates.

[0094] 4. Triggering partial rollback: Due to an error in Windows 5, predictions for Windows 6-7 that depend on its results are invalidated.

[0095] 5. Incremental Task Redispatch: The CPU utilizes the updated Error Subnet to accurately simulate the correct state of reg_file after the error in Windows 5, and corrects subsequent states accordingly. Subsequently, only the logic cones affected by this error (potentially involving address decoding, data selection, and other logic around the register file, approximately several dozen cones) are redistributed to the GPU for simulation tasks in Windows 5 (starting from the error point), Windows 6, and Windows 7. The computation results of the vast majority of other logic cones (over 900) are reused.

[0096] Step 4: Continuous Simulation and Dynamic System Optimization Prediction accuracy continues to improve: As simulation progresses, the Error Subnet acts like an "experience bank," continuously accumulating discovered temporal critical paths. When generating predictions for subsequent Windows 8, 9, 10, etc., the locally accurate temporal simulation engine performs synchronous and accurate simulations on this ever-expanding subnet, making the initial state predictions provided to the GPU increasingly closer to the final accurate values. This significantly reduces the probability and frequency of GPU-side alignment errors. The Error Subnet is always adding value as the simulation progresses.

[0097] Dynamic subnetting refinement: Redundancy Removal: The subnet management module monitors the performance of each component in the Suspicious Subnet. If the predictions of certain logical paths consistently match the final GPU results over a large number of consecutive windows (e.g., 100 windows), the system can determine that the RTL model for that path is reliable under the given test stimulus. To reduce the overhead of accurate CPU simulation, this part of the logic can be marked and may be dynamically removed from the Suspicious Subnet. The Suspicious Subnet is constantly being reduced as the simulation progresses.

[0098] GPUs maintain high-efficiency computing: Due to the significantly reduced rollback frequency and range, GPUs spend most of their time performing large-scale, regularized cyclic parallel computations, keeping computational core utilization at a high level. Communication between CPU and GPU also remains efficient due to incremental task delivery and persistent data storage.

[0099] This embodiment uses an MCU (Microcontroller Unit) as a real processor core to demonstrate the powerful performance of this invention in complex scenarios: it successfully handles circuits with complex timing structures including pipelines, state machines, and register files, and its netlist partitioning, pre-analysis, and dynamic learning mechanisms are all effectively addressed. The mixed-precision predictor not only intercepts some errors (such as mem_state) before GPU computation, but also incorporates known timing critical paths into accurate simulation through continuous learning, fundamentally reducing the rollback trigger rate on the GPU side. When an error occurs on the GPU side, the system can accurately locate a few affected logic cones, recalculate and distribute only these parts, achieving a "surgical" partial rollback and preserving effective computation to the maximum extent. The system has "learning-memory-optimization" capabilities, and the simulation process is adaptive, with efficiency typically increasing as the simulation progresses. The three-level mapping model of cone-block-gate-bundle-cycle-thread, combined with hierarchical synchronization and event filtering, enables the massive number of threads on the GPU to efficiently and coordinately simulate the behavior of complex digital circuits over dozens of cycles.

[0100] The method and system of this embodiment enable the simulation to continuously self-optimize during operation, resulting in increasingly higher prediction accuracy and smaller rollback overhead. Thus, while ensuring the accuracy of gate-level timing simulation, it achieves high performance close to that of RTL simulation. It can effectively solve the core contradiction (accuracy requirements versus parallel efficiency) faced when applying GPUs to large-scale, high-precision gate-level timing simulation, and provide a practical and feasible high-performance solution for chip verification.

[0101] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0102] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0104] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0105] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A GPU-accelerated gate-level temporal parallel simulation method, characterized in that, include: Based on the circuit partitioning information, the gate-level circuit netlist is divided into L logic cones; The simulation time is divided into M simulation windows, and each simulation window includes N consecutive clock cycles; Through RTL simulation, register state prediction values ​​for M×N clock cycles are generated; Launch L thread blocks of the GPU to perform simulation calculations based on the test stimulus. Each thread block is responsible for the calculation of a logic cone within N clock cycles, and obtains the actual values ​​of the register states corresponding to the L logic cones. The actual register status value is compared with the corresponding predicted register status value. If an inconsistency is detected, the first faulty register and the first faulty time window are located. Extract the first error register and all its predecessor combinational logic, and add them to the local error gate subnet; Perform gate-level simulation on the partially faulty gate-level subnet to generate the first fault time window and the first register state prediction correction value for subsequent time windows; The register state prediction value is updated using the first register state prediction correction value; A partial rollback is triggered, and the logic cone related to the first error register is sent to the GPU for simulation tasks in the first error time window and subsequent time windows. The corresponding thread block of the GPU is then started to re-perform the simulation calculation.

2. The method as described in claim 1, characterized in that, Before launching the L thread blocks of the GPU, the following is also included: Static timing and structural analysis are performed on the gate-level circuit netlist to identify high-risk registers; Extract high-risk registers and all their predecessor combinational logic to form a high-risk, suspicious gate-level subnet; Gate-level simulation was performed on high-risk, suspicious gate-level subnets to obtain reference values ​​for register state prediction. The register state prediction reference value is compared with the corresponding register state prediction value. If an inconsistency is detected, the second fault register and the second fault time window are located. Extract the second error register and all its predecessor combinational logic, and add them to the local error gate subnet; Perform gate-level simulation on the partially faulty gate-level subnet to generate the second fault time window and the second register state prediction correction value for the subsequent time window; The register state prediction value is updated using the second register state prediction correction value.

3. The method as described in claim 2, characterized in that, Extract the second error register and all its predecessor combinational logic, and add them to the local error gate-level subnet, including: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove the subnet from the high-risk, suspicious gate-level subnet.

4. The method as described in claim 1, characterized in that, The addition to the local error gate-level subnet includes: The newly extracted local error gate-level subnets are merged with the existing local error gate-level subnets in the netlist. During the merging process, identical logical parts are identified and eliminated.

5. The method as described in claim 4, characterized in that, The simulation task for each logic gate in the logic cone is assigned to an independent thread bundle of the corresponding thread block; The multiple threads within the thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

6. A GPU-accelerated gate-level temporal parallel simulation system, characterized in that, include: CPU and GPU sides; The CPU side includes a task scheduling and communication module, a subnet management module, and a mixed-precision simulation predictor. The task scheduling and communication module is used to: divide the gate-level circuit netlist into L logic cones according to the circuit partitioning information; and divide the simulation time into M simulation windows, each simulation window including N consecutive clock cycles. The mixed-precision simulation predictor is used to: generate register state prediction values ​​for M×N clock cycles through RTL simulation; The GPU is used to: launch L thread blocks of the GPU, perform simulation calculations according to the test stimulus, each thread block is responsible for the calculation of a logic cone in N clock cycles, and obtain the actual values ​​of the register states corresponding to the L logic cones; compare the actual values ​​of the register states with the corresponding predicted values ​​of the register states, and if an inconsistency is detected, locate the first fault register and the first fault time window. The subnet management module is used to: extract the first error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; The hybrid precision simulation predictor is used to: perform gate-level simulation on a locally faulty gate-level subnet, generate a first error time window and a first register state prediction correction value for subsequent time windows; and use the first register state prediction correction value to update the register state prediction value. The task scheduling and communication module is also used to: trigger a partial rollback, send the simulation task of the logic cone related to the first error register to the GPU in the first error time window and subsequent time windows, and start the corresponding thread block of the GPU to re-perform the simulation calculation.

7. The system as described in claim 6, characterized in that, The subnet management module dynamically maintains and runs partially faulty gate-level subnets and high-risk, suspicious gate-level subnets.

8. The system as described in claim 7, characterized in that, The task scheduling and communication module is also used to: acquire high-risk registers; The subnet management module is also used to: extract high-risk registers and all their predecessor combinational logic to form high-risk suspicious gate-level subnets; The hybrid precision simulation predictor is also used to: perform gate-level simulation on high-risk suspicious gate-level subnets to obtain register state prediction reference values; compare the register state prediction reference values ​​with the corresponding register state prediction values, and if an inconsistency is detected, locate the second fault register and the second fault time window. The subnet management module is also used to: extract the second error register and all its predecessor combinational logic, and add them to the local error gate-level subnet; The hybrid precision simulation predictor is also used to: perform gate-level simulation on the locally faulty gate-level subnet, generate a second fault time window and a second register state prediction correction value for subsequent time windows; and use the second register state prediction correction value to update the register state prediction value.

9. The system as described in claim 8, characterized in that, The subnet management module is also used for: Starting from the second error register, extract its complete logic cone in reverse to form a subnet; Remove the subnet from the high-risk, suspicious gate-level subnet.

10. The system as described in claim 6, characterized in that, The simulation task for each logic gate in the logic cone is assigned to an independent thread bundle of the corresponding thread block; The multiple threads within the thread bundle calculate the output values ​​of the corresponding logic gates in different simulation cycles.

11. The system as described in claim 7, characterized in that, The hybrid precision simulation predictor includes an RTL simulator and a gate-level simulation engine; The RTL simulator is used to perform RTL simulation; The gate-level simulation engine is used to perform gate-level simulation; Both the RTL simulator and the gate-level simulation engine support quaternary logic systems with 0, 1, unknown states, and high-impedance states.

12. The system as described in claim 7, characterized in that, The data communication between the CPU and GPU overlaps with the computation process on the GPU in a pipelined manner.

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