Circuit parameter optimization method and related device

Abstract

The embodiment of the application provides a circuit parameter optimization method and related equipment, and belongs to the technical field of circuit design. The method first initializes circuit parameters, and respectively performs circuit simulation under all PVT angles of a PVT angle set according to the circuit parameters to obtain circuit performance under the corresponding PVT angles, then repeatedly performs circuit parameter optimization and simulation operations according to the PVT angle set until a preset iteration condition is reached to obtain optimal circuit parameters. In each optimization and simulation process, an angle sampling strategy of selecting the worst N PVT angles from the PVT angle set and randomly selecting M PVT angles can not only evaluate the circuit design under the worst angles to quickly approach the robustness boundary of the design, but also introduce random angles to increase the diversity of exploration and avoid falling into a local optimal solution, thereby further improving the adaptability of the circuit parameter optimization result under different PVT conditions.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and in particular to a method and related equipment for optimizing circuit parameters. Background Technology

[0002] In traditional analog circuit design, especially when facing complex circuit parameter optimization, reliance on expert knowledge and manual adjustments remains the primary optimization method. However, as the scale and complexity of circuit designs increase, traditional manual adjustment methods are increasingly unable to meet the demands for efficient and accurate design, particularly when dealing with various process, temperature, and voltage (PVT) variations. Traditional optimization processes often fail to achieve the required performance metrics. Traditional circuit design methods, such as heuristic optimization algorithms (e.g., evolutionary algorithms) and Bayesian optimization, while performing well in certain scenarios, exhibit poor adaptability to different PVT conditions, easily leading to performance instability. Currently, in circuit optimization design, to improve the adaptability of the optimization scheme under different PVT conditions, all possible PVT conditions are considered during the optimization process. This results in a high computational resource requirement and low efficiency in the circuit optimization process, making it difficult to quickly find the optimal circuit parameters. Summary of the Invention

[0003] The main objective of this application is to propose a circuit parameter optimization method and related equipment, which aims to improve the adaptability of circuit parameter optimization results under different PVT conditions and improve the efficiency of circuit parameter optimization.

[0004] To achieve the above objectives, one aspect of this application proposes a circuit parameter optimization method, comprising the following steps: Initialize the circuit parameters, and perform circuit simulations at all PVT angles in the PVT angle set according to the circuit parameters to obtain the circuit performance at the corresponding PVT angles; The circuit parameter optimization and simulation operations are repeatedly performed based on the PVT angle set until the preset iteration conditions are met to obtain the optimal circuit parameters; the circuit parameter optimization and simulation operations include the following steps: Select the N worst-performing PVT angles from the PVT angle set and randomly select M PVT angles to update the PVT angle subset; The simulation data from the previous circuit simulation and the PVT angle subset are input into the optimization decision model to optimize the circuit parameters, resulting in optimized circuit parameters. The simulation data includes circuit parameters, PVT angles, and corresponding circuit performance. The optimized circuit parameters are simulated under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round. The circuit performance of the corresponding PVT angle in the PVT angle set is updated based on the circuit performance obtained in the current round.

[0005] In some embodiments, the optimization decision model employs a network architecture based on a conditional variational autoencoder.

[0006] In some embodiments, the optimization decision model makes circuit parameter optimization decisions through the following steps: The circuit parameters are used as input parameters, and the PVT angles and circuit performance of the previous round, along with the subset of PVT angles, are used as additional conditions to input into the encoder for feature extraction, thereby obtaining the latent space representation features. The latent space representation features are reparameterized and sampled to obtain the probability distribution statistics in the latent space representation features, and then the probability distribution statistics are converted into a differentiable initial latent feature vector. The initial latent feature vector is denoised and reconstructed using a reconstructor to obtain the reconstructed latent feature vector; The reconstructed latent feature vector is decoded by a decoder to obtain the optimized circuit parameters.

[0007] In some embodiments, the reconstructor is a diffusion probability model, and the step of denoising and reconstructing the initial latent feature vector using the reconstructor to obtain the reconstructed latent feature vector includes the following steps: Based on the prior knowledge of the data distribution learned and the constraint guidance of the PVT corner subset, noise identification is performed on the initial latent feature vector to determine the noise component in the initial latent feature vector; Based on the noise components, the initial latent feature vector is subjected to inverse denoising inference to obtain the reconstructed latent feature vector.

[0008] In some embodiments, the circuit parameter optimization and simulation operation further includes the following steps: The optimization decision model is updated based on the circuit performance and expected performance obtained in the current round.

[0009] In some embodiments, updating the optimization decision model based on the circuit performance and expected performance obtained in the current round includes the following steps: The reward value is determined based on the circuit performance and expected performance obtained in the current round; The value network in the reinforcement learning framework is updated based on the reward value; The circuit parameters output by the optimization decision model, which serves as the policy network, are evaluated based on the updated value network, and then the policy network is updated based on the evaluation results.

[0010] To achieve the above objectives, another aspect of this application proposes a circuit parameter optimization system, comprising: The first module is used to initialize circuit parameters and perform circuit simulations at all PVT angles in the PVT angle set according to the circuit parameters, so as to obtain the circuit performance at the corresponding PVT angle. The second module is used to repeatedly perform circuit parameter optimization and simulation operations based on the PVT angle set until the preset iteration conditions are met to obtain the optimal circuit parameters. The circuit parameter optimization and simulation operation includes the following steps: Select the N worst-performing PVT angles from the PVT angle set and randomly select M PVT angles to update the PVT angle subset; The simulation data from the previous circuit simulation and the PVT angle subset are input into the optimization decision model to optimize the circuit parameters, resulting in optimized circuit parameters. The simulation data includes circuit parameters, PVT angles, and corresponding circuit performance. The optimized circuit parameters are simulated under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round. The circuit performance of the corresponding PVT angle in the PVT angle set is updated based on the circuit performance obtained in the current round.

[0011] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0012] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0013] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0014] The embodiments of this application include at least the following beneficial effects: This application provides a circuit parameter optimization method, system, electronic device, program product, and storage medium. The scheme first initializes the circuit parameters, and then performs circuit simulation under all PVT angles of the PVT angle set according to the circuit parameters to obtain the circuit performance under the corresponding PVT angle. Then, the circuit parameter optimization and simulation operations are repeated according to the PVT angle set until the preset iteration conditions are reached to obtain the optimal circuit parameters. In each optimization and simulation process, by selecting the N worst-performing PVT angles from the PVT angle set and randomly selecting M PVT angles, the angle sampling strategy can not only evaluate the circuit design under the worst angle, thereby quickly approaching the robustness boundary of the design, but also increase the diversity of exploration by introducing random angles, avoid getting trapped in local optima, and further improve the adaptability of the circuit parameter optimization results under different PVT conditions. Attached Figure Description

[0015] Figure 1 This is a flowchart of the circuit parameter optimization method provided in the embodiments of this application; Figure 2 This is a flowchart of a single-round circuit parameter optimization and simulation operation provided in an embodiment of this application; Figure 3 This is a schematic diagram of the network structure of the optimization decision model provided in the embodiments of this application; Figure 4 This is a schematic diagram of the circuit parameter optimization process under the reinforcement learning framework provided in the embodiments of this application; Figure 5 This is a schematic diagram of the overall circuit parameter optimization process provided in the embodiments of this application; Figure 6 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0018] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0019] PVT conditions (also known as PVT angles) refer to the combination of three key variables that need to be considered in the field of integrated circuit design and simulation to ensure that the chip can operate reliably in various real-world manufacturing and operating environments: process, voltage, and temperature. Generally, a complete PVT simulation needs to cover all possible combinations of process angles, voltage, and temperature. For example, if 5 process angles, 3 voltages (nominal value ±10%), and 3 temperatures (such as -40°C, 25°C, and 125°C) are considered, up to 45 simulation conditions will be generated.

[0020] In traditional analog circuit design, especially when facing complex circuit parameter optimization, reliance on expert knowledge and manual adjustments remains the primary optimization method. However, as the scale and complexity of circuit designs increase, traditional manual adjustment methods are increasingly unable to meet the demands for efficient and accurate design, particularly when dealing with various process, temperature, and voltage (PVT) variations. Traditional optimization processes often fail to achieve the required performance metrics. Traditional circuit design methods, such as heuristic optimization algorithms (e.g., evolutionary algorithms) and Bayesian optimization, while performing well in certain scenarios, still have many limitations. First, these methods typically require extensive simulation calculations, leading to inefficiency. Second, they exhibit poor adaptability to different PVT conditions, making them prone to performance instability.

[0021] In recent years, deep reinforcement learning (DRL), as an innovative optimization method, has made significant progress in circuit design. Especially in analog circuit design optimization, reinforcement learning automatically adjusts design parameters by continuously interacting with the environment and optimizing strategies, avoiding the limitations of traditional optimization methods. However, existing reinforcement learning methods typically rely on single simulation conditions and still face problems such as low sample efficiency and slow convergence speed when dealing with complex circuits or multi-dimensional constraints. While current reinforcement learning methods have made some progress in circuit design optimization, they still have limitations in PVT robustness. Most current solutions rely on traditional simulation and, considering the weak adaptability to PVT variations, improve the reliability of optimization results by performing numerous PVT condition simulations, but this leads to high computational resource requirements and low optimization efficiency.

[0022] Analysis of relevant technologies reveals that current circuit parameter optimization design methods suffer from at least one of the following problems: Low sample efficiency: Current PVT robust optimization methods usually require a large number of circuit simulations to collect sample data. Especially when dealing with complex circuits, multiple rounds of simulation calculations are often required to find a suitable optimization solution.

[0023] High computational complexity: Current methods typically rely on multiple simulations and complex calculations during the optimization process, especially under multi-dimensional constraints. This results in high computational overhead and long runtime. When dealing with multi-sub-block circuits or complex designs, the computational burden is heavy, making it difficult to meet the needs of rapid optimization.

[0024] Poor adaptability to PVT variations: Many current optimization frameworks have not been able to effectively incorporate circuit performance variations under different PVT conditions, resulting in the optimization process often only considering a few simulation angles, thus failing to fully guarantee the PVT robustness of the optimized solution.

[0025] Ineffective handling of complex circuits and high-dimensional parameter spaces: Most current circuit optimization methods have significant limitations when dealing with complex circuits and high-dimensional parameter spaces, especially in terms of the excessively large dimensionality of the search space and the lack of efficient exploration and generalization capabilities. As the number of parameters involved in circuit design increases, the dimensionality of the optimization problem expands rapidly, and traditional optimization methods often struggle to find the global optimum effectively in such a vast search space. These methods typically rely on local searches, easily getting trapped in local optima, thus limiting optimization performance. Furthermore, traditional methods lack sufficient exploration capabilities, especially when facing new design space regions, often making it difficult to perform effective optimization from a global perspective.

[0026] In view of this, this application provides a circuit parameter optimization method and related equipment, which can improve the adaptability of circuit parameter optimization results under different PVT conditions and improve the efficiency of circuit parameter optimization.

[0027] The circuit parameter optimization method provided in this application relates to the field of circuit design technology. This method can be applied to terminals, servers, or software running on either a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing the circuit parameter optimization method, but is not limited to the above forms.

[0028] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0029] Figure 1 This is an optional flowchart of the circuit parameter optimization method provided in the embodiments of this application. Figure 1 The method may include, but is not limited to, steps S101 to S102.

[0030] S101, initialize the circuit parameters, and perform circuit simulation under all PVT angles of the PVT angle set according to the circuit parameters to obtain the circuit performance under the corresponding PVT angle; S102, repeatedly perform circuit parameter optimization and simulation operations based on the PVT angle set until the preset iteration conditions are met to obtain the optimal circuit parameters.

[0031] In step S101 of some embodiments, circuit parameters refer to the relevant parameters of the designed analog circuit, which may include, but are not limited to, transistor parameters, capacitor values, and resistor values. The PVT angle set refers to a complete set of PVT conditions sampled from all possible process deviations and all possible operating voltages and ambient temperatures of the analog circuit. Each PVT angle in the PVT angle set, together with the initialized circuit parameters, forms an analog circuit simulation system, and the corresponding circuit performance is obtained through system simulation. Circuit performance may include, but is not limited to, power consumption, delay, and waveform quality. In this embodiment, the PVT angle set stores all PVT angles and a comprehensive score value corresponding to each PVT angle for evaluating circuit performance.

[0032] In step S102 of some embodiments, circuit parameter optimization and simulation operations are repeatedly performed based on the PVT angle set until a preset iteration condition is met, resulting in the optimal circuit parameters. The preset iteration condition can refer to reaching a certain number of iterations, the circuit performance reaching the desired performance, or the circuit performance reaching the optimal performance, etc., at which point the corresponding circuit parameters are the optimal circuit parameters. This embodiment, by repeatedly performing circuit parameter optimization and simulation operations based on the PVT angle set, updates the comprehensive score value of the corresponding PVT angle in the PVT angle set after calculating the comprehensive score value of the circuit performance using the PVT angle-circuit performance data obtained from each simulation. This solution can also store the "circuit parameter-PVT angle-circuit performance" data obtained from each simulation into an experience replay pool. In subsequent optimization iterations, the optimizer can repeatedly extract data from the pool for model learning, enabling exploration across all PVT angles throughout the entire optimization process, thus maintaining robustness under a wide range of PVT conditions.

[0033] According to some embodiments of this application, please refer to Figure 2 Each iteration in step S103, i.e., each round of circuit parameter optimization and simulation operations, may include, but is not limited to, the following steps: S201, Select the N worst-performing PVT corners from the PVT corner set and randomly select M PVT corners to update the PVT corner subset; S202, input the simulation data and PVT angle subset from the previous circuit simulation into the optimization decision model to make circuit parameter optimization decisions, and obtain the optimized circuit parameters; the simulation data includes circuit parameters, PVT angles and corresponding circuit performance. S203, perform circuit simulation on the optimized circuit parameters under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round; S204, update the circuit performance of the corresponding PVT angle in the PVT angle set based on the circuit performance obtained in the current round.

[0034] In step S201 of some embodiments, this application defines a PVT corner subset to store several PVT corners obtained by corner sampling of the PVT corner set each time. Specifically, the corner sampling strategy of this embodiment involves selecting the N worst-performing PVT corners from the PVT corner set and randomly selecting M PVT corners to update and store in the PVT corner subset. For example, four PVT corners from the previous simulation (i.e., the PVT corners with the lowest circuit performance) and four randomly selected PVT corners can be selected from the PVT corner set as subsequent optimization conditions and simulations. In another example, four worst-performing PVT corners from the previous simulation and four randomly selected PVT corners can also be selected from the PVT corner set as subsequent optimization conditions and simulations. This strategy ensures that the optimization iteration process not only evaluates the circuit design at the worst-case angle, but also increases the diversity of exploration by introducing random angles. This avoids the limitations of traditional methods that rely on only a few angles for optimization, thereby improving the robustness and efficiency of the optimization, significantly accelerating the convergence speed of the optimization process, and achieving efficient and accurate circuit optimization results.

[0035] In step S202 of some embodiments, the simulation data and PVT angle subset from the previous circuit simulation are input into the optimization decision model to make circuit parameter optimization decisions, resulting in optimized circuit parameters. The simulation data from the previous circuit simulation includes circuit parameters, PVT angles, and corresponding circuit performance. The optimization decision model can employ a neural network model. For example, the optimization decision model can employ a network architecture based on conditional autoregressive flow learning, or it can employ a network architecture based on conditional variational autoencoder.

[0036] A Conditional Variational Autoencoder (CVAE) is a generative model that learns the conditional probability distribution of data. Building upon a standard variational autoencoder, it receives additional conditional information (such as the PVT environment and performance metrics in circuit design) as input. Its core mechanism is as follows: the encoder compresses observed data (such as circuit parameters) into a latent space vector that follows a specific distribution; the decoder then reconstructs or generates new data from this latent space based on the given conditional information. In this embodiment, the role of the CVAE is to learn the distribution that qualified circuit parameters should follow under specific simulation conditions, thereby providing a structured and physically constrained search starting point for subsequent optimization. The network architecture of the Conditional Variational Autoencoder can be represented as follows: x+c—encoder—μ+σ; z+c—decoder—x; Where x is the input and also the output to be generated, c is the condition, μ and σ are the mean and variance of the Gaussian distribution used to construct the latent space, z is the sampling point of the latent space, and encoder and decoder are the two networks to be trained.

[0037] In analog circuit design, the number of circuit parameters is often enormous, resulting in a huge computational burden for the optimization process and a high risk of getting trapped in local optima. Furthermore, traditional RL methods typically rely on global search, but when dealing with high-dimensional, complex circuits, the search space becomes too large, leading to a very slow and inefficient training process. Therefore, the optimization decision model in this embodiment can employ a network architecture based on a conditional variational autoencoder. This architecture effectively explores circuit parameters through dimensionality reduction, mapping high-dimensional circuit parameters to a low-dimensional latent space, thereby simplifying the optimization process and further improving optimization efficiency.

[0038] According to some embodiments of this application, the optimization decision model can perform circuit parameter optimization decisions through, but is not limited to, the following steps: S301, the circuit parameters are used as input parameters, and the PVT angles and circuit performance and PVT angle subsets from the previous round are used as additional conditions to input into the encoder for feature extraction, so as to obtain the latent space representation features. S302, reparameterize the latent space representation features to obtain the probability distribution statistics in the latent space representation features, and then convert the probability distribution statistics into a differentiable initial latent feature vector. S303, the initial latent feature vector is denoised and reconstructed by the reconstructor to obtain the reconstructed latent feature vector; S304 decodes the reconstructed latent feature vectors using a decoder to obtain the optimized circuit parameters.

[0039] While CVAE can improve optimization efficiency in some embodiments, it also faces certain limitations. One such limitation is that the latent space distribution, due to insufficient precision, may not fully match the actual circuit design requirements, thus affecting the accuracy of the optimization results. Therefore, this application introduces a generative network model as a reconstructor on top of the CVAE architecture to reconstruct its latent space by learning the data distribution, making the latent space more closely resemble the actual circuit performance distribution. This combination effectively solves the distribution matching problem of CVAE in high-dimensional data spaces, thereby improving the quality and accuracy of the optimization results. The generative network model can be a Generative Adversarial Network (GAN) or a diffusion model, etc.

[0040] In this embodiment, the optimization decision model can adopt an optimization framework combining CVAE and diffusion models. It utilizes a generative model to reconstruct the latent space distribution, avoiding the reliance on a large number of simulation samples in traditional methods. This significantly improves sample efficiency during the optimization process, reduces the number of simulations, computational complexity, and runtime, thereby accelerating the optimization speed. The diffusion model is a generative model that learns complex data distributions through a stepwise "denoising" process. Its training consists of two processes: the forward process gradually adds noise to the data until it becomes pure random noise; the reverse process trains a neural network to learn how to gradually reconstruct the original data from the noise. This model has extremely strong distribution fitting and detail generation capabilities.

[0041] Specifically, the optimization decision model in this embodiment can adopt the following approach: Figure 3 The integrated network structure of the conditional variational autoencoder (CVAE) and diffusion model is shown below. The components of this network structure are explained as follows: Analog circuit parameters include circuit parameters (such as transistor parameters, capacitance values, resistance values, etc.) that serve as inputs to the variational autoencoder. The inputs to the variational autoencoder also include the performance values ​​obtained from the previous simulation, the one-hot encoding of the PVT angle from the previous simulation, and the one-hot encoding of the PVT angle from this simulation.

[0042] Encoder network: The encoder network in CVAE, also called an encoder, maps the input circuit parameters to a latent space using one-hot encoding of PVT conditions. The encoder learns the distribution characteristics of the input parameters and generates corresponding latent space representations, thereby learning the inherent rules of circuit design. The encoder network mainly uses a deep neural network structure to extract features from the high-dimensional input circuit parameters and generate low-dimensional latent space representations, enabling complex circuit design problems to be processed and optimized in the latent space.

[0043] CVAE Initial Latent Space: CVAE generates a latent representation of the circuit design using an initial latent space learned from the prior art, representing the latent data characteristics of the circuit design. The efficient construction of the latent space is crucial for the entire optimization process; the optimization implementation is based on this space, allowing the search for the most suitable circuit design parameters within the latent space.

[0044] The diffusion model reconstructs the latent space: Here, the diffusion model is used to further optimize the latent space of the CVAE by reconstructing it to better reflect the actual circuit performance distribution. The initial latent space suffers from insufficient accuracy, leading to generated parameters that fail to meet design requirements. The diffusion model, by simulating a "diffusion" process from a high-dimensional distribution to a low-dimensional latent space, generates a new, more realistic latent space representation, making the latent space closer to the actual distribution and improving data stability during optimization. In this embodiment, the diffusion model can employ a Denoising Diffusion Probability Model (DDPM) based on a Multilayer Perceptron (MLP) architecture, or a U-Net architecture built on a one-dimensional convolutional neural network (1D-CNN), or a Transformer architecture based on self-attention (such as DiffusionTransformer).

[0045] The decoder network in CVAE, also known as a decoder, maps the optimized latent space back to the circuit parameter space, thus outputting optimized circuit parameters. These output circuit parameters are then directly used in simulations for performance verification and further optimized through reinforcement learning. This stage represents the output of the entire single-step optimization process; the optimized circuit parameters will be simulated under a PVT subset.

[0046] The specific optimization process in the optimization decision model of this embodiment is as follows: First, the relevant parameters of the simulated circuit are used as input data, which may include various parameters of the circuit design such as transistor size, capacitance, and resistance. The circuit parameters and additional information such as PVT conditions are used as input through the encoder network of CVAE (i.e., encoder). The encoder encodes the circuit parameters to generate a representation of the latent space (i.e., initial latent feature vector) and learns the complex relationship between the circuit design and its performance. Then, the initial latent feature vector generated by CVAE is reconstructed through a diffusion model to optimize the distribution of the latent space, resulting in a reconstructed latent feature vector. The decoder extracts data from the reconstructed latent feature vector and converts it back to the actual circuit parameters to obtain the circuit parameters of the optimized design.

[0047] According to some embodiments of this application, step S303, which involves denoising and reconstructing the initial latent feature vector using a reconstructor to obtain a reconstructed latent feature vector, may include, but is not limited to, the following steps: S401, based on the prior knowledge of the data distribution learned and the constraint guidance of the PVT corner subset, performs noise identification on the initial latent feature vector to determine the noise component in the initial latent feature vector; S402, perform inverse denoising reasoning on the initial latent feature vector based on the noise components to obtain the reconstructed latent feature vector.

[0048] This embodiment employs a reparameterized sampling strategy as a differentiable coupling interface between the variational autoencoder (CVAE) and the diffusion model to achieve directional optimization of the latent space. The method first introduces an auxiliary noise variable following a standard normal distribution. Through linear transformation, the abstract probability distribution statistics (including the mean vector and variance vector) output by the encoder are converted into a specific, differentiable initial latent feature vector. This initial latent feature vector serves as the initial noisy state in the inverse generation process of the diffusion model. The diffusion model utilizes its prior data distribution learned during training. Guided by the constraints of the target circuit's PVT conditions, it identifies feature components in this vector that deviate from the true physical manifold as noise. Through iterative inverse denoising inference calculations, the distribution deviation of this vector is gradually corrected, projecting it from a coarse region of low probability density to a high probability density region conforming to physical laws. This completes the refined reconstruction and performance optimization of the initial latent feature vector, yielding the reconstructed latent feature vector.

[0049] According to some embodiments of this application, the above-described single-round circuit parameter optimization and simulation process may also include, but is not limited to, the following steps: S501 updates the optimization decision model based on the circuit performance and expected performance obtained in the current round.

[0050] In this embodiment, during the single-round circuit parameter optimization and simulation operation, the optimization decision model can also be optimized by combining the circuit performance feedback from the simulation system, so that the optimization decision model can quickly and accurately find the circuit parameters that achieve the desired performance. The optimization decision model can be implemented using a model optimization method based on a reinforcement learning framework, or it can be implemented using a multi-objective optimization method based on a loss function, etc. In the reinforcement learning optimization framework, the optimization decision model is used as a policy network (actor network), and a value network (critic network) is used to evaluate and update it. Reinforcement learning (RL) is a machine learning paradigm that allows an agent to learn the optimal decision sequence through continuous interaction with the environment. Its core framework includes an agent, an environment, and a reward signal: the agent observes the state of the environment and takes an action; the environment reacts by transitioning to a new state and giving a reward; the agent's goal is to learn an optimal policy (i.e., a mapping from state to action) by maximizing the long-term cumulative reward. In this embodiment, the reinforcement learning framework models circuit parameter optimization as a sequential decision-making process: the agent generates actions to adjust parameters based on the current circuit state (performance), the simulation environment returns performance indicators and rewards, the Critic network evaluates the value of the actions, and finally guides the optimization to efficiently advance towards the goal of comprehensively improving multi-faceted performance.

[0051] According to some embodiments of this application, step S501 may include, but is not limited to, the following steps: S601, determine the reward value based on the circuit performance and expected performance obtained in the current round; S602, update the value network in the reinforcement learning framework based on the reward value; S603: The circuit parameters output by the optimization decision model, which serves as the policy network, are evaluated based on the updated value network, and then the policy network is updated based on the evaluation results.

[0052] This embodiment combines the advantages of CVAE, diffusion models, and reinforcement learning, and can effectively handle complex circuit designs and high-dimensional parameter spaces. Therefore, it can be well extended to circuit design problems with multiple sub-modules, providing more accurate and robust optimization results and significantly improving the automated optimization capability of complex circuit designs.

[0053] Specifically, the optimization decision model in this embodiment can adopt the following approach: Figure 4 The reinforcement learning framework shown has been updated, and the components are explained below: Analog circuit parameters include circuit parameters (such as transistor parameters, capacitor values, and resistor values) that serve as inputs to the variational autoencoder. The inputs to the variational autoencoder also include the performance values ​​obtained from the previous simulation, the one-hot encoding of the PVT angle from the previous simulation, and the one-hot encoding of the PVT angle from this simulation.

[0054] Actor Networks: In reinforcement learning frameworks, actor networks (i.e., optimization decision models) are responsible for generating optimized circuit parameters. They select the optimal action based on the current state (i.e., the performance of the input in the previous step) to adjust the input circuit parameters, resulting in optimized circuit parameters. The actor network acts as the optimization decision-maker, generating action policies based on the input circuit parameters and performance objectives, thereby guiding the circuit optimization process.

[0055] Circuit parameter simulation: By simulating the optimized circuit parameters, the performance of the circuit under different PVT conditions in a subset of PVT corners is calculated. Circuit parameter simulation is used to evaluate the performance of the current circuit design and calculate the corresponding reward value for subsequent optimization decisions. Specifically, the reward value can be obtained by combining the circuit performance under different PVT conditions, such as by averaging the circuit performance under different PVT conditions.

[0056] Critics networks are used to evaluate the value of circuit parameters generated by actor networks. They assess the effectiveness of the policy based on the reward value of the current circuit design. Critics networks provide feedback to actor networks, helping them improve their policies. They evaluate the effectiveness of actions taken in the current state by calculating the Q-score (value function).

[0057] Evaluating parameter value: This involves calculating the Q-value. In reinforcement learning, evaluating parameter value means assessing the reward of the current circuit design through a critic network and determining the design's worth. This process helps the model understand how the current design affects the final result throughout the optimization process, thus determining which design parameters need further optimization.

[0058] Network Update: Based on feedback from the actor and critic networks, update the network parameters (weights). This ensures the model can progressively improve its strategy based on rewards and evaluation results, thereby selecting more suitable circuit parameters in the next round of optimization and driving the optimization process towards the goal.

[0059] First, the relevant parameters of the simulated circuit are used as input data for the entire reinforcement learning process. These parameters include various aspects of the circuit design (such as resistance and capacitance). The actor network generates optimized circuit parameters based on the current circuit parameters. The generated circuit parameters are then simulated in the environment to obtain the corresponding performance. This simulation result is first used to calculate the reward value for a single step and update the critic network. The updated critic network is then used to calculate the value function (Q-value) of the policy network output. The Q-value output by the critic network serves as a feedback signal to update the parameters of the actor network. Backpropagation is used to adjust the network weights to improve the policy and drive the circuit design towards a better outcome.

[0060] According to some embodiments of this application, the optimization framework of this embodiment combines a conditional variational autoencoder (CVAE) with a diffusion model, utilizing the actor-critic mechanism in reinforcement learning for circuit design optimization. Circuit parameters are generated through an actor network, and their performance is evaluated by a critic network. Combined with simulation and feedback under PVT conditions, the circuit parameters are progressively updated, enabling efficient and robust optimization from multiple PVT perspectives. The optimization framework of this embodiment includes the following two parts: The local framework, namely the integrated network of conditional variational autoencoder (CVAE) and diffusion model, combines CVAE with diffusion model as a reinforcement learning generation strategy. It learns the potential mapping relationship between circuit parameters and performance through CVAE and optimizes the latent space distribution of CVAE using diffusion model, which further improves the expressive power of latent space and enables circuit design to be optimized more accurately in multi-dimensional parameter space.

[0061] The global framework, or reinforcement learning exploration framework under PVT conditions, employs reinforcement learning (RL) to conduct a comprehensive exploration across the entire PVT spectrum during circuit optimization. By training the network in a full PVT environment, it learns how to effectively select circuit parameters under different PVT conditions, thereby improving the circuit's robustness under various process, voltage, and temperature variations. This method addresses the shortcomings of traditional optimization methods due to the lack of a full-spectrum evaluation, enhancing both the globality and robustness of the optimization.

[0062] Specifically, please refer to Figure 5 The overall optimization process for circuit parameters in this embodiment is as follows: S11, Generate the initial dataset: First, a set of circuit parameters is randomly sampled, and simulations are performed on the initial circuit parameters under all PVT angles in the PVT angle set to obtain all PVT angles in the PVT angle set and their corresponding circuit performance (this circuit performance can be represented by a comprehensive score value for circuit performance). The performance data obtained through simulation and the corresponding PVT conditions are stored in the experience replay pool. The experience replay pool contains the circuit parameters, PVT conditions, and performance data for each iteration round, serving as the basis for subsequent model training.

[0063] S12 uses an optimization decision model combining the CVAE model and the diffusion model to optimize the circuit parameters of the previous round. The additional conditions for optimization include the PVT conditions and circuit performance of the previous round simulation, as well as the PVT conditions of this round obtained by sampling all PVT corners through the corner sampling strategy.

[0064] In this model, the initial circuit parameters and conditional data are concatenated and input into the encoder. The encoder outputs the mean and log-variance of the latent space by maximizing the log-likelihood function. Then, the encoded latent space variables are input into the decoder to reconstruct the circuit parameters. The CVAE model is updated by calculating the reconstruction loss and the KL divergence loss, as follows: The total loss of the CVAE model is expressed as: ; in, Represents the reconstruction loss, used to measure the error between the circuit parameters generated by the decoder and the actual circuit parameters; KL divergence loss (Kullback–Leibler divergence) is used to constrain the distribution of the latent space to approximate the standard normal distribution. This represents the weighting coefficient, used to adjust the relative importance between the reconstruction loss and the KL divergence loss.

[0065] The reconstruction loss is expressed as follows: ; in, This represents the actual circuit parameters of the i-th group; This represents the circuit parameters reconstructed by the CVAE decoder for the i-th group; represents the squared Euclidean distance; N represents the number of samples.

[0066] The KL divergence loss is expressed as follows: ; in, This represents the posterior distribution of the latent variables obtained by the encoder; This represents the prior distribution (usually set as the standard normal distribution). This represents the KL divergence (Kullback–Leibler divergence, information divergence), which measures the difference between two probability distributions.

[0067] The diffusion model starts with latent space variables generated by CVAE and, combined with conditional data, is trained using the diffusion model. The diffusion model involves adding and denoising noise to gradually recover the latent space and optimize the model parameters. The noise addition formula is expressed as follows: ; in, Represents the original latent variables of the diffusion process; This represents noise sampled from a standard normal distribution; This represents the noise attenuation coefficient (cumulative retention rate) during the diffusion process.

[0068] S13, Environment Interaction: Simulate the generated circuit parameters and obtain the corresponding performance values ​​by selecting multiple PVT angles through the angle sampling strategy.

[0069] S14, Calculate Reward and Next State: Calculate the reward based on the gap between the new simulation results (such as the average performance) and the target value (such as the expected performance constraint), and update the next state to a new combination of PVT conditions and performance data.

[0070] S15, Network Update: A training batch is constructed based on the current state, action, and reward data. The target Q-value is calculated, and the Critic network is updated by minimizing the difference between the target Q-value and the predicted Q-value, providing accurate value assessment for the policy network. The Actor network aims to maximize the Critic's Q-value output, updating its parameters by minimizing the loss function. The Q-value is calculated recursively, as follows: ; Where r represents the immediate reward from environmental feedback; This represents a discount factor (0–1), used to balance the importance of current rewards and future rewards; This represents the target Q value for taking action a′ in the next state s′.

[0071] S16, Update the experience replay pool and optimize the decision model: Store the newly generated circuit parameters, PVT conditions and performance data into the experience replay pool, and update the parameters of the optimized decision model according to the training process.

[0072] S17, Iterative Loop: Repeat the above process until the termination condition is met, such as reaching the maximum number of training steps or the optimization goal.

[0073] According to some embodiments of this application, CVAE effectively reduces dimensionality and optimizes the exploration efficiency of circuit design by mapping high-dimensional circuit parameters to a low-dimensional latent space. Based on this, the diffusion model further optimizes the latent space distribution, enabling circuit design to more accurately capture complex relationships in the high-dimensional parameter space. This combination not only improves the sample efficiency of optimization but also extends to higher-dimensional circuit design optimization tasks, making it particularly suitable for the design of multi-submodule and complex circuits.

[0074] This embodiment improves the comprehensiveness and efficiency of the optimization process by selecting several historically worst PVT angles and several random PVT angles for simulation. This strategy avoids the problem of traditional methods optimizing only a few angles, enabling a comprehensive evaluation of all PVT angles, while also saving simulation resources and improving computational efficiency, ultimately enhancing the accuracy and efficiency of the optimization. This innovation combines dimensionality reduction and intelligent sampling strategies, making the circuit design optimization process more efficient and accurate, capable of handling more complex design tasks, and possessing greater application potential.

[0075] This application also provides a circuit parameter optimization system, including: The first module is used to initialize circuit parameters and perform circuit simulations at all PVT angles in the PVT angle set according to the circuit parameters, so as to obtain the circuit performance at the corresponding PVT angle. The second module is used to repeatedly perform circuit parameter optimization and simulation operations based on the PVT angle set until the preset iteration conditions are met to obtain the optimal circuit parameters. The circuit parameter optimization and simulation operation includes the following steps: Select the N worst-performing PVT angles from the PVT angle set and randomly select M PVT angles to update the PVT angle subset; The simulation data from the previous circuit simulation and the PVT angle subset are input into the optimization decision model to optimize the circuit parameters, resulting in optimized circuit parameters. The simulation data includes circuit parameters, PVT angles, and corresponding circuit performance. The optimized circuit parameters are simulated under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round. The circuit performance of the corresponding PVT angle in the PVT angle set is updated based on the circuit performance obtained in the current round.

[0076] It is understood that the methods described in the above method embodiments are applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0077] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0078] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0079] Please see Figure 6 , Figure 6 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0080] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0081] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0082] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0083] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0084] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0085] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0086] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0087] The system embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0089] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0090] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0091] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0092] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0094] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0095] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for optimizing circuit parameters, characterized in that, Includes the following steps: Initialize the circuit parameters, and perform circuit simulations at all PVT angles in the PVT angle set according to the circuit parameters to obtain the circuit performance at the corresponding PVT angles; The circuit parameters are repeatedly optimized and simulated based on the PVT angle set until the preset iteration conditions are met, and the optimal circuit parameters are obtained. The circuit parameter optimization and simulation operation includes the following steps: Select the N worst-performing PVT angles from the PVT angle set and randomly select M PVT angles to update the PVT angle subset; The simulation data from the previous circuit simulation and the PVT angle subset are input into the optimization decision model to optimize the circuit parameters, resulting in optimized circuit parameters. The simulation data includes circuit parameters, PVT angles, and corresponding circuit performance. The optimized circuit parameters are simulated under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round. The circuit performance of the corresponding PVT angle in the PVT angle set is updated based on the circuit performance obtained in the current round.

2. The circuit parameter optimization method according to claim 1, characterized in that, The optimization decision model adopts a network architecture based on conditional variational autoencoders.

3. The circuit parameter optimization method according to claim 2, characterized in that, The optimization decision model performs circuit parameter optimization decisions through the following steps: The circuit parameters are used as input parameters, and the PVT angles and circuit performance of the previous round, along with the subset of PVT angles, are used as additional conditions to input into the encoder for feature extraction, thereby obtaining the latent space representation features. The latent space representation features are reparameterized and sampled to obtain the probability distribution statistics in the latent space representation features, and then the probability distribution statistics are converted into a differentiable initial latent feature vector. The initial latent feature vector is denoised and reconstructed using a reconstructor to obtain the reconstructed latent feature vector; The reconstructed latent feature vector is decoded by a decoder to obtain the optimized circuit parameters.

4. The circuit parameter optimization method according to claim 1, characterized in that, The reconstructor is a diffusion probability model. The process of denoising and reconstructing the initial latent feature vector using the reconstructor to obtain the reconstructed latent feature vector includes the following steps: Based on the prior knowledge of the data distribution learned and the constraint guidance of the PVT corner subset, noise identification is performed on the initial latent feature vector to determine the noise component in the initial latent feature vector; Based on the noise components, the initial latent feature vector is subjected to inverse denoising inference to obtain the reconstructed latent feature vector.

5. The circuit parameter optimization method according to claim 1, characterized in that, The circuit parameter optimization and simulation operation also includes the following steps: The optimization decision model is updated based on the circuit performance and expected performance obtained in the current round.

6. The circuit parameter optimization method according to claim 5, characterized in that, The step of updating the optimization decision model based on the circuit performance and expected performance obtained in the current round includes the following steps: The reward value is determined based on the circuit performance and expected performance obtained in the current round; The value network in the reinforcement learning framework is updated based on the reward value; The circuit parameters output by the optimization decision model, which serves as the policy network, are evaluated based on the updated value network, and then the policy network is updated based on the evaluation results.

7. A circuit parameter optimization system, characterized in that, include: The first module is used to initialize circuit parameters and perform circuit simulations at all PVT angles in the PVT angle set according to the circuit parameters, so as to obtain the circuit performance at the corresponding PVT angle. The second module is used to repeatedly perform circuit parameter optimization and simulation operations based on the PVT angle set until the preset iteration conditions are met to obtain the optimal circuit parameters. The circuit parameter optimization and simulation operation includes the following steps: Select the N worst-performing PVT angles from the PVT angle set and randomly select M PVT angles to update the PVT angle subset; The simulation data from the previous circuit simulation and the PVT angle subset are input into the optimization decision model to optimize the circuit parameters, resulting in optimized circuit parameters. The simulation data includes circuit parameters, PVT angles, and corresponding circuit performance. The optimized circuit parameters are simulated under all PVT angles of the PVT angle subset to obtain the circuit performance under each PVT angle in the current round. The circuit performance of the corresponding PVT angle in the PVT angle set is updated based on the circuit performance obtained in the current round.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

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