Chip parameter optimization method and system based on finite element analysis

Abstract

The application discloses a chip parameter optimization method and system based on finite element analysis, and relates to the technical field of chips. The corresponding key areas are determined based on the identification of the finite element model of the chip. The corresponding multi-modal data is determined according to each key area and corresponding parameter information. The performance level of the corresponding key area is determined based on the identification of the multi-modal data. The precision of the performance level of the key area is improved. A plurality of groups of design variables are determined according to a plurality of response data and the physical performance of the chip. The corresponding key design contents are determined along the finite element analysis of each group of design variables. Each key design content is iterated in the same finite element space. The optimal parameter combination is determined. The process report of the chip is determined based on the matching of the optimal parameter combination and the layout of the chip. The precision of the optimal parameter combination is improved. The parameter optimization of the chip is realized.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to a method and system for chip parameter optimization based on finite element analysis. Background Technology

[0002] In the field of chip physical verification and parameter optimization, existing technologies typically only construct simplified two-dimensional or quasi-three-dimensional models based on chip layout data. When performing finite element analysis, they often adopt the assumption of homogenized material properties, ignoring the differences in material properties at the microscale of different layers (such as metal interconnect layers and dielectric layers) in multi-layer stacked structures. They lack in-depth correlation analysis of multi-physics data (thermal, mechanical, and electrical), which affects the accuracy of performance levels in key areas and results in low accuracy of the optimal parameter combination, thus delaying chip parameter optimization. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for optimizing chip parameters based on finite element analysis.

[0004] This invention provides a method for optimizing chip parameters based on finite element analysis, including:

[0005] The chip layout is collected, and the corresponding layer information is determined based on the identification of the chip layout. A finite element model of the chip is constructed based on the layer information, the overall shape of the chip, and the corresponding usage scenario. Based on the identification of the finite element model of the chip, the corresponding key regions are identified, and the corresponding parameter information is marked in each key region. Based on each key region and the corresponding parameter information, the corresponding multimodal data is determined, and the performance level of the corresponding key region is determined based on the identification of the multimodal data. Based on the detection of chip usage scenarios, multiple environmental factors are identified, and the functions and corresponding performance levels of these environmental factors, key areas, and chip performance are deeply integrated to output multiple response data for the chip. Multiple sets of design variables are determined based on multiple response data and the physical properties of the chip. The corresponding key design contents are determined by finite element analysis along each set of design variables. Each key design content is iterated in the same finite element space to determine the optimal parameter combination. The chip process report is determined based on the optimal parameter combination and the matching of the chip layout.

[0006] This invention provides a chip parameter optimization system based on finite element analysis, which is applied to the aforementioned chip parameter optimization method based on finite element analysis. The chip parameter optimization system based on finite element analysis includes: The finite element module is used to acquire the chip layout, determine the corresponding layer information based on the chip layout identification, and construct the chip's finite element model based on the layer information, the chip's overall shape, and the corresponding usage scenario. The key region module is used to identify the corresponding key regions based on the identification of the chip's finite element model, mark the corresponding parameter information in each key region, determine the corresponding multimodal data based on each key region and the corresponding parameter information, and determine the performance level of the corresponding key region based on the identification of the multimodal data. The response data module is used to determine multiple environmental factors based on the chip's usage scenario and to deeply integrate these environmental factors, the functions of each key area, and their corresponding performance levels to output multiple response data for the chip. The parameter optimization module is used to determine multiple sets of design variables based on multiple response data and the physical performance of the chip. It determines the corresponding key design contents by performing finite element analysis along each set of design variables. Each key design content is iterated in the same finite element space to determine the optimal parameter combination. Based on the optimal parameter combination and the matching with the chip layout, the chip process report is determined.

[0007] Compared with the prior art, the beneficial effects of the present invention are: (1) Collect the chip layout, determine the corresponding layer information based on the chip layout identification, construct the chip finite element model based on the layer information, the overall shape of the chip and the corresponding usage scenario; determine the corresponding key areas based on the chip finite element model identification, and mark the corresponding parameter information in each key area, determine the corresponding multimodal data based on each key area and the corresponding parameter information, determine the performance level of the corresponding key area based on the identification of the multimodal data, introduce the chip finite element model, and further control the multimodal data to improve the accuracy of the performance level of the key area.

[0008] (2) Based on the detection of the chip's usage scenario, multiple environmental factors are determined, and the functions and corresponding performance levels of multiple environmental factors, key areas and the chip are deeply integrated to output multiple response data of the chip; multiple sets of design variables are determined based on multiple response data and the chip's physical performance, and the corresponding key design contents are determined along the finite element analysis of each set of design variables. Each key design content is iterated in the same finite element space and the optimal parameter combination is determined. Based on the optimal parameter combination and the matching of the chip's layout, the chip's process report is determined, the response data is controlled, and multiple sets of design variables are fully considered, which improves the accuracy of the key design contents and the accuracy of the optimal parameter combination, and realizes the chip's parameter optimization. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating the chip parameter optimization method based on finite element analysis in an embodiment of the present invention. Figure 2 This is a flowchart illustrating step S11 in the chip parameter optimization method based on finite element analysis in this embodiment of the invention. Figure 3 This is a flowchart illustrating step S12 in the chip parameter optimization method based on finite element analysis in this embodiment of the invention. Figure 4 This is a flowchart illustrating step S13 in the chip parameter optimization method based on finite element analysis in this embodiment of the invention. Figure 5 This is a flowchart illustrating step S14 in the chip parameter optimization method based on finite element analysis in this embodiment of the invention. Figure 6 This is a schematic diagram of the structural composition of the chip parameter optimization system based on finite element analysis in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0011] Please see Figures 1 to 6 A parameter optimization method for chips based on finite element analysis is applied to chip scenarios. The parameter optimization method for chips based on finite element analysis includes: Step S11: Collect the chip layout, determine the corresponding layer information based on the chip layout identification, and construct the chip finite element model based on the layer information, the overall shape of the chip and the corresponding usage scenario; Step S12: Based on the identification of the finite element model of the chip, the corresponding key regions are determined, and the corresponding parameter information is marked in each key region. Based on each key region and the corresponding parameter information, the corresponding multimodal data is determined, and the performance level of the corresponding key region is determined based on the identification of the multimodal data. Step S13: Based on the detection of the chip's usage scenario, determine multiple environmental factors, and deeply integrate the functions and corresponding performance levels of multiple environmental factors and each key area to output multiple response data of the chip; Step S14: Based on multiple response data and the physical performance of the chip, determine multiple sets of design variables, determine the corresponding key design contents by finite element analysis along each set of design variables, iterate each key design contents in the same finite element space, determine the optimal parameter combination, and determine the chip process report based on the optimal parameter combination and the matching of the chip layout.

[0012] refer to Figure 2In step S11, the specific steps are as follows: S111: Mark the chip database and determine the chip layout based on the traversal of the chip database. Perform image segmentation on the chip layout and identify multiple key layers during the image segmentation process. These key layers cover the metal interconnect layer, active layer, and dielectric layer. In each key layer, mark the corresponding layer information, which includes the material properties of the key layer and the corresponding region boundary. S112: Collect the chip's usage scenario, identify multiple usage constraints based on the chip's usage scenario, determine the chip's finite element framework based on each usage constraint and the information at this level, determine the chip's finite element model by fusing multiple factors along the finite element framework and the chip's overall shape, and use the chip's finite element model as a digital twin to capture local subtle stress concentrations and electric field distortions.

[0013] In the embodiments of this application, a database of chips is marked, and the chip layout is determined based on the traversal of the chip database. The chip layout is image segmented, and multiple key layers are identified during the image segmentation process. These key layers cover the metal interconnect layer, the active layer, and the dielectric layer. In each key layer, corresponding layer information is marked. This layer information includes the material properties of the key layer and the corresponding region boundary, which takes into account the overall consideration of the traversal of the chip database and ensures the accuracy of the chip layout.

[0014] At this point, the system performs a full scan and marking of the chip's design database. This typically involves reading GDSII or OASIS stream files. The system will establish database indexes and identify different cell reference relationships to ensure the integrity of the hierarchical structure.

[0015] By traversing the marked database, all vector geometric data constituting the chip layout are parsed out. This step reconstructs the discrete data stream into a continuous two-dimensional planar geometry, distinguishing primitives such as polygons, paths, and text, and providing a basic coordinate system and geometric boundaries for subsequent image processing.

[0016] The extracted layout geometry is mapped to a high-resolution bitmap or raster image. Image segmentation based on edge detection or region growing is then applied, which separates the tightly interwoven structures in the layout and eliminates visual confusion between different design levels. Based on the segmented image features, the system automatically identifies and divides three key physical layers: metal interconnect layer: identifies geometric grids with high conductivity characteristics, responsible for transmitting electrical signals and current; active layer: identifies regions where transistors are concentrated, usually appearing as regular array structures or specific doped region outlines; dielectric layer: identifies insulating regions filled between metals and between metals and the substrate.

[0017] Each identified critical layer is digitally labeled, which not only involves assigning a name but also establishing a physical property ID. Based on the layer label, the corresponding material physical properties are automatically attached. For example, electrical conductivity, thermal conductivity, Young's modulus, and coefficient of thermal expansion are attached to the metal interconnect layer; dielectric constant, breakdown strength, and Poisson's ratio are attached to the dielectric layer. The regional boundaries of each critical layer are precisely determined, including inner boundaries (such as via locations) and outer boundaries (such as chip dicing channels). These boundaries will serve as the geometric constraints for subsequent finite element mesh generation and the physical interface for load application.

[0018] Specifically, for the chip, the GDSII database used for its tape-out is called; the system marks the TopCell in the database and recursively traverses all Sub-Cells under it; during the traversal, the geometric coordinate data of the chip's core computing unit, I / O interface and power management module are extracted, and the complete two-dimensional layout outline of the chip is reconstructed to ensure that the line width and spacing data of each interconnect line are accurately restored.

[0019] The chip employs a multi-layer copper interconnect process; the partitioning method successfully separates the 6th metal layer (M6, a thick metal layer, mainly used for power distribution) from the 1st metal layer (M1, a thin line width, used for local logic connections) in the image space; at the same time, the system accurately identifies the active layer distribution in the logic core area, as well as the complex dielectric layer structure filling the metal lines, thus clarifying the functional areas for subsequent multiphysics analysis.

[0020] For chip parameter optimization, the attribute labeling is particularly refined; Metal interconnect layer: The system labels the chip's power grid layer and attaches the material properties of "copper", including its isotropic coefficient of thermal expansion (approximately 17ppm / K) and thermal conductivity as high as 400W / m·K, while defining the thickness boundary of this layer (e.g., 3μm); Dielectric layer: For the interlayer insulating layer, the system labels and attaches the "low-k dielectric material" property, setting its Young's modulus to be low (approximately 10GPa) to simulate its buffering effect on mechanical stress; Active layer: The silicon substrate region is labeled, the anisotropic material properties of single-crystal silicon are attached, and the high heat generation boundary of the transistor dense region is defined; The chip was successfully transformed from a database file into a physical model containing geometry, material properties, and region boundaries, laying a solid foundation for the subsequent construction of a high-precision finite element digital twin.

[0021] Furthermore, the chip's usage scenarios are collected, and multiple usage constraints are determined based on the identification of these scenarios. The finite element framework of the chip is determined according to each usage constraint and the information at this level. The finite element model of the chip is determined by fusing multiple factors along the finite element framework and the overall shape of the chip. The finite element model of the chip serves as a digital twin and captures localized subtle stress concentrations and electric field distortions. It incorporates the overall consideration of each usage constraint and the information at this level, ensuring the accuracy of the chip's finite element framework.

[0022] At this time, the system comprehensively collects the chip's operating mode in the terminal device, including but not limited to power cycling curves, changes in ambient temperature and humidity, mechanical vibration spectrum, and electromagnetic interference environment; based on the collected scenarios, it identifies key physical constraints, which typically include: thermal constraints: such as extreme ambient temperatures, thermal resistance, and power density distribution; mechanical constraints: such as the clamping force of the package on the chip, bending deformation of the PCB board, and displacement constraints caused by thermal expansion coefficient (CTE) mismatch; electrical constraints: such as the operating voltage range, peak current density, and high-frequency impacts caused by signal rising and falling edges.

[0023] Determine the coupling mode of the physical field based on the type of constraint factors. For example, if there is a large current and high heat dissipation, a strong "electric-thermal-mechanical" coupling framework needs to be established, i.e., Joule heating leads to thermal expansion, and thermal expansion leads to mechanical stress. Map the hierarchical information (such as metal interconnect layers and dielectric layers) into the framework and assign boundary conditions according to the application scenario. For example, the active layer is defined as a volume heat source, and the bottom contact surface is defined as a convective heat transfer boundary or a fixed temperature boundary. Select the appropriate solver settings for different physical fields, such as using full-wave analysis for high-frequency electric fields and nonlinear static analysis for structural deformation.

[0024] By integrating the finite element framework with the overall shape of the chip (such as the chip's aspect ratio and thickness), a three-dimensional solid simulation model is generated. This model serves as a virtual mapping of the physical chip, reflecting its global response under real-world conditions. The system employs adaptive mesh refinement technology to densify the mesh at points of geometric abrupt changes and regions with drastic field strength variations. High-density meshing is performed at interfaces between different materials (such as the connection between copper vias and silicon substrates) to analyze stress concentration points caused by abrupt changes in elastic modulus. Fine-grained modeling is performed on geometric singularities such as sharp corners and cross-shaped intersections of metal wires to capture electric field distortion phenomena caused by charge accumulation.

[0025] Specifically, for the chip, the target application scenario is a high-performance edge computing server, which operates under extremely harsh conditions. When the chip is running inference tasks, it will experience a jump from low power consumption to full load (power consumption suddenly increases to 50W) within a few microseconds. Based on this, the system identified two key constraints: transient thermal shock constraint: the chip surface temperature needs to fluctuate rapidly between 85℃ and 125℃; electromagnetic integrity constraint: since the chip integrates a high-speed SerDes interface, its operating frequency is as high as 28Gbps, and the skin effect and dielectric loss at high frequencies must be considered.

[0026] To accurately simulate chip reliability, an electro-thermal-mechanical multiphysics coupling framework was constructed. Here, the top-level power network (metal interconnect layer) of the chip identified in S111 was mapped as a Joule heat source region, and its resistivity change characteristics with temperature were incorporated into the framework. Elastic support constraints based on the properties of the packaging material were applied to the bump region at the bottom of the chip. Convective heat transfer boundary conditions simulating air cooling were applied to the chip surface. The framework was set to sequential coupling, first performing electro-thermal analysis to calculate the temperature field, and then applying the temperature field as a volume load to the mechanical analysis module to calculate thermal stress.

[0027] When constructing the digital twin of the chip, special attention was paid to the microstructures that lead to early failure; a complete 3D model of the chip with a size of 15mm×15mm was constructed; the system automatically detected a large number of microvia arrays in the chip's power module; around these vias with diameters only at the micrometer level, the mesh size was automatically refined to the submicrometer level. Through this refined modeling, the digital twin successfully captured the stress concentration phenomenon at the copper interconnect interface at the bottom of the via (the stress peak was 3 times higher than the average value), as well as the electric field distortion at the corner of the metal wire caused by high-frequency signal transmission (singular points appeared in the electric field strength). The capture of these subtle features directly guided the subsequent chamfer optimization and via layout adjustment of the chip layout.

[0028] refer to Figure 3 In step S12, the specific steps are as follows: S121: Perform effective simulation of the finite element model of the chip, and identify multiple distribution features during the simulation process, including thermal field gradient and stress concentration tensor; cluster the multiple distribution features and the preset functional modules of the chip to construct the corresponding key regions; extract features from the key regions and output the current density, mechanical stress, and temperature within the key regions, and further analyze the corresponding multi-scale features. S122: Multiple parameter combinations are determined by matching current density, mechanical stress, temperature and multi-scale characteristics. Based on the identification of each parameter combination, the corresponding parameter information is determined. Multi-factor synthesis is performed on each key region and the corresponding parameter information, and the corresponding multimodal data is output. S123: Perform nonlinear mapping training on multimodal data, and further perform deep identification on multimodal data to determine multiple performance contents of the corresponding key regions. Based on the mapping relationship between multiple performance contents and performance levels, determine the performance level of the corresponding key regions.

[0029] In the embodiments of this application, the finite element model of the chip is effectively simulated, and multiple distribution features are included in the simulation process, including thermal field gradient and stress concentration tensor. The multiple distribution features and the preset functional modules of the chip are clustered to construct the corresponding key regions. Features are extracted from the key regions, and the current density, mechanical stress and temperature in the key regions are output. Furthermore, the corresponding multi-scale features are analyzed, and the corresponding multi-scale features are further analyzed.

[0030] At this point, boundary conditions are applied to the constructed digital twin, and transient or steady-state solvers are run. The solution process needs to converge to a preset residual accuracy to ensure that the calculated nodal solutions (such as displacement, electric potential, and temperature) have physical meaning. The post-processing module extracts vector field and tensor field data across the entire domain. Two key features are identified: thermal field gradient: characterizing the rate of temperature change in space; high gradient regions indicate severe thermal expansion and contraction, which are potential sources of thermal stress; stress concentration tensor: characterizing the internal stress state. By calculating the von Mises stress or the maximum principal stress, the clustering points of numerical anomalies in the tensor matrix are identified. These points are often the starting points of material failure.

[0031] The extracted thermal gradient and stress tensor are mapped back to the chip's layout coordinates and superimposed with preset functional modules (such as CPU cores, GPU arrays, SRAM storage areas, and PLL clock trees). Clustering methods (such as DBSCAN or K-Means) are used to aggregate regions with spatially dense distribution of physical feature anomalies (such as high stress points) that belong to the same important functional module. The clustering results form several independent critical regions. These regions are not only physically weak links but also logically core functional areas. Failure in these areas will lead to the paralysis of the entire chip's functionality.

[0032] Within critical regions, precise node-level physical parameters are extracted, including: current density (J): used to assess electromigration risk; mechanical stress (σ): used to assess crack initiation risk; and temperature (T): acting as an acceleration factor affecting all the above physical processes. Macroscopic (chip-level) field distributions are correlated with microscopic (material grain-level / interconnect-level) structural features. Analyze how macroscopic gradients lead to microstructural distortions, such as how thermal gradients drive metal atom diffusion or how stress tensors cause microcrack propagation at dielectric layer interfaces.

[0033] Specifically, for the chip, a high-load transient simulation lasting 10 milliseconds was performed; thermal gradient: the simulation results show that there is a huge difference in heat flux density between the core computing area of ​​the chip and the surrounding I / O area. The system captured a thermal gradient as high as 5℃ / mm, which indicates that the heat transfer from the core area to the outside is blocked; stress concentration tensor: at the interface between the filler layer and the silicon substrate at the bottom of the chip, due to the mismatch of the thermal expansion coefficients of the materials, the system calculated significant stress concentration tensor components, especially below the flip chip bumps, where the tensor values ​​show a non-uniform peak distribution.

[0034] In the post-processing analysis of the chip, two-dimensional clustering was performed. The system superimposed the high thermal gradient region with the chip's "intelligent tensor computing core" module; at the same time, it superimposed the high stress concentration region with the "on-chip high-speed interconnect network" module. Through clustering, two main key regions were identified: the key thermal-mechanical region: a local area located at the center of the intelligent core, which not only bears the highest computing load, but also experiences the most severe thermal coupling effect due to the pressure of the heat sink above; and the key electrical-mechanical region: the SerDes (high-speed serial interface) region located at the edge of the chip, where wiring is dense, current density is high, and the impact of packaging stress is most significant.

[0035] Deep multi-scale feature analysis was performed on the key areas identified by clustering. In the key area of ​​the intelligent core, the local temperature reached 115℃ and the peak current density of the power rail reached 3×106A / cm². In the key area of ​​SerDes, the mechanical stress of the TSV (through silicon via) interface reached 250MPa, which is close to the fracture strength threshold of silicon material.

[0036] Analysis revealed that the high thermal gradient on a macroscopic scale causes thermal expansion of the lattice of the metal interconnects on a microscopic scale, which in turn squeezes the surrounding low-k dielectric layer, resulting in micron-level electric field distortion inside the dielectric layer. This multi-scale coupling characteristic indicates that the chip faces not only heat dissipation problems in these regions, but also the risk of stress-driven dielectric breakdown and electromigration failure, which provides a clear direction for subsequent parameter optimization.

[0037] Furthermore, multiple parameter combinations are determined by matching current density, mechanical stress, temperature, and multi-scale features. Based on the identification of each parameter combination, the corresponding parameter information is determined. Multi-factor synthesis is performed on each key region and the corresponding parameter information, and the corresponding multimodal data is output. This approach takes into account the overall consideration of identifying each parameter combination and ensures the accuracy of the corresponding parameter information.

[0038] At this point, the distribution characteristics of current density, mechanical stress, temperature, etc. extracted by S121 are correlated and matched with the designable parameters of the chip. This is usually based on accompanying sensitivity analysis or empirical engineering rules. The set of parameters that have the greatest impact on specific physical characteristics is identified. For example, high current density regions are usually related to the cross-sectional area parameters of metal lines; high stress concentration regions are usually related to the arrangement density of vias or the Young's modulus of the dielectric layer. The system pairs these related parameters with the corresponding physical characteristics to form multiple "parameter-feature" combinations.

[0039] For a given combination of parameters, the physical properties, value range, and process constraints of each parameter are analyzed. These include geometric parameters (such as minimum linewidth and maximum spacing) and material parameters (such as dielectric constant and thermal conductivity). Combined with the chip's process design rules (DRC), effective value boundaries are set for each parameter. For example, the metal linewidth cannot be less than the minimum resolution of photolithography, and the via density cannot exceed the upper limit of manufacturing capability. This ensures that the parameters optimized later are manufacturable.

[0040] The spatial coordinates of the key region, the corresponding parameter information (design variables), and the physical response of the region in S121 (objective function or constraint function) are uniformly encapsulated. This is no longer a single data stream, but a comprehensive vector containing multi-dimensional information such as geometry, physics, and materials. A structured data format (such as tensor or feature map) is output. This dataset contains both the dynamic relationship of "how the physical field B will change if parameter A is adjusted" and the static values ​​in the current state. This multimodal data can comprehensively describe the position of the key region in the multi-dimensional parameter space.

[0041] Specifically, for the chip, feature matching was performed on the high-risk areas identified by S121; thermo-mechanical parameter combination: in the intelligent core area with extremely high thermal gradient, the system matched the "temperature distribution characteristics" with the "dielectric layer thickness (hox)" and the "metal linewidth (Wmetal)", which constructed the parameter combination {T,hox,Wmetal}, meaning that adjusting the linewidth and thickness can directly affect the thermal resistance and thermal capacity.

[0042] Electrical-mechanical parameter combination: In the stress-concentrated SerDes interface region, the system matches the "mechanical stress tensor" with the "via pitch (Pvia)" and the "copper interconnect height (Hcu)", which constructs the parameter combination {σ,Pvia,Hcu}, designed to release stress by adjusting the via layout.

[0043] The system performed detailed information identification on the above parameter combinations. For the {Pvia,Hcu} combination in the SerDes region, the system identified that the current design value of the via spacing Pvi is 1.0 μm, and the allowable optimization range is 0.8 μm to 1.5 μm (limited by photolithography accuracy). The copper interconnect layer height Hcu is fixed at 2.0 μm, but its effective residual stress parameter can be adjusted through chemical mechanical polishing (CMP). For the {hox,Wmetal} combination in the core region, the system defined the thickness error range of the dielectric layer and marked the influence weight of metal linewidth adjustment on parasitic capacitance, which is used as part of the parameter information.

[0044] The above information is synthesized into a multimodal data packet for the chip's SerDes region; inputs include: critical region ID (SerDes_Ring_01), design parameters (via spacing Pvia variation range), and physical response (current maximum principal stress 250MPa, target <180MPa); the system calculates the sensitivity coefficient of via spacing variation to stress release and weights it with temperature distribution; finally, a set of multimodal data is output, in the following format: <Region_Coord,{Pvia,ΔPvia},{σcurrent,σgrad,Tlocal},Sensitivity_Matrix> .

[0045] This data clearly tells the optimizer that in the SerDes_Ring_01 region, for every 0.1 μm increase in the via spacing Pvia, the first invariant of the mechanical stress tensor σ decreases by an average of 15 MPa, but the local temperature rise increases by 0.5 °C due to the reduction in metal filling. This multimodal data, which includes competing relationships (stress improvement but increased thermal resistance), provides a precise mathematical basis for the subsequent search for the Pareto optimal solution.

[0046] Therefore, nonlinear mapping training is performed on multimodal data, and further deep identification is carried out on multimodal data to determine multiple performance contents of the corresponding key regions. Based on the mapping relationship between multiple performance contents and performance levels, the performance level of the corresponding key regions is determined. This approach takes into account the overall consideration of the mapping relationship between multiple performance contents and performance levels, ensuring the accuracy of the performance level of the corresponding key regions. At the same time, a finite element model of the chip is introduced, and multimodal data is further controlled, which improves the accuracy of the performance level of the key regions.

[0047] At this point, the multimodal data output by S122 is used as the training set. The input vector includes design parameters (such as via spacing and linewidth), and the output vector includes physical responses (such as stress tensor components and temperature gradient). Deep neural networks or Gaussian process regression are used to fit the input and output. Since the physical behavior of the chip (such as stress release caused by thermal expansion and void growth caused by electromigration) usually has highly nonlinear characteristics, this training process aims to capture those "hidden physical laws" that are difficult to describe with explicit formulas through the learning of multiple hidden layers. By minimizing the loss function, the mapping model can quickly predict the physical response under a given combination of parameters, thereby achieving a "second-level" response simulation effect.

[0048] By inputting the parameter scheme of the key region into the mapping model, the system not only outputs a single physical quantity, but also identifies the interactive effects between physical quantities through deep feature extraction; for example, it analyzes how temperature rise specifically deteriorates mechanical strength; based on the identification results, it calculates the specific performance content that determines chip reliability, which typically includes: electromigration lifetime: calculated based on the Black equation from current density and temperature; thermomechanical fatigue lifetime: calculated based on the Coffin-Manson model from stress-strain range; time delay and power consumption: calculated from changes in resistance and capacitance.

[0049] Establish threshold mapping rules between performance index values ​​and levels, which are usually based on industry standards (such as JEDEC standards) or internal enterprise reliability specifications; for example, set MTTF greater than 10 to the power of 5 hours as "excellent" and less than 10 to the power of 4 hours as "poor"; perform weighted comprehensive evaluation of multiple performance contents (such as lifetime, thermal resistance, and margin) determined in S22; output the performance level of key areas, common classifications such as "high performance level" (meets all indicators), "available level" (meets major indicators but has risks), and "critical level" (requires immediate optimization).

[0050] Specifically, a nonlinear mapping model of electro-thermal-mechanical coupling was constructed for the SerDes region of the chip. The input layer consists of the variation sequence of via spacing Pvia and dielectric layer thickness hox. The model successfully captured a key nonlinear phenomenon: when the via spacing is reduced to below a certain threshold (0.9 μm), the stress concentration factor does not decrease nonlinearly, but rebounds due to the proximity effect, while the Joule heating caused by the current density increases exponentially. After tens of thousands of iterations, the model achieved extremely high prediction accuracy and can accurately simulate the complex physical response of the chip under micron-level parameter adjustments.

[0051] The system performed in-depth analysis of the chip's intelligent core region. It identified that at a high temperature of 125 degrees Celsius, the metal interconnects in this region exhibited significant creep due to thermal stress, leading to a reduction in their effective conductive cross-sectional area over time. Based on this analysis, the system determined three core performance parameters for this region: MTTF (Mean Time To Failure): calculated as 5.2 × 10⁴ hours; thermal resistance: 1.8℃ / W; and voltage noise margin: only 8%, nearing its limit. These performance parameters directly reveal the chip's potential failure modes under current parameters.

[0052] The chip's key regions were ultimately graded; mapping rules: MTTF > 10^5 h and thermal resistance < 2.0℃ / W were classified as Grade A (high performance); MTTF between 10^4 and 10^5 h was Grade B (monitoring grade); MTTF < 10^4 h was Grade C (risk grade); SerDes region rating: Although its thermal resistance was acceptable, its voltage noise margin was only 8%, and its calculated MTTF was slightly lower than 10^5 h, therefore it was rated as Grade B. This means that although this region will not fail immediately, it lacks sufficient safety margin, and parameter fine-tuning is recommended; Intelligent core region rating: Due to its MTTF of only 5.2 × 10^4 h and high thermal resistance, it was directly rated as Grade C (risk grade). This clearly indicates that this region is a priority for subsequent parameter optimization (step S14), and must be upgraded to Grade A by increasing linewidth or optimizing the heat dissipation structure.

[0053] refer to Figure 4 In step S13, the specific steps are as follows: S131: Mark the application scenario of the chip, detect and quantify multiple coupled disturbances in the application scenario, and convert transient thermal shock, broadband mechanical vibration and electromagnetic interference intensity into time-varying boundary load of the chip in real time to determine multiple environmental factors; S132: Determine the corresponding functions based on the detection of each key area, determine the corresponding matching relationship based on the matching of multiple environmental factors and the functions of each key area, determine the corresponding multi-dimensional content by tracing along the matching relationship, deeply integrate the multi-dimensional content and the performance level of each key area, and output the corresponding coupling relationship, and determine multiple response data of the chip based on the monitoring of the coupling relationship.

[0054] In the embodiments of this application, the usage scenarios of the chip are marked, and multiple coupled disturbances in the usage scenarios are detected and quantified. The transient thermal shock, broadband mechanical vibration and electromagnetic interference intensity are converted into time-varying boundary loads of the chip in real time to determine multiple environmental factors. This approach incorporates the overall consideration of converting the chip into time-varying boundary loads in real time, ensuring the accuracy of multiple environmental factors.

[0055] At this point, the system performs high-precision labeling of the chip's terminal application scenarios, distinguishing them into steady-state, transient, or extreme operating conditions. This involves detailed descriptions of the ambient temperature range, atmospheric pressure, heat dissipation conditions, and installation methods; transforming qualitative scenario descriptions into quantitative parameter ranges; for example, defining "vehicle scenario" includes not only the temperature range, but also cold start characteristics, random vibration spectrum caused by vehicle bumps, and electromagnetic noise levels in the engine compartment.

[0056] The system identifies and separates three main sources of physical disturbance: transient thermal shock: large temperature changes in a very short time, resulting in extremely high thermal strain rates; broadband mechanical vibration: wide-spectrum excitation covering everything from low-frequency structural resonance to high-frequency acoustic vibration; and electromagnetic interference (EMI): spatial radiated or conducted interference that affects the signal integrity inside the chip.

[0057] Analyze the interactions between these disturbances; for example, quantify whether mechanical vibrations cause changes in the contact resistance of the heat sink, thereby exacerbating thermal shock; or whether strong electromagnetic fields induce eddy currents in interconnects, thereby generating additional Joule heat. Use time-frequency analysis techniques to quantify these disturbances into computable mathematical functions or power spectral density (PSD) curves.

[0058] Transient thermal shock is transformed into a time-varying temperature boundary function T(t) or heat flux density boundary function q(t); broadband mechanical vibration is transformed into time-varying acceleration boundary a(t), displacement boundary d(t), or power spectral density (PSD) inputs, which are applied to the chip mounting points; electromagnetic interference intensity is transformed into port excitation voltage / current V(t) / I(t) or incident wave boundary conditions; these time-varying loads are combined to form a complete set of "environmental factors", which will serve as inputs for the deep fusion calculation in step S13 to drive the finite element model for transient dynamics or transient thermodynamics analysis.

[0059] Specifically, for the chip, its usage scenario is precisely marked as "5G outdoor base station edge computing unit". This marking means that the chip will be directly exposed to the natural environment. The system automatically loads the standard parameter envelope of this scenario: the ambient temperature range is -40℃ to +85℃ (the local temperature inside the chassis is even higher due to direct sunlight). At the same time, the physical constraints unique to this scenario are defined, namely the periodic airflow disturbance caused by the start and stop of the cooling fan, and the strong electromagnetic environment generated by the surrounding high-power radio frequency transmitter.

[0060] In the base station scenario of the chip, the following coupling disturbances were quantified: Transient thermal shock: When the chip was processing burst data traffic, the power consumption of the computing core surged from 10W to 80W within 5ms, resulting in a severe transient thermal shock with a thermal change rate exceeding 100℃ / s; Wideband mechanical vibration: Vibrations generated by the operation of the base station air conditioner outdoor unit and fan were collected, with frequencies concentrated in a wide band from 10Hz to 2kHz, and a resonance peak near the natural frequency of the heat sink; EMI intensity: Transient high voltage pulses generated by antenna switching were detected, with radiation intensity reaching a specific level.

[0061] The above-mentioned disturbance dynamics are transformed into dynamic boundary conditions of the chip finite element model: Thermal load transformation: A step function Pheat(t) is constructed to simulate power consumption jumps and is applied as a volume heat source to the active layer of the chip; at the same time, the convective heat transfer coefficient h(t) is set as a time-varying parameter that varies with the fan speed to simulate airflow disturbances; Mechanical load transformation: The collected broadband vibration PSD spectrum is transformed into a basic random vibration excitation and applied to the bump array at the bottom of the chip package to simulate chip board-level jitter caused by chassis vibration; Electromagnetic load transformation: EMI pulses are transformed into time-domain voltage signals and directly applied to the chip's power input pins and I / O ports to form the boundary load of electromagnetic interference; The identified environmental factors include: "step transient heat flow", "broadband PSD random vibration excitation" and "port pulse electromagnetic interference", which together constitute the "extreme test load" that the chip must withstand under harsh operating conditions.

[0062] Furthermore, based on the detection of each key area, the corresponding functions are determined. According to the matching of multiple environmental factors and the functions of each key area, the corresponding matching relationship is determined. The corresponding multi-dimensional content is determined by tracing along the matching relationship. The multi-dimensional content and the performance level of each key area are deeply integrated, and the corresponding coupling relationship is output. Based on the monitoring of the coupling relationship, multiple response data of the chip are determined. This is compatible with the overall consideration of coupling relationship monitoring and ensures the accuracy of multiple response data of the chip.

[0063] At this point, based on the circuit layout and logic definition, the functions of the key areas are divided as follows: High computing power function: responsible for logic operations, characterized by high power consumption and high heat generation; Signal transmission function: responsible for high-speed I / O, characterized by extreme sensitivity to timing and noise; Power distribution function: responsible for power supply, characterized by high current and sensitivity to electromigration and voltage drop; Structural support function: responsible for mechanical connections, characterized by bearing packaging stress and thermal expansion stress.

[0064] Output parameters describing the strength of multiphysics interactions; for example, thermo-mechanical coupling coefficient (describing the proportion of stress generated by temperature changes) and electromechanical coupling coefficient (describing the proportion of electrical performance changes generated by mechanical deformation); construct the transfer function from environmental input to system output, explicitly indicating how the input disturbance is amplified or attenuated by the system.

[0065] The evolution of the above coupling relationship is monitored in real time in the finite element solver; at each time step, the coupling response is calculated based on the current environmental load; the final dataset for subsequent optimization is output, including: full field data: nodal temperature, displacement, and voltage changing over time; extreme value data: maximum stress point and its location, highest temperature point and its time; failure indices: cumulative fatigue damage degree, Weibull distribution probability, etc.

[0066] Specifically, the chip underwent deep dynamic fusion: Intelligent core area fusion: the transient thermal shock data of S131 was fused with the "C-level (risk level)" performance of S123; analysis revealed that the transient high temperature gradient caused plastic deformation of the silicon substrate, further exacerbating the original thermal stress risk, causing the actual reliability level of this area to be lower than expected during the shock, and to be in an "extremely dangerous" state; SerDes interface area fusion: the broadband vibration data was fused with the "B-level (monitoring level)" performance; calculations showed that vibration at a specific frequency (150Hz) caused resonance of the PCB board, causing the clock jitter in the SerDes area to exceed the preset threshold, causing the signal transmission performance level to briefly drop to the failure edge at a specific moment.

[0067] The key coupling relationships of the chip were output: thermo-mechanical coupling relationship: the output shows that the mismatch of the thermal expansion coefficient of the intelligent core area is the main contradiction. A nonlinear mapping of ΔT→σVonMises was established, indicating that the stress concentration coefficient at the via increases exponentially with each 1℃ increase in temperature. Electromechanical coupling relationship: the transfer function between external vibration acceleration a(t) and SerDes bit error rate (BER) was established, revealing that near the 150Hz frequency, the change in solder joint contact resistance caused by package warping is the root cause of bit errors.

[0068] The chip's response data under complex environments were determined as follows: Thermal response data: The intelligent core region reaches a peak temperature of 128℃ at 5ms, exceeding the junction temperature limit, and the interlayer shear force caused by thermal stress reaches its maximum value at this time; Mechanical response data: Due to vibration, periodic tensile stress with an amplitude of 180MPa was detected at the bump of the SerDes interface region; Electrical performance response data: Under vibration coupling, the common-mode noise voltage of the SerDes differential pair rises to 150mV. These specific response data will directly serve as constraints and optimization objectives for finding the optimal parameter combination in step S14.

[0069] refer to Figure 5 In step S14, the specific steps are as follows: S141: Collect the physical performance of the chip, match multiple response data with the physical performance of the chip; and during the matching process, determine the deviation gradient between multiple response data and the physical performance of the chip, and based on the analysis of the deviation gradient, generate multiple sets of design variables, including linewidth fine-tuning, via redundancy layout, and dielectric layer thickness correction. S142: Input all key design contents into the same finite element space, and dynamically update the element properties and geometric topology in real time in the same finite element space to trigger multiple iterations of each key design contents in order to determine multiple optimized parameters, and determine the best parameter combination based on the multiple optimized parameters. S143: The optimized parameters are mapped to the chip layout through reverse mapping technology, and multiple process items are output. The chip process report is determined based on the project content, corresponding project priority and chip usage scenario of each process item. The chip process report covers detailed modification suggestions, expected performance gains and process risk assessment.

[0070] In the embodiments of this application, the physical performance of the chip is collected, and multiple response data and the physical performance of the chip are matched; during the matching process, the deviation gradient between the multiple response data and the physical performance of the chip is calculated, and multiple sets of design variables are introduced based on the analysis of the deviation gradient. The multiple sets of design variables include linewidth fine-tuning, via redundancy layout, and dielectric layer thickness correction.

[0071] At this point, the system reads the chip's physical design specifications and extracts key hard indicators, including: thermal indicators: maximum junction temperature (Tj,max) and thermal resistance (θJA); mechanical indicators: yield strength (σyield) and fatigue life cycle; electrical indicators: maximum current density (Jmax), allowable voltage drop (IRDroplimit), and electromagnetic compatibility (EMC) standards. The system then compares the multiple response data output by the S132 (such as maximum temperature, peak stress, and noise voltage) with the aforementioned physical performance indicators item by item. Simultaneously, it calculates the difference between the simulated response value and the performance indicator threshold. If the response value exceeds the threshold, a positive deviation (risk) occurs and needs to be suppressed; if the response value is far below the threshold, a negative deviation (redundancy) occurs, indicating that the design is too conservative and can be reduced to optimize cost or area.

[0072] Establish the partial derivative matrix of the deviation with respect to the design variables, analyze the magnitude of the gradient, and identify the parameters most sensitive to the deviation. For example, if the gradient of linewidth variation on temperature deviation is much greater than the gradient of dielectric layer thickness variation on temperature deviation, then linewidth is the dominant factor. Analyze the coupling gradient between different deviations. For example, although increasing the linewidth can reduce thermal deviation (negative gradient), it will increase parasitic capacitance, thereby worsening the electrical signal integrity deviation (positive gradient).

[0073] Based on the gradient analysis results, key design variable categories were identified: linewidth fine-tuning: optimizing the geometry of conductive and heat dissipation channels; simultaneously, optimizing the topology of mechanical connections and current conduction; dielectric layer thickness correction: optimizing the material thickness for insulation withstand voltage and mechanical buffering; considering the coupling between physical fields, instead of adjusting a single variable, multiple sets of combined variables were generated; each set of variables targets a different optimization objective (e.g., "heat dissipation focused group", "reliability focused group", "balanced group"); allowable value ranges were set for each set of variables to ensure that the adjusted layout still conforms to the lithography process rules (DRC).

[0074] Specifically, for the chip, the dynamic response obtained in S132 was strictly matched with the design specifications; thermal matching: the design specifications require that the junction temperature of the chip should not exceed 110℃; S132 shows that the peak temperature of the intelligent core area reaches 128℃ under thermal shock; deviation results: a positive deviation of +18℃ was identified, which poses a serious risk of thermal failure.

[0075] Mechanical matching: The design requires the shear stress at the package interconnect to be less than 150MPa; S132 shows that the stress at the bump in the SerDes region reaches 220MPa; Deviation results: A positive deviation of +70MPa was identified, indicating a risk of solder joint breakage.

[0076] Electrical matching: The power network allows an IRDrop of 5%; simulation shows that the local voltage drop reaches 7.2% under high load; deviation results: a positive deviation of +2.2% was identified, causing a logic timing error.

[0077] A deep analysis of the chip's deviation gradient was conducted to find the most cost-effective optimization path. The calculation results show that the temperature deviation in the intelligent core region has an extremely high gradient with respect to the "metal linewidth." Specifically, for every 1 μm increase in linewidth, the core temperature can decrease by approximately 0.8 °C. Meanwhile, the temperature gradient with respect to the "dielectric layer thickness" is relatively small. The stress deviation in the SerDes region exhibits a significant negative gradient with respect to the "via density." Analysis revealed that for every 10% increase in the number of vias, the local stress concentration factor can decrease by approximately 12%. Further analysis showed that simply increasing the linewidth to improve thermal performance leads to an increase in metal layer density, which in turn exacerbates mechanical stress (the stress gradient increases positively with increasing linewidth). Therefore, a balance must be found among multiple sets of variables.

[0078] Based on gradient analysis, the following sets of design variable schemes were determined for the chip: The first set of variables (thermal-electrical balance type): Linewidth fine adjustment: the top power metal linewidth of the intelligent core area is increased by 2μm on the original basis (using the high thermal gradient to reduce the temperature); Dielectric layer thickness correction: the thickness of the dielectric layer below it is adjusted accordingly to maintain the target impedance value and offset the parasitic capacitance effect caused by the increase in linewidth.

[0079] The second set of variables (mechanical reinforcement type): redundant via layout: "redundant vias" are introduced around the SerDes region and the stress concentration bump array, that is, non-functional conductive vias are added in the filling area that does not affect the circuit function, and they are used to share mechanical stress and current density; layout optimization: the via arrangement is adjusted from "rectangular array" to "staggered hexagonal array" to improve the isotropic stress release capability; the third set of variables (global comprehensive optimization type): the local widening of linewidth (for hot spots) and redundant filling of vias (for stress points) are combined, and the dielectric layer thickness in key areas is finely modified at the nanometer level to obtain the global optimal solution between thermal resistance, stress and capacitance. These design variables will serve as input dimensions in the subsequent iteration process of S14, driving the finite element model to find the optimal solution in the parameter space.

[0080] Furthermore, all key design elements are input into the same finite element space, and the element properties and geometric topology are dynamically updated in real time within the same finite element space to trigger multiple iterations of each key design element to determine multiple optimized parameters. Based on the multiple optimized parameters, the optimal parameter combination is determined, which takes into account the overall consideration of multiple optimized parameters and ensures the accuracy of the optimal parameter combination.

[0081] At this point, a parameterized full-chip finite element master model is established. This model is not a static mesh stacking, but a dynamic space based on geometric constraints and parameter associations. All key design contents (variables determined in S141) are mapped to control parameters in this space.

[0082] When design variables (such as via layout) change, the system automatically triggers mesh reconstruction. For example, when adding redundant vias, the mesh engine automatically generates new nodes and elements at specified locations and modifies the surrounding connections to change the topology. Meanwhile, when design variables (such as linewidth and medium thickness) change, the system does not need to reconstruct the entire mesh. Instead, it modifies the attribute cards of relevant elements in real time through the parametric interface (such as updating the cross-sectional area, principal axis direction of the material, and thickness parameters of the element). After each update, the system's stiffness matrix, mass matrix, and conduction matrix are automatically reassembled to ensure that the calculation model maintains strict consistency with the current parametric design.

[0083] The system's built-in multi-objective optimization methods (such as genetic methods, sequential quadratic programming, or particle swarm optimization) trigger simulation loops; each loop represents a specific set of parameter combinations; in each iteration, the updated finite element model is submitted to the solver for multi-physics coupled calculations (thermal-mechanical-electrical); the obtained response data (such as peak temperature and maximum stress) is fed back to the optimization method in real time; the deviation between the current response and the target performance is calculated; if the deviation does not meet the convergence condition, the next set of improved parameters will be generated according to the optimization strategy (such as gradient descent or random search), and the dynamic update in sub-step S141 will be triggered again, forming a reciprocating oscillating optimization process.

[0084] After the iteration, the system organizes the data from all convergence steps and extracts the final optimized value of each design variable. These values ​​are the values ​​that minimize the objective function (such as weighted total power consumption and total deformation energy) while satisfying all physical constraints. Since chip design often involves conflicting objectives (such as good heat dissipation vs. low stress), the system usually generates a Pareto optimal solution set. In this set, no solution can further optimize a certain indicator without compromising other indicators. Based on the focus of the actual application scenario, the "best parameter combination" is selected from the solution set. For example, if the chip prioritizes long-term reliability, the combination with the lowest stress is selected; if computational performance is prioritized, the combination with the lowest thermal resistance is selected.

[0085] Specifically, for the chip, design variables were loaded and dynamically updated in a unified finite element space; the system received parameter instructions and adjusted the linewidth parameter W of the top metal layer of the intelligent core area from 2.0μm to 2.4μm; the mesh nodes in the finite element space expanded outward accordingly, the cross-sectional area properties of the elements were updated synchronously, and the heat conduction matrix was recalculated, reflecting the improvement in heat dissipation capacity.

[0086] In the SerDes region, the mesh topology changed in real time according to the "add via" command—new grounding via cells were automatically inserted between signal vias and electrical connections were established with the upper and lower metal layers; the system adjusted the thickness parameter Hox of the interlayer dielectric layer, the corresponding solid cells were stretched in the Z-axis direction, and the dielectric constant property was corrected according to the new material fill rate.

[0087] Through multiple iterations, the chip model was continuously tested at the edge of performance limits. The first iteration significantly increased the linewidth to reduce the temperature. The calculation results showed that the thermal performance met the standards, but the excessive metal density caused the mechanical stress to exceed the limit. The second iteration introduced redundant via layout to release stress based on feedback. The calculation results showed that the stress decreased, but the increase of vias introduced additional parasitic capacitance, which affected signal integrity. The third iteration fine-tuned the dielectric layer thickness. While ensuring impedance matching, a thicker dielectric layer was used to alleviate mechanical stress. This process was repeated dozens of times, each time seeking a better balance between temperature, stress, and electrical performance.

[0088] After dozens of iterations, the optimal combination of parameters for the chip was determined; optimized parameter output: power line width in the intelligent core area: 2.35μm (achieving a balance between heat dissipation and area); via redundancy in the SerDes region: increased by 18% (achieving significant stress relief at a minimal area cost); critical dielectric layer thickness: 1.05 × initial thickness (correcting parasitic effects).

[0089] This combination was identified as "superior" because it reduced the maximum temperature in the intelligent core region to 108℃ (better than the target of 110℃), while reducing the mechanical stress in the SerDes region to 145MPa (better than the target of 150MPa), and keeping IRDrop below 4.8%. This set of parameters demonstrates that, in a unified finite element space, complex multiphysics conflict problems that cannot be solved by a single adjustment can be successfully solved through multivariate collaborative iteration.

[0090] Therefore, by using reverse mapping technology, multiple optimized parameters are mapped to the chip layout, and multiple process projects are output. Based on the project content, corresponding project priority, and chip usage scenario of each process project, a chip process report is determined. The chip process report covers detailed modification suggestions, expected performance gains, and process risk assessments. It is compatible with the overall consideration of the project content, corresponding project priority, and chip usage scenario of each process project, ensuring the accuracy of the chip process report. At the same time, response data is controlled, and multiple sets of design variables are fully considered, improving the accuracy of key design content and the accuracy of the optimal parameter combination, thus achieving chip parameter optimization.

[0091] At this point, a bidirectional mapping table is established between finite element mesh nodes and chip layout polygons. After S142 determines the optimized parameters (such as increased linewidth and new vias), the system uses parametric driving technology to reverse-drive the geometric deformation of the primitives in the layout database. For size changes (such as linewidth and layer thickness), the system directly modifies the coordinate data of the corresponding primitives and performs DRC (Design Rule Check) cleanup to ensure that the line spacing meets the minimum manufacturing rule. For topology changes (such as new vias), the system automatically generates a new via array in the layout database and automatically connects the relevant metal layers, while repairing the connectivity breakage caused by the topology change. After the reverse mapping is completed, the system compares the modified layout parameters with the optimization target of S142 to ensure that the error of physical properties (such as resistance and thermal conductivity) during the conversion process is controlled within the allowable range of engineering.

[0092] Analyze the impact of layout changes on the manufacturing process and break it down into specific process steps; this includes changes to the mask or adjustments to the photoresist exposure path; etching / deposition projects: involving changes in aspect ratio and adjustments to material thickness; CMP (chemical mechanical polishing) projects: involving the impact of changes in metal density on flatness; assign an ID to each process project and define its specific execution parameters, such as the increment of etching time and the adjustment amount of deposition rate.

[0093] Specifically, for the chip, the optimal solution of S142 was precisely mapped back to the GDSII layout file; linewidth mapping: the metal linewidth of the intelligent core area determined by S142 is 2.35μm; through reverse mapping, the system automatically expanded the width of the Metal6 layer primitives of the power grid in this area from the original 2.0μm to 2.35μm, and at the same time automatically adjusted the spacing of other traces in the same layer to avoid short circuit risks; at the same time, via layout mapping: based on the optimization results, the system automatically inserted 18% redundant vias in the fill area of ​​the SerDes region. These vias were instantiated as specific Via2 arrays in the layout, and the inter-layer routing network was automatically updated to ensure the integrity of physical connections.

[0094] Based on the inverse mapping results, a specific list of layout modifications is provided, including the modified coordinate layers, size values, and affected module regions; the physical performance improvement after quantification optimization; using the calculation results of S142, key indicators before and after modification (such as junction temperature reduction, MTBF extension factor, and frequency response improvement) are compared; production risks are assessed in conjunction with the usage scenario (such as the high temperature and vibration environment of base stations) and the priority of process projects; special attention is paid to DRC limits, yield loss, and reliability risks introduced by new materials; the report will provide clear recommendations, such as "recommend tape-out" or "further verification required," and indicate risk mitigation measures.

[0095] In response to the chip layout change, the following key process items were output: Item P1 (Metal layer lithography correction): Due to the increase in the linewidth of the smart core area, the metal density of the Metal6 layer has changed significantly; Content: It is necessary to update the mask data of the Metal6 layer and adjust the lithography depth of focus to accommodate the wider lines; Priority: High; because the power grid directly determines the yield.

[0096] Project P2 (Via Filling and CMP Optimization): Due to the addition of a large number of redundant vias, the local copper density has increased; Content: Adjust the polishing parameters of the CMP process to prevent "dish-shaped" defects caused by excessive copper density; At the same time, optimize the Via filling electroplating process to ensure that there are no voids at the bottom of the high aspect ratio vias; Priority: Medium; Involves process stability. Project P3 (Dielectric Layer Deposition Control): Corresponds to fine-tuning of dielectric layer thickness; Content: Precisely control the chemical vapor deposition (CVD) time of interlayer dielectric (ILD) to achieve nanometer-level thickness accuracy; Priority: Medium.

[0097] A detailed chip process optimization report was generated; the following modifications were suggested: The Metal6 linewidth in the intelligent core region (coordinate range) should be uniformly increased by 0.35μm; a DummyVia array with a density of 18% should be inserted in the SerDes region. Expected performance gains: Thermal: Under full load, the chip junction temperature is expected to decrease from 128°C to 108°C (a reduction of 16.4%), fully meeting the specification of junction temperature <110°C; Reliability: Under base station vibration scenarios, the shear stress at the bump is expected to decrease from 220MPa to 145MPa. According to the Coffin-Manson model, fatigue life is expected to increase by more than 3 times; Electrical: IRDrop decreases from 7.2% to 4.8%, eliminating the risk of timing violations. Process risk assessment: Risk points: Increased metal density leads to a higher risk of "copper erosion" in the CMP process, requiring additional metal filler in the Metal5 layer to balance the density; Scenario relevance: Given that the chip is used in outdoor base stations (high-temperature environment), the new linewidth design is beneficial for heat dissipation, but it is necessary to ensure that stress relaxation failure due to metal creep will not occur during high-temperature aging tests; Conclusion: It is recommended to adopt the modified solution and require the foundry to perform CMP process window verification during the MPW (Multi-Project Wafer) stage.

[0098] Please see Figure 6 , Figure 6 This is a schematic diagram of the structural composition of a chip parameter optimization system based on finite element analysis according to an embodiment of the present invention; the chip parameter optimization system based on finite element analysis is applied to the above-mentioned chip parameter optimization method based on finite element analysis; the chip parameter optimization system based on finite element analysis includes: Finite element module 21 is used to acquire the chip layout, determine the corresponding layer information based on the chip layout identification, and construct the chip finite element model based on the layer information, the overall shape of the chip and the corresponding usage scenario. The key region module 22 is used to identify the corresponding key regions based on the identification of the chip's finite element model, mark the corresponding parameter information in each key region, determine the corresponding multimodal data based on each key region and the corresponding parameter information, and determine the performance level of the corresponding key region based on the identification of the multimodal data. The response data module 23 is used to determine multiple environmental factors based on the detection of the chip's usage scenario, and to deeply integrate the multiple environmental factors, the functions of each key area and their corresponding performance levels to output multiple response data of the chip. The parameter optimization module 24 is used to determine multiple sets of design variables based on multiple response data and the physical performance of the chip, determine the corresponding key design contents by finite element analysis along each set of design variables, iterate each key design contents in the same finite element space, determine the optimal parameter combination, and determine the chip process report based on the optimal parameter combination and the matching of the chip layout.

[0099] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A parameter optimization method for a chip based on finite element analysis, characterized in that, include: The chip layout is collected, and the corresponding layer information is determined based on the identification of the chip layout. A finite element model of the chip is constructed based on the layer information, the overall shape of the chip, and the corresponding usage scenario. Based on the identification of the finite element model of the chip, the corresponding key regions are identified, and the corresponding parameter information is marked in each key region. Based on each key region and the corresponding parameter information, the corresponding multimodal data is determined, and the performance level of the corresponding key region is determined based on the identification of the multimodal data. Based on the detection of chip usage scenarios, multiple environmental factors are identified, and the functions and corresponding performance levels of these environmental factors, key areas, and chip performance are deeply integrated to output multiple response data for the chip. Multiple sets of design variables are determined based on multiple response data and the physical properties of the chip. The corresponding key design contents are determined by finite element analysis along each set of design variables. Each key design content is iterated in the same finite element space to determine the optimal parameter combination. The chip process report is determined based on the optimal parameter combination and the matching of the chip layout.

2. The chip parameter optimization method based on finite element analysis according to claim 1, characterized in that, The layout of the acquisition chip is identified, and the corresponding hierarchical information is determined based on the chip layout. A finite element model of the chip is constructed based on this hierarchical information, the overall shape of the chip, and the corresponding usage scenario, including: The system identifies a database of chips and determines the chip layout based on the database traversal. It then performs image segmentation on the chip layout and identifies multiple key layers during the segmentation process. These key layers encompass metal interconnect layers, active layers, and dielectric layers. Within each key layer, the system marks the corresponding layer information, which includes the material properties of the key layer and the corresponding region boundaries.

3. The chip parameter optimization method based on finite element analysis according to claim 2, characterized in that, The chip layout is used to determine the corresponding layer information based on the chip layout identification. A finite element model of the chip is constructed based on this layer information, the overall shape of the chip, and the corresponding usage scenario. The method also includes: The chip's usage scenarios are collected, and multiple usage constraints are determined based on the identification of the chip's usage scenarios. The finite element framework of the chip is determined according to each usage constraint and the information at this level. The finite element model of the chip is determined by fusing multiple factors along the finite element framework and the overall shape of the chip. The finite element model of the chip serves as a digital twin and captures local subtle stress concentrations and electric field distortions.

4. The chip parameter optimization method based on finite element analysis according to claim 1, characterized in that, The chip-based finite element model is used to identify corresponding key regions, and corresponding parameter information is marked in each key region. Multimodal data is determined based on each key region and its corresponding parameter information. The performance level of the corresponding key region is determined based on the identification of this multimodal data, including: The finite element model of the chip is effectively simulated, and multiple distribution features, including thermal field gradient and stress concentration tensor, are included in the simulation. The multiple distribution features and the preset functional modules of the chip are clustered to construct the corresponding key regions. Features are extracted from the key regions, and the current density, mechanical stress and temperature in the key regions are output. Furthermore, the corresponding multi-scale features are analyzed.

5. The chip parameter optimization method based on finite element analysis according to claim 4, characterized in that, The process of identifying key regions based on the chip-based finite element model, marking corresponding parameter information in each key region, determining corresponding multimodal data based on each key region and its corresponding parameter information, and determining the performance level of the corresponding key region based on the identification of this multimodal data, further includes: Multiple parameter combinations are determined by matching current density, mechanical stress, temperature and multi-scale characteristics. Based on the identification of each parameter combination, the corresponding parameter information is determined. Multi-factor synthesis is performed on each key region and the corresponding parameter information, and the corresponding multimodal data is output. Nonlinear mapping training is performed on multimodal data, and deep identification is further performed on multimodal data to determine multiple performance contents of the corresponding key regions. The performance level of the corresponding key regions is determined based on the mapping relationship between multiple performance contents and performance levels.

6. The chip parameter optimization method based on finite element analysis according to claim 1, characterized in that, The detection based on the chip's usage scenario determines multiple environmental factors, and deeply integrates these environmental factors, the functions of each key area, and their corresponding performance levels to output multiple response data for the chip, including: The chip's usage scenarios are labeled, and multiple coupled disturbances in the usage scenarios are detected and quantified. The transient thermal shock, broadband mechanical vibration, and electromagnetic interference intensity are converted into time-varying boundary loads of the chip in real time to determine multiple environmental factors.

7. The chip parameter optimization method based on finite element analysis according to claim 6, characterized in that, The method of detecting multiple environmental factors based on the chip's usage scenario, and deeply integrating these environmental factors, the functions of each key area, and their corresponding performance levels to output multiple response data for the chip, also includes: Based on the detection of each key area, the corresponding functions are determined. The corresponding matching relationship is determined according to the matching of multiple environmental factors and the functions of each key area. The corresponding multi-dimensional content is determined by tracing along the matching relationship. The multi-dimensional content and the performance level of each key area are deeply integrated, and the corresponding coupling relationship is output. The multiple response data of the chip are determined by monitoring the coupling relationship.

8. The chip parameter optimization method based on finite element analysis according to claim 1, characterized in that, The process involves determining multiple sets of design variables based on multiple response data and the chip's physical properties, identifying corresponding key design elements through finite element analysis of each set of design variables, iterating through each key design element in the same finite element space to determine the optimal parameter combination, and then determining the chip's process report based on the optimal parameter combination and its matching with the chip's layout. This includes: The system acquires the chip's physical performance data and matches it with multiple response data points. During the matching process, it analyzes the deviation gradient between the multiple response data points and the chip's physical performance, and then uses this deviation gradient to determine multiple sets of design variables, including linewidth fine-tuning, via redundancy placement, and dielectric layer thickness correction.

9. The chip parameter optimization method based on finite element analysis according to claim 8, characterized in that, The process of determining multiple sets of design variables based on multiple response data and the chip's physical properties, identifying corresponding key design elements through finite element analysis of each set of design variables, iterating through each key design element in the same finite element space to determine the optimal parameter combination, and determining the chip's process report based on the optimal parameter combination and its matching with the chip's layout, also includes: Each key design element is input into the same finite element space, and the element properties and geometric topology are dynamically updated in real time within the same finite element space to trigger multiple iterations of each key design element in order to determine multiple optimized parameters. Based on the multiple optimized parameters, the optimal parameter combination is determined. The optimized parameters are mapped to the chip layout using reverse mapping technology, and multiple process projects are output. The chip process report is determined based on the project content, corresponding project priority and chip usage scenario of each process project. The chip process report covers detailed modification suggestions, expected performance gains and process risk assessment.

10. A parameter optimization system for a chip based on finite element analysis, characterized in that, The parameter optimization system for the chip based on finite element analysis is applied to the parameter optimization method for the chip based on finite element analysis as described in any one of claims 1-9; The parameter optimization system for the chip based on finite element analysis includes: The finite element module is used to acquire the chip layout, determine the corresponding layer information based on the chip layout identification, and construct the chip's finite element model based on the layer information, the chip's overall shape, and the corresponding usage scenario. The key region module is used to identify the corresponding key regions based on the identification of the chip's finite element model, mark the corresponding parameter information in each key region, determine the corresponding multimodal data based on each key region and the corresponding parameter information, and determine the performance level of the corresponding key region based on the identification of the multimodal data. The response data module is used to determine multiple environmental factors based on the chip's usage scenario and to deeply integrate these environmental factors, the functions of each key area, and their corresponding performance levels to output multiple response data for the chip. The parameter optimization module is used to determine multiple sets of design variables based on multiple response data and the physical performance of the chip. It determines the corresponding key design contents by performing finite element analysis along each set of design variables. Each key design content is iterated in the same finite element space to determine the optimal parameter combination. Based on the optimal parameter combination and the matching with the chip layout, the chip process report is determined.

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