Adaptive adjustment system and method for signal quality of display device, display device, storage medium

Abstract

The application relates to the technical field of display devices, and discloses a self-adaptive adjustment system and method for signal quality of a display device, the display device and a storage medium; the self-adaptive adjustment system comprises a mainboard system controller, a screen end system controller and an information transmission and feedback channel; the mainboard system controller is configured to output a high-speed differential signal and has the ability to adjust the output parameters of the high-speed differential signal; the screen end system controller is configured to receive the high-speed differential signal, sample and analyze the received high-speed differential signal, and obtain a signal quality detection result representing the quality of the high-speed differential signal; the information transmission and feedback channel is arranged between the mainboard system controller and the screen end system controller and is used for transmitting the signal quality detection result generated by the screen end system controller; and the mainboard system controller is further configured to adjust the output parameters of the high-speed differential signal according to the received signal quality detection result. The accuracy of signal quality evaluation can be improved.

Description

Technical Field

[0001] This application relates to the field of display device technology, such as an adaptive adjustment system and method for display device signal quality, a display device, and a storage medium. Background Technology

[0002] With the development of display technology, the resolution and refresh rate of display devices such as televisions and monitors are constantly improving. Video data transmission between the motherboard and the display screen is increasingly adopting high-speed differential signal interface forms such as LVDS, V-by-One, and P2P. High-speed differential signals are easily affected by factors such as impedance mismatch of transmission lines, differences in cable length, connector discontinuities, and deviations in component manufacturing processes during transmission. This can lead to problems such as signal attenuation, increased jitter, overshoot, or undershoot, which in turn affect the stability and display quality of the displayed image.

[0003] In existing technologies, to ensure that the high-speed differential signal output by the motherboard meets the display's reception requirements, signal quality testing and adjustment are typically required. A common approach is to sample the high-speed differential signal on the display side using testing equipment such as an oscilloscope during the R&D or production phase, generate an eye diagram, and determine signal quality based on whether the eye diagram meets preset template requirements. When signal quality is detected as unsatisfactory, engineers usually need to manually adjust the motherboard's output parameters, such as pre-emphasis parameters or output swing parameters, to improve signal transmission quality.

[0004] In the process of realizing this invention, at least the following problems were found in the prior art: The aforementioned methods based on external testing equipment and manual debugging have shortcomings. The signal quality debugging process relies on human experience and usually requires repeated "test-adjust-retest" operations, resulting in low debugging efficiency and difficulty in meeting the consistency and automation requirements of large-scale production processes.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides an adaptive adjustment system and method for signal quality of a display device, a display device, and a storage medium to improve the accuracy of signal quality assessment and reduce reliance on manual adjustments.

[0008] In some embodiments, the adaptive adjustment system for display device signal quality includes: a motherboard system controller, disposed on the motherboard, configured to output a high-speed differential signal and capable of adjusting the output parameters of the high-speed differential signal; a screen-end system controller, disposed on the screen end, configured to receive the high-speed differential signal and sample and analyze the received high-speed differential signal to obtain a signal quality detection result characterizing the quality of the high-speed differential signal; and an information transmission and feedback channel, disposed between the motherboard system controller and the screen-end system controller, for transmitting the signal quality detection result generated by the screen-end system controller; wherein, the motherboard system controller is further configured to adjust the output parameters of the high-speed differential signal according to the received signal quality detection result.

[0009] In some embodiments, the adaptive adjustment method for display device signal quality is applied to the aforementioned adaptive adjustment system for display device signal quality; the adaptive adjustment method includes: a motherboard system controller outputting a high-speed differential signal; a screen-end system controller receiving the high-speed differential signal and sampling and analyzing the received high-speed differential signal to obtain a signal quality detection result characterizing the quality of the high-speed differential signal; an information transmission and feedback channel transmitting the signal quality detection result to the motherboard system controller; and the motherboard system controller adjusting the output parameters of the high-speed differential signal according to the received signal quality detection result.

[0010] In some embodiments, the display device includes a motherboard and a screen; it also includes an adaptive adjustment system for display device signal quality as described above, the adaptive adjustment system for display device signal quality being used to adjust the signal transmission quality between the motherboard and the screen.

[0011] In some embodiments, the storage medium is used to store program instructions, which, when executed, perform the adaptive adjustment method for display device signal quality as described above.

[0012] The adaptive adjustment system and method for display device signal quality, the display device, and the storage medium provided in this disclosure can achieve the following technical effects: In this invention, the screen-end system controller is responsible for signal quality detection, while the motherboard system controller is responsible for output parameter adjustment. The two controllers form a closed-loop collaborative mechanism through information transmission and feedback channels, enabling the output state of the high-speed differential signal to be dynamically updated based on the detection results from the screen side. This improves the targeting and effectiveness of signal quality adjustment. The output parameter adjustment of the motherboard system controller is based on the signal quality detection results fed back by the screen-end system controller, and does not rely on fixed parameter configurations. This solution can adaptively adjust to signal quality differences under different screen models and transmission channel conditions, which helps improve the system's versatility and adaptability, enhances the accuracy of signal quality assessment, and reduces reliance on manual debugging.

[0013] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of an adaptive adjustment system for the signal quality of a display device provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another adaptive adjustment system for display screen signal quality provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating an adaptive adjustment method for the signal quality of a display device provided in an embodiment of this disclosure; Figure 4 This is a flowchart illustrating another adaptive adjustment method for display device signal quality provided in an embodiment of this disclosure; Figure 5 This is the Mask template image used in the embodiments of this disclosure; Figure 6 This is a qualified eye diagram under ideal conditions; Figure 7 These are unqualified eye diagrams that require additional pre-emphasis parameter values; Figure 8 This is an unqualified eye diagram that requires an increase in the output swing parameter value; Figure 9 It is an unqualified eye diagram that needs to be adjusted and the pre-emphasis and output swing amplitude parameter values ​​increased simultaneously; Figure 10 It is an unqualified eye diagram that needs to be adjusted simultaneously to reduce the pre-emphasis and output swing parameter values. Detailed Implementation

[0015] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0016] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0017] Unless otherwise stated, the term "multiple" means two or more.

[0018] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0019] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0020] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0021] In the field of high-speed differential signal transmission technology between the motherboard and the display screen of a display device, those skilled in the art typically rely on external testing equipment to test the signal when solving signal quality detection and debugging problems. For example, during the research and development or production of display devices, high-speed differential signals are often sampled on the display screen side using an oscilloscope to generate an eye diagram, and then the signal quality is judged based on whether the eye diagram meets the preset template requirements. Those skilled in the art generally believe that the eye diagram is a direct means of reflecting the quality of high-speed differential signal transmission, and only by using professional instruments such as high-bandwidth oscilloscopes to test the signal can an accurate judgment of signal quality be made. Therefore, for a long time, related technical solutions and engineering practices have largely revolved around external testing equipment and manual debugging processes.

[0022] However, the inventors discovered limitations in the aforementioned technical understanding during their research. While eye diagrams generated by oscilloscopes can reflect signal transmission quality to some extent, external testing equipment and probes often introduce additional loads and noise interference when connected to high-speed differential signals, causing test results to deviate from the actual signal state received by the display screen. Furthermore, different oscilloscope models, probe configurations, and operating methods by different testers can all lead to variations in eye diagram results, making it difficult to guarantee the repeatability and consistency of signal quality assessments. During production and debugging, relying solely on external testing equipment and human experience makes it difficult to simultaneously ensure the accuracy of test results, debugging efficiency, and consistency requirements in large-scale application scenarios.

[0023] Based on the above understanding, the inventors have broken through the technical inertia of "relying on external testing equipment for signal quality judgment" in existing technologies, and proposed a technical approach that detects signal quality based on the actual received signal state on the display side, and adaptively adjusts the signal output parameters on the motherboard side accordingly. The inventors recognize that the display side's reception status of high-speed differential signals can truly reflect the signal quality at the end of the transmission channel, while the motherboard side's signal output parameters directly determine the amplitude and spectral characteristics of the signal during transmission. If the signal quality detection results from the display side can be fed back to the motherboard side, and the output parameters can be adjusted based on these results, effective optimization of signal quality can be achieved without relying on external testing equipment.

[0024] Based on the above technical concept, this application constructs an adaptive adjustment mechanism combining signal quality detection and parameter adjustment within the display device. Specifically, by sampling and analyzing the high-speed differential signal at the display screen side, a detection result characterizing the signal quality is obtained, and this detection result is fed back to the motherboard system controller. The motherboard system controller then adjusts the output parameters of the high-speed differential signal according to the detection result, thereby gradually bringing the signal quality closer to meeting preset requirements. Through experiments and engineering verification, the inventors have found that this method can complete signal quality detection and optimization within the display device without relying on external testing equipment such as oscilloscopes, effectively reducing reliance on manual debugging and improving the automation and consistency of the debugging process.

[0025] It should be noted that during the actual transmission of high-speed differential signals, signal quality is affected by a combination of factors, including transmission channel characteristics, connector manufacturing process variations, and component parameter variability. A single static parameter configuration is insufficient to adapt to the signal quality differences under different display screens and channel conditions. By adaptively adjusting the motherboard output parameters based on the display screen's test results, the signal transmission process can be dynamically optimized from the signal reception results. This more accurately reflects and improves the signal quality status of the display device during actual operation, rather than relying solely on a fixed test condition or a single parameter setting.

[0026] Figure 1 This is a schematic diagram of an adaptive adjustment system for the signal quality of a display device provided in an embodiment of this disclosure.

[0027] This embodiment provides an adaptive adjustment system for display screen signal quality. This system is applied in a display device to perform quality detection and parameter adjustment of the high-speed differential signal transmitted between the motherboard and the display screen. For example... Figure 1 As shown, the adaptive adjustment system includes: A motherboard system controller (SOC1) is located on the motherboard 100. The motherboard system controller (SOC1) is configured to output a high-speed differential signal and has the ability to adjust the output parameters of the high-speed differential signal. The screen-end system controller SOC2 is located at the screen end 200. The screen-end system controller SOC2 is configured to receive high-speed differential signals and sample and analyze the received high-speed differential signals to obtain signal quality detection results that characterize the quality of the high-speed differential signals. The information transmission and feedback channel 300 is located between the motherboard system controller SOC1 and the screen terminal system controller SOC2 and is used to transmit information. The motherboard system controller is further configured to adjust the output parameters of the high-speed differential signal based on the received signal quality detection results.

[0028] The motherboard system controller (SOC1) is located on the motherboard 100 of the display device and is configured to output a high-speed differential signal to transmit video data or related control data to the display screen. The motherboard system controller (SOC1) also has the ability to adjust the output parameters of the high-speed differential signal, which affect the transmission characteristics of the high-speed differential signal to improve the signal quality during transmission.

[0029] The screen-end system controller SOC2 is located on the display screen side 200 and is configured to receive high-speed differential signals from the motherboard system controller, and to sample and analyze the received high-speed differential signals. Through sampling and analysis of the high-speed differential signals, the screen-end system controller SOC2 can obtain signal quality detection results characterizing the actual reception state of the high-speed differential signals on the display screen side. These signal quality detection results reflect the quality status of the high-speed differential signals on the display screen side, providing a basis for subsequent parameter adjustments.

[0030] The information transmission and feedback channel 300 is located between the motherboard system controller and the screen-end system controller for transmitting information, such as transmitting the signal quality detection results generated by the screen-end system controller SO2 to the motherboard system controller SOC1. Through this information transmission and feedback channel 300, the signal quality detection results obtained by the screen-end system controller SOC2 can be fed back to the motherboard side, enabling the motherboard system controller SOC1 to make control decisions based on the actual received signal status on the display screen side.

[0031] During system operation, the motherboard system controller SOC1 first outputs a high-speed differential signal to the display screen. The screen-side system controller SOC2 samples and analyzes the received high-speed differential signal, generates corresponding signal quality detection results, and feeds these results back to the motherboard system controller SOC1 via an information transmission and feedback channel. After receiving the signal quality detection results, the motherboard system controller SOC1 adjusts the output parameters of the high-speed differential signal based on these results, thereby enabling the output characteristics of the high-speed differential signal to dynamically change with the signal quality status on the display screen.

[0032] Through the aforementioned structure and operating method, the adaptive adjustment system of this embodiment can detect signal quality based on the actual high-speed differential signal state received at the display screen side, and adjust the output parameters at the motherboard side accordingly. This creates an adaptive optimization mechanism within the display device that combines signal quality detection and parameter adjustment. This method achieves effective evaluation and optimization of high-speed differential signal quality without relying on external testing equipment, reducing reliance on manual debugging and improving the stability and adaptability of the display device under different display screen models and transmission conditions.

[0033] Optionally, the screen-end system controller SOC2 includes: The sampling module is configured to sample the high-speed differential signal; The signal quality monitoring module is configured to analyze the sampling results and generate the signal quality detection results.

[0034] Here, the screen-end system controller SOC2 specifically includes a sampling module and a signal quality monitoring module, which work together to complete the signal quality detection of the high-speed differential signal.

[0035] The sampling module is configured to sample the high-speed differential signal output from the motherboard system controller SOC1 and transmitted to the display screen. During actual operation, the sampling module performs multi-point sampling of the high-speed differential signal according to a preset sampling sequence to obtain sampling data reflecting the high-speed differential signal at different time positions and voltage states. By sampling the high-speed differential signal, the sampling module can provide basic data for subsequent signal quality analysis.

[0036] The signal quality monitoring module is configured to analyze and process the sampling results output by the sampling module. Specifically, the signal quality monitoring module evaluates the quality status of the high-speed differential signal based on the distribution relationship of the sampling points in the time and voltage dimensions, and generates corresponding signal quality detection results. These signal quality detection results characterize the actual reception quality of the high-speed differential signal on the display screen side, such as whether there is abnormal distortion or the quality does not meet preset requirements.

[0037] In this embodiment, the signal quality detection results generated by the signal quality monitoring module are sent to the motherboard system controller via the information transmission and feedback channel. This allows the motherboard system controller SOC1 to adjust the output parameters of the high-speed differential signal based on the actual signal quality status on the display side. Through this method, the screen-side system controller SOC2 can complete the detection of high-speed differential signal quality without relying on external testing equipment, and provide reliable feedback for adaptive adjustments on the motherboard side.

[0038] Furthermore, the signal quality monitoring module is configured as follows: Based on the distribution relationship of sampling points in the time and voltage dimensions, signal quality characterization data is generated. The signal quality characterization data is then compared with a preset quality criterion to obtain a signal quality detection result indicating whether a sampling point falls into a restricted area.

[0039] Here, the signal quality monitoring module is configured to perform more detailed analysis and processing of the quality status of the high-speed differential signal based on the sampling point data output by the sampling module.

[0040] Specifically, the signal quality monitoring module organizes and maps the sampling points according to their distribution in the time and voltage dimensions to generate signal quality characterization data that represents the quality status of the high-speed differential signal. This signal quality characterization data reflects the distribution of sampling points along the time and voltage axes, thus describing the overall quality characteristics of the high-speed differential signal on the display screen.

[0041] After generating the signal quality characterization data, the signal quality monitoring module further compares the signal quality characterization data with a preset quality criterion. The quality criterion is used to limit the allowable signal range of the high-speed differential signal under normal operating conditions. When the distribution of sampling points meets the quality criterion, it indicates that the quality of the high-speed differential signal is within an acceptable range; when there are sampling points falling into the prohibited area defined by the quality criterion, it indicates that the quality of the high-speed differential signal is abnormal.

[0042] Based on the above comparison results, the signal quality monitoring module generates signal quality detection results to characterize whether any sampling points fall into the restricted area. These signal quality detection results reflect whether the high-speed differential signal meets the preset signal quality requirements on the display side, and serve as the basis for subsequent qualification judgment and output parameter adjustment by the motherboard system controller.

[0043] In this embodiment, the signal quality monitoring module can effectively detect the quality status of high-speed differential signals on the display screen side, providing a reliable data foundation for the overall adaptive adjustment process of the system without relying on external testing equipment or manual intervention.

[0044] For example, in this embodiment, the quality criterion is defined using template constraints to limit the allowable signal distribution range of the high-speed differential signal under normal operating conditions. The template constraints are pre-stored in the screen-end system controller and used to determine the distribution of sampling points during signal quality detection.

[0045] Specifically, the template constraint jointly defines the effective region of the high-speed differential signal in both the time and voltage dimensions, sets the range of allowed sampling point distribution within the effective region, and defines a no-entry region outside the effective region. The no-entry region is used to characterize the sampling point distribution location that may occur when the high-speed differential signal experiences abnormalities such as severe jitter, attenuation, overshoot, or undershoot.

[0046] During signal quality detection, the signal quality monitoring module compares the generated signal quality characterization data with the template constraints. When all sampling points are distributed within the effective area defined by the template constraints, it indicates that the quality of the high-speed differential signal is within the expected range; when any sampling point falls into the prohibited area, it indicates that the quality of the high-speed differential signal is abnormal.

[0047] In this preferred embodiment, the restricted area can be divided into multiple sub-regions based on the different offset directions of the high-speed differential signal in the time and voltage dimensions. Different sub-regions correspond to different types of signal quality anomalies. By statistically analyzing or identifying the cases where sampling points fall into the restricted area, the signal quality monitoring module can generate signal quality detection results containing anomaly location information for subsequent parameter adjustment decisions.

[0048] It should be noted that the quality criterion is not limited to the template constraint method described above. In other embodiments, the quality criterion can also employ other judgment rules that can limit the normal distribution range of high-speed differential signals, such as judgment methods based on statistical characteristics, threshold ranges, or combinations of rules. As long as the quality state of the high-speed differential signal can be distinguished according to the distribution of sampling points in the time and voltage dimensions, it can be used as an optional implementation method of the quality criterion in this embodiment.

[0049] Optionally, the motherboard system controller SCO1 includes: The pass / fail determination module is configured to determine whether the high-speed differential signal meets the preset signal quality requirements based on the signal quality detection results fed back by the screen terminal system controller. The parameter adjustment module is configured to adjust the output parameters of the high-speed differential signal according to the signal quality detection result when the high-speed differential signal does not meet the signal quality requirements.

[0050] In this embodiment, the motherboard system controller SOC1 specifically includes a qualification judgment module and a parameter adjustment module, which work together to complete the judgment and adjustment of the output parameters of the high-speed differential signal.

[0051] The pass / fail determination module is configured to receive signal quality detection results fed back by the screen-end system controller, and determine whether the current high-speed differential signal meets preset signal quality requirements based on the signal quality detection results. Specifically, the pass / fail determination module determines whether any sampling points fall into the prohibited area defined by the quality criterion based on the sampling point distribution represented in the signal quality detection results; when the signal quality detection results show that no sampling points fall into the prohibited area, the pass / fail determination module determines that the high-speed differential signal meets the preset signal quality requirements; when the signal quality detection results show that some sampling points fall into the prohibited area, the high-speed differential signal does not meet the signal quality requirements.

[0052] The parameter adjustment module is configured to adjust the output parameters of the high-speed differential signal based on the signal quality detection result when the pass / fail judgment module determines that the high-speed differential signal does not meet the preset signal quality requirements. The output parameters are used to influence the transmission characteristics of the high-speed differential signal to improve its quality performance during transmission between the motherboard and the display screen. By adjusting the output parameters, the parameter adjustment module can change the output state of the high-speed differential signal, gradually bringing it closer to meeting the signal quality requirements.

[0053] In this embodiment, the pass / fail judgment module and the parameter adjustment module work together to enable the motherboard system controller SOC1 to make targeted adjustments to the output parameters of the high-speed differential signal based on the signal quality detection results fed back from the display screen side. This forms a closed-loop working mechanism that combines signal quality detection and parameter adjustment with the screen-end system controller. Through this method, the motherboard system controller does not need to directly participate in signal quality sampling and analysis; it can optimize the output state of the high-speed differential signal based on the detection results fed back from the screen-end system controller.

[0054] Furthermore, the parameter adjustment module is configured to determine the corresponding output parameter adjustment strategy based on the restricted area location information contained in the signal quality detection result.

[0055] The output parameters include pre-weighting parameters and / or output swing parameters.

[0056] Here, the parameter adjustment module is configured to determine the corresponding output parameter adjustment strategy based on the restricted area location information contained in the signal quality detection results. Specifically, the signal quality detection results not only indicate whether a sampling point falls into a restricted area, but also reflect the specific location or type of the restricted area where the sampling point falls. Based on the restricted area location information, the parameter adjustment module determines the main types of signal quality anomalies that exist during the transmission of the high-speed differential signal, and then selects an output parameter adjustment strategy that matches the type of anomaly.

[0057] In this embodiment, the output parameters include pre-emphasis parameters and / or output swing parameters. The pre-emphasis parameters are used to adjust the spectral characteristics of the high-speed differential signal at the transmitting end to compensate for the attenuation of high-frequency components caused by the transmission channel; the output swing parameters are used to adjust the output amplitude of the high-speed differential signal to improve the signal-to-noise ratio and edge characteristics during transmission. When the signal quality anomaly represented by the restricted area location information is mainly related to high-frequency attenuation, the parameter adjustment module prioritizes compensating for the high-speed differential signal by adjusting the pre-emphasis parameters; when the signal quality anomaly represented by the restricted area location information is mainly related to insufficient amplitude or excessive amplitude, the parameter adjustment module optimizes the high-speed differential signal by adjusting the output swing parameters; in some cases, the parameter adjustment module can also combine the restricted area location information to adjust both the pre-emphasis parameters and the output swing parameters simultaneously.

[0058] In this way, the parameter adjustment module can make targeted adjustments to the output parameters of the high-speed differential signal based on the restricted area position information fed back by the screen-end system controller. This makes the parameter adjustment process no longer dependent on fixed rules or human experience, but matches the specific manifestation of signal quality anomalies, thereby improving the efficiency and effectiveness of the adaptive adjustment process.

[0059] For example, when generating signal quality detection results, the signal quality monitoring module further divides the restricted area defined by the quality criteria into multiple sub-regions. Different sub-regions are used to characterize different abnormal directions of the high-speed differential signal in the time and voltage dimensions. The signal quality detection results carry the sub-region identifiers where the sampling points fall, which are fed back to the mainboard system controller as restricted area location information.

[0060] Here, the restricted area can be divided into multiple sub-regions in terms of time and voltage dimensions, such as a first restricted area, a second restricted area, a third restricted area, and a fourth restricted area, wherein: The first restricted area is used to characterize the situation where the sampling point mainly falls into the region with a low voltage dimension; The second restricted area is used to characterize the situation where the sampling point mainly falls into the region with a relatively high voltage dimension; The third restricted area is used to characterize the situation where the sampling point mainly falls into the region where the time dimension is ahead or behind. The fourth forbidden zone is used to characterize the situation where the sampling point has anomalies in both the time and voltage dimensions.

[0061] After receiving the signal quality detection result containing restricted area location information, the parameter adjustment module of the motherboard system controller determines the corresponding output parameter adjustment strategy based on the restricted area location information.

[0062] Specifically, when the sampling points representing the restricted area location information mainly fall within the first restricted area, the parameter adjustment module preferentially determines that the effective amplitude of the high-speed differential signal is too low, and prioritizes an adjustment strategy that increases the output swing parameter to improve the effective received amplitude of the signal on the display screen side; when the sampling points representing the restricted area location information mainly fall within the second restricted area, the parameter adjustment module preferentially determines that the amplitude of the high-speed differential signal is too high or there is a risk of overshoot, and adopts an adjustment strategy that reduces the output swing parameter.

[0063] When the sampling points representing the restricted area location information mainly fall into the third restricted area, the parameter adjustment module preferentially determines that the high-speed differential signal has problems such as increased jitter or insufficient high-frequency component compensation during transmission, and prioritizes the adjustment strategy of adjusting the pre-emphasis parameters to improve the edge characteristics and high-frequency compensation effect of the high-speed differential signal.

[0064] When the sampling points representing the restricted area location information mainly fall within the fourth restricted area, the parameter adjustment module can adopt a combined adjustment strategy. For example, it can first adjust the output swing parameter to bring the signal amplitude into a reasonable range, and then adjust the pre-emphasis parameter to improve the signal edge characteristics; or it can first adjust the pre-emphasis parameter to reduce jitter, and then fine-tune the output swing parameter. The order of combined adjustments can be determined according to the proportion of different anomalies in the restricted area location information.

[0065] After each adjustment of the output parameters, the parameter adjustment module controls the motherboard system controller to re-output the high-speed differential signal and waits for feedback from the screen-end system controller regarding the new signal quality detection results. When the new signal quality detection result is better than the previous one, the parameter adjustment module continues to adjust in the current direction or maintains the current parameter configuration; when the new signal quality detection result does not improve or deteriorates, the parameter adjustment module reverts to the previous parameter configuration and selects another adjustment strategy to avoid ineffective or over-adjustment.

[0066] Through the above-described implementation of multiple restricted area division and corresponding adjustment strategies, the parameter adjustment module can establish a clear mapping relationship between the restricted area position information fed back by the screen-end system controller and the output parameter adjustment action, so that the adaptive adjustment process has a clear decision basis and adjustment sequence, thereby improving the efficiency and stability of high-speed differential signal quality optimization.

[0067] Optionally, the screen-end system controller is also configured to perform the signal quality detection before... Based on the training signal sent by the motherboard system controller, the high-speed differential signal is synchronously processed to establish a sampling reference for signal quality detection.

[0068] Here, the screen-end system controller is also configured to synchronously process the high-speed differential signal based on the training signal sent by the motherboard system controller before performing the signal quality detection, so as to establish a sampling reference for signal quality detection.

[0069] Specifically, at the beginning of the adaptive adjustment process, the motherboard system controller sends a training signal of a predetermined format to the screen-end system controller. This training signal assists the screen-end system controller in performing timing alignment and signal synchronization. Upon receiving the training signal, the screen-end system controller performs synchronization processing on the high-speed differential signal to determine the sampling timing reference and sampling standard for the high-speed differential signal.

[0070] During the synchronization process, the screen-end system controller performs clock recovery and data alignment on the received signal based on the characteristic information of the training signal to establish a stable sampling timing relationship. Through the above synchronization process, the screen-end system controller can determine the reference position for sampling in the time dimension, thereby providing a reliable timing basis for subsequent sampling and analysis of high-speed differential signals.

[0071] After establishing the sampling reference, the screen-end system controller samples the subsequently received high-speed differential signals based on the established sampling reference and performs a signal quality detection process. By introducing synchronization processing and sampling reference establishment before signal quality detection, detection deviations caused by unstable sampling timing or alignment errors can be effectively reduced, improving the accuracy and consistency of signal quality detection results.

[0072] In this way, the screen-end system controller in this embodiment can complete the necessary synchronization preparations before performing signal quality detection, so that the signal quality detection process is based on a stable sampling reference, which helps to improve the reliability and convergence of the adaptive adjustment process.

[0073] Furthermore, the motherboard system controller is configured to send a training bitstream before the adaptive adjustment begins; The screen-end system controller is configured to perform clock recovery and / or data alignment based on the training bitstream to determine the sampling timing reference of the high-speed differential signal.

[0074] Here, the motherboard system controller is configured to send a training bitstream to the screen-end system controller before the adaptive adjustment process begins. The training bitstream is a data sequence in a predetermined format, used to assist the screen-end system controller in completing the synchronization establishment process of the high-speed differential signal. By sending the training bitstream before the adaptive adjustment begins, the screen-end system controller can obtain stable and predictable signal characteristics before formally performing signal quality detection.

[0075] After receiving the training bitstream, the screen-end system controller performs clock recovery and / or data alignment operations on the high-speed differential signal based on the training bitstream to determine the sampling timing reference of the high-speed differential signal. Specifically, the screen-end system controller performs clock synchronization on the received signal according to the timing characteristics in the training bitstream and performs alignment processing on the received data, thereby establishing a reference position for subsequent sampling in the time dimension.

[0076] After completing the clock recovery and / or data alignment, the screen-end system controller applies the determined sampling timing reference to the subsequent high-speed differential signal sampling and analysis process, enabling the signal quality detection process to be performed under stable timing conditions. This method effectively reduces the detection uncertainty introduced by sampling timing offsets or alignment errors, improving the accuracy and consistency of signal quality detection results.

[0077] By introducing a training bitstream before the adaptive adjustment begins and performing clock recovery and / or data alignment based on the training bitstream, this embodiment can establish a reliable sampling timing reference before signal quality detection, providing a stable foundation for subsequent signal quality detection and output parameter adjustment, thereby improving the overall reliability of the adaptive adjustment process.

[0078] Figure 2 This is a schematic diagram of another adaptive adjustment system for display screen signal quality provided in an embodiment of this disclosure.

[0079] like Figure 2 As shown, this adaptive adjustment system for display screen signal quality is applied in a display device to achieve signal quality detection and adaptive adjustment of output parameters for high-speed differential signals between the motherboard 100 and the screen terminal 200. The system generally adopts a distributed architecture of screen terminal detection, motherboard judgment, and parameter adjustment, including a motherboard system controller SOC1 on the motherboard 100 side, a screen terminal system controller SOC2 on the screen terminal 200 side, and an information transmission and feedback channel 300 located between the two.

[0080] In this embodiment, the motherboard 100 includes a motherboard system controller (SOC1), which is mounted on the motherboard and connected to a high-speed differential signal transmission link. The motherboard system controller (SOC1) is configured to output a high-speed differential signal and has the ability to adjust the output parameters of the high-speed differential signal.

[0081] Furthermore, the motherboard-side hardware platform may also include the following components: The motherboard DDR4 memory is connected to the motherboard system controller SOC1 and is used to store the programs, parameter configuration data, training bitstream data and / or display data cache required for the operation of the motherboard system controller SOC1.

[0082] The motherboard eMMC memory, connected to the motherboard system controller SOC1, is used to store system firmware, boot programs, configuration files, and optional adaptive adjustment strategy parameter tables, etc.

[0083] The power management module (PMIC) is configured to provide multiple power supplies to the motherboard system controller (SOC1), motherboard DDR4 memory, motherboard eMMC memory, and high-speed differential transmission links.

[0084] A clock source module, including, for example, a crystal oscillator and / or a clock generator, is used to provide a reference clock for the motherboard system controller SOC1 and the high-speed differential transmission link.

[0085] The high-speed differential signal transmission module Tx PHY is connected to the motherboard system controller SOC1 and is used to convert the data signal output by the motherboard system controller SOC1 into a high-speed differential signal and send it to the screen side; the Tx PHY can be an internal module or an external module of SOC1.

[0086] A parameter configuration register or configuration interface is used to configure the output parameters of a high-speed differential signal, wherein the output parameters include pre-emphasis parameters and / or output swing parameters.

[0087] In this embodiment, the motherboard system controller SOC1 is also configured to send a training bitstream before the adaptive adjustment begins, and after receiving the signal quality detection result from the screen system controller SOC2, the qualification judgment module determines whether the high-speed differential signal meets the preset signal quality requirements; if it does not meet the requirements, the parameter adjustment module adjusts the output parameters of the high-speed differential signal.

[0088] The screen-end side includes a screen-end system controller (SOC2), which is located on the display screen side and connected to a high-speed differential signal receiving link. The screen-end system controller (SOC2) is configured to receive high-speed differential signals and sample and analyze the received high-speed differential signals to obtain signal quality detection results characterizing the quality of the high-speed differential signals.

[0089] In a preferred embodiment, the screen-side hardware platform may further include the following components: The on-screen DDR4 memory is connected to the on-screen system controller SOC2 and is used to cache sampled data, signal quality characterization data (such as eye diagram data), quality criterion template data, and the running program of the on-screen system controller SOC2.

[0090] The screen-side eMMC memory, connected to the screen-side system controller SOC2, is used to store screen-side firmware, boot program, quality criterion template, preset coordinate system parameters and / or optional training parameters, etc.

[0091] The power management module (PMIC) is configured to provide multiple power supply voltages for the system controller (SOC2), the DDR4 memory, the eMMC memory, and the high-speed differential receiver link.

[0092] A clock source module, including, for example, a crystal oscillator and / or a clock generator, is used to provide a reference clock for the screen-end system controller SOC2 and the high-speed differential receiver link.

[0093] The high-speed differential signal receiving module Rx PHY is connected to the screen-end system controller SOC2 and is used to receive high-speed differential signals and output data streams for subsequent processing; the Rx PHY can be an internal module of SOC2 or an external module.

[0094] The Clock Recovery Module (CDR) is used to perform clock recovery based on the training bitstream to determine the sampling timing reference of the high-speed differential signal; the CDR can be an internal functional module of the screen-end system controller SOC2 or integrated by Rx PHY.

[0095] The data alignment module is used to perform data alignment based on the training bitstream to determine the sampling reference of the high-speed differential signal; the data alignment module can be implemented internally by the screen-end system controller SOC2.

[0096] A FIFO buffer structure is used to buffer the sampling data obtained from sampling high-speed differential signals and output the sampling data in sequence; the FIFO buffer structure can be implemented as a component of the sampling module.

[0097] The template storage module is used to store template constraints corresponding to quality criteria, such as Mask templates, and forbidden area definition information; the template storage module can be implemented by screen-side DDR4 memory, screen-side eMMC memory, or SOC2 internal storage resources.

[0098] Furthermore, in this embodiment, the screen-end system controller SOC2 includes a sampling module and a signal quality monitoring module. Wherein: The sampling module is configured to sample the high-speed differential signal based on the sampling timing reference and write the sampled data into the FIFO buffer structure; The signal quality monitoring module is configured to read the sampling data output by the FIFO buffer structure and map the sampling points sequentially to the pre-trained coordinate system to gradually form signal quality characterization data; and during the formation of signal quality characterization data, it continuously judges whether there are sampling points falling into the forbidden area of ​​the Mask template to generate signal quality detection results.

[0099] An information transmission and feedback channel 300 is provided between the motherboard system controller SOC1 and the screen terminal system controller SOC2 to transmit the signal quality detection results generated by the screen terminal system controller SOC2.

[0100] In a preferred embodiment, the information transmission and feedback channel 300 is implemented using the SPI protocol. The screen-end system controller SOC2 feeds back the signal quality detection results to the motherboard system controller SOC1 in a timely manner via SPI. The signal quality detection results may include a determination of whether a sampling point falls into a restricted area, and may optionally include restricted area location information or falling statistics, for use by the parameter adjustment module of the motherboard system controller SOC1 to determine the output parameter adjustment strategy.

[0101] To improve the accuracy and consistency of signal quality detection, the system also includes a pre-training and synchronization mechanism. Specifically, the motherboard system controller SOC1 sends a training bitstream before adaptive adjustment begins; the screen-end system controller SOC2 performs clock recovery and / or data alignment based on the training bitstream to determine the sampling timing reference for the high-speed differential signal.

[0102] In a preferred embodiment, after establishing the sampling timing reference, the screen-end system controller SOC2 further establishes a coordinate system reference for signal quality detection, enabling subsequent sampling points to be mapped to the coordinate system to form signal quality characterization data. Through the aforementioned pre-training and synchronization mechanism, the sampling module and the signal quality monitoring module can complete sampling and analysis under stable timing conditions, thereby improving the accuracy and consistency of the signal quality detection results.

[0103] Based on the above overall architecture, the adaptive adjustment system in this embodiment forms a closed-loop working mechanism: the motherboard system controller SOC1 outputs a high-speed differential signal, the screen-end system controller SOC2 samples and analyzes the received high-speed differential signal and generates a signal quality detection result, which is fed back to the motherboard system controller SOC1 via SPI; the qualification judgment module of the motherboard system controller SOC1 determines whether the signal quality requirements are met based on the signal quality detection result, and adjusts the output parameters by the parameter adjustment module if the requirements are not met. Through this closed-loop mechanism, the system can realize the detection of high-speed differential signal quality and adaptive optimization of output parameters within the display device, improving the stability and consistency of the display device under different transmission conditions.

[0104] Figure 3 This is a schematic flowchart illustrating an adaptive adjustment method for display device signal quality provided in an embodiment of this disclosure. It is applied to the aforementioned adaptive adjustment system for display device signal quality.

[0105] like Figure 3 As shown, the adaptive adjustment method includes: Step S301: The motherboard system controller outputs a high-speed differential signal.

[0106] The motherboard system controller is located on the motherboard side and is configured to output a high-speed differential signal to transmit display data or related data to the display screen. Furthermore, the motherboard system controller has the capability to adjust the output parameters of the high-speed differential signal so that the signal output state can be adjusted in subsequent steps based on feedback results.

[0107] In step S302, the screen-end system controller receives the high-speed differential signal and samples and analyzes the received high-speed differential signal to obtain a signal quality detection result characterizing the quality of the high-speed differential signal.

[0108] The screen-end system controller is located on the display screen side and is configured to receive high-speed differential signals output by the motherboard system controller. The screen-end system controller samples and analyzes these high-speed differential signals to obtain signal quality detection results that reflect the actual reception status on the display screen side. By generating signal quality detection results by the screen-end system controller, signal quality assessment is based on the actual received signal status on the display screen side, thereby improving the objectivity and reliability of signal quality assessment.

[0109] In step S303, the information transmission and feedback channel transmits the signal quality detection result to the motherboard system controller.

[0110] An information transmission and feedback channel is set up between the motherboard system controller and the screen-end system controller to transmit the signal quality detection results generated by the screen-end system controller to the motherboard system controller. By establishing this feedback channel, the motherboard system controller can obtain the signal quality detection results from the screen-end system controller, thereby providing a basis for subsequent output parameter adjustments and forming a closed-loop foundation that combines signal quality detection and parameter adjustment.

[0111] In step S304, the motherboard system controller adjusts the output parameters of the high-speed differential signal based on the received signal quality detection results.

[0112] After receiving the signal quality detection results, the motherboard system controller adjusts the output parameters of the high-speed differential signal based on these results. This alters the output characteristics of the high-speed differential signal, thereby improving its signal quality during transmission. Adjusting output parameters based on detection results from the display screen reduces reliance on external testing equipment and manual adjustments, enabling automated signal quality optimization and enhancing the system's adaptability to different display screens and transmission channel conditions.

[0113] Thus, this embodiment can realize signal quality detection based on the actual received signal status on the display screen side within the display device, and adaptively adjust the high-speed differential signal output parameters on the motherboard side accordingly, thereby forming a closed-loop mechanism that combines detection and adjustment, which is beneficial to improving the stability and consistency of the display device.

[0114] Optionally, in step S302, the screen-end system controller samples and analyzes the high-speed differential signal to obtain a signal quality detection result, including: sampling the high-speed differential signal to obtain a sampling result; and analyzing the sampling result to generate the signal quality detection result.

[0115] Furthermore, the step of analyzing the sampling results to generate the signal quality detection results includes: generating signal quality characterization data based on the distribution relationship of sampling points in the time and voltage dimensions; and comparing the signal quality characterization data with a preset quality criterion to obtain a signal quality detection result indicating whether there are sampling points falling into the restricted area.

[0116] Specifically, the screen-end system controller samples the high-speed differential signal to obtain sampling results. Specifically, the screen-end system controller samples the received high-speed differential signal based on a preset sampling timing sequence to obtain multiple sampling point data. This sampling point data reflects the sampling status of the high-speed differential signal at different time positions and voltage states. By sampling the high-speed differential signal, basic data characterizing the actual received signal state at the screen-end can be obtained, providing data support for subsequent signal quality analysis.

[0117] Subsequently, the screen-end system controller analyzes the sampling results to generate the signal quality detection results. Specifically, the screen-end system controller generates signal quality characterization data based on the distribution relationship of sampling points in the time and voltage dimensions, and compares the signal quality characterization data with preset quality criteria to obtain signal quality detection results indicating whether any sampling points fall into prohibited areas. The signal quality detection results reflect the actual reception quality of the high-speed differential signal at the screen end and serve as the basis for subsequent pass / fail determination and output parameter adjustment by the motherboard system controller.

[0118] Furthermore, after sampling the high-speed differential signal, the screen-end system controller writes the sampled data into a first-in-first-out (FIFO) buffer structure to achieve buffering and sequential output of the sampled data. The FIFO buffer structure can be used as a component of the sampling module to buffer the sampled data and output it in the sampling order. The signal quality monitoring module is configured to read the data output from the FIFO buffer structure and sequentially map the data to a pre-trained coordinate system, thereby gradually forming signal quality characterization data; wherein, the signal quality characterization data can be eye diagram data to reflect the overall distribution characteristics of the sampling points in the time and voltage dimensions.

[0119] Furthermore, in this preferred embodiment, the quality criterion is preferably implemented using a template constraint method, for example, using a Mask template to limit the effective area where sampling points are allowed to be distributed and defining a no-entry area. As the eye diagram data gradually forms, the signal quality monitoring module continuously determines whether any data points fall into the no-entry area of ​​the Mask template; specifically, after mapping the coordinates of each sampling point, the signal quality monitoring module determines whether the sampling point falls into the no-entry area and generates the signal quality detection result based on the determination result. The signal quality detection result may include whether a no-entry area is hit and optional no-entry area location information, used to characterize the specific location or area type where the sampling point falls into the no-entry area.

[0120] In this embodiment, after generating the signal quality detection result, the screen-end system controller promptly feeds back the signal quality detection result to the motherboard system controller through the information transmission and feedback channel. In a preferred embodiment, the information transmission and feedback channel is implemented using the SPI protocol, enabling the screen-end system controller to promptly transmit the judgment result to the motherboard system controller during eye diagram formation and restricted area judgment, so that the motherboard system controller can perform subsequent qualification judgment and output parameter adjustment based on the feedback result.

[0121] By having the screen-end system controller perform sampling and analysis and generate signal quality detection results, signal quality assessment can be directly based on the actual received signal status at the screen end, thereby improving the authenticity and reliability of signal quality detection and providing effective feedback information for the subsequent adaptive adjustment process.

[0122] In step S303, the information transmission and feedback channel is implemented using the SPI protocol, and the signal quality detection result is transmitted to the motherboard system controller via the SPI protocol. Specifically, after generating the signal quality detection result, the screen-end system controller sends the signal quality detection result to the motherboard system controller via the SPI interface, enabling the motherboard system controller to promptly obtain the detection status of the high-speed differential signal at the screen end.

[0123] In a preferred embodiment, the signal quality detection result includes a determination result indicating whether a sampling point falls into a restricted area, and optionally includes restricted area location information and / or restricted area hit statistics. After receiving the signal quality detection result, the motherboard system controller provides it to the pass / fail determination module to determine whether the high-speed differential signal meets preset signal quality requirements. If the signal quality requirements are not met, the signal quality detection result is provided to the parameter adjustment module to determine the output parameter adjustment strategy.

[0124] Furthermore, in a preferred embodiment, as the eye diagram data gradually forms and continues to determine restricted areas, the screen-end system controller can send the signal quality detection results periodically or in an event-triggered manner via the SPI protocol. This enables the motherboard system controller to obtain the signal quality status in real time or near real time during the adaptive adjustment process, thereby improving the response speed and adjustment efficiency of the output parameter adjustment.

[0125] By using the SPI protocol as the information transmission and feedback channel, the signal quality detection result feedback between the screen-end system controller and the motherboard system controller can be realized without adding extra complex communication structures. This is conducive to forming a closed-loop adaptive adjustment mechanism that combines detection and parameter tuning.

[0126] In step S304, the motherboard system controller adjusts the output parameters of the high-speed differential signal based on the received signal quality detection result, including: Based on the signal quality detection results, determine whether the high-speed differential signal meets the preset signal quality requirements; When the signal quality detection results for a preset number of consecutive iterations all indicate that no sampling point falls into the restricted area, the high-speed differential signal is determined to meet the preset signal quality requirements. Specifically, based on the restricted area location information contained in the signal quality detection results, a corresponding output parameter adjustment strategy is determined; the output parameters include pre-emphasis parameters and / or output swing parameters.

[0127] After receiving the signal quality detection result from the screen-end system controller via the information transmission and feedback channel, the motherboard system controller adjusts the output parameters of the high-speed differential signal based on the signal quality detection result. Specifically, the motherboard system controller first determines whether the high-speed differential signal meets the preset signal quality requirements based on the signal quality detection result.

[0128] As a preferred implementation, the motherboard system controller employs a continuous judgment mechanism to improve the reliability of the pass / fail determination. Specifically, the motherboard system controller statistically analyzes the continuously received signal quality detection results. When the signal quality detection results for a preset number of consecutive times indicate that no sampling point falls into the prohibited area, the motherboard system controller determines that the high-speed differential signal meets the preset signal quality requirements and maintains the current output parameter configuration.

[0129] Furthermore, in another preferred embodiment, when the motherboard system controller detects during continuous statistical analysis that any signal quality detection result indicates that a sampling point falls into the prohibited area, the motherboard system controller resets the continuous statistical count to zero or restarts the count, and triggers a subsequent output parameter adjustment process to improve the signal quality status by adjusting the output parameters of the high-speed differential signal. By adopting the above-mentioned continuous judgment mechanism, the impact of occasional noise or a small number of abnormal sampling points on the pass / fail judgment can be reduced, thereby improving the stability and consistency of signal quality pass / fail judgment.

[0130] Figure 4 This is a schematic flowchart of another adaptive adjustment method for display device signal quality provided in this embodiment. It is applied to the aforementioned adaptive adjustment system for display device signal quality.

[0131] like Figure 4 As shown, the adaptive adjustment method includes: Step S401: The motherboard system controller and the screen-end system controller are powered on and initialized. The motherboard system controller enters adaptive adjustment mode, ready to send the training bitstream.

[0132] In step S402, the motherboard system controller sends a training bitstream to the screen-end system controller. This training bitstream assists the screen-end system controller in completing the synchronization processing of the high-speed differential signal, ensuring that subsequent sampling is based on a stable timing reference.

[0133] In step S403, the screen-end system controller performs clock recovery and / or data alignment based on the training bitstream; according to the recovered clock and alignment results, it determines the sampling timing reference and calculates the V=0 and T=0 reference points of the eye diagram coordinate system. After receiving the training bitstream, the screen-end system controller performs clock recovery and / or data alignment based on the training bitstream to determine the sampling timing reference of the high-speed differential signal. Further, during the pre-training process, the screen-end system controller calculates the reference points of the eye diagram coordinate system, so that the time zero point T=0 and voltage zero point V=0 of the coordinate system are determined, thereby establishing a coordinate reference for subsequent eye diagram formation and signal quality detection.

[0134] In step S404, the screen-end system controller loads a preset Mask template and delineates a restricted area based on the Mask template. The restricted area is used to limit the allowable data point distribution range of the eye diagram and is used for subsequent restricted area hit determination. By completing the Mask template loading and restricted area delineation during the pre-training phase, a unified and reusable quality criterion basis can be provided for subsequent signal quality detection.

[0135] like Figure 5 As shown, this embodiment uses a diamond-shaped mask template of a Tconless screen as an example. The mask template area is used as a reference point to construct a data restricted area. To provide more accurate feedback on signal quality and improve the targeting of parameter adjustments, this embodiment further divides the mask template restricted area into regions: connecting the midpoints of the four hypotenuses forms a square restricted area F, where A and B are left and right triangular restricted areas, C and D are top and bottom triangular restricted areas, and regions E and F are amplitude limiting restricted areas. Through the above region division, different regions of the restricted area can correspond to specific signal distortion types, such as signal overshoot, jitter, and amplitude abnormalities, thereby providing a basis for determining the subsequent output parameter adjustment strategy.

[0136] In step S405, the motherboard system controller sends high-speed differential signal data to the screen-end system controller. The high-speed differential signal data can be actual video data or a data stream used for signal detection.

[0137] In step S406, the screen-end system controller samples the high-speed differential signal; the sampled data is buffered in a FIFO and output sequentially. The FIFO's function is to buffer the sampled data and output it sequentially, so that the subsequent eye diagram formation process can process the data point by point according to the sampling order.

[0138] In step S407, the screen-end system controller reads the FIFO output data; it sequentially maps the sampling points to the coordinate system, gradually forming an eye diagram; during the eye diagram formation process, it continuously checks whether any sampling points fall into restricted areas. As the sampling points are continuously mapped, the eye diagram gradually becomes complete, reflecting the overall distribution of sampling points in the time and voltage dimensions. During the gradual formation of the eye diagram, the screen-end system controller continuously checks whether any sampling points fall into restricted areas of the Mask template; when a restricted area hit is detected, a signal quality detection result representing the restricted area hit is generated.

[0139] like Figure 6 As shown, under ideal conditions, a qualified eye diagram shape has sufficient eye height and width, and the jitter is within a reasonable range. No sampling points inside the eye diagram fall into the forbidden zone of the Mask template. Therefore, it can be determined that the high-speed differential signal meets the preset signal quality requirements.

[0140] Step S408: When it is detected that a sampling point falls into the forbidden zone, the screen - end system controller feeds back the forbidden - zone marking information to the main - board system controller through the SPI protocol. The information transmission and feedback channel is implemented using the SPI protocol, enabling the screen - end system controller to timely feed back the forbidden - zone hit judgment result to the main - board system controller during the eye - diagram formation and forbidden - zone judgment process. The signal - quality detection result at least includes the judgment result of whether there is a sampling point falling into the forbidden zone, and optionally includes the forbidden - zone position information, which is used to determine the subsequent parameter - adjustment strategy on the main - board side.

[0141] Step S409: When it is not detected that a sampling point falls into the forbidden zone, the screen - end system controller feeds back no - forbidden - zone marking information to the main - board system controller through the SPI protocol.

[0142] Step S410: The main - board system controller receives the SPI feedback information; counts the number of times T that there is no marking in the forbidden zone during continuous detection; when T > 10 and there are still no sampling points in the forbidden zone, it determines that the eye diagram is qualified; when there is a marking in the forbidden zone, it determines that the eye diagram is unqualified. In this embodiment, a continuous - determination mechanism is adopted: The main - board system controller counts the number of times T that the forbidden zone is not hit. When the repeated detection times T > 10 and there are still no sampling points detected in the forbidden zone, the main - board system controller determines that the quality of the eye diagram is qualified, that is, the high - speed differential signal meets the preset signal - quality requirements. If it is detected that there is a hit in the forbidden zone, it determines that the eye diagram is unqualified. Through the above - mentioned monitoring and judgment mechanism, the main - board system controller can complete the qualified judgment of the eye diagram based on the real reception status of the screen - end system controller, thereby avoiding manual debugging relying on external instruments and improving the accuracy and engineering applicability of signal - quality judgment.

[0143] Step S411: When it is determined that the eye diagram is qualified, the main - board system controller saves the current output parameters to the eMMC; and outputs a qualified result to indicate that the display screen shows a qualified prompt screen. In this way, the output parameters after debugging can remain unchanged after subsequent power - on or reset, thereby avoiding parameter loss or signal - quality degradation caused by power - on and power - off. The main - board system controller outputs a qualified result to the display screen, causing the display screen to show a qualified prompt screen, such as "Qualified" in green characters on a black background, thereby indicating to the user that the current high - speed differential signal quality meets the requirements and the adaptive - adjustment process ends.

[0144] Step S412: When it is determined that the eye diagram is unqualified, the main - board system controller enters the parameter - adjustment process. Here, the main - board system controller enters the parameter - adjustment process and determines the output - parameter adjustment strategy according to the forbidden - zone position information fed back by the screen end to improve the eye - diagram quality.

[0145] In step S413, the motherboard system controller determines whether the number of adjustments M is greater than the preset upper limit k. When M>k, an unqualified result is output and the manual adjustment procedure is initiated. When M≤k, the process proceeds to step S414. If M>k, automatic adjustment is stopped and an unqualified result is output, causing the display screen to show an unqualified prompt, such as "Unqualified" in red on a black background, and the system enters the manual adjustment stage. If M≤k, automatic adjustment continues.

[0146] In step S414, when M=1, the motherboard system controller determines the output parameter adjustment strategy based on the restricted area location information. Then, proceed to step S416. As a preferred implementation, the restricted area location information can be divided into areas A, B, C, D, E, F, and an optional P area, and the following strategy is executed accordingly: This includes: adding a pre-emphasis parameter when the restricted area location information falls into area A or area C; When the restricted area location information falls into area B or area D, add the Swing (output swing) parameter; When the restricted area location information falls into area B or area D and also falls into area P, the pre-emphasis parameter and Swing parameter are increased simultaneously. When the restricted area location information falls into region E or region F, the pre-emphasis parameter and Swing parameter are reduced simultaneously.

[0147] Specifically, such as Figure 7 As shown, when the sampling point is in region A or region C, it indicates that the high-speed differential signal has distortion characteristics that need to be compensated by enhancing the high-frequency components of the transmitter. Therefore, the parameter adjustment module determines that the pre-emphasis parameter value needs to be increased to improve the eye diagram opening state.

[0148] like Figure 8 As shown, when the sampling point is located in region B or region D, it indicates that the high-speed differential signal has insufficient amplitude or related distortion characteristics. Therefore, the parameter adjustment module determines that the Swing parameter value needs to be increased to improve the output swing and improve the signal amplitude performance.

[0149] like Figure 9 As shown, when the sampling points simultaneously hit regions B, D, and P, it indicates that the high-speed differential signal has both amplitude and time domain anomalies. Therefore, the parameter adjustment module determines that it is necessary to synchronously adjust and increase the pre-emphasis parameter value and the Swing parameter value to achieve joint compensation.

[0150] like Figure 10 As shown, when the sampling point is in region E or region F, it indicates that the high-speed differential signal has overshoot or excessive amplitude, which are characteristics of amplitude limiting-related distortion. Therefore, the parameter adjustment module determines that it is necessary to simultaneously adjust and reduce the pre-emphasis parameter value and the Swing parameter value to reduce overshoot and avoid the sampling point from falling into the amplitude limiting forbidden zone.

[0151] Through the above mapping of the signal quality criterion and parameter adjustment strategy based on the Mask template forbidden area partition, this embodiment enables the main board system controller to quickly determine the adjustment direction of the pre-emphasis parameter and / or Swing parameter according to the forbidden area position information fed back by the screen end system controller, thereby improving the convergence speed and adjustment efficiency of the adaptive adjustment and reducing the manual debugging cost.

[0152] Step S415, when 1 < M ≤ k, the main board system controller compares the forbidden area judgment results of the Mth time and the (M - 1)th time; determines whether the current adjustment becomes worse, and determines the corresponding adjustment strategy. It includes: Whether the number of sampling points in the original forbidden area increases; and / or Whether new forbidden area markings appear.

[0153] When the judgment result becomes worse, the main board system controller rolls back the output parameter to the parameter version of the (M - 1)th time and switches the adjustment direction; When the judgment result does not become worse, the main board system controller maintains the current adjustment direction and continues to adjust.

[0154] The main board system controller compares the forbidden area judgment results of the Mth time and the (M - 1)th time, and determines whether the number of data points in the original forbidden area increases or whether new forbidden area hits occur. If it is judged that the current adjustment causes the effect to become worse, the main board system controller rolls back to the parameter version of the (M - 1)th time and switches the adjustment direction. For example, when the previous adjustment of the pre-emphasis parameter causes it to become worse, it switches to adjusting the output swing parameter; if there is no worsening situation, it continues to adjust the output parameter in the current direction.

[0155] Step S416, the main board system controller updates the output parameter according to the determined adjustment strategy. It includes adjusting the pre-emphasis parameter and / or Swing parameter; after the update, return to execute steps S405 to S410 to reform the eye diagram and determine whether it is qualified.

[0156] The main board system controller updates the output parameter according to the determined adjustment strategy, and re-outputs the high-speed differential signal, enabling the screen end system controller to re-perform sampling, eye diagram formation and forbidden area judgment, and feedback the signal quality detection result again. Thus, a closed-loop iterative process of detection - feedback - judgment - parameter adjustment - re-detection is formed until the eye diagram is qualified or the maximum adjustment number is reached.

[0157] Exit the adaptive adjustment process when the eye diagram is qualified; exit the adaptive adjustment process and enter the manual adjustment stage when M > k and it is still unqualified.

[0158] In summary, this embodiment gradually forms an eye diagram based on FIFO buffer and coordinate system mapping through the screen-end system controller. During the eye diagram formation process, it continuously judges the mask template restricted areas and promptly feeds back restricted area hit information through the SPI protocol. The motherboard system controller performs a pass / fail judgment for T>10 consecutive times. When the result is unqualified, it adaptively adjusts the pre-emphasis parameters and / or output swing parameters based on the restricted area position information, thereby realizing automated closed-loop optimization of the high-speed differential signal quality of the display device.

[0159] This disclosure also provides a display device, including a motherboard and a screen, and further includes: As described above, the adaptive adjustment system for display device signal quality is used to adjust the signal transmission quality between the motherboard and the screen.

[0160] This disclosure provides a storage medium for storing program instructions, which, when executed, perform the adaptive adjustment method for display device signal quality as described above.

[0161] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0162] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0163] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0164] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0165] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. An adaptive adjustment system for signal quality of a display device, characterized in that, include: A motherboard system controller, located on the motherboard, is configured to output a high-speed differential signal and has the ability to adjust the output parameters of the high-speed differential signal; A screen-end system controller is installed at the screen end. The screen-end system controller is configured to receive high-speed differential signals and sample and analyze the received high-speed differential signals to obtain signal quality detection results that characterize the quality of the high-speed differential signals. The information transmission and feedback channel is located between the motherboard system controller and the screen terminal system controller, and is used to transmit the signal quality detection results generated by the screen terminal system controller; The motherboard system controller is further configured to adjust the output parameters of the high-speed differential signal based on the received signal quality detection results.

2. The adaptive adjustment system according to claim 1, characterized in that, The screen-end system controller includes: The sampling module is configured to sample the high-speed differential signal; The signal quality monitoring module is configured to analyze the sampling results and generate the signal quality detection results.

3. The adaptive adjustment system according to claim 2, characterized in that, The signal quality monitoring module is configured as follows: Based on the distribution relationship of sampling points in the time and voltage dimensions, signal quality characterization data is generated. The signal quality characterization data is then compared with a preset quality criterion to obtain a signal quality detection result indicating whether a sampling point falls into a restricted area.

4. The adaptive adjustment system according to claim 1, characterized in that, The motherboard system controller includes: The pass / fail determination module is configured to determine whether the high-speed differential signal meets the preset signal quality requirements based on the signal quality detection results fed back by the screen terminal system controller. The parameter adjustment module is configured to adjust the output parameters of the high-speed differential signal according to the signal quality detection result when the high-speed differential signal does not meet the signal quality requirements.

5. The adaptive adjustment system according to claim 4, characterized in that, The parameter adjustment module is configured to determine the corresponding output parameter adjustment strategy based on the restricted area location information contained in the signal quality detection result.

6. The adaptive adjustment system according to claim 5, characterized in that, The output parameters include pre-weighting parameters and / or output swing parameters.

7. The adaptive adjustment system according to claim 1, characterized in that, The screen-end system controller is also configured to perform the signal quality detection before... Based on the training signal sent by the motherboard system controller, the high-speed differential signal is synchronously processed to establish a sampling reference for signal quality detection.

8. The adaptive adjustment system according to claim 7, characterized in that, The motherboard system controller is configured to send a training bitstream before adaptive adjustment begins; The screen-end system controller is configured to perform clock recovery and / or data alignment based on the training bitstream to determine the sampling timing reference of the high-speed differential signal.

9. An adaptive adjustment method for the signal quality of a display device, applied to the adaptive adjustment system for the signal quality of a display device as described in any one of claims 1-8; characterized in that, The adaptive adjustment method includes: The motherboard system controller outputs high-speed differential signals; The screen-end system controller receives high-speed differential signals and samples and analyzes the received high-speed differential signals to obtain signal quality detection results that characterize the quality of the high-speed differential signals; The information transmission and feedback channel transmits the signal quality detection results to the motherboard system controller; The motherboard system controller adjusts the output parameters of the high-speed differential signal based on the received signal quality detection results.

10. A display device, comprising a motherboard and a screen; characterized in that, Also includes: The adaptive adjustment system for display device signal quality as described in any one of claims 1 to 8 is used to adjust the signal transmission quality between the motherboard and the screen.

11. A storage medium for storing program instructions, characterized in that, When the program instructions are executed, the adaptive adjustment method for display device signal quality as described in claim 9 is performed.

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