Display device and driving method thereof

Abstract

The application discloses a display device and a driving method thereof. The display device comprises a display area and a non-display area. In the display area, at least part of pixel circuits in the same column correspond to the same data signal line, and at least part of pixel circuits in the same column are electrically connected with the same reset signal line. In the first non-display area of the non-display area, each first connection signal line is electrically connected with each data signal line, each first switch module is electrically connected with each reset signal line, and a second switch module is electrically connected between the first connection signal line and the reset signal line. The first switch module receives and transmits the reset signal to the reset signal line in the reset stage, and writes the reset signal into the corresponding pixel circuit. The first connection signal line receives and transmits the data signal to the data signal line in the first stage. The second switch module transmits the data signal of the data signal line to the reset signal line in the data writing stage, and writes the data signal into the corresponding pixel circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display device and its driving method. Background Technology

[0002] With the development of display technology, the requirements for the display effect of display devices are becoming increasingly higher. Organic light-emitting diode (OLED) display devices have advantages such as self-illumination, low power consumption, high contrast, and rich display colors, and have become a research hotspot in the current display technology field.

[0003] Since OLED elements are current-driven devices, and the data signals output by the driving circuits in display devices are typically voltage signals, corresponding pixel circuits are needed to convert the data signals into driving current to drive the OLED elements for display and light emission. However, the pixel circuits in existing technologies are relatively large, which is detrimental to the high resolution of display devices. How to reduce the size of the pixel circuits while ensuring that they accurately provide driving current has become an urgent technical problem to be solved. Summary of the Invention

[0004] This invention provides a display device and its driving method, which can reduce the size of the pixel circuit and improve the display resolution of the display device while ensuring that the pixel circuit accurately provides driving current, and at the same time ensure that the display device has a high display effect.

[0005] In a first aspect, the present invention provides a display device, comprising: a display area and a non-display area at least partially surrounding the display area; the non-display area includes a first non-display area located on one side of the display area; The display area is provided with multiple pixel circuits, multiple data signal lines and multiple reset signal lines arranged in an array; at least some of the pixel circuits located in the same column correspond to the same data signal line, and at least some of the pixel circuits located in the same column are electrically connected to the same reset signal line. The first non-display area is provided with multiple first switch modules, multiple second switch modules, and multiple first connection signal lines; each first connection signal line is electrically connected to each of the data signal lines; each first switch module is electrically connected to each of the reset signal lines; and each second switch module is electrically connected between the first connection signal lines and the reset signal lines. The driving cycle of the pixel circuit includes at least a reset phase, a first phase, and a data writing phase; the first switching module is at least used to receive and transmit a reset signal to the reset signal line during the reset phase, and write the signal into the corresponding pixel circuit through the reset signal line; the first connection signal line is at least used to receive and transmit a data signal to the data signal line during the first phase before the data writing phase; the second switching module is at least used to transmit the data signal from the data signal line to the reset signal line during the data writing phase, and write the signal into the corresponding pixel circuit through the reset signal line.

[0006] In a second aspect, the present invention provides a driving method for a display device, the display device comprising: a display area and a non-display area at least partially surrounding the display area; the non-display area including a first non-display area located on one side of the display area; the display area being provided with a plurality of pixel circuits, a plurality of data signal lines, and a plurality of reset signal lines arranged in an array; at least a portion of the pixel circuits located in the same column corresponding to the same data signal line, and at least a portion of the pixel circuits located in the same column being electrically connected to the same reset signal line; the first non-display area being provided with a plurality of first switch modules, a plurality of second switch modules, and a plurality of first connection signal lines; each of the first connection signal lines being electrically connected to each of the data signal lines; each of the first switch modules being electrically connected to each of the reset signal lines; the second switch modules being electrically connected between the first connection signal lines and the reset signal lines; the driving cycle of the pixel circuits including at least a reset phase, a first phase, and a data writing phase; the driving method for the display device comprising: During the reset phase, the first switch module is turned on, and the reset signal is transmitted to the reset signal line through the first switch module and written into the pixel circuit through the reset signal line. In the first stage, the data signal is transmitted to the data signal line through the first connection signal line; During the data writing phase, the second switch module is turned on, and the data signal of the data signal line is transmitted to the reset signal line through the second switch module, and then written into the pixel circuit through the reset signal line.

[0007] The technical solution of this invention involves arranging multiple pixel circuits, multiple data signal lines, and multiple reset signal lines in an array in the display area. The data signal lines correspond to at least a portion of the pixel circuits located in the same column, and the reset signal lines are electrically connected to at least a portion of the pixel circuits located in the same column. Simultaneously, multiple first switch modules, multiple second switch modules, and multiple first connection signal lines are arranged in a first non-display area. The first switch modules are electrically connected to the reset signal lines, and the first connection signal lines correspond to the data signal lines. The second switch modules are electrically connected between the first connection signal lines and the reset signal lines. This allows, during the reset phase, the first switch modules to provide a reset signal to the reset signal lines, which is then written into the pixel circuits to reset them. This prevents the signal written to the pixel circuits in the previous driving cycle from affecting the signal writing in the current driving cycle. During data writing... Before the first stage, the control data signal is written to the data signal line through the first connection signal line. When entering the data writing stage, the data signal on the control data signal line is provided to the reset signal line through the second switch module, and then written to the pixel circuit through the reset signal line. This allows the pixel circuit to accurately display and emit light based on the reset signal and data signal written therein, ensuring that the display device has a high display and light emission effect. In addition, since both the data signal and the reset signal are written to the pixel circuit through the reset signal line, the pixel circuit only needs to be equipped with a device electrically connected to the reset signal line to realize the time-division writing of the reset signal and the data signal. This eliminates the need to set up separate memory devices for writing the reset signal and the data signal in the pixel circuit, which helps to reduce the size of the pixel circuit, thereby improving the resolution of the display device and ultimately improving the display effect of the display device.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0009] Figure 1 A schematic diagram of the structure of a display device provided for related technologies; Figure 2 This is a schematic diagram of a pixel circuit structure provided by related technologies; Figure 3 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention; Figure 4 This is a driving timing diagram of a display device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the film layer structure of a display device provided in an embodiment of the present invention; Figure 6This is a schematic diagram of another display device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 9 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 10 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 11 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 12 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 13 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 18 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 22 This is a driving timing diagram of another display device provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention; Figure 24 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 25 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 26This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 27 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 28 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 29 yes Figure 28 A corresponding driving timing diagram for a pixel circuit; Figure 30 This is a flowchart illustrating a driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0011] Figure 1 A schematic diagram of the structure of a display device provided for related technologies. Figure 2 This is a schematic diagram of a pixel circuit structure provided by related technologies, such as... Figure 1 and Figure 2As shown, in the related technology, the display device 001 is provided with multiple pixel circuits P0 arranged in an array, multiple data signal lines 01, and multiple reset signal lines 02. The pixel circuit P0 includes a driving module 010, a data writing module 020, a reset module 030, a light-emitting control module 040, and a light-emitting module 050. The data writing module 020 of the pixel circuit P0 located in the same column is electrically connected to the same data signal line 01, and the reset module 030 of the pixel circuit P0 located in the same column is electrically connected to the same reset signal line 02. In the same pixel circuit, both the data writing module 020 and the reset module 030 are electrically connected to the driving module 010. The reset module 030 is used to control the reset signal Vref´ transmitted by the reset signal line 02 during the reset phase and provide it to the driving module 010 to reset the driving module 010. The data writing module 020 is used to control the data signal line 01 during the data writing phase. The transmitted data signal Vdata´ is provided to the driving module 010 to realize the writing of the data signal Vdata´. The light emission control module 040 and the light emission module 050 are connected in series with the driving module 010 between the first power signal ELVDD and the second power signal ELVEE. The light emission control module 040 is used to control the formation of a current path between the first power signal ELVDD and the second power signal ELVEE during the light emission stage, so that the driving module 010 provides the driving current generated by the written signal to the light emission module 050 to drive the light emission module 050 to display light emission. In this way, the driving cycle of the pixel circuit P0 includes at least a reset stage, a data writing stage, and a light emission stage, so that the reset of the driving module 010 and the writing of the data signal are realized before the light emission stage, ensuring that the signal can be accurately written into the pixel circuit P0, thereby accurately controlling the light emission module 050 to display light emission during the light emission stage.

[0012] However, with the development of display technology, the requirements for display resolution are constantly increasing. The pixel circuit P0 in related technologies needs to set up more device structures, making the pixel circuit P0 larger in size and occupying more space. This is not conducive to further improving the display resolution, and thus affects the improvement of the display effect of the display device.

[0013] To address the aforementioned technical problems, embodiments of the present invention provide a display device, comprising: a display area and a non-display area at least partially surrounding the display area; the non-display area includes a first non-display area located on one side of the display area; The display area is provided with multiple pixel circuits, multiple data signal lines and multiple reset signal lines arranged in an array; at least some pixel circuits located in the same column correspond to the same data signal line, and at least some pixel circuits located in the same column are electrically connected to the same reset signal line. The first non-display area is provided with multiple first switch modules, multiple second switch modules, and multiple first connection signal lines; each first connection signal line is electrically connected to each corresponding data signal line; each first switch module is electrically connected to each corresponding reset signal line; and each second switch module is electrically connected between the first connection signal line and the reset signal line. The driving cycle of the pixel circuit includes at least a reset phase, a first phase, and a data writing phase; the first switching module is at least used to receive and transmit a reset signal to the reset signal line during the reset phase, and write the signal into the corresponding pixel circuit through the reset signal line; the first connection signal line is at least used to receive and transmit a data signal to the data signal line during the first phase before the data writing phase; the second switching module is at least used to transmit the data signal from the data signal line to the reset signal line during the data writing phase, and write the signal into the corresponding pixel circuit through the reset signal line.

[0014] By employing the above technical solution, multiple pixel circuits, multiple data signal lines, and multiple reset signal lines are arranged in an array in the display area. The data signal lines correspond to at least a portion of the pixel circuits located in the same column, and the reset signal lines are electrically connected to at least a portion of the pixel circuits located in the same column. Simultaneously, multiple first switch modules, multiple second switch modules, and multiple first connection signal lines are arranged in the first non-display area. The first switch modules are electrically connected to the corresponding reset signal lines, and the first connection signal lines correspond to the data signal lines. The second switch modules are electrically connected between the first connection signal lines and the reset signal lines. This allows the first switch modules to provide a reset signal to the reset signal lines during the reset phase, and the signal is written into the pixel circuits through the reset signal lines to reset the pixel circuits. This prevents the signal written to the pixel circuits in the previous driving cycle from affecting the signal writing in the current driving cycle. During data writing... Before the first stage, the control data signal is written to the data signal line through the first connection signal line. When entering the data writing stage, the data signal on the control data signal line is provided to the reset signal line through the second switch module, and then written to the pixel circuit through the reset signal line. This allows the pixel circuit to accurately display and emit light based on the reset signal and data signal written therein, ensuring that the display device has a high display and light emission effect. In addition, since both the data signal and the reset signal are written to the pixel circuit through the reset signal line, the pixel circuit only needs to be equipped with a device electrically connected to the reset signal line to realize the time-division writing of the reset signal and the data signal. This eliminates the need to set up separate memory devices for writing the reset signal and the data signal in the pixel circuit, which helps to reduce the size of the pixel circuit, thereby improving the resolution of the display device and ultimately improving the display effect of the display device.

[0015] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0016] It should be noted that the implementation methods provided in the embodiments of the present invention can be combined with each other without contradiction, and all of them fall within the protection scope of the present invention.

[0017] Figure 3 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, for reference. Figure 3 The display device 100 includes a display area AA and a non-display area NA that at least partially surrounds the display area AA; the non-display area NA includes a first non-display area NA1 located on one side of the display area AA. The display area AA is the effective area in the display device 100 for displaying images, while the non-display area NA is the area in the display device 100 where no image is displayed. The fact that the non-display area NA at least partially surrounds the display area AA can be understood as at least one side of the display area AA being the non-display area NA, i.e., the area surrounding the display area AA being the non-display area NA, or at least one side of the display area AA not having a non-display area NA. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose specific limitations on this.

[0018] Continue to refer to Figure 3 The display area AA is provided with multiple pixel circuits P arranged in an array, multiple data signal lines 11 and multiple reset signal lines 12; at least some of the pixel circuits P located in the same column correspond to the same data signal line 11, and at least some of the pixel circuits P located in the same column are electrically connected to the same reset signal line 12.

[0019] The fact that at least some pixel circuits P located in the same column correspond to the same data signal line 11 can be understood as some or all pixel circuits P located in the same column corresponding to the same data signal line 11. This data signal line 11 can be used for time-division multiplexing to transmit and store the data signals Vdata of each corresponding pixel circuit P. The fact that at least some pixel circuits P located in the same column are electrically connected to the same reset signal line 12 can be understood as some or all pixel circuits P located in the same column being electrically connected to the same reset signal line 12, so that the reset signal line 12 can provide reset signals Vref to each pixel circuit P electrically connected to it in a time-division multiplexing manner. The correspondence between the data signal line 11 and the reset signal line 12 and the pixel circuits P located in the same column can be designed according to actual needs, and the embodiments of the present invention do not specifically limit this. For ease of description, unless otherwise specified, the embodiments of the present invention use the example that all pixel circuits located in the same column are electrically connected to the same reset signal line and correspond to the same data signal line to illustrate the technical solutions of the embodiments of the present invention.

[0020] Continue to refer to Figure 3 The first non-display area NA1 is provided with multiple first switch modules 21, multiple second switch modules 22, and multiple first connection signal lines 31. Each first connection signal line 31 is electrically connected to a corresponding data signal line 11. Each first switch module 21 is electrically connected to a corresponding reset signal line 12. The second switch module 22 is electrically connected between the first connection signal line 31 and the reset signal line 12. The driving cycle of the pixel circuit P includes at least a reset phase, a first phase, and a data writing phase. The first switch module 21 is at least used to receive and transmit a reset signal Vref to the reset signal line 12 during the reset phase, and write it into the corresponding pixel circuit P through the reset signal line 12. The first connection signal line 31 is at least used to receive and transmit a data signal Vdata to the data signal line 11 during the first phase before the data writing phase. The second switch module 22 is at least used to transmit the data signal Vdata from the data signal line 11 to the reset signal line 12 during the data writing phase, and write it into the corresponding pixel circuit P through the reset signal line 12.

[0021] The first connection signal line 31 receives and transmits the data signal Vdata at least in the first stage before the data writing stage. The first connection signal line 31 located in the first non-display area NA1 is arranged in a "fan-shaped wiring" to ensure that the driving circuit and other circuits used to provide the data signal Vdata can be electrically connected to the first connection signal line 31 in the relatively concentrated middle area of ​​the first non-display area NA1. This helps to reduce the size of the driving circuit used to provide the data signal line Vdata, meet the space optimization requirements, and reduce the cost of the driving circuit.

[0022] Each first connection signal line 31 is electrically connected to each corresponding data signal line 11, meaning each first connection signal line 31 can be electrically connected to one data signal line 11. This allows the data signal line 11 to receive the data signal Vdata provided by the first connection signal line 31 to which it is electrically connected during the first stage of the pixel circuit P, preventing crosstalk between the data signals Vdata written on each data signal line 11. Each first switch module 21 is electrically connected to each corresponding reset signal line 12, meaning each first switch module 21 can be electrically connected to one reset signal line 12. This allows the reset signal line 12 to receive the reset signal Vref transmitted by the first switch module 21 to which it is electrically connected during the reset stage of the pixel circuit P, and to write it into the pixel circuit P to reset the pixel circuit P, preparing for the writing of the data signal Vdata, and / or preventing the signal written in the previous driving cycle from affecting the signal writing in the current driving cycle. The second switch module 22 is electrically connected to the first connection signal line 31 and the reset signal line 12, respectively. Each second switch module 22 can be electrically connected to one first connection signal line 31 and one reset signal line 12. This allows the data signal Vdata provided by the first connection signal line 31 to its corresponding electrically connected data signal line 11 to be transmitted through the second switch module 22 to the corresponding reset signal line 12 during the data writing stage of the pixel circuit P. The reset signal line 12 then transmits and writes the data signal Vdata into the pixel circuit P, ensuring that the signal written to the pixel circuit P is correlated with its required data signal Vdata. This enables the pixel circuit P to accurately display and emit light based on the written signal. Specifically, in pixel circuits P located in the same column and electrically connected to the same reset signal line 12, each pixel circuit P corresponds to the same data signal line 11, ensuring that the data signal Vdata transmitted by the second switch module 22 can be written into the corresponding pixel circuit P through the reset signal line 12.

[0023] It is understood that the driving cycle of pixel circuit P includes a reset phase, a first phase, and a data writing phase, with the first phase preceding the data writing phase. For the same pixel circuit P, the first phase can occur before or after the reset phase, or the time of the first phase can overlap with the time of the reset phase. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose specific limitations on this. Similarly, the reset phase can occur before or after the data writing phase, again tailored to actual needs, and this embodiment of the invention does not impose specific limitations on this. For ease of description, unless otherwise specified, this embodiment uses the example of the first phase's time overlapping with the reset phase's time, with the reset phase preceding the data writing phase, to exemplify the technical solution of this embodiment of the invention.

[0024] For example, Figure 4 This is a driving timing diagram of a display device provided in an embodiment of the present invention, for reference. Figure 3 and Figure 4 The first switch module 21 can be turned on or off under the control of the first switch control signal SW1, and the second switch module 22 can be turned on or off under the control of the second switch control signal SW2. In one driving cycle of pixel circuit P, during the reset phase and the first phase T1, the first switch control signal SW1 is active, and the second switch control signal SW2 is inactive. The first switch control signal SW1 can control the first switch module 21 to turn on, and the second switch control signal SW2 can control the second switch module 22 to turn off. The reset signal Vref received by the first switch module 21 can be transmitted to the reset signal line 12 and then to the pixel circuit P, allowing the reset signal Vref to be written into the pixel circuit P. Simultaneously, the first connection signal line 31 can receive and transmit the data signal Vdata of the pixel circuit P and transmit it to the data signal line 11. Because the data signal line 11 has a certain length and width, it possesses a certain parasitic capacitance, allowing it to store the received data signal Vdata. Furthermore, because the second switch module 22 is in an inactive state, the data signal... The data signal Vdata on line 12 cannot be transmitted to the reset signal line 12, so that the transmission of the data signal Vdata and the reset signal Vref do not interfere with each other. In the data writing stage T2, the first switch control signal SW1 is at an invalid level, the second switch control signal is at an active level, the second switch control signal SW2 controls the second switch module 22 to be turned on, and the first switch control signal SW1 controls the first switch module 21 to be turned off. The first switch module 21 cannot continue to reset the signal Vref to the reset signal line 12. The second switch module 22 can transmit the data signal Vdata stored on the data signal line 11 to the reset signal line 12 through the first connection signal line 31, and then to the pixel circuit P through the reset signal line 12, so that the data signal Vdata can be written into the pixel circuit P. After the reset stage T1 and the data writing stage T2, the pixel circuit P can enter the light-emitting stage. The pixel circuit P can accurately display light emission according to the written reset signal Vref and data signal Vdata.

[0025] Thus, the data signal Vdata is not directly written to the pixel circuit P through the data signal line 11, but is written to the pixel circuit P through the reset signal line 12. This allows the reset signal line 12 to write the reset signal Vref and the data signal Vdata into the pixel circuit P in a time-division manner. The pixel circuit P can be electrically connected only to the reset signal line 12, without the need for additional devices to connect to the data signal line 11 in the pixel circuit P. This simplifies the structure of the pixel circuit P, helps to reduce the size of the pixel circuit P, and thus helps to achieve a higher resolution in the display device 100 and improve the display effect of the display device.

[0026] It is understood that the data signal Vdata stored on the data signal line 11 is not directly written into the pixel circuit P, but is transmitted sequentially to the reset signal line 12 through the first connection signal line 31 and the second switch module 22, and then transmitted and written into the pixel circuit P by the reset signal line 12. This allows the data signal line 11 to be connected to or not connected to the pixel circuit P. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0027] In an optional embodiment, within the display area AA, the data signal line 11 is not connected to the pixel circuit P. Thus, in the first stage before the data writing stage, the signal written to the data signal line 11 cannot be transmitted to the pixel circuit P, preventing the data signal Vdata from affecting the reset of the pixel circuit P. Simultaneously, because the data signals Vdata corresponding to each pixel circuit P located in the same column are different, the signal transmitted by the data signal line 11 is a transitional signal. When the data signal line 11 is not connected to the pixel circuit P, the data signal line 11 can be located on one side of the pixel circuit P, that is, in a direction perpendicular to the plane of the display device, the data signal line 11 and the pixel circuit P do not overlap, so that no parasitic capacitance is formed between the data signal line 11 and the structure in the pixel circuit P, thereby reducing the influence of the signal transmitted by the data signal line 11 on the pixel circuit P and ensuring that the pixel circuit P can accurately display and emit light. Furthermore, when the data signal line 11 and the pixel circuit P are not connected in the display area AA, the structure of the connecting lines in the display area AA can be further simplified, saving space in the display area AA, which is beneficial to the high resolution of the display device, thereby improving the display effect of the display device.

[0028] It is also understood that when the pixel circuit P and the data signal line 11 do not overlap in the direction perpendicular to the plane where the display device is located, the data signal line 11 can be set on the same layer as some structures in the pixel circuit P, or the data signal line 11 can be set on different layers from the various structures of the pixel circuit P. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0029] In an alternative embodiment, Figure 5 This is a schematic diagram of the film layer structure of a display device provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 5 As shown, the display device 100 can be a silicon-based organic light-emitting display device. In this case, the display device 100 may include a silicon-based substrate 101, a circuit structure and signal lines located on one side of the silicon-based substrate 101, etc.

[0030] Specifically, taking a pixel circuit P, which includes a transistor, disposed on one side of a silicon substrate 101, as an example, the structure of the display device 100 is illustrated by way of example. The display device 100 may also include a first conductive layer 102 and a second conductive layer 103 located on one side of the silicon substrate 101 and insulated from each other. The silicon substrate 101 is provided with a first electrode MO1, a second electrode MO2, a substrate end MO3, and an isolation region GI located between the second electrode MO2 and the substrate end MO3. The first conductive layer 102 includes the gate G0 of the transistor. The second conductive layer 103 includes a first connection electrode S0, a second connection electrode D0, and a third connection electrode B0. The first connection electrode S0 is electrically connected to the first electrode MO1 through a via, the second connection electrode D0 is electrically connected to the second electrode MO2 through a via, and the third connection electrode B0 is electrically connected to the substrate end MO3 through a via.

[0031] Furthermore, a data signal line 11 and a reset signal line 12 are also provided on one side of the silicon substrate 101. The data signal line 11 and the reset signal line 12 can be disposed on the same layer as the structure in the pixel circuit P. For example, the data signal line 11 and the reset signal line 12 can be disposed on the first conductive layer 102 or the second conductive layer 103. At the same time, the data signal line 11 and the reset signal line 12 can be disposed on the same layer, or they can be disposed on different layers. When the data signal line 11 and the reset signal line 12 are arranged in the same layer, they can be made of the same material and formed under the same process. This simplifies the film structure and manufacturing process of the display device, thereby contributing to the thinning and lower cost of the display device. Furthermore, since the data signal line 11 and the reset signal line 12 are made of the same material, they have the same resistivity. Therefore, when the thickness and line width of the data signal line 11 and the reset signal line 12 are consistent, they can have the same voltage drop, ensuring that the signals transmitted by the data signal line 11 and the reset signal line 12 are consistent, improving the accuracy of the signals transmitted by the data signal line 11 and the reset signal line 12, and thus improving the display effect of the display device 100.

[0032] It is also understood that the above description only illustrates the driving cycle of one pixel circuit P. For multiple pixel circuits P arranged in an array in the display device 100, the reset phase T1 time and the first phase time of pixel circuits P in the same row can overlap, the reset phase T1 time of pixel circuits P in the same column do not overlap, and the data writing phase T2 of pixel circuits P in the same row can overlap, while the data writing phase T2 of pixel circuits P in the same column do not overlap. Thus, in the display time Td of one frame, the reset phase T1 of each row of pixel circuits P and the data writing phase T2 of each row of pixel circuits P can be performed sequentially. For example, for two adjacent rows of pixel circuits P, the reset phase T1 and data writing phase T2 of the previous row of pixel circuits P can be performed before the reset phase T1 and data writing phase T2 of the next row of pixel circuits P. Under the premise that each pixel circuit P in the display device 100 can accurately display and emit light, the specific driving method of each row of pixel circuits P in this embodiment of the invention is not limited.

[0033] It should be noted that, Figure 4 The example only shows that the effective level of the first switch control signal SW1 and the second switch control signal SW2 is low and the invalid level is high. However, in the embodiments of the present invention, the effective level of the first switch control signal SW1 and the second switch control signal SW2 can also be high and the invalid level can be low. Furthermore, the effective levels of the first switch control signal SW1 and the second switch control signal SW2 can be the same or different. The specific design can be made according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0034] In an optional embodiment, the first switching module 21 may include a first switching transistor. The first terminal of the first switching transistor can receive a reset signal Vref, and the second terminal of the first switching transistor can be directly or indirectly electrically connected to the reset signal line 12. For example, the second terminal of the first switching transistor can be electrically connected to the reset signal line 12 through a corresponding second connection signal line 32. The gate of the first switching transistor can receive a first switching control signal SW1, allowing the first switching control signal SW1 to control the first switching transistor to turn on or off. The first switching transistor can be an N-type transistor or a P-type transistor. When the first switching transistor is an N-type transistor, the effective level of the first switching control signal SW1 is high, and the ineffective level is low. When the first switching transistor is a P-type transistor, the effective level of the first switching control signal SW1 is low, and the ineffective level is high. For ease of description, unless otherwise specified, the embodiments of the present invention use a P-type transistor as an example to illustrate the technical solutions of the embodiments of the present invention.

[0035] In an optional embodiment, the second switching module 22 may include a second switching transistor. The first terminal of the second switching transistor may be electrically connected to the first connection signal line 31, and the second terminal of the second switching transistor may be directly or indirectly electrically connected to the reset signal line 12. For example, the second terminal of the second switching transistor may be electrically connected to the reset signal line 12 through a corresponding second connection signal line 32. The gate of the second switching transistor may receive a second switching control signal SW2, enabling the second switching control signal SW2 to control the second switching transistor to be turned on or off. The second switching transistor may be an N-type transistor or a P-type transistor. When the second switching transistor is an N-type transistor, the effective level of the second switching control signal SW2 is high, and the ineffective level is low. When the second switching transistor is a P-type transistor, the effective level of the second switching control signal SW2 is low, and the ineffective level is high. For ease of description, unless otherwise specified, the embodiments of the present invention use a P-type transistor as an example to illustrate the technical solutions of the embodiments of the present invention.

[0036] This embodiment arranges multiple pixel circuits, multiple data signal lines, and multiple reset signal lines in an array in the display area. The data signal lines correspond to at least a portion of the pixel circuits located in the same column, and the reset signal lines are electrically connected to at least a portion of the pixel circuits located in the same column. Simultaneously, multiple first switch modules, multiple second switch modules, and multiple first connection signal lines are arranged in the first non-display area. The first switch modules are electrically connected to the reset signal lines, and the first connection signal lines correspond to the data signal lines. The second switch modules are electrically connected between the first connection signal lines and the reset signal lines. This allows, during the reset phase, the first switch modules to provide a reset signal to the reset signal lines, which is then written into the pixel circuits to reset them. This prevents the signal written to the pixel circuits in the previous driving cycle from affecting the signal writing in the current driving cycle. During the data writing phase... In the first stage, the control data signal is written to the data signal line through the first connection signal line. During the data writing stage, the data signal on the control data signal line is provided to the reset signal line through the second switch module, and then written to the pixel circuit through the reset signal line. This allows the pixel circuit to accurately display and emit light based on the reset signal and data signal written therein, ensuring that the display device has a high display and light emission effect. In addition, since both the data signal and the reset signal are written to the pixel circuit through the reset signal line, the pixel circuit only needs to be equipped with a device electrically connected to the reset signal line to realize the time-division writing of the reset signal and the data signal. This eliminates the need to set up separate memory devices for writing the reset signal and the data signal in the pixel circuit, which helps to reduce the size of the pixel circuit, thereby improving the resolution of the display device and ultimately improving the display effect of the display device.

[0037] Optional, Figure 6 This is a schematic diagram of another display device provided in an embodiment of the present invention, for reference. Figure 6 The first non-display area NA1 is also provided with a driving circuit 40; the driving circuit 40 is electrically connected to each of the first connection signal lines 31 and each of the first switch modules 21 respectively; the driving circuit 40 is at least used to provide a reset signal Vref to the first switch module 21 during the reset phase, and to provide a data signal Vdata to the first connection signal line 31 during the first phase.

[0038] The driving circuit 40 can integrate signal storage and logic operation devices, enabling it to provide data signals Vdata of each row of pixel circuits P in a time-division manner according to the display requirements of the display device 100. The data signals Vdata of the same row of pixel circuits P are transmitted to the data signal lines 11 corresponding to the pixel circuits P through the first connection signal lines 31, so that the subsequent data signals Vdata can be accurately written into the pixel circuits P. At the same time, the driving circuit 40 can also provide a reset signal Vref according to the display requirements of the display device 100. The reset signal Vref is provided to each reset signal line 12 through the first switch modules 21, and then provided to each pixel circuit P through the reset signal lines 12, so as to reset each pixel circuit P.

[0039] In addition, the drive circuit 40 may also include a first control module 401, which can provide a first switch control signal SW1 to the first switch module 21 and a second switch control signal SW2 to the second switch module 22 to control the first switch module 21 and the second switch module 22 to be turned on or off, so that the reset signal line 12 can transmit the reset signal Vref and the data signal Vdata in a time-division multiplexing manner.

[0040] Optional, Figure 7 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention, for reference. Figure 7 As shown, the driving circuit 40 includes multiple data driving modules 41 and a reset signal module 42; the reset signal module 42 is electrically connected to each of the first switch modules 21, and the reset signal module 42 is used to provide a reset signal Vref to each of the first switch modules 21; each data driving module 41 is electrically connected to each of the first connection signal lines 31 respectively; the data driving module 41 is used to provide a data signal Vdata to the first connection signal line 31.

[0041] The data driving module 41 can receive the digital signal of the data signal, convert it into an analog signal, and provide the converted analog signal to the first connection signal line 31. This ensures that the analog signal can be transmitted through the first connection signal line 31 and stored in the data signal line 11. During the data writing stage of the pixel circuit P, it is provided to the reset signal line 12 through the second switch module 22, so that it can be transmitted and written into the pixel circuit P through the reset signal line 12. In an exemplary embodiment, the data driving module 41 may include a digital-to-analog converter and a data amplifier. The digital-to-analog converter can convert the digital signal of the data signal into an analog signal, and the analog signal is amplified by the data amplifier before being provided to the first connection signal line 31.

[0042] It is understood that the above description is merely an exemplary illustration of the structure of the data driving module 41. The specific structure of the data driving module 41 in this embodiment can be designed according to actual needs, and this embodiment does not impose specific limitations on it. Furthermore, each data driving module 41 is electrically connected to each of the first connection signal lines 31. That is, in an optional embodiment, each data driving module 41 is electrically connected to one first connection signal line 31, so that each data driving module 41 can provide data signals to each of the first connection signal lines 31 respectively, ensuring that the data signals received by each of the first connection signal lines 31 do not interfere with each other. In other optional embodiments, each data driving module 41 may also correspond to multiple first connection signal lines 31. The correspondence between the data driving module 41 and the first connection signal lines 31 can be designed according to actual needs, and this embodiment does not impose specific limitations on it.

[0043] In an alternative embodiment, Figure 8 This is a schematic diagram of the structure of another display device provided in an embodiment of the present invention, for reference. Figure 8 As shown, the first non-display area N1 is also provided with multiple gating circuits 60 corresponding to multiple data driving modules 41; the gating circuits 60 are electrically connected between the first connection signal line 31 and the data driving module 41; the gating circuits 60 include multiple gating switch modules 61; the first end of each gating switch module 61 of the same gating circuit 60 is electrically connected to the same data driving module 41; the second end of each gating switch module 61 is electrically connected to each of the first connection signal lines 31 respectively; wherein, each gating switch module 61 of the same gating circuit 60 is turned on in a time-division manner.

[0044] It is understood that the gating circuit 60 includes multiple gating switch modules 61, that is, the gating circuit 61 may include two, three or more gating switch modules 61. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0045] In an exemplary embodiment, the pixel circuit in the display device 100 may include a red pixel circuit, a green pixel circuit, and a blue pixel circuit. The display emission color of the red pixel circuit is red, the display emission color of the green pixel circuit may be green, and the display emission color of the blue pixel circuit may be blue. The red pixel circuit, green pixel circuit, and blue pixel circuit located in the same row and adjacent to each other can form a pixel unit. The first connection signal lines 31 that are electrically connected to the data signal lines 11 corresponding to each pixel circuit in the same pixel unit can be electrically connected to the corresponding selection switch modules 61 of the same selection circuit 60. That is, each pixel circuit of the same pixel unit corresponds to the corresponding selection switch modules 61 of the same selection circuit 60. At this time, the selection circuit 60 may include three selection switch modules 61, such that the three selection switch modules 61 are electrically connected to the same data driving module 40. Simultaneously, since each gating switch module 61 in the same gating circuit 60 is turned on in a time-division manner, each gating switch module 61 can receive the data signal output by the data driving module 40 in a time-division manner. At this time, the data driving module 40 can output the data signal corresponding to each pixel circuit P in the same pixel unit in a time-division manner. For example, when the gating switch module 61 corresponding to the red pixel circuit is turned on, the data driving module 41 can output the data signal of the red pixel circuit to the first connection signal line 31 corresponding to the red pixel circuit, and transmit it to the data signal line 11 corresponding to the red pixel circuit through the first connection signal line 31; when the gating switch module 61 corresponding to the red pixel circuit is turned on, the data driving module 41 can output the data signal of the red pixel circuit to the first connection signal line 31 corresponding to the red pixel circuit .... When the gating switch module 61 corresponding to the green pixel circuit is turned on, the data driving module 41 can output the data signal of the green pixel circuit to the first connection signal line 31 corresponding to the green pixel circuit, and transmit it to the data signal line 11 corresponding to the green pixel circuit through the first connection signal line 31; when the gating switch module 61 corresponding to the blue pixel circuit is turned on, the data driving module 41 can output the data signal of the blue pixel circuit to the first connection signal line 31 corresponding to the green pixel circuit, and transmit it to the data signal line 11 corresponding to the blue pixel circuit through the first connection signal line 31. In this way, the data driving module 41 provides data signals to each pixel circuit P in the same pixel unit in a time-division manner, which can prevent crosstalk between the signals of each pixel circuit P and ensure that the data signals corresponding to each pixel circuit P can be accurately written. At the same time, since each data driving module 41 can provide data signals to multiple first connection signal lines 31, it is not necessary to set up a data driving module 41 for each first connection signal line 41. This helps to reduce the number of data driving modules 41 in the driving circuit 40, reduce the size of the driving circuit 40, facilitate the narrow bezel of the display device 100, and reduce the setup cost of the driving circuit, thereby contributing to the low cost of the display device 100.

[0046] It should be noted that the above description is merely illustrative of the technical solution of the present invention by using a gating circuit comprising three gating switch modules as an example. The number of gating switch modules in the gating circuit of the present invention is not limited to this. For ease of description, unless otherwise specified, the embodiments of the present invention will use a gating circuit comprising three gating switch modules as an example to illustrate the technical solution of the present invention.

[0047] In an alternative embodiment, Figure 9 This is a driving timing diagram of another display device provided in an embodiment of the present invention, for reference. Figure 8 and Figure 9 Each gating switch module 61 in the same gating circuit 60 can receive different gating control signals (SW31, SW32, SW33) respectively, so that each gating switch module 61 in the same gating circuit 60 can be turned on in a time-division manner under the control of each gating control signal (SW31, SW32, SW33).

[0048] In an exemplary embodiment, the gating control signal SW31 can control the gating switch module 61 corresponding to the red pixel circuit to be turned on or off, the gating control signal SW32 can control the gating switch module 61 corresponding to the green pixel circuit to be turned on or off, and the gating control signal SW33 can control the gating switch module 61 corresponding to the blue pixel circuit to be turned on or off. For the same gating circuit 60, in the first stage T31 of the driving cycle of the red pixel circuit, the gating control signal SW31 can control the gating switch module 61 corresponding to the red pixel circuit to be turned on, the gating control signal SW32 controls the gating switch module 61 corresponding to the green pixel circuit to be turned off, and the gating control signal SW33 controls the gating switch module 61 corresponding to the blue pixel circuit to be turned off, so that the data signal of the red pixel circuit provided by the data driving module 41 can be transmitted through the turned-on gating switch module 61 to the first connection signal line 31 corresponding to the red pixel circuit and stored in the data signal line 11 electrically connected to the first connection signal line 31; in the first stage T32 of the driving cycle of the green pixel circuit, the gating control signal SW32 can control the gating switch module 61 corresponding to the green pixel circuit to be turned on, the gating control signal SW31 controls the gating switch module 61 corresponding to the red pixel circuit to be turned off, and the gating control signal SW33 controls the gating switch module 61 corresponding to the blue pixel circuit to be turned off. The selection switch module 61 corresponding to the blue pixel circuit is disconnected, so that the data signal of the green pixel circuit provided by the data driving module 41 can be transmitted to the first connection signal line 31 corresponding to the green pixel circuit through the conducting selection switch module 61, and stored in the data signal line 11 electrically connected to the first connection signal line 31; in the first stage T33 of the driving cycle of the blue pixel circuit, the selection control signal SW33 can control the selection switch module 61 corresponding to the blue pixel circuit to be turned on, the selection control signal SW31 controls the selection switch module 61 corresponding to the red pixel circuit to be turned off, and the selection control signal SW32 controls the selection switch module 61 corresponding to the green pixel circuit to be turned off, so that the data signal of the blue pixel circuit provided by the data driving module 41 can be transmitted to the first connection signal line 31 corresponding to the blue pixel circuit through the conducting selection switch module 61, and stored in the data signal line 11 electrically connected to the first connection signal line 31. In this way, the data driving module 41 can provide data signals of each pixel circuit P in the same pixel unit in a time-division manner, and store the data signals of each pixel circuit P in a time-division manner to the data signal line 11 corresponding to each pixel circuit P, so that the transmission and storage of data signals of each pixel circuit P do not interfere with each other.

[0049] In an optional embodiment, the drive circuit 40 may further include a gating control module 402, which can provide gating control signals (SW1, SW2 and SW3) to each gating switch module 61 to control each gating switch module 61 to be turned on or off respectively.

[0050] It is understood that since the data signal of pixel circuit P is stored on the data signal line 11 corresponding to pixel circuit P before the data writing stage T2 of pixel circuit P, that is, the first stage of pixel circuit P is before the data writing stage T2 of pixel circuit P, and the reset stage T1 of pixel circuit P can be before the data writing stage T2 of pixel circuit P, the first stage of pixel circuit P can be before the reset stage T1 of pixel circuit P, or the first stage of pixel circuit P can be after the reset stage T1 of pixel circuit P, or the time of the first stage of pixel circuit P can overlap with the reset stage T1 of pixel circuit P. Specifically, it can be designed according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0051] In an alternative embodiment, reference is made to... Figure 8 , Figure 9 and Figure 10 At least some of the first stages (T31, T32, T33) of the pixel circuit P are located before the reset stage T1 of the pixel circuit P, that is, some or all of the first stages (T31, T32, T33) of the pixel circuit P are located before their own reset stage T1.

[0052] like Figure 8 and Figure 9 As shown, if the first stages (T31, T32, T33) of all pixel circuits P are all located before their own reset stage T1, then when the gating circuit 60 includes three gating switch modules 61, in the driving cycle of a pixel circuit P, the effective pulses of the gating control signals SW31, SW32, and SW33 of the three gating switch modules 61 are shifted sequentially, so that each gating switch module 61 of the same gating circuit 60 is turned on sequentially. The effective pulses of the gating control signals SW31, SW32, and SW33 are located before the effective pulse time of the first switch control signal SW1 used to control the first switch module 21 to turn on. Thus, before the reset stage T1, the data driving module 41 can provide data signals to each first connection signal line 31 through each gating switch module 61 in the gating circuit 60, and transmit and store them to each data signal line 11 through each first connection signal line 31, completing the storage of data signals and facilitating the subsequent writing of data signals.

[0053] like Figure 8 and Figure 10As shown, if the first stage (T31, T32) of a portion of the pixel circuit P is located before its own reset stage T1, then when the gating circuit 60 includes three gating switch modules 61, in one driving cycle of the pixel circuit P, the effective pulses of the gating control signals SW31, SW32, and SW33 of the three gating switch modules 61 can also be controlled to shift sequentially, so that each gating switch module 61 of the same gating circuit 60 is turned on sequentially. The effective pulses of the gating control signals SW31 and SW32 are located before the effective pulse time of the first switch control signal SW1 used to control the first switch module 21 to turn on, while the effective pulse time of the gating control signal SW3 can be located after the effective pulse time of the first switch control signal SW1, or the gating control signal SW3 can be located after the effective pulse time of the first switch control signal SW1. The effective pulse time of the control signal SW33 can overlap with the effective pulse time of the first switch control signal SW1. Thus, before the reset phase T1, the data drive module 41 can provide data signals to each of the first connection signal lines 31 electrically connected to the gating switch modules 61 that receive the gating control signals SW31 and SW32 through the gating switch modules 61 in the gating circuit 60. The data signals are then transmitted and stored to each of the data signal lines 11 through the first connection signal lines 31, completing the storage of the data signals and facilitating the subsequent writing of the data signals. The time when the first connection signal line 31 electrically connected to the gating switch module 61 that receives the gating control signal SW33 receives and transmits the data signals is after the reset phase T1, or overlaps with the time of the reset phase T1. Thus, by placing the first stage (T31, T32) of a portion of the pixel circuit P before the reset stage T1 of the pixel circuit P, and placing the first stage (T33) of a portion of the pixel circuit P after the reset stage T1 of the pixel circuit P, or by having the first stage (T33) of a portion of the pixel circuit P overlap with the reset stage T1 of the pixel circuit P, the data signal transmission and storage time before the reset stage T1 can be shortened. This is beneficial for shortening the non-display light emission time of the pixel circuit P, relatively extending the display light emission time of the pixel circuit P, and further beneficial for improving the display light emission brightness of the pixel circuit P and improving the display contrast of the display device 100.

[0054] In another alternative embodiment, refer to Figure 8 , Figure 11 and Figure 12 At least some of the first stages (T31, T32, T33) of the pixel circuit P are located after the reset stage T1 of the pixel circuit P, that is, some or all of the first stages (T31, T32, T33) of the pixel circuit P are located after their own reset stage T1.

[0055] like Figure 8 and Figure 11As shown, if the first stages (T31, T32, T33) of all pixel circuits P are located after their own reset stages T1, then when the gating circuit 60 includes three gating switch modules 61, after the reset stage T1 of a driving cycle of a pixel circuit P, the effective pulses of the gating control signals SW31, SW32 and SW33 of the three gating switch modules 61 are shifted sequentially, so that each gating switch module 61 of the same gating circuit 60 is turned on sequentially. At this time, the effective pulses of the gating control signals SW31, SW32 and SW33 are located after the effective pulse time of the first switch control signal SW1 used to control the first switch module 21 to turn on. Thus, after the reset stage T1, that is, after the pixel circuit P is reset by the reset signal transmitted by the reset signal line 12, the data driving module 41 can provide data signals to each first connection signal line 31 through each gating switch module 61 in the gating circuit 60, and transmit and store them to each data signal line 11 through each first connection signal line 31, thereby completing the storage of data signals and facilitating the subsequent writing of data signals.

[0056] like Figure 8 and Figure 12As shown, if the first stage (T31, T32) of a portion of the pixel circuit P is located after its own reset stage T1, then when the gating circuit 60 includes three gating switch modules 61, in one driving cycle of the pixel circuit P, the effective pulses of the gating control signals SW31, SW32, and SW33 of the three gating switch modules 61 can also be controlled to shift sequentially, so that each gating switch module 61 of the same gating circuit 60 is turned on sequentially, and the effective pulses of the gating control signals SW32 and SW33 are located after the effective pulse time of the first switch control signal SW1 used to control the first switch module 21 to turn on, while the effective pulse time of the gating control signal SW31 can be located after the effective pulse time of the first switch control signal SW1. Before the effective pulse time of the gating control signal SW31, or the effective pulse time of the gating control signal SW31 can overlap with the effective pulse time of the first switch control signal SW1, so that before or during the reset phase T1, the data driving module 41 can provide the data signal to the first connection signal line 31 electrically connected to the gating switch module 61 that receives the gating control signal SW31, and transmit and store it to each data signal line 11 through the first connection signal line 31 to complete the storage of the data signal, which is convenient for subsequent data signal writing; while the time when the first connection signal line 31 electrically connected to the gating switch module 61 that receives the gating control signals SW32 and SW33 receives and transmits the data signal is after the reset phase T1. Thus, by placing the first stage (T32, T33) of a portion of the pixel circuit P after the reset stage T1 of the pixel circuit P, and placing the first stage (T31) of a portion of the pixel circuit P before the reset stage T1 of the pixel circuit P, or by having the first stage (T31) of a portion of the pixel circuit P overlap with the reset stage T1 of the pixel circuit P, the data signal transmission and storage time before the reset stage T1 can be shortened. This is beneficial for shortening the non-display light emission time of the pixel circuit P, relatively extending the display light emission time of the pixel circuit P, and further beneficial for improving the display light emission brightness of the pixel circuit P and improving the display contrast of the display device 100.

[0057] In yet another alternative embodiment, refer to Figure 8 , Figure 10 , Figure 12 and Figure 13 At least some of the pixel circuit P's first stage T1 time overlaps with the reset stage T1 time of the pixel circuit P, that is, some or all of the pixel circuit P's first stages (T31, T32, T33) are located at the time overlap of their own reset stage T1.

[0058] like Figure 8 and Figure 13As shown, if the first stages (T31, T32, T33) of all pixel circuits P overlap with their own reset stages T1, then when the gating circuit 60 includes three gating switch modules 61, in the reset stage T1 of a driving cycle of a pixel circuit P, the effective pulses of the gating control signals SW31, SW32 and SW33 of the three gating switch modules 61 are shifted sequentially, so that each gating switch module 61 of the same gating circuit 60 is turned on sequentially. At this time, the effective pulse time of the gating control signals SW31, SW32 and SW33 overlaps with the effective pulse time of the first switch control signal SW1 used to control the conduction of the first switch module 21. Thus, during the reset phase T1, that is, while the pixel circuit P is reset by the reset signal transmitted by the reset signal line 12, the data driving module 41 can provide data signals to each first connection signal line 31 through each gating switch module 61 in the gating circuit 60, and transmit and store the data signals to each data signal line 11 through each first connection signal line 31, thus completing the storage of data signals and facilitating the subsequent writing of data signals. This can save the time of the non-light-emitting phase in the driving cycle, relatively extend the display light-emitting time of the pixel circuit P, and thus help improve the display light-emitting brightness of the pixel circuit P and improve the display contrast of the display device 100.

[0059] If the first stage (T31, T32) of a portion of pixel circuit P overlaps with its own reset stage T1, then when the gating circuit 60 includes three gating switch modules 61, within the driving cycle of a pixel circuit P, the effective pulses of the gating control signals SW31, SW32, and SW33 of the three gating switch modules 61 can be sequentially shifted, so that each gating switch module 61 of the same gating circuit 60 is sequentially turned on, and as... Figure 8 and Figure 10 As shown, the effective pulse time of the gating control signal SW31 overlaps with the effective pulse time of the first switch control signal SW1 used to control the first switch module 21 to turn on, or, as... Figure 8 and Figure 12As shown, the effective pulse time of the gating control signal SW33 overlaps with the effective pulse time of the first switch control signal SW1 used to control the conduction of the first switch module 21, while the effective pulse times of other gating control signals can be located before or after the effective pulse time of the first switch control signal SW1. Thus, during the reset phase T1, the data driving module 41 can provide data signals to the first connection signal line 31 electrically connected to a portion of the gating switch modules 61, and transmit and store the data signals to each data signal line 11 through this first connection signal line 31, completing the storage of the data signals and facilitating subsequent data signal writing. Before or after the reset phase, the data driving module 41 can provide data signals to the first connection signal line 31 electrically connected to another portion of the gating switch modules 61. In this way, by overlapping the first phase of a portion of the pixel circuit P with the reset phase T1 of that pixel circuit P, the data signal transmission and storage time before the reset phase T1 can be shortened, thereby shortening the non-display light-emitting time of the pixel circuit P and relatively extending the display light-emitting time of the pixel circuit P, which in turn helps to improve the display light-emitting brightness of the pixel circuit P and improve the display contrast of the display device 100.

[0060] It is understood that the above description is merely an exemplary illustration of the relationship between the time of the first stage and the time of the reset stage. In the embodiments of the present invention, the time of the first stage and the time of the reset stage can be designed according to actual needs. Meanwhile, in the first stage of the pixel circuit P, the gating control signal (SW1, SW2 or SW3) received by the gating switch module 61 corresponding to the pixel circuit P is a valid pulse. This valid pulse can be a high level or a low level, which can be designed according to actual needs.

[0061] In an exemplary embodiment, the gating switch module 61 may include a gating switch transistor. The first terminal of the gating switch transistor may be electrically connected to the data driving module 41, and the second terminal of the gating switch transistor may be electrically connected to the first connection signal line 31. The gate of the gating switch transistor may receive a gating control signal (SW1, SW2 or SW3), so that the gating control signal (SW1, SW2 or SW3) can control the gating switch transistor to be turned on or off.

[0062] Specifically, when the selector transistor is an N-type transistor, the effective pulse level of the selector control signal (SW1, SW2, or SW3) is high; when the selector transistor is a P-type transistor, the effective pulse level of the selector control signal (SW1, SW2, or SW3) is low. The specific type of the selector switch module can be designed according to actual needs, and this embodiment of the invention does not impose specific limitations on it. For ease of description, unless otherwise specified, this embodiment of the invention uses a P-type transistor as an example to illustrate the technical solution of the present invention.

[0063] refer to Figure 7 and Figure 8 The driving circuit 40 may also include a reset signal module 42, which can generate a reset signal Vref and provide the reset signal Vref to each of the first switch modules 21. In the reset stage T1 of the pixel circuit P, the first switch module 21 can transmit the reset signal Vref to the reset signal line 12 and write it into the pixel circuit P through the reset signal line 12 to complete the reset of the pixel circuit P.

[0064] The reset signal module 42 may include a reset operational amplifier, which amplifies the reset signal Vref and provides it to each of the first switch modules 21, thereby ensuring the signal amount of the reset signal Vref provided to each of the first switch modules 21 and thus improving the reset effect of the reset signal Vref on each pixel circuit P.

[0065] This embodiment, by setting a data driving module and a reset signal module separately in the driving circuit, enables the data driving module to provide data signals and the reset signal module to provide reset signals, so that the provision of reset signals and data signals do not interfere with each other, thereby improving the accuracy of data signals and reset signals received by the pixel circuit.

[0066] Based on the above embodiments, optionally, refer to Figure 6 , Figure 7 and Figure 8 The first non-display area NA1 is also provided with a reset transmission bus 50; each first switch module 21 is electrically connected to the reset signal module 42 through the reset transmission bus 50.

[0067] The extension direction of the reset transmission bus 50 can intersect with the extension direction of each reset signal line 12 and be substantially parallel to the arrangement direction of each first switch module 21. In this case, each first switch module 21 can be electrically connected to the reset transmission bus 50, and one end of the reset transmission bus 50 can be electrically connected to the reset signal module 42. This allows the reset signal Vref output by the reset signal module 42 to be provided to the reset transmission bus 50 and transmitted by the reset transmission bus 50 to each first switch module 21. When each first switch module 21 is turned on, the reset signal Vref transmitted by each reset transmission bus 50 can be provided to each reset signal line 12 and transmitted to the pixel circuit P through the reset signal line 12 to reset the pixel circuit P. Thus, there is no need to separately set up connection lines between the reset signal module 42 and the first switch module 21, which simplifies the wiring in the first non-display area NA1, thereby reducing the size of the first non-display area NA1 and consequently contributing to the narrow bezel of the display device 100.

[0068] In an optional embodiment, the line width of the reset transmission bus 50 can be greater than the line width of the reset signal line 12, that is, the reset signal transmission bus 50 has a larger line width, thereby making the reset transmission bus 50 have a smaller signal transmission impedance, so that the reset signals Vref received by each first switch module 21 can have smaller differences, ensuring the consistency of the reset signals Vref received by each first switch module 21, thereby improving the consistency of the reset signals received by each pixel circuit P and improving the display uniformity of the pixel circuit P.

[0069] Optional, see reference Figure 14 and Figure 15 The driving circuit 40 also includes multiple driving amplification modules 43; the driving amplification modules 43 are electrically connected between the reset signal module 42 and the first switch module 21; the multiple first switch modules 21 constitute multiple first switch groups 210, and each first switch group 210 includes at least one first switch module 21; the first switch modules 21 of the same first switch group 210 are electrically connected to the same driving amplification module 43; the driving amplification module 43 is used to amplify the reset signal Vref provided by the reset signal module 42 and then provide it to the first switch module 21.

[0070] Each first switch group 210 includes at least one first switch module 21, that is, each first switch group 210 may include one or more first switch modules 21. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0071] like Figure 14 When each first switch group 210 includes a first switch module 21, each first switch module 21 can be electrically connected to each drive amplification module 43 in a one-to-one correspondence. This allows the reset signal Vref output by the reset signal module 42 to be amplified by each drive amplification module 43 and then provided to each first switch module 21 in a one-to-one correspondence by each drive amplification module 43. This ensures that the reset signal Vref received by each first switch module 21 has a large power, improves the anti-interference capability of the reset signal Vref, and enables the reset signal Vref to accurately reset each pixel circuit P.

[0072] like Figure 15When the first switch group 210 includes multiple first switch modules 21, for example, the first switch group 210 includes three first switch modules 210, the three first switch modules 210 of the same first switch group 210 are electrically connected to the same drive amplification module 43. This allows the reset signal Vref output by the reset signal module 42 to be amplified by the drive amplification module 43 and then provided by the drive amplification module 43 to each first switch module 21 of the same first switch group 210. This ensures that the reset signal Vref received by each first switch module 21 of the same first switch group 210 has a large power, giving the reset signal Vref a high anti-interference capability and ensuring that the reset signal Vref can accurately reset the pixel circuit P.

[0073] It should be noted that the above description only illustrates the case where the first switch group includes one or three first switch modules. However, in the embodiments of the present invention, the first switch group may also include two, four, or more first switch modules. The implementation methods for different numbers of first switch modules in the first switch group are similar to the above implementation methods, and the similarities can be referred to the above description. For ease of description, unless otherwise specified, the embodiments of the present invention will use the example of a first switch group including three first switch modules to illustrate the technical solutions of the embodiments of the present invention.

[0074] In an alternative embodiment, reference is made to... Figure 15 The drive amplification module 43 includes a Class AB power amplifier. The non-inverting input of the Class AB power amplifier is electrically connected to the reset signal module 41, the inverting input is electrically connected to the output, and the output is electrically connected to the first switch module 21. Thus, the drive amplification module 43, with its simple structure, can amplify the power of the reset signal Vref, prevent distortion of the reset signal Vref, and improve the anti-interference capability of the reset signal Vref.

[0075] Based on the above embodiments, optionally, the shortest distance between the driving amplification module 43 and the edge of the display area AA is L1, and the shortest distance between the reset signal module 42 and the edge of the display area AA is L2; ​​wherein, L1 < L2. With this configuration, the driving amplification module 43 is closer to the display area AA, so that the reset signal Vref, after being amplified by the driving amplification module 43, has a shorter signal transmission path and can be transmitted to the pixel circuit P located in the display area AA. This reduces the voltage drop of the reset signal Vref transmitted to the pixel circuit P, improves the accuracy of the reset signal Vref received by the pixel circuit P, and ensures that each pixel circuit P can be accurately reset, enabling the pixel circuit P to accurately write signals and display light emission, thus improving the display effect of the display device 100.

[0076] In an alternative embodiment, reference is made to... Figure 16 and Figure 17 The first non-display area NA1 is also provided with a fourth switch module 24 and at least one reset transmission bus 50; the fourth switch module 24 is electrically connected to each of the first switch modules 21 through the reset transmission bus 50; the fourth switch module 24 is used to receive a reset signal during the reset phase and control the reset signal to be transmitted to each of the first switch modules 21 through the reset transmission bus 50; the driving cycle of the pixel circuit P also includes a discharge phase; the first switch module 21 is also used to control the signal written into the pixel circuit P through the reset signal line 12 to discharge to the reset transmission bus 50 during the discharge phase; the fourth switch module 24 is also used to be in an off state during the discharge phase.

[0077] In this embodiment, when the first non-display area NA1 is provided with at least one reset transmission bus 50, the number of reset transmission buses 50 can be one or more, and can be designed according to actual needs. This embodiment does not impose a specific limitation on this. At least during the reset phase, the fourth switch module 24 can receive and transmit a reset signal to the reset transmission bus 50, which is then provided to each of the first switch modules 21. The signal is then transmitted through the first switch modules 21 to each reset signal bus 12, and written into each pixel circuit P through each reset signal bus 12 to reset the pixel circuit P. Due to differences in transmission paths, processes, etc., during reset signal transmission, the reset signals Vref written into each pixel circuit P differ, resulting in differences in the reset states of each pixel circuit P. At this time, by setting a discharge phase after the reset phase of a driving cycle of the pixel circuit, and controlling the fourth switch module 24 to be turned off and the first switch module 21 to be turned on during the discharge phase, the reset signals written to each pixel circuit P in the same reset phase can be discharged to the reset transmission bus 50 in sequence through the reset signal line 12 and the first switch module 21, thereby balancing the reset signals written to each pixel circuit P and ensuring the reset consistency of each pixel circuit P.

[0078] In an optional embodiment, the fourth switching module 24 may include a fourth switching transistor. The first terminal of the fourth switching transistor can receive a reset signal, the second terminal of the fourth switching transistor can be electrically connected to the reset transmission bus 50, and the gate of the fourth switching transistor can receive a fourth on control signal, enabling the fourth switching control signal to control the fourth switching transistor to turn on or off. The fourth switching transistor can be an N-type transistor or a P-type transistor, and the specific design can be tailored to actual needs; this embodiment of the invention does not impose specific limitations on this. For ease of description, unless otherwise specified, this embodiment of the invention uses a P-type transistor as an example to illustrate the technical solution of the present invention.

[0079] For example, with Figure 17 Taking the display device shown as an example, Figure 18 This is a driving timing diagram of another display device provided in an embodiment of the present invention, for reference. Figure 17 and Figure 18 When the driving circuit 40 includes both a data driving module 41 and a reset signal module 42, during the reset phase T1, the first switch control signal SW1 controls the first switch module 21 to be turned on, the fourth switch control signal SW4 controls the fourth switch module to be turned on, and the gating switch signal SW1 controls the corresponding gating switch module 61 to be turned on, so that the data signal provided by the data driving module 41 can be transmitted through the turned-on gating switch module 61 and the first connection signal line 31 and stored in the data signal line 11 corresponding to the gating switch module 61; at the same time, the reset signal provided by the reset signal module 42 can be transmitted sequentially through the fourth switch module 24, the reset transmission bus 50 and each first switch module 21 to each reset signal line 12, and transmitted through each reset signal line 12 and written into each pixel circuit P, thereby realizing the reset of each pixel circuit P.

[0080] During the discharge phase T4, the first switch control signal SW1 continues to control the first switch module 21 to remain on, while the fourth switch control signal SW4 controls the fourth switch module to be off. The reset signal written into each pixel circuit P during the reset phase T1 can provide the first switch module 21 to discharge to each reset transmission bus 50, so as to balance the reset signals in each pixel circuit P and keep the reset state of each pixel circuit P consistent. At the same time, during the discharge phase T4, the effective pulses of the gating control signals SW2 and SW3 can be shifted sequentially, so that the gating control signals SW2 and SW3 respectively control the corresponding gating switch modules 61 to be turned on sequentially, so that the data signal provided by the data driving module 41 can be transmitted and stored in the corresponding data signal line 11 sequentially through the turned-on gating switch modules 61.

[0081] During the data writing stage T2, the first switch control signal SW1 controls the first switch module 21 to disconnect, the fourth switch control signal SW4 controls the fourth switch module to disconnect, and the gating switch signals SW1, SW2 and SW3 control the corresponding gating switch module 61 to disconnect. The second switch control signal SW2 controls the second switch module 22 to turn on, so that the data signal stored in the data signal line 11 can be transmitted to the reset signal line 12 through the second switch module 22, and then transmitted and written to the pixel circuit P by the reset signal line 12, thereby realizing the data writing of the pixel circuit P.

[0082] It should be noted that the above description only illustrates the driving cycle of the pixel circuit when the driving circuit includes both a data driving module and a reset signal module. In the embodiments of the present invention, the structure of the driving circuit is not limited to this and can be designed according to actual needs. When the structure of the driving circuit changes, the driving cycle of the pixel circuit will also change accordingly.

[0083] Optional, see reference Figure 19 The first non-display area is also provided with a plurality of third switch modules 23; the drive circuit 40 includes a plurality of data drive modules 41; the first end of the third switch module 23 and the first end of the first switch module 21 are both electrically connected to the corresponding data drive module 41; the second end of each third switch module 23 is electrically connected to each corresponding first connection signal line 31; the data drive module 41 is used to provide a reset signal in the reset phase and to provide a data signal in the first phase; the third switch module 23 is used to conduct in the first phase and transmit the data signal to the first connection signal line 31.

[0084] The first end of the third switch module 23 and the first end of the first switch module 21 are both electrically connected to the data drive module 41, so that the number of data drive modules 41 can be equivalent to the number of the third switch module 23 and the first switch module 21, that is, each data drive module 41 can be connected to one third switch module 23 and one first switch module 21. At this time, during the reset phase of one driving cycle of pixel circuit P, the first switch module 21, which is electrically connected to the same data driving module 41, can be turned on, so that the reset signal provided by data driving module 41 can be transmitted to the reset signal line 12 through the turned-on first switch module 21, and written into pixel circuit P through the reset signal line 12 to reset pixel circuit P; while in the first phase of one driving cycle of pixel circuit P, the third switch module 23, which is electrically connected to the same data driving module 41, can be controlled, so that the data signal provided by data driving module 41 can be transmitted to the first connection signal line 31 through the turned-on third switch module 23, and transmitted and stored into data signal line 12 through the first connection signal line 31, so as to facilitate the subsequent writing of data signals. In this way, the data driving module 41 can provide the reset signal and the data signal in a time-division manner, so that there is no need to set up separate structures for providing the reset signal and the data signal in the driving circuit 40. This helps to simplify the structure of the driving circuit 40, reduce the size of the driving circuit 40, and thus reduce the area occupied by the driving circuit 40, which is beneficial to the narrow bezel of the display device 100.

[0085] Correspondingly, the drive circuit 40 may also include a third control module 403, which can provide a third switch control module to the third switch module 23 to control the third switch module 23 to be turned on or off.

[0086] Based on the above embodiments, optionally, the third switch module 23 may include a third switch transistor. The first terminal of the third switch transistor may be electrically connected to the data driving module 41, and the second terminal of the third switch transistor may be electrically connected to the first connection signal line 31. The gate of the third switch transistor may receive a third switch control signal, so that the third switch control signal can control the third switch transistor to be turned on or off. When the third switch control signal controls the third switch transistor to be turned on, the data signal provided by the data driving module 41 can be transmitted to the first connection signal line 31 through the turned-on third switch transistor. The third switch transistor may be an N-type transistor or a P-type transistor. When the third switch transistor is an N-type transistor, the effective pulse of the third switch control signal is high-level; when the third switch transistor is a P-type transistor, the effective pulse of the third switch control signal is low-level.

[0087] It should be noted that the type of the third switching transistor and the polarity of the effective pulse of the third switching control signal can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on this. For ease of description, unless otherwise specified, the embodiments of the present invention use a P-type transistor as the third switching transistor and a low-level effective pulse of the third switching control signal as an example to illustrate the technical solutions of the embodiments of the present invention.

[0088] It should also be noted that the above description is only exemplified by the example of each data driving module corresponding to one first switch module and one third switch module. In the embodiments of the present invention, the correspondence between the data driving module and the first switch module and the third switch module can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0089] In an alternative embodiment, reference is made to... Figure 20Multiple first switch modules 21 constitute multiple first switch groups 210 corresponding to multiple data drive modules 41; multiple third switch modules 23 constitute multiple third switch groups 230 corresponding to multiple data drive modules 41; each first switch module 21 of the same first switch group 210 is electrically connected to the same data drive module 41 at the same switch node; the first end of each third switch module 23 of the same third switch group 230 is electrically connected to the same data drive module 41; the second end of each third switch module 23 is electrically connected to each first connection signal line 31; each third switch module 23 of the same third switch group 230 is turned on in a time-division manner, and among the first switch module 21 and the third switch module 23 electrically connected to the same data drive module 41, at least part of the turn-on time of the first switch module 21 does not overlap with the turn-on time of the third switch module 23.

[0090] The first switch group 210 may include multiple first switch modules 21, and the third switch group 230 may include multiple third switch modules 23. Each first switch module 21 of the same first switch group 210 may be electrically connected to the same data driver module 41 at the same switch node, and each third switch module 23 of the same third switch group 230 may be electrically connected to the same data driver module 41. This allows each data driver module 41 to be electrically connected to multiple first switch modules 21 and multiple third switch modules 23 simultaneously, thereby reducing the number of data driver modules 41 set in the drive circuit 40, simplifying the structure of the drive circuit 40, reducing the setting cost of the drive circuit 40, and contributing to the narrow bezel of the display device 100. Meanwhile, among the first switch modules 21 and the third switch modules 23 electrically connected to the same data driving module 41, the third switch modules 23 are turned on in a time-sharing manner, and at least part of the turn-on time of the first switch module 21 does not overlap with the turn-on time of the third switch module 23. That is, the turn-on time of the first switch module 21 includes a period when the turn-on time of the third switch module 23 does not overlap. During this non-overlapping period, the data driving module 41 can provide a reset signal, so that the reset signal can be transmitted to the reset signal line 12 through the first switch module 21 only, and written into the pixel circuit P through the reset signal line 12 to reset the pixel circuit P. During the turn-on time of each third switch module 23, the data driving module 41 can provide data signals to each third switch module 23 in a time-sharing manner, so that the data signals can be transmitted to the corresponding first connection signal line 31 through the turn-on third switch module 23, and transmitted and stored in the data signal line 11 through the first connection signal line 31, so that the data signals can be accurately written into the pixel circuit P in the subsequent data writing stage. Thus, while simplifying the structure of the drive circuit 40, the transmission of the reset signal and each data signal does not interfere with each other, which helps to improve the accuracy of the reset signal and each data signal.

[0091] Based on the above embodiments, optionally, refer to Figure 21 As shown, the first non-display area NA1 is also provided with a plurality of fourth switch modules 24 corresponding to a plurality of data drive modules 41; each first switch module 21 of the same first switch group 210 is electrically connected to the switch node through the same fourth switch module 24; the fourth switch module 24 is used to turn on during the reset phase and provide a reset signal to each first switch module 21; wherein, the fourth switch module 24 corresponding to the same data drive module 41 and each third switch module 23 are turned on in a time-sharing manner.

[0092] The fourth switch module 24 is configured to correspond to the data drive module 41. Each data drive module 41 can be electrically connected to a fourth switch module 24, so that the data drive module 41 can provide a reset signal to the fourth switch module 24 during the reset phase, and transmit it to the first switch module 21 through the fourth switch module 24, transmit it to the reset signal line 12 through the first switch module 21, and write it into the pixel circuit P through the reset signal bus 12 to reset the pixel circuit P. Simultaneously, the fourth switch module 24 and each of the third switch modules 23, which are electrically connected to the same data drive module 41, are turned on in a time-sharing manner. The reset signal and data signal provided by the data drive module 41 in a time-sharing manner enable the fourth switch module 24 to be turned on when the data drive module 41 provides a reset signal, and the corresponding third switch module 23 to be turned on when the data drive module 41 provides a data signal line. This ensures that the reset signal transmitted from the fourth switch module 24 to each of the first switch modules 21 and the data signal transmitted from each of the third switch modules 23 to each of the first connection signal lines 31 do not interfere with each other, ensuring the accuracy of the data signal and reset signal provided to the pixel circuit P, so that each pixel circuit P can accurately display light emission and improve the display effect of the display device 100.

[0093] In addition, refer to Figure 21 and Figure 22 When the driving cycle of pixel circuit P also includes a discharge stage T4 after the reset stage T1, in the discharge stage T4, the first switch module 21 can be in the on state and the fourth switch module 24 can be in the off state, so that the reset signals written to each pixel circuit P in the same reset stage can be discharged to the reset transmission bus 50 through the reset signal line 12 and the first switch module 21 in sequence, thereby balancing the reset signals written in each pixel circuit P and ensuring the reset consistency of each pixel circuit P.

[0094] Correspondingly, the drive circuit 40 may also include a fourth control module 404, which can provide a fourth switch control signal to the fourth switch module 24 to control the fourth switch module 24 to be turned on or off.

[0095] Based on the above embodiments, optionally, such as Figure 23 As shown, the display device 100 further includes: a plurality of data storage modules 70; each data storage module 70 is electrically connected to each corresponding data signal line 11; the data storage module 70 is used to store the signals of the data signal line 12; and / or, a plurality of reset storage modules 80; each reset storage module 80 is electrically connected to each corresponding reset signal line 11; the reset storage module 80 is used to store the signals of the reset signal line.

[0096] Specifically, by setting up a data storage module 70 electrically connected to each data signal line 11, the data signals written to the data signal lines 11 in the first stage can be simultaneously stored in the parasitic capacitance of the data signal lines 11 and the data storage module 70, thereby expanding the data signal storage space and ensuring the amount of data signal stored. The data storage module 70 may include a data storage capacitor, one of whose plates can be disposed on the same layer as the data signal lines 11 and electrically connected to them, while the other plate of the data storage capacitor can receive a fixed voltage signal to ensure that the data storage capacitor has a high signal storage capacity.

[0097] Correspondingly, by setting a reset storage module 80 electrically connected to each reset signal line 12, the reset signal written to the reset signal line 12 during the reset phase can be simultaneously stored in the parasitic capacitance of the reset signal line 12 and the reset storage module 80, and the data signal written to the reset signal line 12 during the data writing phase can be simultaneously stored in the parasitic capacitance of the reset signal line 12 and the reset storage module 80. This expands the storage space for reset signals and data signals, ensuring the storage capacity of reset signals and data signals. The reset storage module 80 may include a reset storage capacitor. One plate of the reset storage capacitor can be disposed on the same layer as the reset signal line 12 and electrically connected to the reset signal line 12. The other plate of the reset storage capacitor can receive a fixed voltage signal to ensure that the reset storage capacitor has a high signal storage capacity.

[0098] It is understood that the pixel circuit in the embodiments of the present invention may include at least a current-type driving element and related devices for driving the current-type driving element. Under the premise of realizing the core inventive points of the embodiments of the present invention, the specific structure of the pixel circuit can be designed according to actual needs, and the embodiments of the present invention do not specifically limit it.

[0099] In an alternative embodiment, in conjunction with reference to Figure 23 and Figure 24The pixel circuit P includes a driving module 101, a writing module 102, a coupling module 103, and a light-emitting module 104. The driving cycle of the pixel circuit P also includes a light-emitting phase. The writing module 102 is electrically connected to the reset signal line 12 and the coupling module 103, respectively. The writing module 102 is used to control the reset signal Vref on the reset signal line 12 to be provided to the coupling module 103 during the reset phase, and to control the data signal Vdata on the reset signal line 12 to be provided to the coupling module 103 during the data writing phase. The coupling module 103 is electrically connected to the driving module 101. The coupling module 103 is used to control the grayscale voltage written to the driving module 101 according to the data signal Vdata and the reset signal Vref. The driving module 101 is used to drive the light-emitting module 104 to emit light according to the grayscale voltage during the light-emitting phase.

[0100] Specifically, during the reset phase of the pixel circuit P, the first switch module 21 provides a reset signal Vref to the reset signal line 12. At this time, by controlling the write module 102 in the pixel circuit P to be turned on, the reset signal Vref from the reset signal line 12 can be written to the coupling module 103 through the write module 102. During the data writing phase of the pixel circuit P, the second switch module 22 provides the data signal Vdata stored on the data signal line 11 to the reset signal line 12. At this time, by controlling the write module 102 in the pixel circuit P to be turned on, the data signal Vdata from the reset signal line 12 can be written to the coupling module 103 through the write module 102. Thus, the write module 102 in the pixel circuit P can control the writing of the data signal Vdata and the reset signal Vref respectively, eliminating the need for separate modules for controlling the writing of the data signal Vdata and the reset signal Vref. This simplifies the structure of the pixel circuit P, reduces its size, and improves the resolution of the display device 100.

[0101] After completing the writing of the data signal Vdata and the reset signal Vref, the coupling module 103 can control the grayscale voltage of the writing drive module 101 based on its own coupling effect, combined with the written data signal Vdata and the reset signal Vref. The light-emitting module 104 may include a current-type driving element, which may include, but is not limited to, an organic light-emitting diode. During the light-emitting stage of the pixel circuit P, the grayscale voltage written by the coupling module 103 to the drive module 101 can be converted into a driving current by the drive module 101 and provided to the light-emitting module 104 to drive the light-emitting module 104 to display light emission.

[0102] Based on the above embodiments, optionally, refer to Figure 27 and Figure 28The pixel circuit P may also include a light-emitting control module 105. The light-emitting control module 105 is connected in series with the light-emitting module 104 and the driving module 101 between the first power signal PVDD and the second power signal PVEE. The light-emitting control module 105 is used to control the driving module 101 to generate a driving current during the light-emitting stage and provide it to the light-emitting module 104 to drive the light-emitting module 104 to perform display light emission.

[0103] Based on the above embodiments, optionally, refer to the following: Figure 27 The pixel circuit P may also include an initialization module 106, which is electrically connected to the light-emitting module 104 at the first node N1. The initialization module 106 is used to receive an initialization signal Vrst before the light-emitting stage and initialize the first node N1 to prevent the signal of the first node N1 from affecting the display brightness of the light-emitting module 104 during the light-emitting stage. At the same time, by controlling the initialization module 106 to continuously initialize the first node N1 before the light-emitting stage, abnormal display light emission of the light-emitting module 104 during the non-light-emitting stage before the light-emitting stage can be prevented, thus affecting the display effect of the display device.

[0104] In an alternative embodiment, reference continues. Figure 27 The driving module 101 may include a driving transistor M1. The first terminal of the driving transistor M1 can receive a first power signal PVDD, and the second terminal of the driving transistor M1 can be electrically connected to the light-emitting module 104. The gate of the driving transistor M1 can be electrically connected to the writing module 102 and the coupling module 103 respectively, so that the writing module 102 can transmit the data signal Vdata and the reset signal Vref to the gate of the driving transistor M1 and the coupling module 103. The coupling module 103 can write the grayscale voltage to the gate of the driving transistor M1 according to the data signal Vdata and the reset signal Vref, so that during the light-emitting stage, the driving transistor M1 can generate a driving current according to the signals of its gate and its first terminal, driving the light-emitting module 104 to perform display light emission.

[0105] In an alternative embodiment, reference is made to... Figure 27The writing module 102 may include a writing transistor M2, the coupling module 103 may include a holding capacitor C31 and an auxiliary capacitor C32, the light-emitting control module 105 may include a light-emitting control transistor M3, and the initialization module 106 may include an initialization transistor M4. The first terminal of the writing transistor M2 is electrically connected to the reset signal line to receive the reset signal Vref or data signal Vdata transmitted by the reset signal line. The second terminal of the writing transistor M2 is electrically connected to the gate of the driving transistor M1. The gate of the writing transistor M2 can receive a first scan signal Scan1, allowing the first scan signal Scan1 to control the writing transistor M2 to turn on or off. The first terminal of the light-emitting control transistor M3 can receive a first power supply signal PVDD. The second terminal of the light-emitting control transistor M3 can be electrically connected to the first terminal of the driving transistor M1. The gate of the light-emitting control transistor M3 can receive a light-emitting control signal EM, allowing the light-emitting control signal EM to control the light-emitting control transistor M3 to turn on or off. The initialization transistor M4... The first electrode can receive the initialization signal Vrst, and the second electrode of the initialization transistor M4 can be electrically connected to the light-emitting module 104. The gate of the initialization transistor M4 can receive the second scan signal Scan2, so that the second scan signal Scan3 can control the initialization transistor M4 to be turned on or off. The first plate of the auxiliary capacitor C32 receives the first power supply signal PVDD, and the second plate of the auxiliary capacitor is electrically connected to the first plate of the holding capacitor C31. The second plate of the holding capacitor C31 can be electrically connected to the gate of the driving transistor M1. In this way, the grayscale voltage at the gate of the driving transistor M1 can be determined according to the reset signal Vref and data signal Vdata written by the writing transistor M2, as well as the capacitance of the holding capacitor 31 and the auxiliary capacitor 32.

[0106] In another alternative embodiment, reference continues... Figure 28The pixel circuit P may further include a signal storage module 108 and a compensation module 107; in this case, the driving cycle of the pixel circuit P also includes a discharge phase; the driving module 101 includes a driving transistor; the first terminal of the driving transistor M1 receives a first power supply signal PVDD; the signal storage module 108 is electrically connected to the gate of the driving transistor M1; the signal storage module 108 is used to store the gate signal of the driving transistor M1 to ensure that the driving transistor M1 can continuously generate a driving current according to its gate signal during the light emission phase; the compensation module 107 is electrically connected between the gate of the driving transistor M1 and the second terminal of the driving transistor M1; the compensation module 107 is used to control the driving current during the discharge phase. The threshold voltage of the driving transistor M1 is compensated to the gate of the driving transistor M1 so that the driving current generated by the driving transistor M1 during the light-emitting stage is independent of its threshold voltage, ensuring that the driving transistor M1 accurately generates the driving current and drives the light-emitting module 104 to emit light accurately; the light-emitting control module 105 can be electrically connected between the second terminal of the driving transistor M1 and the light-emitting module 104; the light-emitting control module 105 can be used to control the driving transistor M1 to generate the driving current during the light-emitting stage and provide it to the light-emitting module 104; the writing module 102 can also be used to control the signal stored in the coupling module to discharge to the reset signal line during the discharge stage to balance the signals in each pixel circuit P.

[0107] Based on the above embodiments, optionally, such as Figure 28 As shown, the pixel circuit P may further include an initialization module 106, which is electrically connected to the light-emitting module 104 and the light-emitting control module 105 at the first node N1. The initialization module 106 is used to receive the initialization signal Vrst before the light-emitting stage and initialize the first node N1 to prevent the signal of the first node N1 from affecting the display brightness of the light-emitting module 104 during the light-emitting stage. At the same time, by controlling the initialization module 106 to continuously initialize the first node N1 before the light-emitting stage, abnormal display light emission of the light-emitting module 104 during the non-light-emitting stage before the light-emitting stage can be prevented, thus affecting the display effect of the display device.

[0108] In addition, the light emission control module 105 can also be used to control the formation of a conduction path between the first power signal PVDD and the initialization signal Vrst during the reset phase, so that each node between the first power signal PVDD and the initialization signal Vrst can be accurately initialized.

[0109] Based on the above embodiments, optionally, the driving module 101 may further include a current regulating transistor M6; the first terminal of the current regulating transistor M6 receives a first power supply signal PVDD, and the gate and second terminal of the current regulating transistor M6 are both electrically connected to the first terminal of the driving transistor M1. Thus, by setting the current regulating transistor M6, the current signal can be adjusted to meet the display driving requirements.

[0110] In one exemplary embodiment, reference continues to... Figure 28 The writing module 102 may include a writing transistor M2, the coupling module 103 may include a coupling capacitor C30, the light-emitting control module 105 may include a light-emitting control transistor M3, the initialization module 106 may include an initialization transistor M4, the compensation module 107 may include a compensation transistor M5, and the signal storage module 108 may include a signal storage capacitor Cst. The first terminal of the writing transistor M2 may be electrically connected to the reset signal line to receive the reset signal Vref or data signal Vdata transmitted by the reset signal line. The second terminal of the writing transistor M2 may be electrically connected to the first plate of the coupling capacitor C30, and the gate of the writing transistor may receive the first scan signal Scan1. The second plate of the coupling capacitor C30 may be electrically connected to the gate of the driving transistor M1. The first terminal of the compensation transistor M4 may be electrically connected to the second terminal of the driving transistor M1, and the second terminal of the compensation transistor M4 may be electrically connected to the gate of the driving transistor M1. The gate of the compensation transistor M4 may receive the third scan signal Scan3. The light-emitting control transistor... The first terminal of transistor M3 can be electrically connected to the second terminal of driving transistor M1, the second terminal of light-emitting control transistor M3 can be electrically connected to light-emitting module, and the gate of light-emitting control transistor M3 can receive light-emitting control signal EM; the first terminal of initialization transistor M4 can receive initialization signal Vrst, the second terminal of initialization transistor M4 can be electrically connected to light-emitting control transistor M3 and light-emitting module 104 at the first node, and the gate of initialization transistor M4 can receive second scan signal Scan2; the first plate of signal storage module Cst can receive first power signal, and the second plate of signal storage module Cst can be electrically connected to the gate of driving transistor M1.

[0111] For example, taking a pixel circuit where all transistors are P-type transistors as an example, Figure 29 Is with Figure 28 The diagram shown is a driving timing diagram of a pixel circuit, for reference. Figure 29As shown, during the reset phase T1, the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the light emission control signal EM are all at active levels, causing the write transistor M2, the initialization transistor M4, the compensation transistor M5, the light emission control transistor M3, the drive transistor M1, and the current regulation transistor M6 to all be turned on. This allows the reset signal Vref transmitted by the reset signal line to be written to the coupling capacitor C30 through the write transistor M2. Simultaneously, the initialization current flows from the first power supply signal PVDD to the initialization signal Vrst, causing the initialization current to reset the first terminal, the second terminal, the gate, and N1 of the drive transistor M1, respectively. This results in the gate signal of the drive transistor M1 being the charging signal Vinit of the initialization current, the signal of the second terminal of the drive transistor M1 being the signal Vine charged by the initialization current, and the signal of the first node N1 being the initialization signal Vrst.

[0112] During the discharge phase T4, the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all at active levels, the light emission control signal EM is at an inactive level, the write transistor M1, the compensation transistor M5, and the initialization transistor M4 are all turned on, the light emission control transistor M3 is turned off, and the coupling capacitor C30 and the signal storage capacitor Cst begin to discharge, causing the potentials of the first terminal, the second terminal, and the gate of the driving transistor to rise. At the end of the discharge phase, the voltage across the signal storage capacitor Cst stabilizes near the sum of the threshold voltages of the current regulating transistor M6 and the driving transistor M1. Simultaneously, the reset signal Vref written in the coupling capacitor C30 is discharged through the write transistor M2, causing the voltage of the reset signal Vref stored in each pixel circuit P to be redistributed, ensuring that the voltage of the reset signal Vref written in each pixel circuit remains consistent. At the same time, the data signal Vdata of the pixel circuit P can be written and stored in the data storage capacitor electrically connected to the data signal line corresponding to the pixel circuit P.

[0113] During the data writing phase T2, the first scan signal Scan1 and the second scan signal Scan2 are active, while the third scan signal Scan3 and the light emission control signal EM are inactive. The writing transistor M2 and the initialization transistor M4 are turned on, while other transistors are turned off. The data signal Vdata from the data signal line is transmitted to the reset signal line and then to the first terminal of the writing transistor M2. The writing transistor M1 writes to the coupling capacitor C30, and the coupling effect of the coupling capacitor C30 controls the grayscale voltage of the writing driving transistor M1, so that at the end of the data writing phase, the grayscale voltage Vgray of the writing driving transistor M1 can be: Vgray=Vref±Vref×Cp / (Cp+Cd )+ Vdata×Cd / (Cp+Cd )); Where Cp is the capacitance of the reset storage capacitor electrically connected to the reset signal line, and Cd is the capacitance of the data storage capacitor electrically connected to the data signal line. Simultaneously, the signal from the first plate of the coupling capacitor C30 is again divided by the coupling capacitor C30 and the signal storage capacitor Cst before being written to the gate of the driving transistor M1. This allows the grayscale voltage of the driving transistor M1 in the pixel circuit to be determined by the reset storage capacitor, the data storage capacitor, the coupling capacitor C30, and the signal storage capacitor Cst. Therefore, a suitable grayscale voltage range can be obtained by adjusting different capacitance ratios.

[0114] During the light-emitting stage T5, the light-emitting control signal EM is at an active level, while the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are at an inactive level. The current regulating transistor M6, the driving transistor M1, and the light-emitting control transistor M3 are turned on. The driving transistor M1 generates a driving current according to its gate voltage and provides it to the light-emitting module 104, driving the light-emitting module 104 to emit light for display.

[0115] It should be noted that the above description is merely an example of the driving process of the pixel circuit. In the embodiments of the present invention, the driving process of the pixel circuit is not limited to this and can be designed according to actual needs. The embodiments of the present invention do not impose specific limitations on this.

[0116] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display device, which is used to drive the display device provided in the embodiments of the present invention, thereby enabling time-division writing of reset signals and data signals using a reset signal line. Figure 30 This is a schematic flowchart of a driving method for a display device provided in an embodiment of the present invention. (Refer to...) Figure 30 When the driving cycle of the pixel circuit includes at least a reset phase, a first phase, and a data writing phase, the driving method of the display device includes: S110. During the reset phase, the first switch module is turned on, and the reset signal is transmitted to the reset signal line through the first switch module and written into the pixel circuit through the reset signal line.

[0117] S120. In the first stage, the data signal is transmitted to the data signal line through the first connection signal line.

[0118] S130. During the data writing stage, the second switch module is turned on, and the data signal of the data signal line is transmitted to the reset signal line through the second switch module and written to the pixel circuit through the reset signal line.

[0119] In this embodiment, during the reset phase, the first switch module is turned on, enabling it to provide a reset signal to the reset signal line and write it into the pixel circuit via the reset signal line to reset the pixel circuit. This prevents the signal written to the pixel circuit in the previous driving cycle from affecting the signal writing in the current driving cycle. In the first stage before the data writing phase, the data signal is written and stored on the data signal line via the first connection signal line. When entering the data writing phase, the second switch module is turned on, enabling it to transmit the data signal on the data signal line to the reset signal line and write it into the pixel circuit via the reset signal line. This allows the pixel circuit to accurately display and emit light based on the reset signal and data signal written therein, ensuring that the display device has a high display and light emission effect.

[0120] Based on the above embodiments, optionally, when the first non-display area of ​​the display device is further provided with a driving circuit and multiple third switch modules, and the driving circuit includes multiple data driving modules, the first terminals of the third switch modules and the first terminals of the first switch modules are electrically connected to the corresponding data driving modules, and the second terminals of each third switch module are electrically connected to the corresponding first connection signal lines, the driving method of the display device further includes: In a first stage, the third switch module is turned on, and the third switch module transmits the data signal provided by the data driving module to the first connection signal line. Thus, the time for the data signal provided by the data driving module to be transmitted to the first connection signal line can be controlled by the third switch module, ensuring accurate writing of the data signal.

[0121] Based on the above embodiments, optionally, the first non-display area is further provided with a fourth switch module and at least one reset transmission bus; the fourth switch module is electrically connected to each of the first switch modules through the reset transmission bus; the driving cycle of the pixel circuit further includes a discharge phase; the driving method of the display device further includes: in the reset phase, the fourth switch module is turned on, and a reset signal is provided to the first switch module through the fourth switch module; in the discharge phase, the fourth switch module is turned off, the first switch module is turned on, and the signal written into the pixel circuit through the reset signal line is discharged to the reset transmission bus through the first switch module. Thus, by setting a discharge phase after the reset phase, and controlling the fourth switch module to be turned off and the first switch module to be turned on during the discharge phase, the reset signals written into each pixel circuit in the same reset phase can be discharged sequentially through the reset signal line and the first switch module to the reset transmission bus, thereby balancing the reset signals written into each pixel circuit and ensuring the reset consistency of each pixel circuit.

[0122] Based on the above embodiments, optionally, the first stage of at least a portion of the pixel circuit is located before the reset stage of the pixel circuit; or, the first stage of at least a portion of the pixel circuit is located after the reset stage of the pixel circuit; or, the time of the first stage of at least a portion of the pixel circuit overlaps with the time of the reset stage of the pixel circuit.

[0123] It is understood that the display device driving method provided in the embodiments of the present invention can drive the display device provided in the embodiments of the present invention. For the specific driving process of the display device, please refer to the above description of the display device; it will not be repeated here in the embodiments of the display device driving method. Furthermore, since the display device driving method provided in the embodiments of the present invention can be used to drive the display device provided in the embodiments of the present invention, the display device driving method provided in the embodiments of the present invention can have the same or similar effective effects as the display device provided in the embodiments of the present invention. The similarities can be referred to the above description; they will not be repeated here.

[0124] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display device, characterized in that, include: A display area and a non-display area at least partially surrounding the display area; the non-display area includes a first non-display area located on one side of the display area; The display area is provided with multiple pixel circuits, multiple data signal lines and multiple reset signal lines arranged in an array; at least some of the pixel circuits located in the same column correspond to the same data signal line, and at least some of the pixel circuits located in the same column are electrically connected to the same reset signal line. The first non-display area is provided with multiple first switch modules, multiple second switch modules, and multiple first connection signal lines; each first connection signal line is electrically connected to each of the data signal lines; each first switch module is electrically connected to each of the reset signal lines; and each second switch module is electrically connected between the first connection signal lines and the reset signal lines. The driving cycle of the pixel circuit includes at least a reset phase, a first phase, and a data writing phase; the first switch module is at least used to receive and transmit a reset signal to the reset signal line during the reset phase, and to write the data into the corresponding pixel circuit through the reset signal line. The first connection signal line is at least used to receive and transmit data signals to the data signal line in a first stage before the data writing stage; the second switch module is at least used to transmit the data signals of the data signal line to the reset signal line in the data writing stage, and write them into the corresponding pixel circuit through the reset signal line.

2. The display device according to claim 1, characterized in that, The first non-display area is also provided with a driving circuit; The driving circuit is electrically connected to each of the first connection signal lines and each of the first switch modules respectively; the driving circuit is at least used to provide the reset signal to the first switch module during the reset phase, and to provide the data signal to the first connection signal line during the first phase.

3. The display device according to claim 2, characterized in that, The driving circuit includes multiple data driving modules and a reset signal module; The reset signal module is electrically connected to each of the first switch modules, and the reset signal module is used to provide the reset signal to each of the first switch modules; Each of the data driving modules is electrically connected to each of the first connection signal lines; the data driving module is used to provide the data signal to the first connection signal line.

4. The display device according to claim 3, characterized in that, The first non-display area is further provided with a plurality of gating circuits corresponding to the plurality of data driving modules; the gating circuits are electrically connected between the first connection signal line and the data driving module; The gating circuit includes multiple gating switch modules; the first terminal of each gating switch module in the same gating circuit is electrically connected to the same data driving module; the second terminal of each gating switch module is electrically connected to each of the first connection signal lines respectively; wherein, each gating switch module in the same gating circuit is turned on in a time-division manner.

5. The display device according to claim 3, characterized in that, The first non-display area is also provided with a reset transmission bus; Each of the first switch modules is electrically connected to the reset signal module via the reset transmission bus.

6. The display device according to claim 3, characterized in that, The driving circuit further includes multiple driving amplification modules; the driving amplification modules are electrically connected between the reset signal module and the first switch module. Multiple first switch modules constitute multiple first switch groups, and each first switch group includes at least one first switch module; the first switch modules in the same first switch group are electrically connected to the same drive amplification module; the drive amplification module is used to amplify the reset signal provided by the reset signal module and then provide it to the first switch module.

7. The display device according to claim 6, characterized in that, The drive amplification module includes a Class AB power amplifier; The non-inverting input terminal of the Class AB power amplifier is electrically connected to the reset signal module, the inverting input terminal of the Class AB power amplifier is electrically connected to the output terminal of the Class AB power amplifier, and the output terminal of the Class AB power amplifier is electrically connected to the first switching module.

8. The display device according to claim 6, characterized in that, The shortest distance between the drive amplification module and the edge of the display area is L1, and the shortest distance between the reset signal module and the edge of the display area is L2; ​​wherein, L1 < L2.

9. The display device according to claim 2, wherein the first non-display area is further provided with a plurality of third switch modules; the driving circuit includes a plurality of data driving modules; The first terminal of the third switch module and the first terminal of the first switch module are both electrically connected to the corresponding data driving module; the second terminal of each third switch module is electrically connected to each corresponding first connection signal line. The data driving module is used to provide the reset signal during the reset phase and the data signal during the first phase; The third switch module is used to turn on in the first stage and transmit the data signal to the first connection signal line.

10. The display device according to claim 9, characterized in that, The plurality of first switch modules constitute a plurality of first switch groups corresponding to the plurality of data drive modules; the plurality of third switch modules constitute a plurality of third switch groups corresponding to the plurality of data drive modules; Each of the first switch modules in the same first switch group is electrically connected to the same data driving module at the same switch node; The first end of each of the third switch modules in the same third switch group is electrically connected to the same data driving module; the second end of each of the third switch modules is electrically connected to each of the first connection signal lines; each of the third switch modules in the same third switch group is turned on in a time-division manner, and among the first switch module and the third switch module electrically connected to the same data driving module, at least part of the turn-on time of the first switch module does not overlap with the turn-on time of the third switch module.

11. The display device according to claim 10, characterized in that, The first non-display area is also provided with a plurality of fourth switch modules corresponding to the plurality of data driving modules; Each of the first switch modules in the same first switch group is electrically connected to the switch node through the same fourth switch module; The fourth switch module is used to turn on during the reset phase and provide the reset signal to each of the first switch modules; Among them, the fourth switch module and each of the third switch modules corresponding to the same data driving module are turned on in a time-division manner.

12. The display device according to claim 1, characterized in that, The first non-display area is also provided with a fourth switch module and at least one reset transmission bus; The fourth switch module is electrically connected to each of the first switch modules via the reset transmission bus; the fourth switch module is used to receive the reset signal during the reset phase and control the reset signal to be transmitted to each of the first switch modules via the reset transmission bus. The driving cycle of the pixel circuit also includes a discharge phase; the first switch module is further configured to control the signal written into the pixel circuit through the reset signal line to discharge to the reset transmission bus during the discharge phase; the fourth switch module is further configured to be in an off state during the discharge phase.

13. The display device according to claim 1, characterized in that, Also includes: Multiple data storage modules; Each of the data storage modules is electrically connected to each of the corresponding data signal lines; The data storage module is used to store the signals of the data signal line; And / or, Multiple reset storage modules; Each of the reset storage modules is electrically connected to each of the reset signal lines; the reset storage module is used to store the signals of the reset signal lines.

14. The display device according to claim 1, characterized in that, Within the display area, the data signal lines are not connected to the pixel circuits.

15. The display device according to claim 1, characterized in that, The data signal line and the reset signal line are arranged on the same layer.

16. The display device according to claim 1, characterized in that, The pixel circuit includes a driving module, a writing module, a coupling module, and a light-emitting module; the driving cycle of the pixel circuit also includes a light-emitting phase. The writing module is electrically connected to the reset signal line and the coupling module respectively; the writing module is used to control the reset signal on the reset signal line to be provided to the coupling module during the reset phase, and to control the data signal on the reset signal line to be provided to the coupling module during the data writing phase; The coupling module is electrically connected to the driving module; the coupling module is used to control the grayscale voltage written to the driving module according to the data signal and the reset signal. The driving module is used to drive the light-emitting module to emit light according to the grayscale voltage during the light-emitting stage.

17. The display device according to claim 16, characterized in that, The pixel circuit also includes a signal storage module, a compensation module, and a light emission control module; the driving cycle of the pixel circuit also includes a discharge phase. The driving module includes a driving transistor; the first terminal of the driving transistor receives a first power signal. The signal storage module is electrically connected to the gate of the driving transistor; The signal storage module is used to store the gate signal of the driving transistor; The compensation module is electrically connected between the gate of the driving transistor and the second terminal of the driving transistor; the compensation module is used to control the threshold voltage of the driving transistor to be compensated to the gate of the driving transistor during the discharge phase. The light-emitting control module is electrically connected between the second terminal of the driving transistor and the light-emitting module; the light-emitting control module is used to control the driving transistor to generate a driving current during the light-emitting stage and provide it to the light-emitting module. The writing module is also used to control the signal stored in the coupling module to discharge to the reset signal line during the discharge phase.

18. The display device according to claim 17, characterized in that, The pixel circuit also includes an initialization module; The initialization module is electrically connected to the light-emitting module and the light-emitting control module at the first node; the initialization module is used to receive an initialization signal before the light-emitting stage and to initialize the first node. The light-emitting control module is also used to control the formation of a conduction path between the first power signal and the initialization signal during the reset phase.

19. The display device according to claim 17, characterized in that, The drive module also includes a current regulating transistor; The first terminal of the current regulating transistor receives a first power supply signal, and the second terminal and gate of the current regulating transistor are both electrically connected to the first terminal of the driving transistor.

20. The display device according to claim 1, characterized in that, At least a portion of the first stage of the pixel circuit is located before the reset stage of the pixel circuit; or, The first stage of at least a portion of the pixel circuit is located after the reset stage of the pixel circuit.

21. The display device according to claim 1, characterized in that, The timing of at least a portion of the first phase of the pixel circuit overlaps with the timing of the reset phase of the pixel circuit.

22. The display device according to claim 1, characterized in that, The display device is a silicon-based organic light-emitting display device.

23. A driving method for a display device, characterized in that, The display device includes: a display area and a non-display area at least partially surrounding the display area; the non-display area includes a first non-display area located on one side of the display area; the display area is provided with a plurality of pixel circuits, a plurality of data signal lines, and a plurality of reset signal lines arranged in an array; at least a portion of the pixel circuits located in the same column correspond to the same data signal line, and at least a portion of the pixel circuits located in the same column are electrically connected to the same reset signal line; the first non-display area is provided with a plurality of first switch modules, a plurality of second switch modules, and a plurality of first connection signal lines; each first connection signal line is electrically connected to each corresponding data signal line; each first switch module is electrically connected to each corresponding reset signal line; the second switch modules are electrically connected between the first connection signal lines and the reset signal lines; the driving cycle of the pixel circuits includes at least a reset phase, a first phase, and a data writing phase; the driving method of the display device includes: During the reset phase, the first switch module is turned on, and the reset signal is transmitted to the reset signal line through the first switch module and written into the pixel circuit through the reset signal line. In the first stage, the data signal is transmitted to the data signal line through the first connection signal line; During the data writing phase, the second switch module is turned on, and the data signal of the data signal line is transmitted to the reset signal line through the second switch module, and then written into the pixel circuit through the reset signal line.

24. The driving method for the display device according to claim 23, characterized in that, The first non-display area is also provided with a driving circuit and multiple third switch modules; the driving circuit includes multiple data driving modules; the first terminal of the third switch module and the first terminal of the first switch module are both electrically connected to the corresponding data driving module; The second terminal of each of the third switch modules is electrically connected to the corresponding first connection signal line; The driving method for the display device further includes: In the first stage, the third switch module is turned on, and the third switch module transmits the data signal provided by the data driving module to the first connection signal line.

25. The driving method for the display device according to claim 23, characterized in that, The first non-display area is also provided with a fourth switch module and at least one reset transmission bus; the fourth switch module is electrically connected to each of the first switch modules through the reset transmission bus; The driving cycle of the pixel circuit further includes a discharge phase; the driving method of the display device further includes: During the reset phase, the fourth switch module is turned on, and the reset signal is provided to the first switch module through the fourth switch module; During the discharge phase, the fourth switch module is disconnected, the first switch module is turned on, and the signal written into the pixel circuit through the reset signal line is discharged to the reset transmission bus through the first switch module.

26. The driving method for the display device according to claim 23, characterized in that, At least a portion of the first stage of the pixel circuit is located before the reset stage of the pixel circuit; or, The first stage of at least a portion of the pixel circuit is located after the reset stage of the pixel circuit; or, The timing of at least a portion of the first phase of the pixel circuit overlaps with the timing of the reset phase of the pixel circuit.

Images