A high specific capacity chip tantalum capacitor and a method for manufacturing the same

Abstract

The application discloses a high specific capacity chip tantalum capacitor and a preparation method thereof, and belongs to the technical field of capacitor preparation. Mainly comprising: a gradient porous tantalum anode, a composite interface oxide film, a composite solid electrolyte layer, a multilayer shielding cathode and a synergistic packaging layer. By constructing the integrated synergistic system of the gradient porous tantalum anode, the composite interface oxide film, the composite solid electrolyte layer, the multilayer shielding cathode and the synergistic packaging layer, the technical bottleneck that the specific capacity and performance of the chip tantalum capacitor are difficult to balance is broken. The three-stage particle size design and in-situ doping modification of the gradient porous anode realize the balance of porosity and mechanical strength. The synergistic application of pulse oxidation and ALD composite modification film effectively reduces the interface defects.

Description

Technical Field

[0001] This invention relates to the field of capacitor manufacturing technology, and in particular to a high specific capacitance tantalum chip capacitor and its manufacturing method. Background Technology

[0002] Tantalum chip capacitors are surface-mount capacitors that use tantalum metal as the anode and tantalum pentoxide as the dielectric layer. Due to their advantages such as small size, large capacitance, low leakage current, good high-frequency characteristics, and high operating stability, they are widely used in circuits of portable electronic devices, communication power supplies, automotive electronics, and aerospace. They are mainly used for power filtering, decoupling, bypassing, and energy storage, thereby effectively improving the electrical performance and reliability of the system.

[0003] The prior art patent document with authorization announcement number CN118016450A discloses "a chip tantalum electrolytic capacitor and its preparation method". In the preparation method of the chip tantalum electrolytic capacitor, the present invention uses an aqueous solution of (3-mercaptopropyl)trimethoxysilane to treat the surface of the tantalum pentoxide dielectric film, thereby laying the foundation for the formation of a directionally arranged carbon nanotube array on the surface of the tantalum pentoxide dielectric film.

[0004] The patent document with authorization announcement number CN119008248A discloses "a chip tantalum capacitor and its preparation method". The preparation method includes the following steps: pressing tantalum metal powder into tantalum blocks, sintering the tantalum blocks in a vacuum environment; forming an oxide film on the surface of the sintered tantalum blocks, depositing MnO2 on the surface of the oxide film, coating the surface of the MnO2 layer with a graphite layer to obtain a tantalum core, then immersing the tantalum core in a surface treatment agent; then performing drying and baking treatments; impregnating a layer of silver paste on the graphite layer, and finally performing a curing treatment.

[0005] While existing technologies have optimized the performance of chip tantalum capacitors through methods such as silane coupling agent surface treatment and carbon nanotube-conductive polymer composites, and can further enhance product molding resistance, reduce leakage current and equivalent series resistance, and optimize high and low temperature characteristics and temperature shock resistance by combining carbon nanotube arrays with composite conductive films and composite carbon layers, existing technologies suffer from several drawbacks. The anodes often use single-size tantalum powder, resulting in poor pore connectivity and limited specific capacitance improvement. Defects at the oxide film and electrolyte interface lead to high leakage current and insufficient stability. The encapsulation materials exhibit poor high-temperature resistance and are prone to cracking and failure due to mismatched thermal expansion coefficients. Furthermore, the manufacturing process is cumbersome with poor parameter coordination, resulting in low product consistency and yield. The cathode structures are simple, with weak anti-interference capabilities and poor high-frequency performance. These technologies fail to simultaneously achieve miniaturization, high specific capacitance, high temperature resistance, and high reliability, making it difficult to meet the demands of high-end electronic devices. Summary of the Invention

[0006] Purpose of the invention: The purpose of this invention is to provide a high specific capacitance tantalum chip capacitor and its preparation method, so as to solve the problems mentioned in the background art.

[0007] Technical Solution: To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a high-capacitance chip tantalum capacitor includes: a gradient porous tantalum anode, a composite interface oxide film, a composite solid electrolyte layer, a multilayer shielded cathode, and a co-encapsulation layer; the overall size is controlled within 0.8mm × 0.4mm × 0.3mm, wherein the gradient porous tantalum anode is a three-level gradient particle size composite doping structure, the composite interface oxide film is a two-layer composite structure, the composite solid electrolyte layer is a polymer-inorganic nanoparticle-ionic liquid composite system, the multilayer shielded cathode is a three-layer gradient shielding structure, and the co-encapsulation layer is a ceramic-epoxy resin composite layer.

[0008] Preferably, the gradient porous tantalum anode is composed of tantalum powder with three particle sizes from the center to the surface: 1.2-1.5µm, 0.5-0.8µm, and 0.1-0.3µm, in a mass ratio of 3:4:3. It is in-situ doped with 0.8%-1.2% of the rare earth element holmium and 0.3%-0.5% of boron. The anode uses an embedded lead-out electrode with a tantalum wire diameter of 0.05-0.08mm and an embedding depth of 2 / 3 of the anode height. The composite interface oxide film includes an inner Ta2O5 oxide film and an outer Al2O3-TiO2 composite modified film. The thickness of the inner layer is 80-100nm, and the thickness of the outer layer is 20-30nm. The molar ratio of Al2O3 to TiO2 is 7:3. The inner layer is prepared by pulsed anodizing and the outer layer is prepared by atomic layer deposition.

[0009] Preferably, the composite solid electrolyte layer uses polyimide as the matrix, composite nano-ZrO2 particles, 1-ethyl-3-methylimidazolium tetrafluoroborate ionic liquid, and γ-aminopropyltriethoxysilane modifier, and is formed by vacuum impregnation in-situ curing process, with a total thickness of 150-180 nm; the multi-layer shielded cathode consists of a Ti-Ni alloy contact layer, a Cu-Ni-Zn alloy shielding layer, and an Au protective layer from the inside out, and adopts a side-leading hemispherical bump structure; the synergistic encapsulation layer is composed of AlN ceramic powder, maleic anhydride modified epoxy resin, and nano-SiC particles, and adopts a groove-type step-by-step curing encapsulation structure.

[0010] According to another aspect of the present invention, a method for manufacturing a high-capacitance tantalum chip capacitor is provided, comprising the following steps: S1. Select three grades of high-purity tantalum powder with particle sizes of 1.2-1.5µm, 0.5-0.8µm, and 0.1-0.3µm. Vacuum anneal at 800-850℃ for 2 hours. Mix them in a mass ratio of 3:4:3 and add 0.8%-1.2% holmium powder, 0.3%-0.5% boron powder, and 2%-3% forming agent. After ultrasonic dispersion, melt doping is carried out at 1800-1900℃ under vacuum conditions ≤10Pa. Rapid cooling is then performed to obtain tantalum-holmium-boron solid solution powder. The solid solution powder is bidirectionally pressed into shape and embedded into a tantalum wire electrode. After gradient heating and sintering, a gradient porous tantalum anode is obtained for later use.

[0011] S2. After ultrasonic cleaning and vacuum drying of the gradient porous tantalum anode with anhydrous ethanol, the inner Ta2O5 oxide film is prepared by pulse anodizing in oxalic acid solution. Then, the anode is placed in an atomic layer deposition device to prepare an outer Al2O3-TiO2 composite modified film using trimethylaluminum and titanium tetrachloride as precursors, and the anode with composite interface oxide film is obtained for later use.

[0012] S3. Prepare an electrolyte precursor solution by mixing polyimide, nano ZrO2 particles, ionic liquid and modifier in a certain proportion. Place the anode with composite interface oxide film under vacuum of ≤10Pa and 80-100℃ to vacuum impregnate the precursor solution, and then solidify it in situ at 180-200℃ for 2-3h to form a composite solid electrolyte layer. Finally, the intermediate is obtained for later use.

[0013] S4. Place the intermediate into a magnetron sputtering device to prepare a Ti-Ni alloy inner contact layer, prepare a Cu-Ni-Zn alloy middle shielding layer by sulfate electroplating, and then prepare an Au outer protective layer by atomic layer deposition. Use laser etching and electroplating processes to prepare a side hemispherical bump lead-out structure to obtain a core with a multi-layer shielded cathode for later use.

[0014] S5. Prepare inner and outer layer encapsulation materials by mixing AIN ceramic powder, modified epoxy resin and nano SiC particles in a certain proportion. Use vacuum stepwise curing process to encapsulate the inner and outer layers in sequence. After preparing heat dissipation grooves on the surface of the encapsulation layer, laser trimming is performed to ensure that the product size is precisely controlled within 0.8mm×0.4mm×0.3mm, and the encapsulated core is obtained for later use.

[0015] S6. After encapsulation, the core is soldered with the anode tantalum wire and the cathode bump. After soldering, it is ultrasonically cleaned and vacuum dried to obtain the initial product. The initial product is screened by specific capacitance, leakage current and high temperature resistance performance tests. Qualified products are vacuum packaged and put into storage to obtain the finished high specific capacitance chip tantalum capacitor.

[0016] Preferably, in step S1, the purity of the tertiary tantalum powder is ≥99.99%, the bidirectional pressing pressure is 80-100MPa, and the pressing time is 10-15s; the gradient sintering is carried out in three stages, namely, holding at 200-400℃ for 1h, holding at 800-900℃ for 2h, and holding at 1200-1300℃ for 3h, with a heating rate of 50℃ / min.

[0017] Preferably, in S2, the pulsed anodizing voltage is 120-150V, the frequency is 500-800Hz, and the duty cycle is 30%-40%; the atomic layer deposition temperature is 250-300℃, and the deposition cycle is 100-120.

[0018] Preferably, in S3, the mass percentages of each component of the electrolyte precursor are: 60%-65% polyimide, 15%-20% nano ZrO2, 10%-15% ionic liquid, and 5%-8% modifier; the vacuum impregnation time is 30-40 min, and the in-situ curing heating rate is 20℃ / min.

[0019] Preferably, in step S4, the magnetron sputtering power is 150-200W, the Ti-Ni alloy contact layer thickness is 30-40nm, and the electroplating current density is 1-2A / dm². 2 The Cu-Ni-Zn alloy shielding layer has a thickness of 50-60nm; the atomic layer deposition temperature is 200-250℃; the Au protective layer has a thickness of 10-15nm; and the bump diameter is 0.1-0.12mm.

[0020] Preferably, in step S5, the mass percentage of each component of the encapsulation material is 40%-45% AlN ceramic powder, 55%-60% modified epoxy resin, and 2%-3% nano SiC; the inner layer encapsulation is cured at 150-160℃ for 1 hour, the outer layer encapsulation is cured at 180-190℃ for 2 hours, the encapsulation vacuum degree is ≤5Pa, and the width of the heat dissipation groove is 0.05-0.08mm and the depth is 0.03-0.05mm.

[0021] Preferably, in step S6, the pin soldering temperature is 250-280℃, the soldering time is 5-8s, the performance screening criteria are specific capacitance ≥2200µF·V / g, leakage current ≤3µA / g, and high temperature resistance ≥150℃; the finished product storage temperature is 10-30℃, and the relative humidity is ≤60%.

[0022] Beneficial Effects: By constructing an integrated synergistic system comprising a gradient porous tantalum anode, a composite interface oxide film, a composite solid electrolyte layer, a multi-layer shielded cathode, and a synergistic encapsulation layer, this invention overcomes the technical bottleneck of balancing specific capacitance and performance in chip tantalum capacitors. The three-level particle size design and in-situ doping modification of the gradient porous anode achieve a balance between porosity and mechanical strength. The synergistic application of pulse oxidation and ALD composite modification film effectively reduces interface defects. The vacuum impregnation and in-situ curing process of the composite solid electrolyte ensures the unity of ionic conductivity and insulation. The combination of the multi-layer shielded cathode and the synergistic encapsulation layer with matched thermal expansion coefficients significantly improves electromagnetic shielding effectiveness and high-temperature stability. This invention achieves miniaturization and high capacitance while solving problems such as high leakage current, poor high-temperature resistance, and insufficient high-frequency performance in traditional products. The synergistic linkage of the manufacturing process ensures high product consistency and high yield, providing support for the upgrading of tantalum capacitors for high-end electronic devices. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0024] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example 1

[0025] A high-capacitance tantalum chip capacitor and its fabrication method are described below: S1. Select high-purity tantalum powder of three grades with particle sizes of 1.2µm, 0.5µm, and 0.1µm (purity ≥99.99%), vacuum anneal at 800℃ for 2 hours, mix them in a 3:4:3 mass ratio, add 0.8% holmium powder, 0.3% boron powder, and 2% forming agent, ultrasonically disperse, and then melt-dopide at 1800℃ and vacuum degree ≤10Pa. Rapidly cool to obtain tantalum-holmium-boron solid solution powder. Biaxially press the solid solution powder into shape at a pressing pressure of 80MPa and a pressing time of 10s, while embedding a tantalum wire electrode with a diameter of 0.05mm to a depth of 2 / 3 of the anode height. Use gradient heating sintering at a heating rate of 50℃ / min, successively holding at 200℃ for 1 hour, 800℃ for 2 hours, and 1200℃ for 3 hours. After cooling, obtain a gradient porous tantalum anode for later use.

[0026] S2. After ultrasonic cleaning and vacuum drying of the gradient porous tantalum anode with anhydrous ethanol, the inner Ta2O5 oxide film is prepared by pulse anodizing in oxalic acid solution at a voltage of 120V, a frequency of 500Hz, and a duty cycle of 30%. An 80nm thick inner oxide film is obtained. Then, atomic layer deposition is performed at 250℃ for 100 cycles to obtain a 20nm thick Al2O3-TiO2 composite modified film, resulting in an anode with a composite interface oxide film, which is ready for use.

[0027] S3. Prepare an electrolyte precursor solution with a mass ratio of 60% polyimide, 15% nano ZrO2, 10% ionic liquid, and 5% modifier. Place the anode under vacuum impregnation at 80℃ and ≤10Pa for 30 min, then heat it to 180℃ at 20℃ / min and cure it in situ for 2 h to form a 150nm thick composite solid electrolyte layer. The final intermediate is then prepared for use.

[0028] S4. A 30 nm thick Ti-Ni alloy inner contact layer was prepared by magnetron sputtering of the intermediate at 150 W; with an A / dm 2 A 50nm thick Cu-Ni-Zn alloy middle shielding layer was prepared by current density electroplating; a 10nm thick Au protective layer was prepared by atomic layer deposition at 200℃; a side hemispherical bump lead-out structure with a diameter of 0.1mm was prepared to obtain a core with a multi-layer shielded cathode for later use.

[0029] S5. Prepare encapsulation material by mixing 40% AlN ceramic powder, 55% modified epoxy resin, and 2% nano-SiC. Under vacuum conditions ≤5Pa, cure the inner layer encapsulation at 150℃ for 1 hour and the outer layer encapsulation at 180℃ for 2 hours to prepare a heat dissipation groove with a width of 0.05mm and a depth of 0.03mm. Trim the groove to the standard size with a laser to obtain the encapsulated core for later use.

[0030] S6. After soldering the pins at 250℃ for 5 seconds, ultrasonic cleaning and vacuum drying are performed to obtain the initial product. Qualified products are screened according to standards and vacuum-packed and stored at 10℃ and relative humidity ≤60% to obtain the finished product. Example 2

[0031] A high-capacitance tantalum chip capacitor and its fabrication method are described below: S1. Select high-purity tantalum powder of three grades with particle sizes of 1.35µm, 0.65µm, and 0.2µm (purity ≥99.99%), vacuum anneal at 825℃ for 2 hours, mix them in a 3:4:3 mass ratio, add 1.0% holmium powder, 0.4% boron powder, and 2.5% forming agent, ultrasonically disperse, and melt-dopide at 1850℃ and vacuum degree ≤10Pa. Rapidly cool to obtain tantalum-holmium-boron solid solution powder. Biaxially press the solid solution powder into shape at a pressing pressure of 90MPa and a pressing time of 12s, and simultaneously embed a tantalum wire electrode with a diameter of 0.065mm to an embedding depth of 2 / 3 of the anode height. Use gradient heating sintering at a heating rate of 50℃ / min, successively holding at 300℃ for 1 hour, 850℃ for 2 hours, and 1250℃ for 3 hours. After cooling, obtain a gradient porous tantalum anode for later use.

[0032] S2. After ultrasonic cleaning and vacuum drying of the gradient porous tantalum anode with anhydrous ethanol, the inner Ta2O5 oxide film is prepared by pulse anodizing in oxalic acid solution with a voltage of 135V, a frequency of 650Hz and a duty cycle of 35%, resulting in a 90nm thick inner oxide film. Then, atomic layer deposition is performed at 275℃ for 110 cycles to obtain a 25nm thick Al2O3-TiO2 composite modified film, resulting in an anode with a composite interface oxide film, which is ready for use.

[0033] S3. Prepare an electrolyte precursor solution with a mass ratio of 62.5% polyimide, 17.5% nano ZrO2, 12.5% ​​ionic liquid, and 6.5% modifier. Place the anode under vacuum conditions of 90℃ and ≤10Pa for 35 min, and then heat it to 190℃ at 20℃ / min to cure it in situ for 2.5 h to form a 165nm thick composite solid electrolyte layer. The final intermediate is then prepared for use.

[0034] S4. A 35 nm thick Ti-Ni alloy inner contact layer was prepared by magnetron sputtering of the intermediate at 175 W; with a sputtering speed of 1.5 A / dm 2 A 55nm thick Cu-Ni-Zn alloy middle shielding layer was prepared by current density electroplating; a 12.5nm thick Au protective layer was prepared by atomic layer deposition at 225℃; a side hemispherical bump lead-out structure with a diameter of 0.11mm was prepared to obtain a core with a multi-layer shielded cathode for later use.

[0035] S5. Prepare encapsulation material using 42.5% AlN ceramic powder, 57.5% modified epoxy resin, and 2.5% nano-SiC. Under vacuum conditions ≤5Pa, cure the inner layer encapsulation at 155℃ for 1 hour and the outer layer encapsulation at 185℃ for 2 hours to prepare a heat dissipation groove with a width of 0.065mm and a depth of 0.04mm. Trim the groove to the standard size with a laser to obtain the encapsulated core for later use.

[0036] S6. After soldering the pins at 265℃ for 6.5s, ultrasonic cleaning and vacuum drying are performed to obtain the initial product. Qualified products are screened according to standards and vacuum-packed and stored at 20℃ and relative humidity ≤60% to obtain the finished product. Example 3

[0037] A high-capacitance tantalum chip capacitor and its fabrication method are described below: S1. Select high-purity tantalum powder of three grades with particle sizes of 1.5µm, 0.8µm, and 0.3µm (purity ≥99.99%), vacuum anneal at 850℃ for 2 hours, mix them in a 3:4:3 mass ratio, add 1.2% holmium powder, 0.5% boron powder, and 3% forming agent, ultrasonically disperse, and then melt-dopide at 1900℃ and vacuum degree ≤10Pa. Rapidly cool to obtain tantalum-holmium-boron solid solution powder. Biaxially press the solid solution powder into shape at a pressing pressure of 100MPa and a pressing time of 15s, and simultaneously embed a tantalum wire electrode with a diameter of 0.08mm to an embedding depth of 2 / 3 of the anode height. Use gradient heating sintering at a heating rate of 50℃ / min, successively holding at 400℃ for 1 hour, 900℃ for 2 hours, and 1300℃ for 3 hours. After cooling, obtain a gradient porous tantalum anode for later use.

[0038] S2. After ultrasonic cleaning and vacuum drying of the gradient porous tantalum anode with anhydrous ethanol, the inner Ta2O5 oxide film is prepared by pulse anodizing in oxalic acid solution at a voltage of 150V, a frequency of 800Hz, and a duty cycle of 40%. A 100nm thick inner oxide film is obtained. Then, atomic layer deposition is performed at 300℃ for 120 cycles to obtain a 30nm thick Al2O3-TiO2 composite modified film, resulting in an anode with a composite interface oxide film, which is ready for use.

[0039] S3. Prepare an electrolyte precursor solution with a mass ratio of 65% polyimide, 20% nano ZrO2, 15% ionic liquid, and 8% modifier. Place the anode under vacuum impregnation at 100℃ and ≤10Pa for 40 min, then heat it to 200℃ at 20℃ / min and cure it in situ for 3 h to form a 180nm thick composite solid electrolyte layer. The final intermediate is then prepared for use.

[0040] S4. A 40 nm thick Ti-Ni alloy inner contact layer was prepared by 200 W magnetron sputtering of the intermediate; with a sputtering rate of 2 A / dm 2 A 60nm thick Cu-Ni-Zn alloy middle shielding layer was prepared by current density electroplating; a 15nm thick Au protective layer was prepared by atomic layer deposition at 250℃; a side hemispherical bump lead-out structure with a diameter of 0.12mm was prepared to obtain a core with a multi-layer shielded cathode for later use.

[0041] S5. Prepare encapsulation material by mixing 45% AlN ceramic powder, 60% modified epoxy resin, and 3% nano-SiC. Under vacuum conditions ≤5Pa, cure the inner layer encapsulation at 160℃ for 1 hour and the outer layer encapsulation at 190℃ for 2 hours to prepare a heat dissipation groove with a width of 0.08mm and a depth of 0.05mm. Trim the groove to the standard size with a laser to obtain the encapsulated core for later use.

[0042] S6. After soldering the pins at 280℃ for 8 seconds, ultrasonic cleaning and vacuum drying are performed to obtain the initial product. Qualified products are screened according to standards and vacuum-packed and stored at 30℃ and relative humidity ≤60% to obtain the finished product.

[0043] Comparative Example 1 The difference between Comparative Example 1 and Examples 1-3 is as follows: Comparative Example 1 (refer to the prior art document CN118016450A in the background section) is specifically: Tantalum metal powder with a particle size of 1~10µm was selected, pressed into blocks, and then subjected to a vacuum of 7.5×10⁻⁶ at 2000℃. -3 Sintering under Pa conditions yields a porous tantalum anode body; the tantalum anode body is immersed in a 10% (w / w) ammonium dihydrogen phosphate forming solution, and the voltage is increased to 3 times the rated voltage under constant current and then decreased under constant voltage. After heat treatment at 450℃, a Ta2O5 dielectric film is formed on the surface.

[0044] Prepare an ethanol mixture solution containing 5% pyrrole and 10% ammonium persulfate by mass. Immerse the tantalum anode with a Ta2O5 dielectric film in the solution for 8 min and keep it at 150±10℃ for 30±5 min to allow pyrrole to polymerize and form an inner layer of polypyrrole. After cleaning with methanol, dry the anode.

[0045] The product was immersed in a 1% (3-mercaptopropyl)trimethoxysilane aqueous solution, and then immersed in a 0.5% (3 ...

[0046] A mixed solution containing 5% pyrrole, 4% p-nitrobenzyl alcohol, and 20% sodium naphthalenesulfonate was prepared. A tantalum block was used as the anode and a stainless steel plate as the cathode. A three-stage electroplating process was adopted (current 0.2mA / piece → 0.3mA / piece → 0.4mA / piece, time 60min → 60min → 120min) to form a polypyrrole-carbon nanotube composite polymer conductive film.

[0047] A conductive carbon paste with a graphene to carbon nanotube mass ratio of 6:4 was prepared. A tantalum block was impregnated with the carbon paste and dried to form a composite carbon layer. Then, it was impregnated with silver paste and dried to obtain a tantalum core block. The tantalum core block was mounted on a copper lead frame, and tantalum wires were welded to the lead frame. The capacitor was then encapsulated with epoxy resin and cured at 150°C for 2 hours to obtain a chip tantalum electrolytic capacitor.

[0048] Comparative Example 2 The difference between Comparative Example 2 and Examples 1-3 is as follows: Comparative Example 2 (refer to the prior art document CN119008248A in the background section) specifically is: Tantalum metal powder is pressed into tantalum blocks, at a density of 2×10⁻⁶. -3 Pa ~ 4 × 10 -3 Porous tantalum blocks were obtained by sintering in a vacuum environment at 1390~1450℃ for 20~40 min.

[0049] A Ta2O5 dielectric oxide film was formed on the surface of a sintered tantalum block using an anodic oxidation method, and then a MnO2 layer was deposited on the surface of the dielectric film using a thermal decomposition method.

[0050] A tantalum core is obtained by coating a graphite layer on the surface of a MnO2 layer. The tantalum core is then immersed in a surface treatment agent prepared with silane coupling agent, anhydrous ethanol and deionized water (ethanol-water volume ratio 4~7:4~1, silane coupling agent mass concentration 15%~25%, hydrolysis 0.5~1h) for 1~10min.

[0051] Dry the impregnated tantalum core at room temperature for 10-30 minutes, and then bake it at 150-200℃ for 30-60 minutes.

[0052] Silver paste is impregnated onto the treated graphite layer to form a 0.15~0.30 mm thick silver paste layer, and dried at room temperature for 15~30 min until surface dry.

[0053] The tantalum core is cured at 180~210℃ for 20~40 min. After the preparation is completed, the capacitance and withstand voltage are tested to obtain the chip tantalum capacitor.

[0054] Comparative Example 3 The difference between Comparative Example 3 and Examples 1-3 is as follows: Comparative Example 3 (refer to prior art document CN113077987B) is specifically: Prepare a hydrofluoric acid alcohol solution with a mass fraction of 1% to 8% (the solvent is at least one of ethanol, isopropanol, and n-butanol), and add citric acid with a mass fraction of 0.01% to 0.1%.

[0055] Connect the tantalum foil to the positive terminal of the power supply and the platinum electrode to the negative terminal, control the parallel distance between the two electrodes to 1~3cm, and immerse the tantalum foil to a depth 30%~70% deeper than the platinum electrode. Apply a DC voltage of 20~80V for electrochemical etching for 0.5~7h to obtain the chip tantalum electrolytic capacitor core.

[0056] The capacitor core is placed in a 0.1% phosphoric acid solution and energized at 80°C with a voltage of 5-90V for 3-5 hours to obtain an energized anode.

[0057] Prepare an aqueous solution containing 0.02-0.1 mol / L pyrrole, p-benzylsulfonic acid, and ammonium persulfate at 0-5℃ (pyrrole: p-benzylsulfonic acid = 1:2, pyrrole: ammonium persulfate = 5:1). Use pyrrole solutions of increasing concentration to perform in-situ polymerization on the anode 4-8 times, with each reaction lasting 10 minutes, followed by cleaning and drying.

[0058] After the coating is completed, it is vacuum dried, and then carbon and silver layers are coated in sequence to obtain a chip tantalum electrolytic capacitor with a total thickness of 30~100µm.

[0059] To illustrate the use of the capacitors described in this invention, tests were conducted on the capacitors prepared in Examples 1-3 and Comparative Examples 1-3. The test methods are as follows: Specific volume test: Referring to GB / T2886-2017 "Tantalum Capacitors", the capacitance was measured using an LCR digital bridge at 1 kHz and 1.0 V, and the specific capacitance (µF・V / g) was calculated in conjunction with the anode mass.

[0060] Leakage current test: According to GB / T2886-2017, after applying the rated voltage to the capacitor for 5 minutes, the leakage current value (µA / g) is measured using a digital microammeter.

[0061] High temperature stability test: The sample was aged in a 150℃ constant temperature chamber for 1000 hours. The capacitance value before and after aging was tested, and the capacitance value change rate (%) was calculated. The smaller the change rate, the better the high temperature stability.

[0062] Electromagnetic shielding effectiveness test: The electromagnetic shielding effectiveness (dB) of the capacitor was tested in the 100kHz~1MHz frequency band using a vector network analyzer.

[0063] Mechanical strength test: Using a universal testing machine, radial pressure is applied to the sample, and the critical pressure value (MPa) at which the sample breaks is recorded.

[0064] The test results are shown in the table below: As can be seen from the comparison of the examples and comparative examples, this invention achieves synergistic optimization of anode porosity and mechanical strength by designing a gradient porous tantalum anode with three-level gradient particle size composite doping, combined with in-situ modification of holmium and boron elements, providing core structural support for high specific capacitance. Simultaneously, a double-layer composite interface oxide film is prepared using pulsed anodizing and atomic layer deposition processes, effectively reducing interface defects and significantly lowering leakage current. A composite solid electrolyte based on polyimide is then vacuum-impregnated and in-situ cured, balancing ionic conductivity and insulation stability. Finally, a three-layer gradient shielded cathode combined with a ceramic-epoxy resin synergistic encapsulation layer significantly improves electromagnetic shielding effectiveness and high-temperature stability. The product of this invention exhibits significant advantages in specific capacitance, leakage current, high-temperature capacitance change rate, electromagnetic shielding, and mechanical strength, providing an innovative path for capacitor fabrication.

[0065] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A high-capacitance tantalum chip capacitor, characterized in that, include: Gradient porous tantalum anode, composite interface oxide film, composite solid electrolyte layer, multilayer shielded cathode, and synergistic encapsulation layer; The overall size is controlled within 0.8mm×0.4mm×0.3mm. The gradient porous tantalum anode has a three-level gradient particle size composite doping structure, the composite interface oxide film has a two-layer composite structure, the composite solid electrolyte layer has a polymer-inorganic nanoparticle-ionic liquid composite system, the multi-layer shielded cathode has a three-layer gradient shielding structure, and the co-encapsulation layer has a ceramic-epoxy resin composite layer.

2. A high-capacitance tantalum chip capacitor according to claim 1, characterized in that, include: The gradient porous tantalum anode uses tantalum powder with three particle sizes from the center to the surface: 1.2-1.5µm, 0.5-0.8µm, and 0.1-0.3µm, in a mass ratio of 3:4:

3. It is in-situ doped with 0.8%-1.2% rare earth element holmium and 0.3%-0.5% boron. The anode uses an embedded lead-out electrode with a tantalum wire diameter of 0.05-0.08mm and an embedding depth of 2 / 3 of the anode height. The composite interface oxide film includes an inner Ta2O5 oxide film and an outer Al2O3-TiO2 composite modified film. The inner layer has a thickness of 80-100nm, and the outer layer has a thickness of 20-30nm. The molar ratio of Al2O3 to TiO2 is 7:

3. The inner layer is prepared by pulse anodizing, and the outer layer is prepared by atomic layer deposition.

3. A high-capacitance tantalum chip capacitor according to claim 1, characterized in that, include: The composite solid electrolyte layer uses polyimide as the matrix, composite nano-ZrO2 particles, 1-ethyl-3-methylimidazolium tetrafluoroborate ionic liquid, and γ-aminopropyltriethoxysilane modifier, and is formed by vacuum impregnation in-situ curing process, with a total thickness of 150-180 nm; the multi-layer shielded cathode consists of a Ti-Ni alloy contact layer, a Cu-Ni-Zn alloy shielding layer, and an Au protective layer from the inside out, and adopts a side-leading hemispherical bump structure; the co-encapsulation layer is composed of AlN ceramic powder, maleic anhydride modified epoxy resin, and nano-SiC particles, and adopts a groove-type step-by-step curing encapsulation structure.

4. A method for manufacturing a high-capacitance tantalum chip capacitor, comprising the high-capacitance tantalum chip capacitor as described in claims 1-3, characterized in that, Includes the following steps: S1. Select three grades of high-purity tantalum powder with particle sizes of 1.2-1.5µm, 0.5-0.8µm, and 0.1-0.3µm. Vacuum anneal at 800-850℃ for 2 hours. Mix them in a mass ratio of 3:4:3 and add 0.8%-1.2% holmium powder, 0.3%-0.5% boron powder, and 2%-3% forming agent. After ultrasonic dispersion, melt doping is carried out at 1800-1900℃ under vacuum conditions ≤10Pa. Rapid cooling is then performed to obtain tantalum-holmium-boron solid solution powder. The solid solution powder is bidirectionally pressed into shape and embedded into a tantalum wire electrode. After gradient heating and sintering, a gradient porous tantalum anode is obtained for later use. S2. After ultrasonic cleaning and vacuum drying of the gradient porous tantalum anode with anhydrous ethanol, the inner Ta2O5 oxide film is prepared by pulse anodizing in oxalic acid solution. Then, the anode is placed in an atomic layer deposition device to prepare an outer Al2O3-TiO2 composite modified film using trimethylaluminum and titanium tetrachloride as precursors, and the anode with composite interface oxide film is obtained for later use. S3. Prepare an electrolyte precursor solution by mixing polyimide, nano ZrO2 particles, ionic liquid and modifier in a certain proportion. Place the anode with composite interface oxide film under vacuum of ≤10Pa and 80-100℃ to vacuum impregnate the precursor solution, and then solidify it in situ at 180-200℃ for 2-3h to form a composite solid electrolyte layer. Finally, the intermediate is obtained for later use. S4. Place the intermediate into a magnetron sputtering device to prepare a Ti-Ni alloy inner contact layer, prepare a Cu-Ni-Zn alloy middle shielding layer by sulfate electroplating, and then prepare an Au outer protective layer by atomic layer deposition. Use laser etching and electroplating processes to prepare a side hemispherical bump lead-out structure to obtain a core with a multi-layer shielded cathode for later use. S5. Prepare inner and outer layer encapsulation materials by mixing AIN ceramic powder, modified epoxy resin and nano SiC particles in a certain proportion. Use vacuum stepwise curing process to encapsulate the inner and outer layers in sequence. After preparing heat dissipation grooves on the surface of the encapsulation layer, laser trimming is performed to ensure that the product size is precisely controlled within 0.8mm×0.4mm×0.3mm, and the encapsulated core is obtained for later use. S6. After encapsulation, the core is soldered with the anode tantalum wire and the cathode bump. After soldering, it is ultrasonically cleaned and vacuum dried to obtain the initial product. The initial product is screened by specific capacitance, leakage current and high temperature resistance performance tests. Qualified products are vacuum packaged and put into storage to obtain the finished high specific capacitance chip tantalum capacitor.

5. The method for preparing a high-capacitance tantalum chip capacitor according to claim 4, characterized in that: In S1, the purity of the tertiary tantalum powder is ≥99.99%, the bidirectional pressing pressure is 80-100MPa, and the pressing time is 10-15s; the gradient sintering is carried out in three stages, namely, holding at 200-400℃ for 1h, holding at 800-900℃ for 2h, and holding at 1200-1300℃ for 3h, with a heating rate of 50℃ / min.

6. The method for preparing a high-capacitance tantalum chip capacitor according to claim 4, characterized in that: In S2, the pulsed anodizing voltage is 120-150V, the frequency is 500-800Hz, and the duty cycle is 30%-40%; the atomic layer deposition temperature is 250-300℃, and the deposition cycle is 100-120.

7. The method for preparing a high-capacitance tantalum chip capacitor according to claim 4, characterized in that: In S3, the mass percentages of each component of the electrolyte precursor are: 60%-65% polyimide, 15%-20% nano ZrO2, 10%-15% ionic liquid, and 5%-8% modifier; the vacuum impregnation time is 30-40 min, and the in-situ curing heating rate is 20℃ / min.

8. The method for preparing a high specific capacitance tantalum chip capacitor according to claim 4, characterized in that: In step S4, the magnetron sputtering power is 150-200W, the Ti-Ni alloy contact layer thickness is 30-40nm, and the electroplating current density is 1-2A / dm². 2 The Cu-Ni-Zn alloy shielding layer has a thickness of 50-60nm; the atomic layer deposition temperature is 200-250℃; the Au protective layer has a thickness of 10-15nm; and the bump diameter is 0.1-0.12mm.

9. The method for preparing a high-capacitance tantalum chip capacitor according to claim 4, characterized in that: In S5, the mass percentage of each component of the encapsulation material is 40%-45% AlN ceramic powder, 55%-60% modified epoxy resin, and 2%-3% nano SiC; the inner layer encapsulation is cured at 150-160℃ for 1 hour, the outer layer encapsulation is cured at 180-190℃ for 2 hours, the encapsulation vacuum degree is ≤5Pa, and the width of the heat dissipation groove is 0.05-0.08mm and the depth is 0.03-0.05mm.

10. The method for preparing a high specific capacitance tantalum chip capacitor according to claim 4, characterized in that: In S6, the pin soldering temperature is 250-280℃ and the soldering time is 5-8s. The performance screening criteria are: specific volume ≥2200µF·V / g, leakage current ≤3µA / g, and high temperature resistance ≥150℃; the finished product storage temperature is 10-30℃, and the relative humidity is ≤60%.

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