A power distribution network voltage sag detection and harmonic treatment system and method based on improved recursive variation mode

Abstract

The application belongs to the technical field of power systems, and discloses a voltage sag detection and treatment system applied to a distribution network, which comprises a signal acquisition unit, a recursive operation controller, a multifunctional cooperative control unit and a converter execution unit. The signal acquisition unit is used for collecting three-phase voltage and current signals of a distribution network point of common coupling in real time, and converting analog signals into digital signals. The input end of the recursive operation controller is connected with the output end of the signal acquisition unit, and the controller separates pure real-time fundamental wave components and real-time residual error components containing full-band harmonics from the collected distorted voltage signals. The input end of the multifunctional cooperative control unit is connected with the output end of the recursive operation controller, and the unit drives the converter execution unit to act. The control end of the converter execution unit is connected with the output end of the multifunctional cooperative control unit, and the unit is used for injecting compensation current into the distribution network in response to the synthesized current instruction. The system has high transient state identification precision and good timeliness, and can fully utilize existing devices for flexible reuse.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and more specifically, to a voltage sag detection and mitigation technology applied to distribution networks, and more particularly to a multifunctional mitigation method based on an improved variational decomposition algorithm that enables rapid voltage sag detection and coordinated voltage support and harmonic compensation. Background Technology

[0002] In modern power distribution networks, with the widespread application of power electronics technology and the rapid development of high-end manufacturing, the characteristics of power grid loads have changed significantly, exhibiting both high sensitivity and nonlinearity. On the one hand, critical loads such as precision manufacturing (e.g., semiconductor lithography), data centers, and continuous chemical industries are extremely sensitive to voltage dips; even millisecond-level voltage drops can lead to production interruptions or equipment damage. On the other hand, the connection of numerous nonlinear loads (e.g., frequency converters and rectifiers) to the power grid has resulted in a significant increase in background harmonic content at the point of common coupling. This presents power grid management with the dual challenges of maintaining transient states and mitigating steady-state conditions.

[0003] To ensure power quality, rapid and accurate signal detection is a prerequisite for effective mitigation. Existing voltage sag detection methods mainly include the RMS method, dq transform method, and wavelet transform method. However, existing detection algorithms present an irreconcilable contradiction between real-time performance and interference immunity.

[0004] Among them, the effective value method, which is based on integral calculation within a sliding time window, inherently has a delay of at least half a power frequency cycle, and cannot meet the requirements of sensitive loads. The stringent requirement of ultra-fast response; While the dq transform method based on a synchronous rotating coordinate system outperforms the RMS method in terms of dynamic performance, severe AC pulsations occur in the dq-axis components when the grid voltage is unbalanced or contains harmonic interference. To extract the DC fundamental frequency, a low-pass filter must be connected in series in the loop. Lowering the LPF cutoff frequency to obtain a clean signal inevitably introduces significant phase lag and amplitude attenuation, leading to slow sag detection; conversely, increasing the cutoff frequency for speed makes the detection results highly susceptible to harmonic noise interference, triggering malfunctions.

[0005] In recent years, Variational Mode Decomposition (VMD) has been introduced into the field of power quality analysis due to its excellent adaptive frequency domain partitioning capability and anti-modal aliasing characteristics. However, the standard VMD algorithm is essentially an "offline" global optimization algorithm, and it has fundamental defects that hinder its engineering and real-time applications: (1) Non-causality and endpoint effects: Standard VMD relies on data samples over the entire time period when solving variational problems. However, in real-time control, the controller can only acquire data from the current and historical moments. This data truncation can cause severe Gibbs oscillations in the variational model at the latest sampling point, resulting in instantaneous distortion of the fundamental amplitude detection and directly threatening the stability of the closed-loop control.

[0006] (2) Computational complexity barrier: The standard VMD algorithm performs iterative search in the frequency domain using the alternating direction multiplier method, involving a large number of fast Fourier transforms and inverse transforms. Its computational complexity is as high as... Furthermore, convergence requires multiple iterations. This represents an unbearable computational burden for embedded controllers (such as DSPs or FPGAs) that are required to complete calculations within 50µs or even shorter interrupt cycles, rendering them unsuitable for online real-time control.

[0007] In terms of governance methods, existing dynamic voltage restorers (DVRs) are typically designed only for the single operating condition of voltage sags. Since voltage sags are low-frequency, intermittent events, expensive power devices remain idle for the vast majority of the time (>99%) of normal grid operation, resulting in extremely low asset utilization. Although some literature has proposed reusing DVRs as active filters, the lack of a unified algorithm architecture capable of simultaneously achieving "fast fundamental frequency locking" and "full-band harmonic separation" with extremely low computing power makes this idea difficult to implement on low-cost industrial hardware.

[0008] Based on the above analysis, the problems and shortcomings of the existing technology are as follows: Existing detection algorithms have an irreconcilable contradiction between "real-time performance" and "disturbance immunity". In particular, the standard VMD algorithm is limited by the high computing power consumption of full-frequency domain iterative calculation and the endpoint effect caused by data truncation, which cannot meet the real-time requirements of closed-loop control. In addition, existing governance devices lack a multi-functional collaborative mechanism based on algorithm reuse, resulting in power hardware being idle for a long time during steady-state operation of the power grid, leading to low overall utilization rate and investment efficiency of the equipment. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, embodiments of the present invention provide a voltage sag detection and mitigation system, method, and computer equipment for use in power distribution networks. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0010] According to a first aspect of the present invention, a distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes is provided.

[0011] In one embodiment, the system includes: The signal acquisition unit is used to acquire the three-phase voltage and current signals at the common connection point of the power distribution network in real time and convert the analog signals into digital signals. The recursive operation controller, whose input is connected to the output of the signal acquisition unit, is internally configured with a boundary prediction logic module, a recursive differential operation module and a state variable storage module. By executing the time-domain recursive differential equation with center frequency locked, it separates the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal. The multi-functional collaborative control unit, whose input is connected to the output of the recursive operation controller, is internally configured with a voltage sag detection logic channel, a harmonic suppression logic channel, and a dynamic command arbitrator. The voltage sag detection logic channel calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command. The harmonic suppression logic channel directly uses the real-time residual component as the grid distortion target to generate a corresponding active power filter current command. The dynamic command arbitrator dynamically limits the active power filter current command according to the remaining capacity of the device, and combines the reactive power support current command with the limited active power filter current command to drive the converter execution unit to operate. The converter execution unit, whose control terminal is connected to the output terminal of the multi-functional collaborative control unit, is used to inject compensation current into the distribution network in response to the synthetic current command.

[0012] According to a second aspect of the present invention, a method for detecting voltage sags and controlling harmonics in distribution networks based on improved recursive variational modes is provided.

[0013] In one embodiment, the method is based on the system described in any of the foregoing embodiments, comprising: Step (1): Real-time acquisition of three-phase voltage and current signals at the common connection point of the distribution network, and conversion of analog signals into digital signals; Step (2): Use a recursive operation controller to separate the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal. Step (3): The voltage sag detection logic channel calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental wave component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command; The harmonic suppression logic channel directly uses the real-time residual component as the grid distortion target and generates a corresponding active filter current command. Step (4): The dynamic command arbitrator dynamically limits the active filter current command according to the remaining capacity of the device, and combines the reactive power support current command with the limited active filter current command to drive the converter execution unit to operate. Step (5): The converter execution unit responds to the composite current command and injects compensation current into the distribution network.

[0014] According to a third aspect of the present invention, a computer device is provided.

[0015] In some embodiments, the computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described above.

[0016] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: First, this invention breaks through the traditional full-frequency-domain iterative mode of variational mode decomposition and constructs a single-mode computation architecture with center frequency locking and recursive differential update. This architecture utilizes prior knowledge of the fundamental frequency of the power grid to transform the complex functional extremum problem into a single-step linear recursive calculation with O(1) complexity, thereby overcoming the core pain point of traditional signal processing algorithms, which have large computational load and are difficult to run in real time on embedded platforms, at the level of mathematical principles. Meanwhile, this invention utilizes the pure fundamental wave and residual components naturally separated by the algorithm to construct a synergistic mechanism for voltage sag control and harmonic compensation, enabling a single device to achieve multi-functional reuse without increasing additional hardware costs. It is suitable for modern power distribution network management scenarios that are cost-sensitive and have extremely high real-time requirements.

[0017] Secondly, the significant technological advancements brought about by the improved detection and control method proposed in this invention include: This method reduces the computational requirements of the detection algorithm: it derives the recursive update equation for the fundamental component, reducing the algorithm complexity from exponential to zero. The computational complexity is reduced to O(1) on the constant level. This enables complex variational decomposition algorithms to run in microseconds on low-cost DSP or FPGA chips for the first time, breaking through the computational bottleneck of high-end algorithm engineering implementation; This method improves the accuracy of voltage sag detection: Addressing the Gibbs oscillation problem in traditional sliding window processing, this method introduces a boundary extension mechanism based on multinomial prediction, combined with causal recursive logic, effectively suppressing numerical distortion at data truncation points. Experiments show that it reduces the voltage sag amplitude detection delay to within 1 / 4 of a power frequency cycle, with no overshoot oscillation, significantly improving the dynamic response speed of the control device during transient processes. Enhanced robustness against disturbances under complex operating conditions: The single-mode variational model constructed by this method is equivalent to a high-quality factor adaptive bandpass filter in the frequency domain. Even under conditions where the grid voltage contains background harmonics, spike noise, or small frequency fluctuations, the algorithm can still stably lock the fundamental amplitude, avoiding malfunctions caused by noise interference in traditional zero-crossing detection methods and improving the inherent reliability of the system.

[0018] Third, this invention proposes and implements a recursive detection algorithm that combines instantaneous response, strong anti-interference capability, and low computational consumption. Existing voltage sag mitigation devices are often idle during normal grid operation. This invention utilizes a single recursive operation to simultaneously obtain the fundamental frequency (for sags) and residual (for harmonics), enabling the same power hardware to seamlessly switch between transient support and steady-state filtering modes. This provides a practical technical path to enhance the asset value of key equipment in the distribution network.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] Figure 1 This is a schematic diagram of a voltage sag detection and mitigation system applied to a power distribution network in an embodiment of the present invention; Figure 2 This is a detailed schematic diagram of the voltage sag detection and mitigation system applied to the power distribution network in this embodiment of the invention; Figure 3a This is a flowchart illustrating a voltage sag detection and mitigation method applied to a distribution network according to an exemplary embodiment; Figure 3b This is a detailed flowchart illustrating a voltage sag detection and mitigation method applied to a distribution network, according to an exemplary embodiment. Figure 4 This is a schematic diagram of the three-phase voltage sag waveform under a simulated standard power grid condition of 0.1s in an embodiment of the present invention. Figure 5 This is a schematic diagram of a distorted grid voltage sag waveform containing complex background harmonics, as simulated in an embodiment of the present invention. Figure 6a This is a schematic diagram of the sag indicator waveform of the detection method provided in this embodiment of the invention under standard power grid operating conditions; Figure 6b This is a schematic diagram of the fundamental wave envelope amplitude waveform detected by the detection method provided in this embodiment of the invention; Figure 7a This is a schematic diagram of the waveform of the sag detection mark under high-order harmonic conditions provided by the detection method of the present invention. Figure 7b This is a schematic diagram of the fundamental wave envelope amplitude waveform detected by the detection method provided in this embodiment of the invention under conditions containing higher harmonics; Figure 8a This is a waveform and THD diagram of the treatment method provided in this embodiment of the invention before treatment; Figure 8b This is a waveform and THD diagram of the treatment method provided in this embodiment of the invention after treatment; Figure 9 This is a schematic diagram of the structure of a computer device according to an exemplary embodiment; Detailed Implementation

[0022] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0023] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing the document and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0024] In this document, unless otherwise stated, the term "multiple" means two or more.

[0025] In this article, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0026] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0027] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0028] The modules in the apparatus or system of this application can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0029] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0030] Figure 1An embodiment of the voltage sag detection and mitigation system of the present invention applied to a power distribution network is shown.

[0031] In this optional embodiment, the voltage sag detection and mitigation system applied to the distribution network includes: a signal acquisition unit 110, used to acquire three-phase voltage and current signals at the distribution network's common coupling point in real time and convert analog signals into digital signals; a recursive operation controller 120, whose input is connected to the output of the signal acquisition unit 110, and internally configured with a boundary prediction logic module 121, a recursive differential operation module 122, and a state variable storage module 123, which separates the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal by executing a center frequency locked time-domain recursive differential equation; and a multi-functional collaborative control unit 130, whose input is connected to the output of the recursive operation controller 120, and internally configured with parallel sag detection logic... The system includes a voltage sag detection logic channel 131, a harmonic suppression logic channel 132, and a dynamic command arbitrator 133. The voltage sag detection logic channel 131 calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental wave component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command. The harmonic suppression logic channel 132 directly uses the real-time residual component as the grid distortion target to generate a corresponding active power filter current command. The dynamic command arbitrator 133 dynamically limits the active power filter current command according to the remaining capacity of the device, and synthesizes the reactive power support current command with the limited active power filter current command to drive the converter execution unit to operate. The converter execution unit 140, whose control terminal is connected to the output terminal of the multi-functional collaborative control unit, is used to respond to the synthesized current command and inject compensation current into the distribution network.

[0032] The following is combined Figure 2 The system of the present invention will be described in detail.

[0033] Optionally, the signal acquisition unit is configured with a multi-channel high-frequency synchronous sampling circuit, the input of which is coupled to the secondary side of the voltage and current transformer at the common connection point of the power distribution network, for outputting real-time digital voltage and digital current sequences and transmitting them to the recursive operation controller.

[0034] Optionally, the coefficients of the time-domain recursive difference equation are calculated and stored offline based on the sampling frequency and a preset bandwidth penalty factor.

[0035] Optionally, the boundary prediction logic module is used to receive the sampled value at the current time, and includes a FIFO (First In First Out) buffer and a polynomial extrapolation unit. It performs boundary extension on the sampled value at the current time based on historical sampled data to generate a smooth input sequence.

[0036] Optionally, the recursive difference operation module is configured as a fixed-point time-domain difference engine, which includes a multiply-accumulate (MAC) unit for performing weighted summation and feedback correction. It utilizes the current input sequence preprocessed by the boundary prediction logic module and the stored historical fundamental state variables to solve the fundamental voltage component at the current moment in one step by executing the time-domain discretized recursive update equation.

[0037] Optionally, the recursive difference operation module further includes a lookup table in which the coefficients of the recursive difference equations executed by the recursive difference calculation submodule are stored; the system also includes a low-bandwidth frequency observer for monitoring the actual operating frequency of the power grid, and the recursive operation controller addresses the lookup table according to the actual operating frequency of the power grid and updates the coefficients of the recursive difference equations in real time to achieve adaptive following of the center frequency.

[0038] Specifically, the coefficients in the recursive difference equation The fixed-point complement values ​​are pre-calculated in Q31 format and stored in the lookup table of the recursive differential operation module. During runtime, the processor directly calls these fixed-point constants for multiplication and accumulation operations, completely avoiding time-consuming floating-point unit calls. A low-bandwidth frequency observer monitors the actual operating frequency of the power grid and dynamically changes the index pointer of the lookup table according to this frequency, loading the corresponding recursive coefficients in real time. This design enables the algorithm to adaptively follow power grid frequency fluctuations without complex online calculations, further enhancing the system's robustness.

[0039] Optionally, the state variable storage module is configured as a set of register files to latch the historical fundamental state quantities and Lagrange multiplier state quantities required by the recursive difference operation module, and to form a closed-loop feedback path.

[0040] Optionally, the voltage sag detection logic channel is connected to the fundamental output terminal of the recursive operation controller, and is internally configured with an orthogonal signal generator, a no-delay amplitude calculation logic circuit, and a hysteresis comparison logic circuit. The orthogonal signal generator is used to perform phase shifting processing on the input fundamental voltage sequence; the no-delay amplitude calculation logic circuit uses a second-order generalized integrator to construct orthogonal signals for the fundamental components and obtains the instantaneous amplitude of the fundamental through square root operation; the hysteresis comparison logic circuit is used to determine the voltage sag state and generate a reactive power support current command using hysteresis comparison logic.

[0041] Optionally, the harmonic suppression logic channel is connected to the residual output terminal of the recursive operation controller, and is internally configured with a wideband harmonic controller with an embedded phase lead compensation algorithm, which is used to directly generate an inverted active filter current command using the residual sequence under the premise of compensating for the phase lag of digital control delay.

[0042] Optionally, when generating the active filter current command, the harmonic suppression logic channel introduces a transient gain blocking mechanism. The transient gain blocking mechanism monitors the residual sequence change rate in real time. When the residual sequence change rate exceeds a preset safety threshold, or when the voltage sag judgment flag is set, the gain coefficient of the active filter channel is forcibly set to zero. After the residual sequence change rate falls back below the threshold, the gain coefficient is controlled to return to the rated value.

[0043] Optionally, the dynamic command arbitrator connects the outputs of the sag detection logic channel and the harmonic suppression logic channel, and is internally configured with a capacity calculation logic circuit and a dynamic limiting logic circuit. The capacity calculation logic circuit is used to calculate the remaining capacity of the converter in real time, and the dynamic limiting logic circuit limits and truncates the active filter command generated by the harmonic suppression logic channel according to the principle of voltage support priority, and outputs a current reference command.

[0044] Optionally, the dynamic limiting strategy executed by the command dynamic arbitrator is as follows: prioritize fully satisfying the output demand of the reactive power support current command, and use the remaining capacity of the converter rated current to cut off the active filter current command to ensure that the device is not overloaded under any operating conditions.

[0045] Optionally, the converter execution unit includes a DC-side energy storage capacitor, a three-phase full-bridge inverter topology, and an LCL filter circuit; the power switching transistors in the three-phase full-bridge inverter topology respond to the PWM drive signal output by the multi-functional collaborative control unit and inject compensation current into the distribution network to perform voltage support or harmonic filtering operations.

[0046] Figure 3a An embodiment of the present invention for voltage sag detection and mitigation in a power distribution network is shown.

[0047] In this optional embodiment, the method, based on the system of any of the above embodiments, includes the following steps: Step (1): Real-time acquisition of three-phase voltage and current signals at the common connection point of the distribution network, and conversion of analog signals into digital signals; Step (2): Use a recursive operation controller to separate the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal. Step (3): The voltage sag detection logic channel calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental wave component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command; The harmonic suppression logic channel directly uses the real-time residual component as the grid distortion target and generates a corresponding active filter current command. Step (4): The dynamic command arbitrator dynamically limits the active filter current command according to the remaining capacity of the device, and combines the reactive power support current command with the limited active filter current command to drive the converter execution unit to operate. Step (5): The converter execution unit responds to the composite current command and injects compensation current into the distribution network.

[0048] The following is combined Figure 3b The method of the present invention will be described in detail.

[0049] In step (1) above, the three-phase voltage at the distribution network point of common coupling (PCC) is sampled in real time at high frequency. Specifically, to adapt to the subsequent dimensionless calculations, the original sampling sequence is first processed. Perform per-unit processing:

[0050] This indicates the peak value of the rated phase voltage of the distribution network.

[0051] Furthermore, to address the Gibbs effect caused by sliding window data truncation, a confidence-weighted boundary prediction mechanism is introduced. Specifically, a three-point second-order polynomial extrapolation algorithm is constructed, which uses the states at historical time points (n-1, n-2, n-3) to calculate the theoretical prediction value at the current time based on the second-order Taylor expansion principle.

[0052] Define dynamic confidence factors When the first-order difference of the signal is detected Exceeding the preset mutation threshold In this case, the weight of the measured value is reduced and the weight of the predicted value is increased to suppress transient overshoot.

[0053] The input recursive core sequence is:

[0054] In practical processing, a hybrid input strategy is adopted. In steady state, the weighted average of the measured value and the predicted value is taken, and when a signal jump is detected, it is briefly switched to the predicted value, thereby effectively suppressing the overshoot of the step response.

[0055] In step (2) above, in order to overcome the computational bottleneck caused by full-frequency domain iteration and non-causality in the standard VMD algorithm, this invention establishes a time-domain recursive architecture based on variational constraints, specifically as follows: A. Mathematical Reconstruction of Variational Problems Standard VMD aims to find a center frequency of Inherent mode functions with limited bandwidth For voltage sag detection, this invention degenerates the multimodal problem into a single-mode constrained optimization problem, the original form of which is defined as:

[0056] This invention omits the iterative search process of the aforementioned functional in the frequency domain and directly derives the analytical solution of its optimal path using variational extremum conditions.

[0057] B. Time-domain recursive difference equations Based on the analytical solution of the above functional, the bandpass problem is transformed into a baseband problem by shifting the center frequency, and the continuous domain differential equation is discretized by combining the bilinear transformation. Finally, a set of time-domain equations containing only addition, subtraction, and multiplication operations are derived:

[0058] This equation requires only 3 multiplications, 3 additions, and 1 shift operation within a single interrupt cycle. This is significantly less than the requirements of FFT. With a few operations, this algorithm achieves a strict O(1) complexity.

[0059] Recursive coefficients of time-domain recursive difference equations All are determined by the sampling period and bandwidth penalty factor The unique characteristic, which has been pre-calculated and fixed during the controller initialization phase, is:

[0060] C. Frequency robustness design and parameter tuning This invention addresses power grid frequency fluctuations (typically...) To address this engineering challenge, this approach abandons the complex path of real-time frequency tracking and dynamic algorithm parameter adjustment via phase-locked loops in traditional methods, and proposes a robust design strategy based on quasi-static flat passband.

[0061] First, based on the aforementioned derived time-domain recursive equation, this invention constructs the frequency-domain equivalent transfer function model of the single-mode variational filter. In the frequency domain, the amplitude-frequency response of this recursive system... It approximately follows the Lorentz linear distribution of the Wiener filter:

[0062] in, To lock the center frequency, These are key parameters that determine the filter's quality factor. Although this mathematical form represents bandpass filtering characteristics, its construction mechanism differs fundamentally from that of traditional IIR filters: its recursive coefficients... The optimal value is not directly specified by the pole placement method, but rather analytically derived from the optimal solution of the variational functional. This means that the algorithm inherits the advantages of the variational framework for processing non-stationary signals, namely, by adjusting the penalty factor. In essence, it seeks the variational optimal solution between signal data fitting error and modal smoothness, rather than simply frequency domain truncation.

[0063] Quantitative tuning of passband flatness is necessary to lock onto the center frequency. Under the premise of ensuring that the algorithm is compatible with the actual operating frequency of the power grid The fluctuation has universality in amplitude measurement, and this invention introduces passband flatness constraint conditions.

[0064] Specifically, the maximum permissible relative error in amplitude measurement is defined as follows: Then the parameter The tuning of must satisfy the following boundary inequalities:

[0065] By solving this inequality, the robustness upper bound of the penalty factor can be derived:

[0066] At the same time, in order to ensure effective filtering of adjacent characteristic harmonics (such as the 5th harmonic), It also needs to satisfy a selective lower bound. Taking all factors into consideration, this invention will... The filter is tuned to an optimal flat-top range. Within this range, the filter's passband exhibits a sufficiently flat width so that when the frequency changes... During the offset, the fundamental component remains within the filter's unaffected passband, and its amplitude gain attenuation is negligible.

[0067] Optionally, step (2) further includes: using an adder to separate the full-band residuals and iteratively updating the Lagrange multipliers.

[0068] Specifically, an adder is used to separate the residual across the entire frequency band. This signal is not only a mathematical residue, but also physically contains all the characteristic harmonics (5th, 7th, etc.) and high-frequency noise in the power grid, and is directly used as the input to the subsequent harmonic suppression logic block.

[0069] To strictly satisfy the variational constraint conditions Introducing Lagrange multipliers Iterative updates. In a physical sense, Equivalent to the integral error term in a control system, used to eliminate DC bias and steady-state error:

[0070] in To achieve convergence, the step size typically ranges from [value range missing]. .

[0071] In step (3) above, the orthogonal construction and anti-jitter determination yield a pure fundamental wave. u ( n After that, the voltage sag determination stage begins. To avoid false triggering caused by single-point noise, anti-jitter logic is introduced. u ( n The input is a second-order generalized integrator, whose transfer function is:

[0072] Because the input signal is pure, the damping coefficient can be set. This allows it to function as a fast phase shifter, generating quadrature components within 1 / 4 of a period. Calculate the amplitude without delay. .

[0073] when And the duration exceeds the counting threshold At that time, set the temporary sag flag Flag_Sag = 1. This is the threshold for determining a voltage sag (typically 0.9 pu). A sag is considered to have occurred when the amplitude falls below this threshold. Only when... At this time, the reset sag flag is activated to avoid control oscillations during critical voltage fluctuations. The voltage sag recovery threshold (usually 0.95 pu) is introduced to prevent voltage fluctuations at the critical point from causing frequent switching of the judgment state.

[0074] In step (4) above, the amplitude of the time-delay-free fundamental wave decoupled from the detection phase is used. and full-band residual sequence The converter's final current command is generated through dual-channel parallel processing and dynamic arbitration.

[0075] Specifically, when the voltage sag detection logic is set... Upon this, the system immediately enters low-voltage ride-through mode. According to the grid connection guidelines, the controller calculates the reference value of the dynamic reactive current to be injected into the grid. :

[0076] Where K is the dynamic reactive power support coefficient. This refers to the device's rated current. This directive aims to rapidly increase the voltage at the PCC point to support grid stability.

[0077] Based on dynamic gain scheduling, this invention abandons the complex architecture of traditional active filters that rely on FFT analysis or multi-channel resonant controllers for specific harmonic compensation, and instead proposes a full-band blind compensation strategy based on residual feedback.

[0078] A. Full-band blind compensation principle Since the residual sequence r(n) has mathematically eliminated the fundamental frequency, its essence is the generalized disturbance to be eliminated. Therefore, r(n) is directly used as the error signal, and an inverse compensation command is generated by a wideband controller. :

[0079] in, For the transfer function of the wideband controller, This is the gain for the harmonic channel.

[0080] Considering the inherent delay in digital control systems from sampling and calculation to PWM update, directly inverting the high-frequency residual will cause significant phase lag, and may even induce positive feedback oscillations in certain high-frequency bands. Therefore, the aforementioned The internal cascaded circuit includes a phase lead compensation stage, and its transmission method is as follows: It is configured to provide a leading phase angle at the cutoff frequency to compensate for digital delay and phase lag of the LCL filter, ensuring the stability of the full-band closed-loop system.

[0081] B. Transient blocking and dynamic gain To address the issue of fundamental frequency difference components being mixed into the residual sequence due to physical inertia at the moment of voltage sag, this patent constructs a transient blocking logic based on the rate of energy change in order to prevent inrush current from the converter output.

[0082] Rate of change monitoring: Real-time calculation of the first-order difference modulus of the residual sequence D(n) = |r(n) - r(n-1)|.

[0083] Gain function design: Harmonic channel gain It follows a dynamic scheduling function:

[0084] in, The threshold for mutation determination. The moment when the system returns to steady state. The time constant for gain recovery. This is the rated gain of the harmonic suppression channel.

[0085] Timing logic: Once a voltage sag or residual change is detected, immediately... Forced zeroing ensures that the converter capacity fully serves reactive power support; after the fundamental frequency extraction converges and the residual stabilizes, the gain smoothly recovers to the rated value according to an exponential law. This mechanism solves the electrical safety problem during the switching between transient support and steady-state filtering modes.

[0086] In step (5) above, the dynamic capacity arbitration mechanism implements a dynamic limiting arbitration strategy of "absolute priority of voltage support" to ensure that the converter is not overloaded under any operating condition: A. Remaining capacity calculation First, deduct the current capacity required for reactive power support, then calculate the remaining available capacity of the active filter.

[0087] in This is the maximum allowable output current of the converter.

[0088] B. Dynamic truncation Hard-limiting is applied to the harmonic compensation command:

[0089] C. Final synthesis Output total reference current command

[0090] General Reference Directive The current is fed into the inner loop controller, where it is used to generate drive pulses via space vector pulse width modulation.

[0091] The system and method of the present invention will be described in detail below through specific embodiments. Example 1:

[0092] Application Scenario: A 10kV power distribution bus at a semiconductor wafer fab, under which a group of lithography machines, extremely sensitive to voltage fluctuations, are connected. Peak rated phase voltage of the power grid. The rated frequency is In terms of hardware selection, this embodiment uses a Xilinx Artix-7 series FPGA (XC7A200T) as the core computing platform, with a main frequency set to [missing information]. The current transformer uses a transformation ratio of A high-precision Hall voltage sensor; the analog-to-digital converter (ADC) uses a 16-bit synchronous sampling chip (such as AD7606), and the sampling frequency is set to... That is, the sampling period The power unit uses a 2MVA three-phase three-level NPC topology converter with a switching frequency of [missing information]. DC bus voltage At 0.1s, a standard sine wave and a 20% voltage dip containing harmonics are generated respectively.

[0093] Algorithm parameter tuning: Regarding algorithm parameter tuning and fixed-point normalization, the core recursive parameters are set as follows: Locking the center frequency. Bandwidth penalty factor ,correspond bandwidth approximately SOGI damping coefficient To accommodate FPGA operations, the discretized recursive coefficients are pre-computed and stored in Q31 format.

[0094] Implementation procedure: Step 1, in At that moment, the ADC triggers a sampling interrupt and reads the raw values ​​of the three-phase voltages. The FPGA's internal DSP slice performs a per-unit operation, i.e. The results are then truncated to Q15 format.

[0095] Step 2, in At any given time, boundary prediction and smoothing are performed. The controller maintains a shift register with a depth of 4. The system first calculates the first-order difference. ,like If the value is not found, it is considered a suspected step jump and the Jump_Flag flag is set. Simultaneously, the predicted value is calculated using shift and addition / subtraction methods. When Jump_Flag is set, the algorithm input is the predicted value. Otherwise, take the measured value. This eliminates the Gibbs oscillation at the step moment.

[0096] Step 3, in At any given time, recursive core computation is performed. The FPGA's multiply-accumulate unit (MAC) executes Q31 format fixed-point arithmetic, with the following formula: The result of the operation is shifted right by 31 bits to restore it to the Q15 format, thus obtaining the current fundamental frequency. At the same time, calculate the residuals. and according to step size Update Lagrange multipliers .

[0097] Step 4, in At any given moment, perform zero-delay amplitude calculation and state machine transition. The orthogonal quantities are generated by inputting them into the discretization SOGI module. And the modulus is calculated using the CORDIC algorithm IP core. The state machine logic is configured as follows: when in a normal state and The counter increments as the duration exceeds [time limit]. (i.e., count 3 times), then jump to the sag state (State_Sag) and set the low-voltage ride-through flag (Flag_LVRT); when in the sag state and When the counter increments, it jumps back to the normal state if the duration meets the requirement.

[0098] Step 5, in At that time, a reactive power instruction is generated. If Flag_LVRT is set, then according to the formula... Calculate the reactive current reference value and limit it, ensuring it does not exceed [the maximum value]. , This is the rated current of the device. Implementation effect

[0099] Figure 4 The scenario of voltage dips under ideal sinusoidal conditions is demonstrated. At t=0.1s, the three-phase voltage amplitude drops from 1.0 pu to 0.8 pu, simulating a symmetrical short-circuit fault.

[0100] Figure 6a The flag_Sag is generated internally by the system to determine voltage dips. When a voltage dip occurs in the physical system at t=0.1s, after a very short detection delay, the flag changes from 0 to 1, triggering the device to enter voltage support mode; after the fault is cleared at t=0.14s, the flag is quickly reset. Figure 6b The fundamental amplitude A(n) is extracted in real time by the recursive VMD algorithm. It can be seen that the amplitude curve is smooth and has no overshoot. It can quickly and accurately track the entire process of the grid voltage dropping from 1.0 pu to 0.8 pu, which verifies the dynamic performance of the detection algorithm.

[0101] Figure 7a and Figure 7b This is the control response waveform under operating conditions with severe background harmonics. Under this condition, although the input voltage waveform is severely distorted, Figure 7b The fundamental amplitude A(n) shown remains highly stable, with only very small ripples and no violent oscillations. Figure 7a This indicates that the triggering logic of the voltage dip flag (Flag_Sag) is not affected by harmonic noise and can still stably and correctly toggle at the moment of fault occurrence and termination. Therefore, the above embodiment verifies that in harsh industrial environments, the voltage dip flag can be triggered at the moment of fault occurrence and termination. The amplitude detected by the method of this invention has steadily converged to the actual drop value (error). This guides the converter to output full reactive power support current, effectively preventing the lithography machine from tripping due to low voltage protection. Example 2:

[0102] Application scenario: A chemical plant power distribution network, where the background harmonics are mainly the 5th (20%) and 7th (14%), with a total distortion (THD) of approximately [value missing]. The control objective is set to reduce the THD at the PCC point to a level that does not cause voltage sags. The controller's software logic employs a dual-threaded parallel architecture: Thread A performs the sag detection described in Example 1, while Thread B performs harmonic mitigation (with lower priority).

[0103] Implementation procedure: Step 1, after completing the fundamental frequency extraction (approximately...) The system directly reads the output of the subtractor as the full-band residual. .because It is a pure fundamental frequency, at this time The data fully preserves the 5th, 7th and higher harmonics and random noise data.

[0104] Step 2, in At any given time, transient locking and gain scheduling are executed. First, the first-order difference modulus of the residual is calculated. The gain control logic is configured as follows: if the low-voltage ride-through flag Flag_LVRT is set or... If the transient threshold is exceeded, the harmonic channel gain Gain_H is forcibly set to 0, and the recovery timer is reset to prevent transient shocks; otherwise, if the recovery timer has not reached the set time, control... Gain_H According to the exponential law Smooth recovery; if the set time has been reached, Gain_H remains at its rated value. This logic ensures that the active filtering function starts soft-start at the moment the sag ends.

[0105] Step 3, in At a given time, a blind compensation command is generated. The system employs the P control algorithm to directly calculate... This step does not require identifying the specific harmonic order; it only requires inverting and amplifying the residual waveform. This indicates an active filter current command or harmonic compensation current command. This command is the compensation current value that the control system calculates and theoretically needs to inject into the distribution network to eliminate background harmonics in the power grid.

[0106] Step 4, in At any given time, capacity arbitration and limiting are performed. The remaining capacity is calculated using the FPGA's CORDIC core. Dynamically truncate the harmonic compensation command: If Exceed Then the output is limited to ;like Then the output is limited to Otherwise, maintain the original value. Finally, add the reactive power command and the limited harmonic command to synthesize the total reference command. . This indicates the original active filter current command, which is the ideal compensation current that the converter should output based on the residual condition of the current power grid. This indicates the remaining available capacity of the active filter. This indicates the final synthesized harmonic current command, which is the command actually sent to the converter for execution after being limited by the dynamic command arbitrator.

[0107] Step 5, in At any given moment, the dq axis current command is converted to... The axis voltage command is sent to the SVPWM module to generate 6 PWM pulses, with the dead time set to [value missing]. The total time consumed from ADC sampling to PWM register update. much smaller The control cycle, CPU load is only . Implementation effect

[0108] Figure 8a and Figure 8b This invention visually demonstrates the final mitigation effect of the dual-channel coordinated control of voltage support and harmonic mitigation. Figure 8a The first image shows the power grid waveform before treatment. Due to the presence of the aforementioned 5th, 7th, 11th, and 13th harmonics, the voltage waveform is severely distorted, exhibiting a flat-topped wave shape, with a measured total harmonic distortion (THD) as high as 10.10%. Figure 8 shows the waveform after treatment using the method described in this invention. This invention utilizes the residual components separated by recursive VMD for full-band blind compensation, correcting the voltage waveform to a standard sine wave without relying on FFT spectrum analysis. After treatment, the voltage waveform at point PCC recovers from a flat-topped wave to a standard sine wave, and the THD decreases from... The harmonic distortion was reduced to 0.60%, which is better than the requirements of the national standard GB / T 14549. Furthermore, when a high-power frequency converter is suddenly loaded, causing a sudden increase in harmonics, the device... The tracking compensation was completed within the time limit, verifying the high bandwidth characteristics of the blind compensation strategy and the effectiveness of the algorithm of this invention in multi-functional reuse.

[0109] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores static and dynamic information data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the steps in the above method embodiments.

[0110] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0111] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0112] This invention is not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

Claims

1. A distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes, characterized in that, include: The signal acquisition unit is used to acquire the three-phase voltage and current signals at the common connection point of the power distribution network in real time and convert the analog signals into digital signals. The recursive operation controller, whose input is connected to the output of the signal acquisition unit, is internally configured with a boundary prediction logic module, a recursive differential operation module and a state variable storage module. By executing the time-domain recursive differential equation with center frequency locked, it separates the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal. The multi-functional collaborative control unit has its input end connected to the output end of the recursive operation controller. It is internally configured with a voltage sag detection logic channel, a harmonic suppression logic channel, and a dynamic command arbitrator. The voltage sag detection logic channel calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental wave component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command. The harmonic suppression logic channel directly uses the real-time residual component as the power grid distortion target to generate corresponding active filter current commands. The dynamic command arbitrator dynamically limits the active filter current command based on the remaining capacity of the device, and combines the reactive power support current command with the limited active filter current command to drive the converter execution unit to operate. The converter execution unit, whose control terminal is connected to the output terminal of the multi-functional collaborative control unit, is used to inject compensation current into the distribution network in response to the synthetic current command.

2. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The signal acquisition unit is equipped with a multi-channel high-frequency synchronous sampling circuit. Its input terminal is coupled to the secondary side of the voltage and current transformer at the common connection point of the power distribution network, and is used to output real-time digital voltage and digital current sequences and transmit them to the recursive operation controller.

3. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The coefficients of the time-domain recursive difference equation are calculated offline and stored based on the sampling frequency and a preset bandwidth penalty factor.

4. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The boundary prediction logic module is used to receive the sampled value at the current time. It includes a first-in-first-out data buffer and a polynomial extrapolation unit. Based on historical sampled data, it performs boundary extension on the sampled value at the current time to generate a smooth input sequence.

5. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The recursive difference operation module is configured as a fixed-point time-domain difference equation solving engine. It includes a multiply-accumulate arithmetic logic unit for performing weighted summation and feedback correction. Using the current input sequence preprocessed by the boundary prediction logic module and the stored historical fundamental state variables, it solves the fundamental voltage component at the current time step by step by executing the time-domain discretized recursive update equation.

6. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 5, characterized in that, The recursive difference operation module also includes a lookup table, in which the coefficients of the recursive difference equations executed by the recursive difference calculation submodule are stored; The system also includes a low-bandwidth frequency observer for monitoring the actual operating frequency of the power grid. The recursive operation controller addresses the lookup table according to the actual operating frequency of the power grid and updates the coefficients of the recursive difference equation in real time to achieve adaptive following of the center frequency.

7. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The state variable storage module is configured as a set of registers to latch the historical fundamental state quantities and Lagrange multiplier state quantities required by the recursive difference operation module, and to form a closed-loop feedback path.

8. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The sag detection logic channel is connected to the fundamental output terminal of the recursive operation controller. Internally, it is configured with an orthogonal signal generator, a delay-free amplitude calculation logic circuit, and a hysteresis comparison logic circuit. The quadrature signal generator is used to perform phase shifting processing on the input fundamental voltage sequence; The delay-free amplitude calculation logic circuit uses a second-order generalized integrator to construct orthogonal signals for the fundamental component and obtains the instantaneous amplitude of the fundamental component through square root operation. The hysteresis comparison logic circuit is used to determine the voltage sag state and generate a reactive power support current command.

9. A distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The harmonic suppression logic channel is connected to the residual output terminal of the recursive operation controller. It is equipped with a wideband harmonic controller with an embedded phase lead compensation algorithm, which is used to directly generate an inverted active filter current command using the residual sequence under the premise of compensating for the phase lag of digital control delay.

10. A distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 9, characterized in that, When generating an active filter current command, the harmonic suppression logic channel introduces a transient gain blocking mechanism. The transient gain blocking mechanism monitors the residual sequence change rate in real time. When the residual sequence change rate exceeds a preset safety threshold, or when the voltage sag judgment flag is set, the gain coefficient of the active filter channel is forcibly set to zero. After the residual sequence change rate falls back below the threshold, the control gain coefficient is restored to the rated value.

11. A distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The dynamic command arbitrator connects the outputs of the sag detection logic channel and the harmonic suppression logic channel. It is internally configured with a capacity calculation logic circuit and a dynamic limiting logic circuit. The capacity calculation logic circuit is used to calculate the remaining capacity of the converter in real time. The dynamic limiting logic circuit limits and truncates the active filter command generated by the harmonic suppression logic channel according to the principle of voltage support priority, and outputs a current reference command.

12. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 11, characterized in that, The dynamic limiting strategy executed by the command dynamic arbitrator is as follows: prioritize fully satisfying the output demand of the reactive power support current command, and use the remaining capacity of the converter rated current to cut off the active filter current command to ensure that the device is not overloaded under any operating conditions.

13. The distribution network voltage sag detection and harmonic mitigation system based on improved recursive variational modes according to claim 1, characterized in that, The converter execution unit includes a DC-side energy storage capacitor, a three-phase full-bridge inverter topology, and an LCL filter circuit. The power switching transistors in the three-phase full-bridge inverter topology respond to the PWM drive signal output by the multi-functional collaborative control unit and inject compensation current into the distribution network to perform voltage support or harmonic filtering.

14. A method for voltage sag detection and harmonic mitigation in distribution networks based on improved recursive variational modes, characterized in that, The system based on any one of claims 1 to 13 includes the following steps: Step (1): Real-time acquisition of three-phase voltage and current signals at the common connection point of the distribution network, and conversion of analog signals into digital signals; Step (2): Use a recursive operation controller to separate the pure real-time fundamental component and the real-time residual component containing full-band harmonics from the acquired distorted voltage signal. Step (3): The voltage sag detection logic channel calculates the instantaneous amplitude of the fundamental wave based on the real-time fundamental wave component, determines whether a voltage sag has occurred, and generates a corresponding reactive power support current command; The harmonic suppression logic channel directly uses the real-time residual component as the grid distortion target and generates a corresponding active filter current command. Step (4): The dynamic command arbitrator dynamically limits the active filter current command according to the remaining capacity of the device, and combines the reactive power support current command with the limited active filter current command to drive the converter execution unit to operate. Step (5): The converter execution unit responds to the composite current command and injects compensation current into the distribution network.

15. A method for voltage sag detection and harmonic mitigation in distribution networks based on improved recursive variational modes, as described in claim 14, is characterized in that... Step (2) further includes: The adder is used to separate the residual across the entire frequency band, and the Lagrange multipliers are iteratively updated.

16. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method described in claim 14 or 15.

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