Data integrity multi-checking method and system of dual-channel safety control system

Abstract

The application discloses a data integrity multiple verification method and system of a double-channel safety control system, relates to the technical field of data verification of safety control systems, and comprises the following steps: performing inboard double-channel cross voting on input signals obtained by double channels of a board card, performing one cycle redundancy check on voting result data, and performing cycle redundancy check code packaging based on a communication protocol to obtain a protocol data packet containing double cycle redundancy check codes; performing secondary cycle redundancy check based on the double cycle redundancy check codes after analyzing the protocol data packet in a main control board to obtain effective data; performing cross check and voting on the effective data of double channels of the main control board to generate a channel local voting result; performing board card level check on the channel local voting result and then performing global check, judging global data consistency based on a global check code, and identifying system faults. The application improves the comprehensiveness and effectiveness of data check, and solves the problem that single point faults or data errors cannot be avoided.

Description

Technical Field

[0001] This application relates to the field of data verification technology for security control systems, specifically to a method and system for multiple verification of data integrity in a dual-channel security control system. Background Technology

[0002] In a dual-channel 2oo2 architecture security control system, conventional technologies for data integrity assurance and consistency verification typically perform single-time verification only at the communication link layer (such as protocol CRC) or application layer. This lacks a comprehensive integrity verification system covering the entire lifecycle of data acquisition, transmission, storage, synchronization, and use. As a result, data remains unverified at critical stages such as after voting within the I / O board and after synchronization between main control board channels, posing a risk of error latency and propagation. Furthermore, traditional single-verification methods cannot cover multiple stages such as data transmission, storage, forwarding, and voting, making it difficult to detect undetected errors caused by interference, hardware failure, or asynchronous communication between channels. At the same time, conventional data verification technologies often rely on comparing final voting results or periodic data mirroring comparisons, lacking efficient and lightweight methods for rapid global consistency verification. When a silent error occurs in a localized section of data on a particular channel, it is difficult to detect it in time before business use, potentially leading to error accumulation or the failure of the voting mechanism, which in turn causes the system to operate based on erroneous data. Furthermore, the aforementioned technologies typically only allow for verification of individual data blocks, or require a complete traversal of all data to achieve set verification. They lack a hierarchical verification mechanism that can both perform block-based verification and quickly verify overall consistency. This not only affects the system's real-time performance and scalability, but also results in a lack of efficient and complete data set consistency verification mechanism after data from multiple I / O boards is stored sequentially within the main control board. Moreover, the business software lacks integrity verification for specific board data blocks before using the voting results, posing a risk of using incorrect data. Summary of the Invention

[0003] This application addresses the limitations of data integrity and global consistency verification techniques in dual-channel safety control systems, which cannot avoid single points of failure or data errors. It proposes a multi-layer verification method and system for data integrity in dual-channel safety control systems. Through four layers of verification, it covers the entire process from I / O boards, main control boards, multi-channel synchronization to data application, thereby reducing system risks caused by errors in data transmission and processing and ensuring data validity.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a method for multiple verification of data integrity in a dual-channel security control system, the method comprising: The input signals acquired by the dual channels of the board are cross-voted within the board, the voting result data is subjected to a cyclic redundancy check and encapsulated with a cyclic redundancy check code based on the communication protocol, and a protocol data packet containing a double cyclic redundancy check code is obtained. After parsing the protocol data packets within the main control board, a second cyclic redundancy check is performed based on the double cyclic redundancy check code to obtain valid data; Cross-validation and voting are performed on the valid data of the dual channels of the main control board to generate local voting results for each channel. After performing board-level verification on the local voting results of the channel, a global verification is performed. The global data consistency is determined based on the global checksum to identify system faults.

[0005] In this solution, the integrity of the voting results is initially identified through dual-channel cross-voting followed by a cyclic redundancy check to prevent erroneous data from entering the transmission process. After the first cyclic redundancy check, a communication protocol encapsulation with a redundancy check code is performed, which can accurately detect interference and data packet loss in the transmission link from the I / O board to the main control board, further reducing erroneous data at the source. Valid data is obtained through a second cyclic redundancy check, and cross-checking and voting are performed on the valid data. This dual-checking method filters potential errors in the data and anomalies during the data transmission from the I / O board to the main control board, avoiding single points of failure. Through board-level and global checks, independent verification of single-board data is achieved, and global data consistency can be quickly detected without traversing all data. This solves the problem of the overall voting mechanism failing due to local data errors when subsequent business software calls data, improving fault detection efficiency and preventing the spread of erroneous data in multi-board systems.

[0006] Preferably, the step of performing on-board dual-channel cross-voting on the input signals acquired by the dual channels of the board, performing a cyclic redundancy check on the voting result data, and encapsulating the data with a cyclic redundancy check code based on the communication protocol to obtain a protocol data packet containing double cyclic redundancy check codes includes: External input signals acquired through dual channels on the I / O board are voted on in both channels to generate voting result data. Calculate the first CRC checksum for the voting result data of each channel to perform a cyclic redundancy check on the voting result data; After the voting result data and the first CRC check code are merged and packaged, the second CRC check code with a communication protocol that has CRC check is used for protocol encapsulation to obtain a protocol data packet carrying the voting result data of the first CRC check code and the second CRC check code.

[0007] Preferably, the step of parsing the protocol data packet on the main control board and then performing a second cyclic redundancy check based on a double cyclic redundancy check code to obtain valid data includes: In response to the protocol data packets sent by the IO board, the main control board verifies the second CRC check code. If the verification fails, the corresponding data packet is discarded directly. After the second CRC checksum passes the verification, the protocol data packet is parsed, and the voting result data is verified using the first CRC checksum. If the verification fails, the voting result data is discarded. Once the first CRC checksum passes verification, the voting result data is considered valid data.

[0008] Preferably, the step of parsing the protocol data packet on the main control board and performing a second cyclic redundancy check based on a double cyclic redundancy check code to obtain valid data further includes: Based on the logical sequence of the IO board, the valid data is merged with the corresponding first CRC checksum and stored in the main control board channel memory.

[0009] Preferably, the step of cross-validating and voting on the valid data of the dual channels of the main control board to generate local voting results for each channel includes: The main control board periodically exchanges stored valid data between the two channels and performs a first CRC check on the received valid data. If the check fails, a system fault warning is triggered. Once the first CRC checksum passes verification, each channel on the main control board votes on the corresponding valid data stored in the other channel and this channel, generating and saving the local voting result.

[0010] Preferably, the step of performing a global check after verifying the local voting results of the channel at the board level, and determining the global data consistency based on the global checksum to identify system faults, includes: Based on the valid data of each IO board stored in each channel of the main control board, the third CRC check code is calculated respectively; The third CRC checksum of all valid data from all IO cards in the main control board channel is used to calculate the fourth CRC checksum. Before the next round of voting by the dual channels of the main control board, the two channels of the main control board exchange their respective fourth CRC check codes and compare them. If the fourth CRC check codes are inconsistent, the system is determined to be faulty and the corresponding fault decision is triggered.

[0011] Preferably, the method further includes: Before the business software calls the voting result data of the IO board, it performs verification based on the third CRC check code. The business software data access authorization channel is opened only if the third CRC check code passes the verification.

[0012] Secondly, embodiments of this application provide a data integrity multi-verification system for a dual-channel security control system, comprising: A layer of verification module is used to perform on-board dual-channel cross-voting on the input signals acquired by the dual channels of the board, perform a cyclic redundancy check on the voting result data and encapsulate the cyclic redundancy check code based on the communication protocol to obtain a protocol data packet containing the double cyclic redundancy check code; The Layer 2 verification module is used to parse the protocol data packets within the main control board and then perform a second cyclic redundancy check based on the double cyclic redundancy check code to obtain valid data. The three-layer verification module is used to perform cross-verification and voting on the valid data of the dual channels of the main control board and generate the local voting results of the channels. The four-layer verification module is used to perform board-level verification on the local voting results of the channel and then perform global verification. It judges the consistency of global data based on the global verification code to identify system faults.

[0013] Thirdly, embodiments of this application provide a computer device, including: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement the steps of the method described in the first aspect above when executing the program stored in the memory.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0015] The beneficial effects of this application are: 1. By combining the first CRC checksum with the second CRC checksum, the limitation of a single checksum method being unable to cover the entire link is solved. The first CRC checksum is checked before data is exchanged between channels. On the one hand, it can detect errors in the transmission and reception links. On the other hand, it provides a basis for subsequent synchronous verification between channels of the main control board, ensuring that the data stored on each IO board of the main control board is complete and valid, and improving the execution efficiency of subsequent processes. 2. Voting between the two channels of the main control board is based on dual valid data, which improves the reliability of the voting results and reduces voting deviations caused by errors in single-channel data; 3. Through a hierarchical verification mechanism of board-level third CRC checksum and global fourth CRC checksum, independent verification of data from a single board is achieved, while global data consistency can be quickly detected without traversing all data. This eliminates the need to verify all board data one by one, improving fault detection efficiency and preventing the spread of erroneous data in multi-board systems. It solves the problem of local data errors causing the overall voting mechanism to fail, and adapts to the verification requirements of multi-board and large-volume systems. It achieves end-to-end integrity protection from data acquisition, transmission, inter-channel synchronization to business use, significantly improving the reliability and fault diagnosis capabilities of the dual-channel security control system. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0017] Figure 1 A flowchart illustrating the data integrity multi-verification method for a dual-channel security control system provided in this application embodiment.

[0018] Figure 2 A flowchart of another data integrity multi-verification method provided in this application embodiment.

[0019] Figure 3 A schematic diagram of the system module for the data integrity multi-verification method of the dual-channel security control system provided in this application embodiment.

[0020] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely one preferred embodiment of this application and are only used to explain this application. They do not limit the scope of protection of this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Example 1: As Figure 1 As shown, a data integrity multi-verification method for a dual-channel security control system includes: S1. Perform on-board dual-channel cross-voting on the input signals acquired by the dual channels of the board, perform a cyclic redundancy check on the voting result data, and encapsulate the cyclic redundancy check code based on the communication protocol to obtain a protocol data packet containing double cyclic redundancy check codes.

[0023] As an optional implementation, step S1 includes: External input signals acquired through dual channels on the I / O board are voted on in both channels to generate voting result data. Calculate the first CRC checksum for the voting result data of each channel to perform a cyclic redundancy check on the voting result data; After the voting result data and the first CRC check code are merged and packaged, the second CRC check code with a communication protocol that has CRC check is used for protocol encapsulation to obtain a protocol data packet carrying the voting result data of the first CRC check code and the second CRC check code.

[0024] In this embodiment, after the voting result data is verified by the first CRC check code, errors in the data stream after voting on the board can be quickly identified, such as distortion of the voting result caused by hardware failure, thereby preventing erroneous data from entering the transmission link. By encapsulating the communication protocol with the second CRC check code, interference, data packet loss and other problems in the transmission link from the IO board to the main control board can be accurately detected. If the verification fails, the data cannot enter the main control board, reducing the probability of erroneous data flowing into the core link of the system from the source.

[0025] Among them, CRC (Cyclic Redundancy Check) is a fast algorithm that generates a short, fixed-length check code based on data such as network data packets or computer files. It is mainly used to detect or check errors that may occur after data transmission or storage.

[0026] Specifically, if the external signal collected by the IO board is erroneous due to sensor interference, the single abnormal collection value can be eliminated through dual-channel voting, and the correct voting result is solidified by the first CRC check code. Even if a link error occurs during transmission, the second CRC check code can intercept it in time, preventing erroneous data from becoming the basis for system decisions.

[0027] S2. After parsing the protocol data packet in the main control board, perform a second cyclic redundancy check based on the double cyclic redundancy check code to obtain valid data.

[0028] As an optional implementation, step S2 includes: In response to the protocol data packets sent by the IO board, the main control board verifies the second CRC check code. If the verification fails, the corresponding data packet is discarded directly. After the second CRC checksum passes the verification, the protocol data packet is parsed, and the voting result data is verified using the first CRC checksum. If the verification fails, the voting result data is discarded. Once the first CRC checksum passes verification, the voting result data is considered valid data.

[0029] As an optional implementation, the step of parsing the protocol data packets on the main control board and then performing a second cyclic redundancy check based on a double cyclic redundancy check code to obtain valid data further includes: Based on the logical sequence of the IO board, the valid data is merged with the corresponding first CRC checksum and stored in the main control board channel memory.

[0030] In this embodiment, a dual verification checkpoint is set at the receiving end of the main control board, which includes transmission link verification based on the second CRC check code and data verification based on the first CRC check code. This allows for direct filtering of data packets with damaged transmission links through the second CRC check code, preventing data distortion caused by link interference from entering the storage stage. The first CRC check code performs a second verification to further confirm that the data itself has not been tampered with or distorted. The false negative rate of the dual verification is much lower than that of the single verification, ensuring that the data stored on each IO board of the main control board is complete and valid.

[0031] Furthermore, the data and the first CRC checksum are stored in the main control board channel according to the logical order of the IO boards, providing a structured basis for the rapid comparison and verification of data from multiple boards and improving the execution efficiency of subsequent processes.

[0032] S3. Perform cross-validation and voting on the valid data of the dual channels of the main control board to generate local voting results for each channel.

[0033] As an optional implementation, step S3 includes: The main control board periodically exchanges stored valid data between the two channels and performs a first CRC check on the received valid data. If the check fails, a system fault warning is triggered. Once the first CRC checksum passes verification, each channel on the main control board votes on the corresponding valid data stored in the other channel and this channel, generating and saving the local voting result.

[0034] In some embodiments, the main control board periodically exchanges stored valid data between the two channels in order to ensure real-time data alignment between the channels and avoid data inconsistency caused by asynchronous operation between the channels.

[0035] In this embodiment, the first CRC checksum is verified before data exchange between the two channels of the main control board to identify data errors in the storage stage or synchronous transmission. For example, if data tampering is caused by a failure of the single-channel storage module of the main control board, the verification failure will directly trigger a serious fault handling, preventing erroneous data from participating in subsequent voting. Voting between the two channels of the main control board is based on dual valid data, which improves the reliability of the voting results and reduces voting bias caused by single-channel data errors.

[0036] In some examples, if the data of an I / O board in channel A of the main control board is erroneous due to a storage chip failure, and the first CRC checksum verification fails when synchronized to channel B, the system will crash directly. This prevents the erroneous data from being voted on with the data in channel B to generate an incorrect result, thus avoiding erroneous decisions that could affect the system's safety functions, such as alarm triggering and emergency stop commands in industrial safety systems.

[0037] S4. After performing board-level verification on the local voting results of the channel, a global verification is performed. The global data consistency is judged based on the global checksum to identify system faults.

[0038] As an optional implementation, step S4 includes: Based on the valid data of each IO board stored in each channel of the main control board, the third CRC check code is calculated respectively; The third CRC checksum of all valid data from all IO cards in the main control board channel is used to calculate the fourth CRC checksum. Before the next round of voting by the dual channels of the main control board, the two channels of the main control board exchange their respective fourth CRC check codes and compare them. If the fourth CRC check codes are inconsistent, the system is determined to be faulty and the corresponding fault decision is triggered.

[0039] In this embodiment, the third CRC checksum provides an independent integrity identifier for the voting result of each I / O board, accurately locating erroneous board data without requiring a comprehensive check. The fourth CRC checksum is generated based on the aggregation of all third CRC checksums. Comparing the fourth CRC checksums between channels quickly determines whether the global data is consistent. Compared to the traditional verification method of "completely traversing all data," this significantly improves verification efficiency and fault detection efficiency, overcoming the limitations of low overall verification efficiency and lack of a fast global consistency verification method for multi-IO board datasets. Furthermore, if the fourth CRC checksum comparison fails, a serious fault is triggered, ensuring that the system stops operating when global data is inconsistent, preventing error accumulation that could lead to the failure of system security functions.

[0040] As an optional implementation, the method further includes: Before the business software calls the voting result data of the IO board, it performs verification based on the third CRC check code. The business software data access authorization channel is opened only if the third CRC check code passes the verification.

[0041] In this embodiment, the business software can only use data that has passed the third CRC checksum verification to ensure that security control commands (such as equipment security status judgment and control parameter output) are generated based on complete and correct data. This strengthens the system security boundary from the software level, further reduces the impact of single point of failure or data error on the core functions of the system, and meets the reliability requirements of the Security Integrity Level (SIL) for data usage.

[0042] As one specific implementation method, such as Figure 2 As shown, the data integrity multi-verification method for the dual-channel security control system provided in this embodiment is applicable to high-reliability data exchange and voting scenarios between the I / O board and the main control board in a dual-channel 2oo2 architecture, as well as between the two channels of the main control board. The specific data verification process is as follows: A1. External inputs collected by the IO board are voted on in a dual-channel manner. After the voting is completed, each board calculates the first CRC checksum (called CRC_1) of the result. The IO board sends the voting result data and CRC_1 together to the main control board. When sending, the built-in CRC checksum (second CRC checksum, called CRC_2) protocol is used for packaging. A2. After receiving the data, the main control board first parses the data packet and verifies CRC_2 using the protocol with built-in CRC check. After CRC_2 verification passes, CRC_1 is then verified. Data that passes CRC_1 is saved as valid data to the main control board, while data that fails CRC_2 is discarded directly. A3. The main control board periodically sends the locally stored IO data (i.e. the valid data obtained) between the two channels to the other channel. After receiving the data sent by the other channel, it will check CRC_1. If it fails, the system will crash, indicating that a serious system failure may occur. If it passes, it will perform a voting operation with the local data of the channel. A4. The main control board stores the voting results of its two channels of valid data, that is, the local voting results of the channels. It also calculates CRC_3 based on the data for each IO board. Each board has its own CRC_3, and then calculates CRC_4 based on all the CRC_3. A5. Before the next vote, the two channels of the main control board send their respective CRC_4 data to the other channel. After receiving the CRC_4 data sent by the other channel, the CRC_4 data is voted on. If they are inconsistent, the system will crash (serious failure). If they are consistent, the system will run normally. A6. Under normal system operation, when business software needs to use IO voting result data, it will first check CRC_3, and use it only if the third CRC check code passes the verification.

[0043] Furthermore, in step A2, since there are many IO boards, the main control board stores the data sequentially according to the board's logical order when saving the IO data, and the CRC_1 is retained in the data.

[0044] Through the above process, and by using multi-level CRC check and inter-channel cross-verification mechanisms, the integrity and consistency of data are ensured throughout the entire chain of acquisition, transmission, storage, voting, and use. This achieves end-to-end integrity protection from data acquisition, transmission, inter-channel synchronization to business use, significantly improving the reliability and fault diagnosis capabilities of the dual-channel security control system.

[0045] Example 2, as Figure 3 As shown in the figure, this application provides a data integrity multi-verification system for a dual-channel security control system, including: A layer of verification module is used to perform on-board dual-channel cross-voting on the input signals acquired by the dual channels of the board, perform a cyclic redundancy check on the voting result data and encapsulate the cyclic redundancy check code based on the communication protocol to obtain a protocol data packet containing the double cyclic redundancy check code; The Layer 2 verification module is used to parse the protocol data packets within the main control board and then perform a second cyclic redundancy check based on the double cyclic redundancy check code to obtain valid data. The three-layer verification module is used to perform cross-verification and voting on the valid data of the dual channels of the main control board and generate the local voting results of the channels. The four-layer verification module is used to perform board-level verification on the local voting results of the channel and then perform global verification. It judges the consistency of global data based on the global verification code to identify system faults.

[0046] In this embodiment, the integrity of the voting results is initially identified through dual-channel cross-voting followed by a cyclic redundancy check to prevent erroneous data from entering the transmission process. After the first cyclic redundancy check, a communication protocol encapsulation with a redundancy check code is performed, which can accurately detect interference and data packet loss in the transmission link from the I / O board to the main control board, further reducing erroneous data at the source. Valid data is obtained through a second cyclic redundancy check, and cross-checking and voting are performed on the valid data. This dual check filters potential errors in the data and anomalies during the data transmission from the I / O board to the main control board, avoiding single points of failure. Through board-level and global checks, independent verification of single-board data is achieved, and global data consistency can be quickly detected without traversing all data. This solves the problem of the overall voting mechanism failing due to local data errors when subsequent business software calls data, improving fault detection efficiency and preventing the spread of erroneous data in multi-board systems.

[0047] This application also provides a computer device, such as... Figure 4 As shown, it includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor, used to execute programs stored in memory, implements a multi-factor verification method for data integrity in a dual-channel security control system.

[0048] The communication bus mentioned in the above computer equipment can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0049] The communication interface is used for communication between the aforementioned computer equipment and other devices.

[0050] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0051] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0052] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements a multi-factor verification method for data integrity of a dual-channel security control system.

[0053] The above-described embodiments are preferred embodiments of this application and are not intended to limit the specific scope of this application. The scope of this application includes but is not limited to the specific embodiments described above. All equivalent changes made in accordance with the shape, structure, and method of this application are within the protection scope of this application.

Claims

1. A multi-factor verification method for data integrity in a dual-channel security control system, characterized in that: Includes the following steps: The input signals acquired by the dual channels of the board are cross-voted within the board, the voting result data is subjected to a cyclic redundancy check and encapsulated with a cyclic redundancy check code based on the communication protocol, and a protocol data packet containing a double cyclic redundancy check code is obtained. After parsing the protocol data packets within the main control board, a second cyclic redundancy check is performed based on the double cyclic redundancy check code to obtain valid data; Cross-validation and voting are performed on the valid data of the dual channels of the main control board to generate local voting results for each channel. After performing board-level verification on the local voting results of the channel, a global verification is performed. The global data consistency is determined based on the global checksum to identify system faults.

2. The data integrity multi-verification method for a dual-channel security control system according to claim 1, characterized in that: The process involves performing on-board dual-channel cross-voting on the input signals acquired from the dual channels of the board, performing a cyclic redundancy check (CRC) on the voting result data, and encapsulating the CRC code based on the communication protocol to obtain a protocol data packet containing double CRC codes, including: External input signals acquired through dual channels on the I / O board are voted on in both channels to generate voting result data. Calculate the first CRC checksum for the voting result data of each channel to perform a cyclic redundancy check on the voting result data; After the voting result data and the first CRC check code are merged and packaged, the second CRC check code with a communication protocol that has CRC check is used for protocol encapsulation to obtain a protocol data packet carrying the voting result data of the first CRC check code and the second CRC check code.

3. The data integrity multi-verification method for a dual-channel security control system according to claim 2, characterized in that: The process of parsing the protocol data packets within the main control board and performing a second cyclic redundancy check based on a double cyclic redundancy check code to obtain valid data includes: In response to the protocol data packets sent by the IO board, the main control board verifies the second CRC check code. If the verification fails, the corresponding data packet is discarded directly. After the second CRC checksum passes the verification, the protocol data packet is parsed, and the voting result data is verified using the first CRC checksum. If the verification fails, the voting result data is discarded. Once the first CRC checksum passes verification, the voting result data is considered valid data.

4. The data integrity multi-verification method for a dual-channel security control system according to claim 3, characterized in that: The step of parsing the protocol data packet on the main control board and performing a second cyclic redundancy check based on a double cyclic redundancy check code to obtain valid data also includes: Based on the logical sequence of the IO board, the valid data is merged with the corresponding first CRC checksum and stored in the main control board channel memory.

5. The data integrity multi-verification method for a dual-channel security control system according to claim 1, characterized in that: The process of cross-validating and voting on the valid data of the dual channels of the main control board to generate local voting results for each channel includes: The main control board periodically exchanges stored valid data between the two channels and performs a first CRC check on the received valid data. If the check fails, a system fault warning is triggered. Once the first CRC checksum passes verification, each channel on the main control board votes on the corresponding valid data stored in the other channel and this channel, generating and saving the local voting result.

6. The data integrity multi-verification method for a dual-channel security control system according to claim 1, characterized in that: The process of performing board-level verification on the local voting results of the channel, followed by global verification, and determining global data consistency based on the global checksum to identify system faults includes: Based on the valid data of each IO board stored in each channel of the main control board, the third CRC check code is calculated respectively; The third CRC checksum of all valid data from all IO cards in the main control board channel is used to calculate the fourth CRC checksum. Before the next round of voting by the dual channels of the main control board, the two channels of the main control board exchange their respective fourth CRC check codes and compare them. If the fourth CRC check codes are inconsistent, the system is determined to be faulty and the corresponding fault decision is triggered.

7. The data integrity multi-verification method for a dual-channel security control system according to claim 6, characterized in that: The method further includes: Before the business software calls the voting result data of the IO board, it performs verification based on the third CRC check code. The business software data access authorization channel is opened only if the third CRC check code passes the verification.

8. A data integrity multi-verification system for a dual-channel security control system, applicable to the data integrity multi-verification method for a dual-channel security control system as described in any one of claims 1-7, characterized in that: include: A layer of verification module is used to perform on-board dual-channel cross-voting on the input signals acquired by the dual channels of the board, perform a cyclic redundancy check on the voting result data and encapsulate the cyclic redundancy check code based on the communication protocol to obtain a protocol data packet containing the double cyclic redundancy check code; The Layer 2 verification module is used to parse the protocol data packets within the main control board and then perform a second cyclic redundancy check based on the double cyclic redundancy check code to obtain valid data. The three-layer verification module is used to perform cross-verification and voting on the valid data of the dual channels of the main control board and generate the local voting results of the channels. The four-layer verification module is used to perform board-level verification on the local voting results of the channel and then perform global verification. It judges the consistency of global data based on the global verification code to identify system faults.

9. A computer device, characterized in that: include: The system includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store computer programs; and the processor, when executing the program stored in the memory, implements the steps of the data integrity multi-verification method of the dual-channel security control system as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data integrity multi-verification method for the dual-channel security control system as described in any one of claims 1-7.

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