Optoelectronic logic gate device and single-pixel imaging system

Abstract

The application discloses an optoelectronic logic gate device and a single-pixel imaging system, and belongs to the technical field of photoelectric detection and logic operation. The optoelectronic logic gate device comprises a substrate, at least two electrodes arranged on the substrate and a photoelectric conversion layer in electrical contact with the electrodes; the photoelectric conversion layer is configured to generate a photoelectric current in response to irradiation of a light signal, and by changing the light intensity of the light signal and the polarity of the bias voltage applied to the electrodes, the device selectively realizes at least five different logic gate functions under a single device structure. The single-pixel imaging system comprises the above-mentioned device, and the imaging quality is regulated by processing the electrical signal under different logic gate functions. The application solves the problem that the existing optoelectronic logic gate needs multiple transistors to be integrated to realize multiple logic functions, resulting in a complex structure and high cost, and has the advantages of simple structure, low power consumption and reconfigurable function.

Description

Technical Field

[0001] This invention relates to the field of photoelectric detection and logic operation technology, and more specifically, to a photoelectric logic gate device and a single-pixel imaging system. Background Technology

[0002] Logic gates, as the basic units of digital circuits, are typically composed of transistors or diodes. They perform logical operations such as AND, OR, and NOT by inputting high and low voltage levels, and are an important foundation for modern information processing. Optoelectronic logic gates use optical signals as logic inputs, converting them into electrical signals using photodetectors. They offer advantages such as high processing speed and low power consumption, and are considered an ideal alternative to traditional electronic logic gates.

[0003] There are two main types of implementations of existing optoelectronic logic gates:

[0004] One type integrates multiple transistors into a single device, using different combinations of transistors to achieve different logic functions. While this approach has clearly defined functions, it suffers from complex device structures, difficult fabrication processes, and high manufacturing costs. Another type utilizes a single photodetector, employing methods such as changing the incident light wavelength (e.g., the method proposed by Song et al. based on the coexistence of positive and negative photoconductivity in Bi₂Se₃ at different wavelengths) or leveraging the device's bipolar response characteristics in conjunction with gate voltage modulation (e.g., the self-powered perovskite photodetector based on a back-to-back pinpp diode structure proposed by Kim et al.) to achieve various logic functions. However, the former still relies on complex bandgap or polarity modulation within the device, placing high demands on material and structural design; the latter requires additional gate voltage or multi-wavelength light sources, increasing system complexity.

[0005] Therefore, there is an urgent need for an optoelectronic logic gate device based on a heterojunction structure that can realize multiple logic functions through light intensity modulation and bias polarity switching, as well as a single-pixel imaging system using this device, to solve the problems existing in the current technology. Summary of the Invention

[0006] The purpose of this invention is to address the aforementioned problems in the prior art by providing an optoelectronic logic gate device and a single-pixel imaging system. A type II heterojunction is constructed using lead-free double perovskite material and organic polymer material as the optoelectronic response layer. By modulating the polarity of the extremely small bias voltage applied to both ends of the device and the illumination intensity of the incident light signal, five different optoelectronic logic gate functions can be reconstructed under a single device structure.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: a photoelectric logic gate device comprising: Substrate; At least two electrodes disposed on the substrate; and A photoelectric conversion layer that is in electrical contact with at least two electrodes; The photoelectric conversion layer is configured to generate photocurrent in response to the illumination of a light signal, and to selectively implement at least five different logic gate functions in a single device structure by changing the light intensity of the light signal and the polarity of the bias voltage applied to the electrodes.

[0008] Furthermore, the photoelectric conversion layer is a heterojunction structure, which includes a lead-free double perovskite material layer and a polyphenylene oxide derivative layer stacked together.

[0009] Furthermore, the lead-free double perovskite material layer is a Cs2AgBiBr6 layer, and the polyphenylene ethylene derivative layer is a poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylacetylene] layer.

[0010] Furthermore, a type II band arrangement is formed between the lead-free double perovskite material layer and the polyphenylene oxide derivative layer to generate a built-in electric field at the heterojunction interface that enhances the separation of photogenerated carriers.

[0011] Furthermore, at least five different logic gate functions include AND logic gate, OR logic gate, NOT logic gate, NOR logic gate, and NAND logic gate.

[0012] Furthermore, the optical signal includes two incident beams, and the photocurrent is compared with a preset reference current to generate an output logic signal; When the bias voltage is forward biased: Under the first illumination intensity, the photocurrent is greater than the reference current only when two incident beams are irradiated simultaneously, and the device implements the AND logic gate function. Under the second illumination intensity, when at least one incident beam illuminates the device, the photocurrent is greater than the reference current, and the device implements the OR logic gate function.

[0013] Furthermore, the optical signal includes at least one incident beam, and the photocurrent is compared with a preset reference current to generate an output logic signal; When the bias voltage is reverse biased: Under the third illumination intensity, with a single incident beam as input, the photocurrent is higher than the reference current when there is no incident beam, and the photocurrent is lower than the reference current when there is an incident beam. The device realizes the NOT logic gate function. Under the fourth illumination intensity, when there is no incident beam, the photocurrent is higher than the reference current. When at least one incident beam illuminates the photocurrent, the photocurrent is lower than the reference current, and the device realizes the NOR logic gate function. Under the fifth illumination intensity, the photocurrent is lower than the reference current only when two incident beams are simultaneously irradiated; otherwise, the photocurrent is higher than the reference current, and the device implements the NAND logic gate function.

[0014] Furthermore, the absolute value of the bias voltage is less than or equal to 1mV, and at least two electrodes are parallel strip electrodes.

[0015] A single-pixel imaging system, comprising: A light source used to generate light signals; A spatial modulation component, disposed in the optical path of the light source, is used to spatially modulate the optical signal to form an optical signal with pattern information; and The aforementioned optoelectronic logic gate device is used to receive spatially modulated optical signals and output electrical signals. The processing module is electrically connected to optoelectronic logic gate devices and is used to acquire electrical signals and reconstruct images based on the electrical signals. Among them, the optoelectronic logic gate device is configured to process electrical signals under different logic gate functions in order to achieve the control of imaging quality.

[0016] Furthermore, the light source includes two laser sources, and the optoelectronic logic gate devices operate in AND logic gate mode; when only one laser source's light signal illuminates the image, the logic output is low, presenting a first image quality; when both laser sources' light signals illuminate the image simultaneously, the logic output is high, presenting a second image quality higher than the first image quality.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. High functional integration and simplified structure: This invention integrates a heterojunction photoelectric conversion layer in a single device, eliminating the need to integrate multiple transistors or set up complex gate structures as in existing technologies. By simply changing two parameters—the polarity of the bias voltage applied to the same device and the intensity of the incident light—arbitrary switching of the functions of five logic gates—AND, OR, NOT, NOR, and NAND—can be achieved, greatly simplifying the device structure and peripheral control circuits and reducing manufacturing costs.

[0018] 2. Significantly reduced power consumption: This invention utilizes the built-in electric field at the heterojunction interface to promote the separation of photogenerated carriers. The device can operate stably at an extremely low bias voltage of less than or equal to 1mV. Compared with the existing technology, which usually requires bias voltages of several volts or even tens of volts, the power consumption is reduced by several orders of magnitude. It is particularly suitable for energy-sensitive edge computing and wearable electronic devices.

[0019] 3. High logic switching efficiency: Thanks to the efficient charge separation characteristics of the heterojunction interface, the device's response time can reach the millisecond level, and its continuous operation stability is excellent, ensuring high-speed and reliable execution of logic operations.

[0020] 4. Controllable imaging quality: When the optoelectronic logic gate device of the present invention is applied to a single-pixel imaging system, by setting different logic gate working modes, especially the AND logic gate mode, the imaging signal can be filtered and enhanced by the logic output state, which significantly improves the contrast and quality of the target image and has important application value in the fields of weak light signal detection and high-precision imaging. Attached Figure Description

[0021] Figure 1 A schematic diagram of the fabrication process of the photoelectric conversion layer in the optoelectronic logic gate device of the present invention is shown; Figure 2 This is a schematic diagram of the device structure and a schematic diagram of the crystal structure of the materials used; Figure 3 Surface morphology and X-ray diffraction pattern of Cs2AgBiBr6 thin film; Figure 4 The light absorption spectrum and photoluminescence spectrum of the material; Figure 5 This is a schematic diagram of the charge transfer mechanism at the heterojunction interface. Figure 6 The current-voltage characteristic curves and current-time response curves of the device under illumination are shown. Figure 7 The device's response time curve and responsivity and specific detectivity curves are shown as a function of optical power density. Figure 8 This is the long-term operational stability curve of the device; Figure 9 The truth tables and corresponding current-time response curves for the five logic gates are provided. Figure 10 This is a schematic diagram of a single-pixel imaging system; Figure 11 This is a schematic diagram of the imaging process of a single-pixel imaging system. Figure 12 This is an image of the single-pixel imaging system.

[0022] In the figure, 1 is the substrate; 2 is the electrode; 3 is the photoelectric conversion layer; 4 is the lead-free double perovskite material layer; 5 is the organic polymer material layer; 6 is the light source; 7 is the spatial modulation component; 71 is the mask; 72 is the lens; 8 is the photodetector; and 9 is the processing module. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of this invention.

[0025] Example 1: Structure of optoelectronic logic gate devices like Figure 2 As shown in (a), the optoelectronic logic gate device provided in this embodiment includes a substrate 1, at least two electrodes 2 (i.e., two Au) disposed on the substrate 1, and a photoelectric conversion layer 3 (i.e., MEH-PPV and Cs2AgBiBr6) electrically in contact with the electrodes 2.

[0026] Substrate 1 employs a silicon / silicon dioxide structure, meaning a silicon dioxide insulating layer is grown on the surface of a single-crystal silicon substrate to provide good electrical insulation and a smooth surface. At least two spaced electrodes 2 are formed on the silicon dioxide insulating layer using a vapor deposition process. In this embodiment, the electrodes 2 are parallel strip-shaped gold electrodes, forming a channel between them. The length of the channel (along the extension direction of the electrode 2) is 2.5 mm, and the width (the distance between the opposite edges of the two electrodes 2) is 50 micrometers. Electrodes 2 are used to apply a bias voltage (such as...). Figure 2 V in (a) ds It collects the photocurrent generated by photogenerated carriers.

[0027] A photoelectric conversion layer 3 is electrically connected between the two electrodes 2, covering the channel region and contacting at least a portion of the electrode 2 surface. The photoelectric conversion layer 3 is configured to generate photogenerated carriers in response to external light irradiation, thereby forming a photocurrent in the circuit. More importantly, through its specific material system and interface characteristics, the photoelectric conversion layer 3 enables the entire device to selectively implement at least five different logic gate functions in a single structure, simply by changing the polarity of the bias voltage applied to the electrodes 2 and the intensity of the incident light signal.

[0028] Example 2: Materials and Heterogeneous Structures of the Photoelectric Conversion Layer This embodiment further defines the specific structure and materials of the photoelectric conversion layer 3.

[0029] See Figure 2 (a) and Figure 2 In (b), the photoelectric conversion layer 3 is a heterojunction structure, which includes a lead-free double perovskite material layer 4 and an organic polymer material layer 5 stacked together. The two are in contact with each other and form a heterojunction at the contact interface.

[0030] Specifically, the lead-free double perovskite material layer 4 uses a Cs2AgBiBr6 thin film. Cs2AgBiBr6 is a typical double perovskite material, and its lattice uses Ag. + and Bi 3+ It replaced the toxic Pb in traditional lead-based perovskites 2+ This achieves both excellent photoelectric performance and environmental friendliness. The material possesses properties such as... Figure 2 The space group symbol shown in (b) is Pm-3m, representing a cubic symmetric crystal structure. This structure can be considered as a framework composed of concurrently arranged BiBr6 octahedra. (Cs) + Ions and Ag + Ions fill the interstitial positions. The organic polymer material layer 5 is a poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinyl] film, i.e., a MEH-PPV film. For example... Figure 1 As shown, the two thin films were prepared and stacked sequentially using a two-step spin coating method.

[0031] See Figure 5 (a) to Figure 5 In (c), the two materials form a type II band structure after contact. Specifically, the conduction band bottom and valence band top of Cs₂AgBiBr₆ are -3.95 eV and -6.02 eV, respectively, while the conduction band bottom and valence band top of MEH-PPV are -3.0 eV and -5.3 eV, respectively, and their bands are interleaved. Meanwhile, the Fermi level of MEH-PPV is higher than that of Cs₂AgBiBr₆. When the two materials come into contact, in order to achieve Fermi level unification, electrons will transfer from the MEH-PPV side to the Cs₂AgBiBr₆ side, thus forming a built-in electric field at the heterojunction interface pointing from Cs₂AgBiBr₆ to MEH-PPV. The presence of this built-in electric field allows for effective spatial separation of photogenerated electron-hole pairs at the interface. Electrons migrate to the Cs2AgBiBr6 layer (lead-free double perovskite material layer 4), while holes migrate to the MEH-PPV layer (organic polymer material layer 5), significantly suppressing carrier recombination and improving the device's photoelectric conversion efficiency and response speed. Figure 4 As shown in the absorption spectrum of (a), the absorption edge of the standalone Cs2AgBiBr6 film is approximately 520 nm, while the heterojunction film formed after combining it with MEH-PPV extends its light absorption range to nearly 600 nm, thus broadening the spectral response range of the device. Meanwhile, Figure 4 The photoluminescence spectrum in (b) shows that the fluorescence intensity of the heterojunction is significantly lower than that of the single material, further confirming the high charge separation efficiency at the interface.

[0032] Example 3: Fabrication method of optoelectronic logic gate device This embodiment provides a preferred method for fabricating the above-mentioned optoelectronic logic gate device, and the specific steps are as follows: Step 1: Preparation of precursor solution. AgBr, BiBr3, and CsBr are dissolved in dimethyl sulfoxide in stoichiometric ratio. The solution is stirred in a 50°C water bath or on a heated surface for 30 minutes to obtain a Cs2AgBiBr6 precursor solution with a concentration of 0.15-0.23 mol / L. Simultaneously, MEH-PPV particles are dissolved in toluene to prepare a MEH-PPV precursor solution.

[0033] Step 2: Preparation of Cs2AgBiBr6 thin film. A Si / SiO2 substrate 1 with a pre-prepared gold electrode 2 was ultrasonically cleaned with acetone, ethanol, and deionized water for 10 minutes each, followed by UV ozone treatment for 10 minutes to improve surface wettability. Then, a Cs2AgBiBr6 precursor solution was drop-added onto the surface of substrate 1 and spin-coated for 30-60 seconds at a speed of 1800-2500 r / min to form a uniform wet film. The spin-coated sample was transferred to a heating stage and annealed at 180-200℃ for 10-30 minutes to evaporate residual solvent and promote grain growth, resulting in a dense Cs2AgBiBr6 thin film. Figure 3 As shown in the scanning electron microscope image (a) in the figure, the obtained film surface is uniform and dense, with no obvious pinholes or cracks. Figure 3 The X-ray diffraction pattern in (b) shows characteristic diffraction peaks corresponding to the crystal planes (111), (002), and (022), proving that a high-quality Cs2AgBiBr6 crystalline thin film was formed.

[0034] Step 3: Preparation of MEH-PPV film. After the sample cools to room temperature, the MEH-PPV precursor solution is dropped onto the surface of the Cs2AgBiBr6 film, and a second spin-coating is performed under the same rotation speed conditions (1800-2500 r / min). The sample is then annealed again at 180-200℃ for 10-30 minutes to remove the toluene solvent and allow the MEH-PPV polymer segments to fully relax. As a result, a uniform MEH-PPV layer (organic polymer material layer 5) is formed on the Cs2AgBiBr6 layer (lead-free double perovskite material layer 4), and the two layers are in close contact to form a heterojunction.

[0035] The device fabrication is now complete. The two-step spin coating process used is simple, has good repeatability, and does not require expensive vacuum equipment, which helps reduce manufacturing costs.

[0036] Example 4: Photoelectric Response Performance of the Device This embodiment describes the basic photoelectric response performance of the device.

[0037] Figure 6Figure (a) shows the current-voltage characteristic curves of the device under 375nm wavelength laser illumination. It can be seen that the device exhibits extremely low dark current in the absence of light, while the current increases significantly under illumination. The curves show obvious asymmetric rectification characteristics, which confirms that a Schottky contact is formed between the heterojunction and the gold electrode 2, and that the built-in electric field has a gain effect on the forward current.

[0038] Figure 6 (b) shows the current-time response curve of the device under a fixed bias voltage and periodic switching light illumination. The device rapidly generates photocurrent and reaches a stable state at the moment the light is turned on, and quickly returns to the dark state after the light is turned off, exhibiting a stable and repeatable switching effect.

[0039] Figure 7 (a) shows the device's response time curve. Measurements show that the rise time (the time required for the current to rise from 10% to 90% of its maximum value) is approximately 3 milliseconds, and the fall time (the time required for the current to drop from 90% to 10% of its maximum value) is approximately 1 millisecond. This millisecond-level fast response ensures high-speed switching of logic states.

[0040] Figure 7 Figure (b) shows the relationship between the device's responsivity and specific detectivity as a function of incident light power density. Under 375 nm illumination, the device achieves a maximum responsivity of 6.42 A / W and a maximum specific detectivity of 1.89 × 10⁻⁶. 11 Jones. The trend of increasing responsivity with decreasing optical power density indicates that the device has a significant advantage in low-light detection.

[0041] Figure 8 For the device at 375nm, 189mW / cm 2 Stability test results after 3500 seconds of continuous operation under continuous illumination. Throughout the entire test period, the photocurrent fluctuation of the device was less than 3%, demonstrating excellent operational stability and reliability.

[0042] Example 5: Implementation of five optoelectronic logic gate functions The comparison process between the photocurrent and the reference current described above can be implemented by an external digital source meter, test system, or back-end comparator circuit that is electrically connected to the optoelectronic logic gate device.

[0043] This embodiment details how to implement the functions of five basic logic gates (AND, OR, NOT, NOR, and NAND) on a single device by modulating the polarity of the bias voltage and the intensity of the incident light. In this embodiment, the logic input signal is provided by two 375nm wavelength laser beams. The logic input is defined as (0,0) when there is no laser illumination, (0,1) or (1,0) when only one laser beam illuminates the device, and (1,1) when both laser beams illuminate the device simultaneously. The output logic signal of the device is determined by comparing the generated photocurrent with a preset reference current. When the photocurrent is greater than the reference current, the output logic is high (logic "1"). When the photocurrent is less than the reference current, the output logic is low (logic "0").

[0044] See Figure 9 The truth table of (a) in the middle and Figure 9 (b) to Figure 9 The current-time curve of (f) in the diagram shows the implementation conditions for each logic function as follows: AND logic gates: see [link] Figure 9 (b) A forward bias voltage of 1 mV is applied between the two electrodes 2, and the reference current is set to a forward bias of 1.5 μA. The intensity of each incident light beam is controlled to be 189 mW / cm². 2 Under these conditions, the photocurrent amplitude can only exceed the reference current of 1.5μA when both beams of light are simultaneously illuminating the device (logic input (1,1)), resulting in a logic "1" output. When there is no light (0,0) or only a single beam of light (0,1 or 1,0), the photocurrent is lower than the reference value, resulting in a logic "0" output. This achieves the AND logic function.

[0045] In another set of verification experiments, by setting the forward bias voltage to 0.5mV and adjusting the incident light intensity accordingly, it was also possible to make the photocurrent greater than the preset reference current only when both beams of light were simultaneously irradiated, thus successfully realizing the AND logic function. This indicates that under the device structure of the present invention, the bias voltage can operate effectively within a range where the absolute value is less than or equal to 1mV, and the device has extremely low power consumption characteristics.

[0046] OR logic gate: See Figure 9 (c) A forward bias voltage of 1 mV is still applied between the two electrodes 2, while the reference current remains constant at a forward bias of 1.5 μA. The intensity of each incident beam is increased to 231 mW / cm². 2At this point, since the photocurrent generated by a single beam of light is large enough, whether illuminated by a single beam (0,1 or 1,0) or by two beams (1,1), the photocurrent can exceed the reference current of 1.5μA, outputting logic "1". Only when there is no light (0,0) does the photocurrent fall below the reference value, outputting logic "0". This achieves the OR logic function.

[0047] NOT logic gate: See also Figure 9 (d) A reverse bias voltage of -1mV is applied between the two electrodes 2, and the reference current is set to reverse -1μA. A single incident beam is used as the input signal for explanation; no light is considered input "0", and light is considered input "1". The intensity of the incident light is controlled at 423mW / cm². 2 When there is no light (input 0), the device's dark current under reverse bias is higher than -1μA (i.e., the absolute value is smaller), and after comparison, it outputs logic "1". When there is light (input 1), the amplitude of the generated reverse photocurrent is greater than the absolute value of the reference current of -1μA, and after comparison, it outputs logic "0". This realizes the NOT logic function of inverting the input and output.

[0048] NOR logic gates: See Figure 9 (e) Maintaining a reverse bias voltage of -1mV and a reference current of -1μA, the incident light intensity is still set to 423mW / cm². 2 At this point, only under the condition of no light (0,0), the reverse current output by the device is less than the absolute value of the reference current, thus outputting logic "1". Once any one or two beams of light are illuminating the device, the resulting photocurrent will exceed the absolute value of the reference current, causing the output logic "0". This achieves the NOR logic function.

[0049] NAND logic gates: See Figure 9 (f) Maintaining a reverse bias voltage of -1mV and a reference current of -1μA, the incident light intensity is adjusted to 353mW / cm². 2 Under these conditions, when there is no light (0,0) or only a single beam of light (0,1 or 1,0), the generated reverse photocurrent is insufficient to exceed the absolute value of the reference current, resulting in an output logic "1". Only when both beams of light illuminate simultaneously (1,1) can the accumulated photocurrent exceed the absolute value of the reference current, causing the output to flip to logic "0". This achieves the NAND logic function.

[0050] The experimental data clearly demonstrate that the optoelectronic logic gate device provided by this invention can implement all five basic logic functions on the same device simply by switching the polarity of the bias voltage (1mV forward or -1mV reverse) and appropriately adjusting the incident light intensity. Compared with existing technologies, it eliminates the need to change the incident light wavelength, apply additional gate voltage, or integrate complex transistor arrays within the device. The entire logic switching process requires fewer control parameters and is easy to operate, fully demonstrating the advantages of the device's simple structure and highly integrated functions.

[0051] It should be noted that although a specific bias voltage value of 1mV is used as an example in this embodiment, it will be obvious to those skilled in the art that, under the teachings of this invention, other bias voltage values ​​with an absolute value less than or equal to 1mV can also achieve the above-mentioned logical function, only requiring adjustment of the specific value of the incident light intensity accordingly.

[0052] Example 6: Single-pixel imaging system and its application This embodiment provides a single-pixel imaging system that uses the above-mentioned optoelectronic logic gate devices, and explains its working principle.

[0053] See Figure 10 The single-pixel imaging system includes: a light source 6, a spatial modulation component 7, a photodetector 8, and a processing module 9.

[0054] Light source 6 is used to generate optical signals. In this embodiment, light source 6 includes two 375nm laser sources to provide incident light that matches the operating mode of the logic gate.

[0055] The spatial modulation component 7 is disposed in the optical path of the light source 6, and includes a custom mask 71 that can be translated along the xy axis and two lenses 72. The mask 71 is fabricated with specific patterned apertures, such as the shapes of the letters "U", "J", and "S". When the mask 71 moves point by point in the xy plane, the light passing through the patterned apertures is spatially modulated to form a changing light signal carrying pattern information.

[0056] The photodetector 8 employs a photoelectric logic gate device according to any one of embodiments 1 to 5. This device is placed behind the mask 71 to receive spatially modulated optical signals and convert them into electrical signals. As previously described, the device can be operated in a specific logic gate mode by setting its bias voltage polarity and reference current.

[0057] The processing module 9 is electrically connected to the photodetector 8 and is used to acquire the changing photocurrent signal output by the photodetector 8. For example... Figure 11As shown, when the letter "S" pattern on the mask 71 is scanned line by line above the device, the device outputs a series of photocurrent signals whose amplitude varies with the brightness of the pattern. The processing module 9 reconstructs the original spatial distribution pattern on the mask 71 based on the preset scanning trajectory and photocurrent amplitude using an algorithm.

[0058] Figure 12 The image results, displaying the letters "UJS" as a pattern, were shown. After reconstruction by processing module 9, the original pattern was clearly displayed on the computer screen, verifying the system's excellent imaging capabilities.

[0059] Specifically, this imaging system can utilize the different logic functions of optoelectronic logic gates to control the quality of the reconstructed image. In a preferred operating mode, the optoelectronic logic gates are set to AND logic gate mode. In this case, the two laser sources are used as two logic inputs respectively. Figure 12 As shown in the bottom row of images, when only one laser source is activated (corresponding to logic input 01 or 10), the device outputs logic "0". At this time, the amplitude of the acquired signal is low, resulting in poor contrast and blurred details in the reconstructed image, presenting a first-quality image. However, when two laser sources are activated simultaneously (corresponding to logic input 11), the device outputs logic "1", and the generated photocurrent signal is significantly enhanced. The contrast of the reconstructed image is greatly improved, and the outline is clear, presenting a second-quality image that is higher than the first-quality image.

[0060] Therefore, by integrating the optoelectronic logic gate device of this invention into a single-pixel imaging system, not only can basic image information acquisition and reconstruction be completed, but also the reconfigurable logic function of the device itself can be utilized to directly and effectively control image contrast and quality through physical-level optical signal filtering without increasing the overhead of additional image processing algorithms. This feature has significant technical advantages in applications with high imaging quality requirements, such as weak light detection, biological tissue imaging, and skin health monitoring.

[0061] The parts of this invention not described in detail are prior art, therefore they are not described in detail here.

[0062] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0063] Although this document uses a considerable amount of technical terminology, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0064] This invention is not limited to the preferred embodiments described above. Anyone can derive other products in various forms under the guidance of this invention. However, regardless of any changes made to their shape or structure, any technical solution that is the same as or similar to this invention falls within the protection scope of this invention.

Claims

1. A photoelectric logic gate device, characterized in that, include: Substrate; At least two electrodes are disposed on the substrate; as well as A photoelectric conversion layer that is in electrical contact with the at least two electrodes; The photoelectric conversion layer is configured as follows: The device generates a photocurrent in response to the illumination of a light signal, and by changing the light intensity of the light signal and the polarity of the bias voltage applied to the electrodes, the device can selectively implement at least five different logic gate functions in a single device structure.

2. The optoelectronic logic gate device according to claim 1, characterized in that, The photoelectric conversion layer is a heterojunction structure, which includes a lead-free double perovskite material layer and a polyphenylene oxide derivative layer stacked together.

3. The optoelectronic logic gate device according to claim 2, characterized in that, The lead-free double perovskite material layer is a Cs2AgBiBr6 layer, and the polyphenylene ethylene derivative layer is a poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylacetylene] layer.

4. The optoelectronic logic gate device according to claim 2, characterized in that, A type II band arrangement is formed between the lead-free double perovskite material layer and the polyphenylene oxide derivative layer to generate a built-in electric field at the heterojunction interface that enhances the separation of photogenerated carriers.

5. The optoelectronic logic gate device according to claim 1, characterized in that, The at least five different logic gate functions include AND logic gate, OR logic gate, NOT logic gate, NOR logic gate and NAND logic gate.

6. The optoelectronic logic gate device according to claim 5, characterized in that, The optical signal includes two incident beams, and the photocurrent is compared with a preset reference current to generate an output logic signal; When the bias voltage is positive bias: Under the first illumination intensity, the photocurrent is greater than the reference current only when two incident beams illuminate simultaneously, and the device implements the AND logic gate function; Under the second illumination intensity, when at least one incident beam illuminates the device, the photocurrent is greater than the reference current, and the device implements the OR logic gate function.

7. The optoelectronic logic gate device according to claim 5, characterized in that, The optical signal includes at least one incident beam, and the photocurrent is compared with a preset reference current to generate an output logic signal; When the bias voltage is reverse biased: Under the third illumination intensity, with a single incident beam as input, the photocurrent is higher than the reference current when there is no incident beam, and lower than the reference current when there is an incident beam. The device implements the NOT logic gate function. Under the fourth illumination intensity, when there is no incident beam, the photocurrent is higher than the reference current; when at least one incident beam illuminates the device, the photocurrent is lower than the reference current. The device implements the NOR logic gate function. Under the fifth illumination intensity, the photocurrent is lower than the reference current only when two incident beams illuminate simultaneously; otherwise, the photocurrent is higher than the reference current, and the device implements the NAND logic gate function.

8. The optoelectronic logic gate device according to any one of claims 1 to 7, characterized in that, The absolute value of the bias voltage is less than or equal to 1mV, and the at least two electrodes are parallel strip electrodes.

9. A single-pixel imaging system, characterized in that, include: A light source used to generate light signals; A spatial modulation component is disposed in the optical path of the light source and is used to spatially modulate the optical signal to form an optical signal with pattern information; as well as The optoelectronic logic gate device according to any one of claims 1 to 8 is used to receive spatially modulated optical signals and output electrical signals; The processing module is electrically connected to the optoelectronic logic gate device and is used to acquire the electrical signal and reconstruct the image based on the electrical signal; The optoelectronic logic gate device is configured to process the electrical signal under different logic gate functions in order to control the imaging quality.

10. The single-pixel imaging system according to claim 9, characterized in that, The light source includes two laser sources, and the optoelectronic logic gate device operates in AND logic gate mode; when only one laser source's light signal illuminates the image, the logic output is low, presenting a first image quality; when both laser sources' light signals illuminate the image simultaneously, the logic output is high, presenting a second image quality higher than the first image quality.

Images